Silicon nanocrystals from high-temperature annealing: Characterization on device level

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Phys. Status Solidi A 210, No. 4, 669–675 (2013) / DOI 10.1002/pssa.201200824 p s sa

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applications and materials science

Silicon nanocrystals fromhigh-temperature annealing:Characterization on device level

Philipp Loper*,1,2, Mariaconcetta Canino3, Julian Lopez-Vidrier4, Manuel Schnabel1, Florian Schindler1,Friedemann Heinz1, Anke Witzky1, Michele Bellettato3, Marco Allegrezza3, Daniel Hiller2,Andreas Hartel2, Sebastian Gutsch2, Sergi Hernandez4, Roberto Guerra5, Stefano Ossicini5,Blas Garrido4, Stefan Janz1, and Margit Zacharias2

1Fraunhofer ISE, Heidenhofstr. 2, 79110 Freiburg, Germany2 IMTEK, University Freiburg, Georges-Koehler-Allee 103, 79110 Freiburg, Germany3CNR-IMM, Via Piero Gobetti 101, 40129 Bologna, Italy4MIND-IN2UB, Universitat de Barcelona, Martı i Franques 1, 08028 Barcelona, Spain5Universita di Modena e Reggio Emilia, Via Giovanni Amendola, 2, 42100 Reggio Emilia, Italy

Received 9 October 2012, revised 15 December 2012, accepted 24 January 2013

Published online 28 February 2013

Keywords quantum dots, silicon carbide, silicon nanocrystals, solar cells, solid phase crystallization

*Corresponding author: e-mail [email protected], Phone: þ49 761 4588 5021, Fax: þ49 761 4588 9250

Silicon nanocrystals (Si NCs) embedded in Si-based dielectrics

provide a Si-based high band gap material (1.7 eV) and enable

the construction of all-crystalline Si tandem solar cells.

However, Si nanocrystal formation involves high-temperature

annealing which deteriorates the properties of any previously

established selective contacts. The inter-diffusion of dopants

during high-temperature annealing alters Si NC formation and

limits the built-in voltage. Furthermore, most devices presented

so far also involve electrically active bulk Si and therefore do

not allow a clear separation of the observed photovoltaic effect

of the nanocrystal layer from that of the bulk Si substrate. A

membrane route is presented for nanocrystal based p–i–n solar

cells to overcome these limitations. In this approach, the

formation of both selective contacts is carried out after high-

temperature annealing and therefore not affected by the latter.

p–i–n Solar cells are investigated with Si NCs embedded in

silicon carbide in the intrinsic region. Device failure due to

damaged insulation layers is analyzed by electron- and light

beam induced current measurements. Open-circuit voltages of

176mV are shown for the NC layer. An optical model of the

device is presented for improving the cell current. Comparison

of the optical limit and the measured short circuit current

demonstrates that the device is governed by recombination

within the absorber layer.

Vertical p–i–n solar cell with a Si nanocrystal thin film in the

intrinsic region and selective electron and hole contacts by

doped amorphous silicon carbide (a-SixC1�x:H).

� 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

1 Introduction The impressive success in reachingvery high conversion efficiencies with c-Si [3] has triggeredthe search for novel concepts which permit to overcomethe fundamental efficiency limits. Module costs havebeen reduced significantly due to upscaled production, and

transfer from the laboratory to industry takes place at anever faster pace. For ongoing long-term cost reduction,however, not only upscaled production and ever moresophisticated technologies are required but the implementa-tion of fundamentally new concepts which permit to


670 P. Loper et al.: Silicon nanocrystals from high-temperature annealingp

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Figure 1 (online color at: www.pss-a.com) Principle of a crystal-line silicon tandem solar cell. The top solar cell consists of siliconnanocrystals in a silicon-based dielectric matrix such as SiO2,Si3N4, or SiC. The bandgap of the nanocrystal solar cell can becontrolled by the nanocrystal size due to quantum confinementeffects.

Figure 2 (online color at: www.pss-a.com) Photoluminescenceintensity from identical samples of 4 nm Si NC in SiO2 for variousannealing processes. The photoluminescence intensity is a measurefor the Si NC–SiO2 interface quality. High thermal budgets arerequired to produce high quality Si NC.

overcome the physical limitations of today’s technologies.One approach to overcome the Shockley–Queisser limit ofc-Si is to introduce a second band gap which still essentiallyconsists of c-Si [5]. This is provided by a dense array ofsilicon nanocrystals (Si NCs) embedded in a Si-baseddielectric. The band gap of such a composite material canbe tuned from the bulk c-Si band gap up to about 2 eV dueto quantum confinement [7] and is well suited for the topcell [9] in an all c-Si tandem cell as shown in Fig. 1. Thepreparation of dense Si NC arrays of controlled size involveshigh thermal budgets and imposes special requirements todevice design. This paper reviews latest developments andexplores challenges and possibilities for fabrication ofSi NC devices. A test device is presented which decouplesthe electrical characterization of the Si NC film from the Siwafer substrate. Results are presented for the substrate-freecharacterization of Si NC embedded in SiC as the absorberof a p–i–n solar cell.

2 Material fabrication and device design2.1 Synthesis of high-quality Si NCs Research

interest in nanostructured Si began with the discovery ofvisible photoluminescence (PL) in porous Si [10]. Sincethen, fabrication methods have matured and Si NCs arenowadays produced by laser pyrolysis [11], wet chemicalsynthesis [12], plasma synthesis [13], direct deposition byplasma enhanced chemical vapor deposition (PECVD) [14]or solid phase crystallization from PECVD films [15, 16].For solar cell applications, however, the choice of fabricationmethods rapidly narrows down: firstly, size controllednanocrystals are required in order to achieve a spatiallyuniform band gap, which so far could only be achieved bysolid phase crystallization within a superlattice [15, 17].Secondly, the defect density at the Si NC interface criticallydepends on the synthesis method. As for planar (bulk)interfaces, SiO2 passivates the Si NC interface very well[18]. Hiller et al. [19] demonstrated that the passivationquality depends critically on the thermal budget employedin the growth process. For that study, Si NCs in SiO2


were grown by a superlattice approach using variousannealing processes. The thermal processes comprisedhigh-temperature conventional furnace annealing, rapidthermal annealing (RTA), low-temperature annealing fordefect passivation and combinations thereof [19]. Theinterface quality was monitored with the PL intensity, asthe latter is a well-suited measure for the Si NC interfacedefect density [19]. Figure 2 summarizes the experiment,details can be found in Ref. [19]. The main finding is thathighly luminescent NCs could only be achieved by usingthe high-temperature conventional furnace annealing. As theformation of Si NC in SiO2 is already well-understood, thematerial is a good test system for fundamental studies. Adifferent host matrix such as SiC or Si3N4 implies afundamentally different electronic structure. However, it isvery likely that the general trends are preserved. Specifically,low defect densities and a tight size control are assumed torequire large thermal budgets. The requirement of a spatiallyuniform band gap and a low defect density therefore stressesthe relevance of device processes compatible with high totalthermal budgets and peak temperatures up to 1150 8C forphotovoltaic applications.

2.2 Device development A solar cell with a Si NCabsorber which avoids any high-temperature step waspresented by Liu and Kortshagen [8]. The authors used wetchemically synthesized Si NC embedded in poly-3(hexyl-thiophene) as absorber in a superstrate configuration withITO on glass as substrate and an Al back contact. Theyreported 510mV open-circuit voltage and 0.148mA cm�2

short-circuit current. This result is included here for complete-ness, even though the rest of this paper is restricted to devicesfor Si NCs prepared by high-temperature annealing.

The necessity of using temperatures up to 1150 8C forthe fabrication of the Si NC layer imposes severe require-ments on the thermal stability and expansion coefficientof the substrate and also the device process because thesubstrate hinders the access to the layer rear side. Thesimplest possibility is to use a conductive substrate as shown

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Figure 3 (online color at: www.pss-a.com) Device structures forrecrystallized layers. The contact can be established directly by aconductive substrate (a), or a doped layer on top of an insulatingsubstrate (b). Inavariantof (b), theSinanocrystal layer itself isdopedduring its deposition, resulting in the structure shown in (c). For fullflexibility in choosing the contact materials and processes, bothcontacts can be placed on top of the recrystallized layer (d).

in Fig. 3a, e.g., a Si wafer. However, as the incident lightis not absorbed completely in the QD film, the wafer alsoabsorbs part of the light and contributes to the photovoltaiceffect. As the Si wafer exhibits superior electronic proper-ties, it masks any effect of the Si NC layer. Especiallythe demonstration of a high band gap on device level ishindered by electrically active bulk Si parts. The challengeof optoelectronic characterization of Si NC films is theircharacterization on device level without any influenceof bulk Si. Table 1 summarizes realizations of Si NCphotovoltaic devices without electrical wafer influence.

In the case of an insulating substrate, highly doped layersare implemented as the back contact to the QD layer (thesolar cell base) as shown in Fig. 3b. This approach waspursued by Kurokawa et al. [2] and Yamada et al. [4], whorealized SiC/Si-NC p–i–n structures on quartz glass withheavily doped bulk Si as a back contact. The drawback ofthis approach is diffusion of dopants into the Si NC filmduring the high temperature treatments, which mightadversely affect crystallization and the electronic quality ofthe film.

Table 1 Overview over Si NC photovoltaic devices without wafer con doped poly-Si on an QZ substrate, on an oxidized wafer that wa

material fabricationmethod

device

Si NC in SiO2 co-sputtering, SPC p–i–n, in situ doAl contacts

Si NC in SiC–‘‘–/w N PECVD, SPC n–i–p, a-Si(n), Sp-type poly-Si o

Si NC in SiC–‘‘–/w O PECVD, SPC n–i–p a-Si(p), Sn-type poly-Si o

Si NC in SiC PECVD, SPC p–i–n, a-SixC1�a-SixC1�x(n), su

colloidal Si NC plasma ITO/Si-NC in A

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Furthermore, it is challenging to clearly separate thephotovoltaic activity of the nanocrystal layer from that of therather thick poly Si film. In a variant of (b), the Si nanocrystallayer itself can be doped during its deposition, resulting inthe structure shown in (c). The approach shown in Fig. 3cdoes in principle allow to measure the nanocrystal layerindependently from any bulk Si contributions. A realizationwas presented by Perez-Wurfl et al. [1], who fabricatedSiO2/Si-rich oxide multilayers on quartz glass and dopedin situ the lowermost bilayers with phosphorus and the topbilayers with boron. After annealing to form Si NC, a mesaetch was performed to contact the doped bottom layers.The device yielded 492mV open-circuit voltage. However,both approaches, the laterally conductive layer and theconductive substrate, suffer from the same drawback.The physical properties of the electrical contact cannot beindependently influenced but are determined by the materialand the recrystallization process. To suppress out-diffusionof dopants from the back contact layer, a diffusion barrierwould have to be implemented. A possibility to separatecontact formation from the recrystallization process andthe substrate properties is to realize both contacts on thefront side of the recrystallized layer, see Fig. 3d. However,this approach requires much higher carrier diffusion lengthsthan any vertical structure. As the employed QD layersare highly resistive, the device performance is likely to belimited by series resistance.

2.3 Approach to substrate-free photovoltaiccharacterization of Si NC thin films For full flexibilityto tune the physical properties of both contacts we havedeveloped a solar cell test structure in which the substrate islocally removed by chemical etching [6]. This facilitateslarge area rear side access to the nanocrystal layer (seeFig. 4). This device structure can be used for any thin filmsthat involve high-temperature processing such as silicon orgermanium nanocrystals in a dielectric matrix or thin c-Sior c-SiC bulk films. The rear contact is insulated from thesubstrate by an additional insulation layer. Between thenanocrystal layer and the substrate, an intermediate layer

ontribution. Devices were realized on quartz glass (QZ) substrates,s later etched back and on ITO covered glass.

VOC

(mV)JSC(mA cm�2)

ref.

ped SiO2/Si NC on QZ, 492 (349) 0.02 [1]

iC/Si NC (i),n QZ

165 1.3� 10�2 [2]

289 0.433iC/Si NC (i),n QZ

165 1.3� 10�2 [4]

518 0.35

x(p), SiC/Si NC(i),bstrate-free

370 0.35 [6]

l 510 0.148 [8]



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Figure 4 (online color at: www.pss-a.com) Structure for a verticalp–i–n solar cell with a Si nanocrystal thin film in the intrinsic regionand selective electron andhole contacts bydoped amorphous siliconcarbide (a-SixC1�x:H). The active cell is an entirely vertical device,i.e., no lateral conductivity is required and the device can beconsidered to be one-dimensional.

Figure 5 (online color at: www.pss-a.com) Process flow chart forthe vertical Si NC cell with p- and n-doped a-SixC1�x:H layersshown in Fig. 4.

serves as a mechanical buffer, electrical insulation andetch stop. As the high temperature annealing is done beforestructuring and deposition of the contact layer and the Si NCfilms is separated from the substrate by the insulation layer A(see Fig. 4), no out-diffusion of impurities influencesSi NC formation. Full flexibility for the choice of the contactmaterials and the interface pretreatment is provided. Theelectrically active parts are vertically stacked and as such canbe described by one-dimensional device physics. No lateralconductivity of any semiconductor device part is required.The device shown in Fig. 4 can also be applied to oxide- ornitride based NC materials. The implementation of Si NCin SiO2 as absorber layer can be realized by preparing anadditional intermediate layer between the Si NC layer andthe Si wafer in order to etch the insulation layer selectivelyto the SiO2 with Si NC. However, the practical realizationis more complex than with a SiC matrix due to the prolongedKOH etching. KOH attacks the SiO2 matrix whichinstabilizes the entire system mechanically. Furthermore,device characterization is facilitated by the better conduc-tivity of SiC with NC with respect to SiO2. Therefore, thispaper focuses the characterization of SiC-based absorbers.

3 Experimental Devices as shown schematically inFig. 4 were realized with Si NCs embedded in SiC.Experimental details and a discussion of the structuralproperties including transmission electron microscopy canbe found in Ref. [20]. The SiC/SRCmultilayer comprises 30bilayers of 3 nm Si rich layers and 6 nm stoichiometric SiClayers. Underneath the multilayer stack a 20 nm SiC bufferlayer was implemented and on top of the uppermost 6 nmSiClayer a 20 nm Si encapsulation layer was deposited. Afterthermal annealing at 600 8C for 4 h and 1100 8C for 30min inN2 with 10% O2, the (then partially oxidized) encapsulationlayer was etched off in HF and tetramethylammoniumhydroxide (TMAH). The SiC and Si-rich carbide (SRC)layers shrink by a factor of 0.5 and 0.7, respectively, due to


thermal annealing. The doped amorphous silicon layersweredeposited with a Roth & Rau AK400M reactor at 250 8C,0.3mbar and 13.56MHz radio frequency. The thicknesseswere set by previously determining the deposition rates ofthe individual processes. The a-SixC1�x:H emitter layerswere deposited with 10W radio frequency power, 5V bias,30 sccm SiH4, 30 sccm CH4, 30 sccm Ar, and 130 sccm PH3

or 100 sccm B2H6 for n- or p-doping, respectively, bothdiluted in H2. The dopant content was measured withsecondary ion mass spectrometry. The n-doped layercontained 1� 1021 cm�3 phosporous, and the p-doped layer4.36� 1021 cm�3 boron.

The device fabrication process is illustrated in Fig. 5.All structuring stepswere done by inkjet printing of a hotmeltresist. First, a SiO2/SiNx layer on the rear side is structuredwhich serves as hard mask for the KOH etch of the wafer.After the wafer and then the hard mask were removedlocally, insulation layer B was deposited on the rear side(top side in Fig. 4), i.e., on the wafer rear surface, on thetrench sidewalls and on the membrane. The insulation layersA and B were then opened locally on the membrane, againusing inkjet printing. After a cleaning step, and an HF-Dip,a-SiC:H(p) was deposited on the rear side. More details onthe fabrication process can be found in Ref. [6]. Current–voltage (I–V) curves were measured under a sun simulatorwith approximately an air mass 1.5 global (AM1.5G)spectrum and 1000Wm�2 light intensity. Light-beaminduced current was measured with a fiber coupled halogenlamp. The light beam was chopped by an optical chopperand the short circuit current was measured using a current-sensitive preamplifier and a lock-in amplifier. The light spotradius was 200mm.

4 Results and discussion4.1 Investigation of device failure One critical

issue in the fabrication of the solar cell test device discussedin this paper is the electrical insulation of the Si wafer fromthe electrically active a-SiC:H(p), a-SiC:H(n), and SiC/Si-NC layers. The insulation layer has to withstand the cleaning

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Figure 7 (online color at: www.pss-a.com) Optical micrographcombined with a LBIC map of one cell structure seen from thestructured side. The membrane does not have any mechanicalsupport and therefore has awavy appearance. The blue area (opticalmicrograph) in the middle is the active cell area, surrounded bythe region in which the insulation layers A and B on the membraneare not opened (see also Fig. 4).

procedures applied before the a-SiC:H(p) layer is deposited.To investigate the insulation properties at high spatialresolution, electron beam induced current (EBIC)mapswererecorded. Figure 6 shows a scanning electron micrograph(SEM) and the corresponding EBIC image of the uppertrench edge in which the insulation layer appears to bedamaged due to an undesired etch attack. The EBIC mapshows a signal (dark¼ high current) exactly from theetched regions. In the optical micrograph, shown in Fig. 6,the etched insulation layer appears blue, surrounded by ayellow area. The blue area corresponds to the etched regionobserved both in the SEM and the EBIC images, but theyellow area does not appear in either. The insulation layerof this sample was a stack consisting of 450 nm SiOx

and 50 nm SiNx. In the blue region, the SiNx and part ofthe SiOx layers were etched, producing a sufficiently highstep to be detected in the SEM. In the greenish region,however, only the 50 nm SiNx layer was partly etched, whichis not being seen in the SEM due to the small heightdifference. Consequently, 450 nm SiOx are sufficient toachieve insulation of the wafer. The relation of the visiblydamaged insulation layer and the EBIC image permitsquality control on the basis of optical microscopy for furtherdevice development.

4.2 Charge carrier collection properties To sep-arate the charge carrier collection properties of a faultlessmembrane cell from the wafer, light beam induced current(LBIC) maps were recorded. In the LBIC map shown inFig. 7, a current of 1.2mA is seen in the center of the p–i–nmembrane. The current drops as the insulation layer (reddishin the optical micrograph) at the membrane margin isreached because here the charge carriers have to diffuselaterally within the SiC/Si-NC layer before reaching the a-SixC1�x:H(i,p) selective contact. Beyond the active cell are,no current is measured anymore.

4.3 Current–voltage characteristics The challengeof the presented device is to achieve proper electricalinsulation of the wafer to suppress any influence on themeasured quantities. Before further characterizing a cell, ithas to be shown unambiguously that the photovoltage andphotocurrent stem from the membrane itself but not from thewafer, i.e., by leakage through an insulation layer. Mostcritical are the slanted sidewall and the upper edge (Fig. 4)

Figure 6 (online color at: www.pss-a.com) Scanning electronmicrograph (a), electron beam induced current map (b) and opticalmicrograph (c) of the upper sidewall edge (see Fig. 7).

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because here the inkjet resist is less dense and the edge isexposed in a large solid angle to the etching solution.

To verify that the electrically measured quantitiesstem from the membrane cell but not from the wafer,current–voltage curves were measured under illuminationof individual devices parts using shadow masks asdescribed in Ref. [6]. Figure 8 shows the I–V curvesunder full area illumination (red squares), with a shadowmask on the peripheral wafer (red triangles), and witha shadow mask on the membrane (diamonds). With a

Figure 8 (online color at: www.pss-a.com)Current–voltage curveof the p–i–n membrane cell under illumination (sun simulator)whose LBIC map is shown in Fig. 7. An open-circuit voltage of176mV and a short-circuit current of 0.33mA cm�2 was measured.The active area of the cell (see Fig. 7) is 1mm2.



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shadowmask on the peripheral wafer parts of themembraneare shadowed as well. For this reason the photo currentis lower. When the membrane is shadowed, but the waferilluminated, no photo current is measured (black). There-fore, the wafer is properly insulated in this device. Thelight I–V curve exhibits a pronounced slope around 0V,indicating a strong shunt. Furthermore, the experimentallyshort circuit current is very low, compared to the opticallimit of around 5mA (see below). This is attributed torecombination in the Si NC layer [21]. The most likelyrecombination channel are grain boundaries between Siand SiC crystallites.

4.4 Optical modeling An analysis of the opticalproperties was carried out using the open source programOPTICAL [22], an implementation of a Fresnel coefficientapproach applied to multilayers which allows the simu-lations of composite materials approximated by an effectivemedium and arranged in any stack of coherent andincoherent layers. The Si NC/SiC layer was considered asa mixture of SiC (77%) and Si (23%), embedded in two SiClayers 10 nm thick, two a-SixC1�x selective contacts and twoITO layers. The layer implemented as selective contact onthe front side of the device (doped a-SixC1�x) absorbs in theshort wavelength region depending on its composition x.Consequently, the absorption of short wavelengths in the NClayer is limited by the top selective contact absorption, anddepends on x. The Si excess x in the top selective contact wasvaried in the simulation, and fixed in the rear selectivecontact to x¼ 0.95. In Fig. 9, we display the calculatedabsorption in the layer containing the Si NC, varying thestoichiometry of the a-SixC1�x selective contact layers withx¼ 0.5, 0.65, 0.75, and 0.95. It can be seen that for x¼ 0.95(the black curve in Fig. 9), considerable absorption of theUVphotons in the top selective contact occurs, interfering withthe nanocrystal absorption. It is possible to improve the UVabsorption by depositing top selective contacts with lowerSi/C ratio, as it is shown by the shift of the absorption

Figure 9 (online color at: www.pss-a.com) Optical modeling of aSi NC membrane pin cell with the structure shown in the inset. Thevarying parameter is the Si content x in the top selective contact.


maxima in Fig. 9 due to the different stoichiometry of thecontact layers.

By considering the absorption in the manufacturedstructure, i.e., the black curve in Fig. 9, themaximum currentunder AM1.5G illumination can be computed, assuming thatall the electron/hole pairs generated in the absorber contain-ing Si NCs are collected. The p–i–n membrane maximumcurrent would be 5.97mA cm�2, i.e., 17 times higher than theexperimental Jsc. This difference is attributed to chargecarrier recombination at the Si/SiC interfaces in the NClayer.

5 Summary Asolar cell test device has been presentedthat permits a photovoltaic analysis of Si NC layer fabricatedby high-temperature processes. Unlike other devices pre-sented so far, the measured quantities are directly related tothe Si NC layer, without being influenced by the wafersubstrate. The device is realized by locally removing thewafer substrate thus enabling full area rear side access to theSi NC layer. p–i–n structures with a SiC/Si NC(i) absorberand doped a-SixC1�x as selective electron and hole contactswere discussed. Open circuit voltages of 176mV and shortcircuit currents of 0.33mA cm�2 were achieved. The resultsunderline the need for further material optimization. Afterinvestigation has so far been focusing on controlling theoptical band gap, transport and recombination in the Si NCfilms have to be addressed to promote their implementationin solar cells.

Acknowledgements The authors would like to thank theircolleagues from the solar cell departments at Fraunhofer ISE. Weare especially grateful to Johannes Greulich, Elisabeth Schaffer,Karin Zimmermann, Dureid Qazzazie, and Rainer Neubauer fortheir support. The research leading to these results has receivedfunding from the European Community’s Seventh FrameworkProgramme (FP7/2007–2013) under grant agreement n-: 245977.P. Loper gratefully acknowledges the scholarship support fromthe Reiner Lemoine Stiftung, and the ideational support from theHeinrich Boll Stiftung.

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Silicon nanocrystals from high-temperature annealing: Characterization on device level

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