Neural-Network-Based Parasitic Modeling and Extraction Verificationfor RF/Millimeter-Wave Integrated Circuit Design

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This paper reports an interconnect modeling approach for RF and millimeter-wave integrated circuits (ICs) using

neural network models and a novel parasitic extraction verification procedure using automatically generated test

structures. The effects of the parasitics in RF/millimeter-wave ICs are investigated with special focus on the

parasitic inductances, since they are not evaluated by most of the commercially available extraction tools. State-

of-the-art silicon-based multilayer RF process parameters are utilized to extract the resistive, the capacitive, and

the inductive components of the layout interconnects. Neural network models are developed using electromagnetic (EM)

simulation results of a set of passive interconnect structures. In addition, an automated layout generation

methodology is used for the verification of the parasitic extraction methodologies. The proposed verification

approach is demonstrated using automatically generated passive test structures and ring oscillators. The effects of

parasitics are also investigated in voltage-controlled oscillators (VCOs) and amplifiers for millimeter-wave

applications, and the neural models are verified using 30-GHz VCO measurement results. Hence, we present a complete

modeling report of layout interconnect parasitics in RF/millimeter-wave integrated circuits as well as a novel

verification procedure to validate non-EM analytical or neural models.Sen, P.; Woods, W.H.; Sarkar, S.; Pratap,

R.J.; Dufrene, B.M.; Mukhopadhyay, R.; Lee, C.-H.; Mina, E.F.; Laskar, J.Microwave Theory and Techniques, IEEE

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2604 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 54, NO. 6, JUNE 2006

Neural-Network-Based Parasitic Modeling andExtraction Verification for RF/Millimeter-Wave

Integrated Circuit DesignPadmanava Sen, Student Member, IEEE, Wayne H. Woods, Member, IEEE, Saikat Sarkar, Student Member, IEEE,

Rana J. Pratap, Brian M. Dufrene, Member, IEEE, Rajarshi Mukhopadhyay, Student Member, IEEE,Chang-Ho Lee, Member, IEEE, Essam F. Mina, and Joy Laskar, Fellow, IEEE

Abstract—This paper reports an interconnect modeling ap-proach for RF and millimeter-wave integrated circuits (ICs) usingneural network models and a novel parasitic extraction verifica-tion procedure using automatically generated test structures. Theeffects of the parasitics in RF/millimeter-wave ICs are investigatedwith special focus on the parasitic inductances, since they are notevaluated by most of the commercially available extraction tools.State-of-the-art silicon-based multilayer RF process parametersare utilized to extract the resistive, the capacitive, and the inductivecomponents of the layout interconnects. Neural network modelsare developed using electromagnetic (EM) simulation results of aset of passive interconnect structures. In addition, an automatedlayout generation methodology is used for the verification of theparasitic extraction methodologies. The proposed verificationapproach is demonstrated using automatically generated passivetest structures and ring oscillators. The effects of parasitics arealso investigated in voltage-controlled oscillators (VCOs) and am-plifiers for millimeter-wave applications, and the neural modelsare verified using 30-GHz VCO measurement results. Hence,we present a complete modeling report of layout interconnectparasitics in RF/millimeter-wave integrated circuits as well asa novel verification procedure to validate non-EM analytical orneural models.

Index Terms—Neural network, parasitic extraction, parasitic in-ductances, tool verification.

I. INTRODUCTION

THE RAPID advancements in semiconductor technologyhave enabled the design of high-performance high-

frequency circuits/systems to meet the increasing demands ofthe present wireless communication industry. However, with theincrease of the frequency of operation of analog–mixed-signal

Manuscript received October 7, 2005; revised December 26, 2005. This workwas supported by the Georgia Institute of Technology through a cooperativeeffort between Georgia Electronic Design Center and IBM, Essex Junction, VT.

P. Sen, S. Sarkar, R. Mukhopadhyay, and J. Laskar are with the Georgia Elec-tronic Design Center, School of Electrical and Computer Engineering, GeorgiaInstitute of Technology, Atlanta, GA 30308 USA (e-mail: psen@ece.gatech.edu; saikat@ece.gatech.edu; raji@ece.gatech.edu; joy.laskar@ece.gatech.edu).

W. H. Woods, B. M. Dufrene, and E. F. Mina are with IBM Microelectronics,Essex Junction, VT 05452 USA (e-mail: whwoods@us.ibm.com; dufrene@us.ibm.com; mina@us.ibm.com).

R. J. Pratap was with the Georgia Institute of Technology, Atlanta, GA 30308USA. He is now with the Intel Corporation, Chandler, AZ 85226 USA (e-mail:rana@ece.gatech.edu).

C.-H. Lee is with the Samsung RFIC Design Center, Georgia Institute ofTechnology, Atlanta, GA 30308 USA (e-mail: chalee@ece.gatech.edu).

Digital Object Identifier 10.1109/TMTT.2006.872926

(AMS) as well as integrated RF/millimeter-wave circuits,the layout-interconnect parasitics need immediate attention.Accurate extraction and modeling of on-chip parasitics havebecome a very critical as well as important step in the wholedesign flow of on-chip realization of RF systems [1], [2].

There are several approaches to extract the parasitic RLC net-work and to include that in the circuit design. For the avail-able electromagnetic (EM) and non-EM solvers, the tradeoffparameters are the accuracy and the extraction time. EM tools(e.g., Momentum, HFSS, and IE3D) are accurate, but the ex-traction time is lengthy, and it is difficult to include the ex-tracted network in a circuit-level simulation environment. How-ever, non-EM solvers (e.g., Calibre XRC, Assura RCX, and StarRCXT) are popular for their fast execution time and easy ap-plication in the circuit-level simulations. Even now, there arevery few analytical-model-based parasitic inductance extractiontools, and they are much slower than their counterparts are. Theunwanted inductances play a very important role in the accuracyof designs for frequencies higher than 10 GHz.They also needto be considered for the design centering of the millimeter-wavebuilding blocks, e.g. oscillators and amplifiers. Neural-network-based methodologies have already been demonstrated to modelthe passives in ceramic and organic processes [3], [4]. In thispaper, the neural approach is applied to estimate the wire/in-terconnect parasitics for the RF integrated circuits in state-of-the-art Si-based IC processes. Modeling and verification areboth essential for a reliable circuit design approach. The accu-racy of tools based on non-EM solving methodology demandsa verification routine that has to be fast, automated, and sys-tematic. In this paper, the novel fast verification approach ispresented for commercially available parasitic extraction (PEX)tools.

Section II of this paper explains the effects of interconnectparasitics on RF/millimeter-wave circuits. The effects of in-ductive and capacitive components are demonstrated usingexamples of 30-GHz voltage-controlled oscillators (VCOs) and60-GHz power amplifier simulations. Section III describes theset of interconnect structures used in this study. These struc-tures expose the majority of layout scenarios. EM extractionsand neural-network-based modeling strategies are adopted topredict the capacitances as well as the inductances for differenttest structures with varying dimensions in a defined layoutenvironment. The developed models can estimate the capac-itive and the inductive effects accurately (1%–3% prediction

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SEN et al.: NEURAL-NETWORK-BASED PARASITIC MODELING AND EXTRACTION VERIFICATION FOR RF/MILLIMETER-WAVE IC DESIGN 2605

error depending on the complexity of structures as well as thetraining data size). Section IV describes a novel approach toverify non-EM parasitic extraction methodologies. Differentextraction tools are compared using an automated layout gen-eration method to create the set of passive structures as well asthe ring oscillator circuits. The proposed approach, which isused for automated layout generation, is illustrated using ringoscillators. Also, 30-GHz VCO measurement results verify themodeling procedure of layout interconnects developed in thisstudy.

II. EFFECTS OF PARASITICS ON

RF/MILLIMETER-WAVE CIRCUITS

In this section, the effects of parasitics in RF/millimeter-wavecircuits are explained, and the common methods of analyses aredescribed.

A. Interconnect Resistances

The interconnect resistances can significantly change circuitbehavior by changing the matching conditions as well as re-ducing the gain, but they also provide stability to the circuits.In state-of-the-art technologies, low-sheet-resistance aluminumor copper lines are used to decrease the interconnect resistances,but the reduced metal sizes in today’s technologies negate themetal resistance reduction. Convenient methodology for a metalline “resistance per length” extraction is given by the followingequation:

(1)

where is the sheet resistance of the metal line and isthe effective width of the line. is a function of the layoutdrawn width and corresponding electrical and physical bias di-mensions. The electrical bias is a technology parameter, andthe decreasing effect of the electrical bias is more significantfor lines with smaller widths. In most of the resistance extrac-tion methodologies, cheesing and fringing effects are consid-ered. The skin effects on the metallization thickness [5] can beestimated with the use of EM tools or a model developed fromEM analyses. The substrate resistance for lossy silicon substrateis another important parasitic component [6].

B. Interconnect Capacitances

Wire capacitances reduce the circuit operating frequency andaffect the design centering and optimization [7]. There are manynumerical methods available for interconnect capacitance ex-traction [8], e.g., the boundary element method and the randomwalk method. The boundary-element-method-based extractionis accurate but it is not suitable for large circuit extraction withunusually large grid requirement. The random-walk method [9]is used in commercially available capacitance extraction tools,e.g., QuickCap [10]. Field solvers based on the random-walkmethod may be efficient for large circuits; however, they takea very long execution time for the chip-level AMS/RF circuitextraction. This is why analytical models are used for very fastextraction times, sacrificing the accuracy for complex structures

Fig. 1. Schematic of the cross-coupled VCO.

[11]. When the tool is proficient, a divide-and-conquer algo-rithm [12] can be applied to extract the net capacitances. It isfor this reason that non-EM tools are generally based on ana-lytical models; the tools are fast but limited by complexity ofthe test structures [8]. In this study, neural network models areused as a faster and more accurate alternative to the analyticalmodels.

C. Inductances at RF/Microwave Frequencies

For RF/microwave applications, inductance has become animportant consideration in the design and analysis of on-chipinterconnects/parasitics [13]. In some topologies, parasitic in-ductances are also used to tune the circuit [14]. For example,a 50-pH inductance has a reactance value of 18 at 60 GHz,which needs to be addressed during circuit simulations. Com-plex mesh analyses [15] combined with different matrix for-mulations are now used to extract three-dimensional (3-D) in-ductances. Quasi-static simulations for inductance extractionsare fast [16], and they can obtain acceptable results in RF fre-quencies, but a foolproof numerical method-based EM simula-tion [17] can give accurate results at multigigahertz frequencies.In millimeter-wave applications, line inductances have becomevery important for their high and self-resonating frequency(SRF) values. This demands an accurate modeling of on-chipinterconnect inductances. In this study, EM-simulation-basedneural network models are developed, and self-inductances andmutual inductances are studied, varying the metal layers for dif-ferent layout structures.

D. Parasitic Extraction Examples for Millimeter-Wave Circuits

The effects of interconnect parasitics on a millimeter-wavecircuit are explained using a 30-GHz VCO. The schematic of thecross-coupled VCO designed on a SiGe-BICMOS technologyis shown in Fig. 1. The significant parasitics are identified asemitter inductances and collector capacitances from theinterconnects and , respectively. The effects of andon the center frequency are plotted in Fig. 2.

The effects of the layout parasitics are prominent in oscil-lators, but it cannot be neglected in other blocks of communi-cation systems, e.g., amplifiers and mixers at millimeter-wavefrequencies. The effects on the performances of a single-stage60-GHz SiGe amplifier are considered in Fig. 3 with differentparasitic extraction routines in different nodes. The effects of

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2606 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 54, NO. 6, JUNE 2006

(a) (b)

Fig. 2. Effects of: (a) parasitic capacitances and (b) parasitic inductances onthe 30-GHz VCO.

Fig. 3. Effects of parasitics on a power amplifier with different extraction rou-tines: (a) gain (S ) and (b) output matching (S ).

capacitances are found to be most significant for the matchingconditions, and the gain is significantly reduced for the layoutparasitics.

III. NEURAL NETWORK MODEL DEVELOPMENT

Here, we describe the application of neural networks to themodeling of parasitics for different interconnect structures.Neural networks have emerged as an attractive techniquefor modeling complex and nonlinear relationships [18]–[20].Neural networks have the capability to learn arbitrary nonlinearmapping between noisy sets of input (layout parameters) andoutput parameters (parasitic components).

A. Neural Network Structure and Training

The type of neural network used for modeling in this paper isthe multilayer perceptron (MLP) network consisting of three ormore layers, as shown in Fig. 4. The structure of the MLP is wellestablished, and this neural model has excellent generalizationcapability [21].

The network is typically trained using the error back-propa-gation (BP) algorithm with a sigmoidal activation function [20].The learning rate determines the speed of convergence by reg-ulating the size of the weight change [4]. The model-accuracyparameters as training and prediction errors [4] are evaluated interms of the rms error (RMSE).

In this study, an input dataset of 20–40 points are used totrain the neural networks in a wide range of width, length, andspacing, wherever applied. A Latin Hypercube Sampling [22]algorithm is used to choose the input dimensions for a better

Fig. 4. MLP neural network structure.

Fig. 5. Cross sections of the test structures for estimating capacitances.

modeling aspect, as the accuracy of the model is dependenton the small input dataset. The range of input data dependson the complexity of test structures and different metal layersused. The model is trained until the prediction error is less than3%–5% for randomly selected input parameters. The modelingerror for the dataset used in training is below 0.1%.

B. Modeling Capacitive Effects

The interconnect capacitances in a complex layout environ-ment can be determined by superposition of to-ground and cou-pling capacitances for simpler test structures, defined in a mul-tilayer process. One such set of test structure is shown in Fig. 5,assuming that the capacitance in only one layer.

The layouts as well as combinations of them in different metallayers can be used to estimate the required interconnect capaci-tances. A silicon-based seven-metal-layer RF process is definedin the EM solver for extraction and modeling purposes. Theprocess has five thin metal layers (i.e., 1M1, 1M2, 1M3, 1M4,and 1M5). The two thicker metal layers are defined as 2M1 and2M2 above the thin metal layers. The 2M1 metal layer is abovethe 1M5 layer. From Fig. 5, the bottom grounded metal layeris assumed to be 1M1 in structures (a), (c), (f), (g), (i), and (k).The signal metal layer chosen for analysis is either 1M2 (i.e., the

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TABLE IRANGES OF DIMENSIONS FOR DIFFERENT METAL LAYERS

TABLE IINEURAL NETWORK PARAMETERS FOR CAPACITANCE MODELING

metal layer just above 1M1) or 2M2 (i.e., the top metal layer).The layouts shown in Fig. 5 can account for fringing effects,different coupling effects, as well as substrate effects.

Neural-network-based models are developed to model the ca-pacitances for the selected test structures. A simple parallel-plate capacitance approximation is no longer valid for the case,when the metal thickness is comparable to the vertical distancefrom ground. Also, it is difficult to estimate nonscalable inter-connect capacitances using analytical models, which is why theneural network models are preferred to analytical models.

The equivalent capacitances are extracted from the simulatedY parameters [23]. To model capacitances in different layers,electrical design rules are satisfied. The ranges and number ofsamples are decided from the current carrying capacity and thereliability issues in layouts for the millimeter-wave transceivercircuits. The ranges of input parameters for different cases aresummarized in Table I.

The width, length, and spacing are of their usual meaningfor the interconnects as shown in Fig. 5. Two separate modelsare developed for different width ( )/length ( ) aspect ratioranges. Case I includes ratios from 0.25 to 4, whereascase II includes the case when ratios vary between0.03–0.5. Also, the number of training data required dependson the range of model as well as the complexity of EM effectsinvolved. For example, case I requires 20 training inputs toobtain a prediction error of less than 3%, whereas the sameaccuracy is achieved for case II using 30 training data points.Table II shows the properties of neural network models as wellas the prediction errors for these two cases. Another model isdeveloped to predict for the combined case where the aspectratio ranges from 0.03 to 4. Fig. 6 shows the capacitancesextracted from these models.

For the structure 5(a) and (b), a comparison is shown inFig. 7 for different metal layers 1M2 and 2M2 with and withoutthe 1M1 layer being grounded. Fig. 8 shows a comparison ofthe modeled equivalent one-port capacitances for the structuresshown in Fig. 5(b), (d), and (e), respectively, with the variationsof length and width in the metal layer 1M2. For the floatingor grounded layer above 1M2, 1M3 is chosen. For cases as

Fig. 6. Modeled capacitances for different aspect ratio cases using the struc-ture shown in Fig. 5(a) for 1M2 lines over 1M1 ground. (a) Separate cases.(b) Combined case.

shown in Fig. 5(g)–(l), neural network models are developedusing three input parameters. The to-ground self-capacitances

, coupling capacitances with varying width, andspacing for the fixed-length (30- m) 2M2 layer lines are shownin Fig. 9 for the structure shown in Fig. 5(g).

The neural-network-based models are compared with anEM-solver and an analytic model-based commercially avail-able layout extractor for randomly selected dimensions indifferent test layouts. The comparison results are summarizedin Table III. It shows that these models can predict the capaci-tances more accurately than analytical models.

As the neural network models are based on EM solver (e.g.,IE3D and HFSS) simulations, it is expected to give closer results.The percent difference of the analytic solver is more in the case of2M2 over 1M1 compared with 1M2 over 1M1 test cases. This isbecause the analytic solver, in general, is more accurate for closerground planes (better parallel plate approximation) but deviatesfrom the EM-solver for other cases. Also, the neural networkmodels, which are developed from only 30 simulation results,were found to be accurate for a large variation of input dimen-sions in the modeled range. To compare the computation time,

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2608 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 54, NO. 6, JUNE 2006

Fig. 7. Modeled capacitances for lines on 1M2 and 2M2 layers with andwithout 1M1 ground planes. (a) Capacitances with ground plane. (b) Capaci-tances without ground plane.

Fig. 8. Comparison of modeled capacitances with the variation of: (a) lengthwith 10-�m width and (b) width with a 30-�m length.

the neural network simulations of 30 test structures can be donein less than a minute on a 1-GB RAM Windows machine in con-trast to 1–2 h of computation in 3-D tools like HFSS.

C. Modeling Inductances

The same process parameters and modeling methods are usedto estimate the interconnect inductances. In most of the cases,2M2 (i.e., a 4- m-thick layer) is chosen for the inductance simu-lations, as thick metal lines are more inductive than thinner metal

Fig. 9. (a) Self-capacitances and (b) coupling capacitances for the structures inFig. 5(g) with 30-�m length in the 2M2 layer with the 1M1 layer grounded.

TABLE IIICOMPARISON OF CAPACITANCES USING DIFFERENT MODELS

Fig. 10. Test structures for inductance extractions.

lines. Different structures are considered as shown in Fig. 10. Thevariations of inductances for the structures given in Fig. 10(a)and (b) for the 2M2 layer with and without 1M1 being groundedare shown in Fig. 11. The inductances without the 1M1 groundplane are always larger than those with a ground plane.

The values of inductances change significantly with thechanges of metal layer and the layer thickness. Fig. 12 demon-strates the differences between the inductance values fordifferent metal layers without 1M1 grounding with the same di-mensions. The strength of such a neural-network-based modellies in the fact that it can find the dimensions for required valuesof inductances [20]. The length-versus-width variation for ex-tracting the same values of inductances (i.e., 2% tolerances)for the case shown in Fig. 10(a) is shown in Fig. 13.

The mutual inductances between close interconnects are alsomodeled using neural networks. The inductances are extractedfrom EM simulations using the methodology described in [24].The modeled mutual inductance variation with length andspacing for 4- m-wide lines are shown in Fig. 14.

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Fig. 11. Self-inductance variation for 2M2 lines with and without the 1M1ground plane.

Fig. 12. Inductance variation with 1M1 ground in different layers for:(a) length = 30 �m and (b) width = 7 �m.

Fig. 13. Self-inductance contours for 2M2 lines on the 1M1 ground plane.

Once trained, the neural network models give a very goodmatch with EM results for all width and length combinationsin the modeled range. The inductances for “2M2 over 1M1”lines are extracted and compared to HFSS (full 3-D solver), atwo-and-one-half-dimensional (2.5-D) EM tool, a semianalyticmodel ( provided by design kit), and an empirical model [25] inTable IV. The neural network results are quite comparable to the3-D simulations in HFSS whereas the deviation with empiricalmodels increases with changing aspect ratios.

Fig. 14. Mutual inductance variation for 2M2 lines with and without the 1M1ground plane.

TABLE IVCOMPARISON OF INDUCTANCES USING DIFFERENT MODELS

Fig. 15. Variation of resistances with dimensions for 2M2 lines.

D. Modeling the Resistances

The interconnect/wire resistances can be modeled using sim-pler models with corrections for fringing, skin, and cheesing ef-fects. However, to develop a systematic automated parasitic ex-traction tool, resistances need to be modeled using neural net-works. The modeled resistance variation of a 1M2 line is shownin Fig. 15. The quality factor can be extracted using modelsdeveloped for the resistances and the inductances for the samestructures. The variation of the quality factor is shown in Fig. 16with 2M2 lines over 1M1 ground planes.

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2610 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 54, NO. 6, JUNE 2006

Fig. 16. Quality factor variation for 2M2 lines.

Fig. 17. Effects of interconnect dimensions on the 30-GHz VCO: (a) with thedimensions of I and (b) with the dimensions of I .

E. Selection of Layout Interconnects inRF/Millimeter-Wave Circuits

The selection of metal layers for interconnects in RF/mil-limeter-wave circuit layouts demands a sensitivity analysis ofdesigns for the node capacitances/inductances. In general, topmetal layers are used for high current carrying capacity, lessto-ground one-port capacitances, and when the inductances oflines do not affect the results significantly. On the other hand,thin metal layers close to the ground plane may have less induc-tive effects, but the parasitic capacitances and resistances mayprove to be critical for the circuit design. The resistances and in-ductances are significant for the via structures in the layout. Theelectrical characteristics of the via cells need to be estimatedusing EM solvers, and parallel via blocks can reduce their ef-fects on circuit performances.

Fig. 17 shows the shifts in center frequencies with the dimen-sions of lines and on the VCO shown in Fig. 1. Intercon-nect block is assumed to be on the 1M2 layer, and the in-terconnect block is assumed to be on the 2M2 metal layers.The center frequencies shift up to 3 GHz for interconnect block

, and, for inductive block , the maximum shift in the givenrange is 1.16 GHz (for a 4- m width and 40- m length line).The effects will add up in the presence of the interconnects, asboth of them reduce the center frequency.

Fig. 18. Cross section of the multilayer passive structures.

Fig. 19. Example of the meander line structures (top metal with 1M1 ground).

IV. VERIFICATION OF PARASITIC EXTRACTION TOOLS

The first step for studying the effects of parasitics on devices,circuits, and systems is to standardize the parasitic extractiontools. In this study, a verification methodology has been de-veloped using commercially available parasitic extraction tools,and the approach is proposed for neural network-based models.

A. Verification Using Passive Structures

A set of multilayer passive structures can be used to verify thetools. Cross sections of one such set is shown in Fig. 18. As aset of simple passive structures is used to account for modelingthe parasitics, complex structures need to be used to verify themodeling concept.

For the same silicon-based RF process, these passive struc-tures are laid out in a meander line topology (shown in Fig. 19),and one set of capacitance comparison resulting from EM andnon-EM tools are summarized in Table V for the structures de-scribed in Table VI. The poly-silicon (poly) layers are includedas ground planes to estimate gate parasitics, which are veryimportant in the estimation of the layout parasitics in CMOSprocesses.

The test cases T1–T10 in Table V are meander-line structuresin different metal layers with repetitive layouts. It is evident thatthe extractions of the non-EM simulation tools A–E give dif-ferent values for the same structures and the coherency with EMtools depends on the complexity and topology of the test struc-tures. For example, the structure T6 is designed to include theedge coupling effects, which are considered in tools like C, D,and E. But tool A overestimates the edge coupling whereas toolB cannot estimate the same effect. That proves the insufficiency

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TABLE VCOMPARISON OF CAPACITANCES FOR ONE SET OF STRUCTURES

TABLE VIDESCRIPTION OF THE SAME SET OF STRUCTURES

of the analytical models developed from test structures. In addi-tion, the analytical models cannot estimate all of the complex ef-fects that are included in EM solvers or a neural-network-basedmethodology.

B. Automated Generation of Layouts

As both the modeling of passive structures and the verifi-cation of PEX tools involve generation of many test-structurelayouts, it will be time-consuming if an automated layout-generation methodology is not developed. Hence, a layout-generation methodology is built using MATLAB codes/Perlscripts. The block diagram represents the methodology asshown in Fig. 20. This method is useful for the generation ofinput passive structures for neural network modeling as well asrepetitive test structures (shown in Fig. 18) used to verify theparasitic extraction tools.

The methodology is very fast, and a set of 20 structurescan be generated within 1 h depending on the complexity ofthe layout. In MATLAB, codes are written with the use of Perlscripts, which in turn can be executed to produce layouts in

Fig. 20. Automated layout-generation methodology.

GDSII stream formats. All codes for layout generation consistof two basic blocks. The first is the input section, where theinputs for the layout generation, such as the technology speci-fications, the design inputs, and the interconnect topologies areincluded. The ground rules for layouts are also incorporatedinto the technology-specified file. Thus, choosing a differenttechnology file, the layer information and ground rules can bemodified automatically. Test structure topology includes defi-nition of the signal layers and the ground planes as well as thedimensions that are back calculated from required delay. Thesecond is the execution section, where functions are executedaccording to the rectangular coordinates defining the blocks indifferent metal layers. A set of structures is generated includingdifferent functions representing several topologies in the samecode and defining the required dimensions. Feeding the inputdimensions from the LHS algorithm to the layout generatorcode can also generate the test structure layouts, which arerequired for generating the neural network model.

The application of the automated generation technique is il-lustrated using ring oscillators as an example of functional cir-cuits. Ring oscillators have been already used for technologybenchmarking [26]. In this paper, it is used as an example of ac-tive circuit, though the parasitic structures used as delay cells inbetween inverter stages can only verify the resistances and ca-pacitance extraction methodology. The main program that gen-erates the ring oscillator structures calls upon different functionsto create the inverter cells, the delay cells for the given numberof inverters in the oscillator, the delay required, and the spacegiven [27]. The connections to the rails are made symmetrically,and the pins are placed using proper metal layers. Any advancedparasitic extraction tool can be used for the parasitic extractionof the ring oscillators if the layout-versus-schematic (LVS) ex-traction and device recognitions are performed correctly. Theextraction procedure is made as automated as possible to reducethe complexity in the MATLAB code. The parasitic extractiontools can generate the net-list in HSpice and/or Spectre format.Spectre is used in most of the examples shown. As the final stepof the automated testing, the simulator outputs are plotted fordifferent decks/tools. The outputs can be plotted in the same

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2612 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 54, NO. 6, JUNE 2006

Fig. 21. Simulated output for one ring oscillator for three different parasiticextraction test decks (i.e., nominal, best case, and worst case).

graph and can be visually compared with each other as well aswith the “gold standard” output.

The output waveforms for three different statistical variations(i.e., best case, nominal, and worst case) are shown in Fig. 21 inthe case of a ring oscillator using a CMOS 90-nm process. Thisgives another dimension to the verification methodology by vi-sually comparing the extraction results. The verification proce-dure is quick using an automated approach and does not use anygraphical interface. For example, the basic flow of layout gener-ation, extraction, and output plotting takes less than 10 min fora conventional ring oscillator in a 1-GB RAM 900-MHz dualprocessor.

C. Application to AMS/RF/Millimeter-Wave Circuit Design

The automated layout-generation procedure has been used tostudy the effects of fillers and the different dielectric definitionsfor the wire parasitics. It can also be used for comparing func-tional circuits [27] with varying different process parameters,e.g., layer options and several dielectric stack representations.The fast layout-generation capability enables fast test-site de-velopment and modeling of active as well as passive structures.

As an example of the millimeter-wave integrated circuits,which is a cross-coupled VCO (see Fig. 1), is laid out in astate-of-the-art SiGe-BiCMOS process. The significant para-sitics are extracted and modeled using the developed neuralnetwork models. The design is also optimized using sensitivityanalysis from neural network models for the circuits. Thecross-coupled core layout with the parasitic matrix is shownin Fig. 22(a). Measurements show excellent match with thefinal optimized results. The VCO simulated without parasiticextraction shows a simulated frequency range of 37–40.5 GHz,where as the simulation with neural models of parasiticsgives 30–32.5 GHz. The measurement results show a centerfrequency of 30.1 GHz with a tuning range of 2.3 GHz. Themaximum power measured at the buffer output was around

11.7 dBm at 29.54 GHz. The die photograph of the fabricatedIC is shown in Fig. 22(b).

Hence, the cross-coupled VCOs have the capability to verifythe inductance and capacitance extraction for very high frequen-

Fig. 22. (a) Layout of the cross-coupled core with the parasitic elements.(b) Die photograph of the VCO.

cies, as ring oscillators can only account for the resistive andcapacitances for AMS designs. The tuning inductancecan be varied using the automated layout-generation procedure,and corresponding measurement frequencies will verify the in-ductance extraction procedure. The design optimization, layoutgeneration, and the parasitic extraction methodology being inthe same (MATLAB) environment demonstrate a novel systemicdesign optimization procedure for millimeter-wave frequencies,including parasitic effects.

V. CONCLUSION

This paper reports a parasitic extraction methodology for RFand millimeter-wave circuits using neural network models and anovel verification procedure using automatically generated teststructures. The effects of the parasitics in RF/millimeter-wavecircuits have been investigated with specific focus on theparasitic inductances, which are not evaluated in most of thecommercially available extraction tools. The importance ofparasitic inductance extraction is explained using an exampleof VCOs. State-of-the-art silicon-based multilayer RF processparameters are utilized to extract the resistive, capacitive,and inductive parasitics of the layout interconnects. Neuralnetwork models are developed using EM simulation results ofa given set of passive interconnect structures. In addition, anautomated layout generation methodology is developed usingMATLAB codes/Perl scripts and used for verification of theparasitic extraction methodologies. The proposed verificationapproach is demonstrated using automatically generated pas-sive test structures and ring oscillators. Also, the measurementresults of the 30-GHz VCO verify the modeling procedure oflayout interconnects developed in this study. In the verificationmethodologies, EM tool extraction results are taken as the“gold standard.” This paper addresses the need for an auto-mated layout-generation technique and an accurate extractionprocedure using neural network models to avoid the long EMsimulation run time. The neural network modeling techniqueand the automated verification procedure can significantlyimprove the extraction–verification time and the accuracy for

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SEN et al.: NEURAL-NETWORK-BASED PARASITIC MODELING AND EXTRACTION VERIFICATION FOR RF/MILLIMETER-WAVE IC DESIGN 2613

RF/microwave as well as AMS/digital applications. Hence, wepresent a complete modeling report of parasitic components inRF/millimeter-wave layouts, as well as a novel verification pro-cedure to validate non-EM analytical or neural-network-basedmodels.

ACKNOWLEDGMENT

The authors would like to acknowledge R. Singh,C. E. Zemke, H. Ding, W. Piper, S. Pinel, and J. D. Cressler fortheir help with this work. The authors would also like to thankall members of the IBM SiGe team for the cooperative effortbetween IBM Corporation, Essex Junction, VT, and the GeorgiaInstitute of technology, Atlanta. The authors would also liketo thank Motorola Corporation and Jazz Semiconductor forproviding design kits and fabrication support.

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[27] P. Sen, W. H. Woods, E. Mina, and J. Laskar, “Parasitic extraction toolverification of an automatically generated set of ring oscillators,” inProc. Eur. Microw. Conf., Paris, France, Oct. 2005, pp. 577–580.

Padmanava Sen (S’04) received the B.Tech. de-gree in electronics and electrical communicationengineering from the Indian Institute of Technology,Kharagpur, India, in 2003, the M.S. degree fromthe Georgia Institute of Technology (Georgia Tech),Atlanta, in 2005, and is currently working towardthe Ph.D. degree at Georgia Tech.

He was with IBM Corporation, Burlington, VT, forseven months in 2004. He is a member of the Mi-crowave Applications Group, Georgia Electronic De-sign Center, Georgia Tech. He has authored or coau-

thored over ten IEEE journal and conference papers. His research interests in-clude analysis and development of millimeter-wave silicon-based transmittersas well as the estimation and optimization of the layout parasitics in millimeter-wave circuits.

Wayne H. Woods (M’03) received the M.Eng. and Ph.D. degrees in electricalengineering from Cornell University, Ithaca, NY, in 1998 and 2003, respectively.

He is currently with IBM Microelectronics, Essex Junction, VT, where heis involved with the modeling of high-frequency on-chip passive devices andparasitic extraction methodologies for high-density digital designs.

Saikat Sarkar (S’04) was born in Asansol, India.He received the B.Tech. degree in electronics andelectrical communication engineering from theIndian Institute of Technology, Kharagpur, India,in 2003, the M.S. degree from the Georgia Instituteof Technology (Georgia Tech), Atlanta, in 2005,and is currently working toward the Ph.D. degree atGeorgia Tech.

He was with Intel Corporation, Hillsboro, OR, asa summer intern in 2004. He is currently a memberof the Microwave Applications Group, Georgia Elec-

tronic Design Center, Georgia Tech. He has authored or coauthored over 15journal and conference papers. His research interests include analysis and de-velopment of millimeter-wave front-end silicon-based integrated circuits forhigh-data-rate wireless applications and passive components development formillimeter-wave front-end system-on-package modules.

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2614 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 54, NO. 6, JUNE 2006

Rana J. Pratap received the B.Tech. degree in elec-trical engineering from the Institute of Technology,Varanasi, India, in 2001, and the M.S. and Ph.D. de-grees in electrical and computer engineering from theGeorgia Institute of Technology, Atlanta, in 2003 and2005, respectively. His doctoral dissertation was ti-tled “Design and optimization of microwave circuitsand systems using artificial intelligence techniques.”

Currently, he is a Test Engineer with the Intel Cor-poration, Chandler, AZ, where he is involved withdeveloping new test methodologies for microproces-

sors. He is specifically involved in test board design and signal integrity. Duringthe summer of 2004, he was an intern with the Integrated Signaling TechnologyGroup, Broadcom Corporation. His research interests include modeling and op-timization of multilayer RF packaging structures using neural networks and ge-netic algorithms. He is also involved in yield modeling and design centering ofmicrowave circuits and devices using artificial intelligence techniques.

Brian M. Dufrene (M’99) received the B.S. andM.S. degrees in electrical engineering from Missis-sippi State University, Mississippi State, in 2000 and2002, respectively.

His graduate research included silicon-on-in-sulator (SOI) device modeling, flicker noisecharacterization, and mixed-signal circuit design.In 2004, he joined IBM Microelectronics, EssexJunction, VT, where he has been active in developingSOI compact models.

Rajarshi Mukhopadhyay (S’02) received theB.Tech. degree (with honors) in electronics andelectrical communication engineering from theIndian Institute of Technology, Kharagpur, India, in2002, the M.S. degree in electrical and computer en-gineering from the Georgia Institute of Technology(Georgia Tech), Atlanta, in 2004, and is currentlyworking toward the Ph.D. degree at Georgia Tech.

He is with the Microwave Applications Group,Georgia Electronic Design Center, Georgia Tech.His research interests include wideband, low-power

RFIC and MMIC transceiver design, high-frequency and broadband signalgeneration for multistandard radios, clock synchronization, and deskewingtechniques. He has authored and coauthored over 20 technical journal papersand conference publications and has three patents pending.

Mr. Mukhopadhyay was a 2004 recipient of the IEEE Microwave Theory andTechniques Society (IEEE MTT-S) International Microwave Symposium (IMS)Third Best Student Paper Award.

Chang-Ho Lee (M’01) received the B.S. and M.S.degrees in electrical engineering from Korea Univer-sity, Seoul, Korea, in 1989 and 1991, respectively,and the M.S. and Ph.D. degrees in electrical and com-puter engineering from the Georgia Institute of Tech-nology (Georgia Tech), Atlanta, in 1999 and 2001,respectively.

He was a Research Engineer with Dacom Corpora-tion, Korea, from 1994 to 1996. In 2000, he joined RFSolutions Inc., Norcross, GA, where he was a StaffEngineer. In 2003, he became a member of the Re-

search Faculty of the Samsung RFIC Design Center, Georgia Tech. His re-search interest includes satellite/wireless communication system design and de-sign/characterization of the transceiver RFICs in GaAs devices and Si-basedCMOS/SiGe HBT processes, as well as LTCC/MLO-based multilayer multichip

modules development for wireless communication applications. His current re-search is related to the low power reconfigurable front-ends design for cognitiveradio applications.

Essam F. Mina received the B.S. degree in electricalengineering from Ain Shams University, Cairo,Egypt, in 1964, and the M.S. degree in solid-statescience from the American University, Cairo, in1977.

Prior to joining IBM in 1981, he was the Di-rector for the Center of Broadcast Transmission,the Radio and TV Federation of Egypt. He is cur-rently the RF and Signal Integrity Manager at IBMMicroelectronics. His responsibilities included thedevelopment of radio and TV broadcast transmission

systems, antenna design, microwave system design, and the management ofthe transmission center operations and personnel. In 1981, he joined the IBMTechnology and Systems Division, Poughkeepsie, NY, where he was involvedwith interconnect high-frequency modeling, signal integrity, and noise analysis.In 1994, he joined IBM Microelectronics, Essex Junction, VT, where he isinvolved with IBM BiCMOS, SiGe, and RFCMOS technology development,RF passive modeling, RF circuit and system designs for cellular handsets,wireless local area networks, and direct broadcast satellite applications.

Joy Laskar (S’84–M’85–SM’02–F’05) received theB.S. degree (highest honors) in computer engineeringwith math/physics minors from Clemson University,Clemson, SC, in 1985, and the M.S. and Ph.D. de-grees in electrical engineering from the Universityof Illinois at Urbana-Champaign, in 1989 and 1991,respectively.

Prior to joining the Georgia Institute of Tech-nology, Atlanta, in 1995, he held faculty positionswith the University of Illinois at Urbana-Champaignand the University of Hawaii. At the Georgia Insti-

tute of Technology, he holds the Joseph M. Pettit Professorship of Electronicsand is currently the Chair for the Electronic Design and Applications TechnicalInterest Group and the Director of the Georgia Electronic Design Center. Withthe Georgia Institute of Technology, he heads a research group of 25 memberswith a focus on integration of high-frequency electronics with optoelectronicsand integration of mixed technologies for next-generation wireless and opto-electronic systems. He has authored or coauthored over 200 papers and severalbook chapters (including three textbooks in development). He has more than 20patents pending. His research has focused on high-frequency integrated-circuit(IC) design and their integration. His research has produced numerous patentsand transfer of technology to industry. Most recently, his research has resultedin the formation of two companies. In 1998, he cofounded the advanced wire-less local area network (WLAN) IC company RF Solutions, which is now partof Anadigics. In 2001, he cofounded the next-generation interconnect companyQuellan Inc., Atlanta, GA, which develops collaborative signal-processingsolutions for enterprise applications, video, storage, and wireless markets.

Dr. Laskar has presented numerous invited talks. For the 2004–2006 term,he has been appointed an IEEE Distinguished Microwave Lecturer for his Re-cent Advances in High Performance Communication Modules and Circuits sem-inar. He was a recipient of the 1995 Army Research Office’s Young Investi-gator Award, 1996 recipient of the National Science Foundation (NSF) CA-REER Award, 1997 NSF Packaging Research Center Faculty of the Year, 1998NSF Packaging Research Center Educator of the Year, 1999 corecipient of theIEEE Rappaport Award (Best IEEE Electron Devices Society journal paper), thefaculty advisor for the 2000 IEEE Microwave Theory and Techniques Society(IEEE MTT-S) International Microwave Symposium (IMS) Best Student PaperAward, 2001 Georgia Institute of Technology Faculty Graduate Student Mentorof the Year, a 2002 IBM Faculty Award, 2003 Clemson University College ofEngineering Outstanding Young Alumni Award, and 2003 Outstanding YoungEngineer of the IEEE MTT-S.

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