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PA01 The 10-b 100kS/s Dual Bypass Window SAR ADC for Physiology Signal Detection Ren-Yong Hung, Po-Quan Hsieh, Ting-Han Hsu, Sheng-Yu Peng National Taiwan University of Science and Technology

Abstract—This paper proposes a dual bypass-switching successive approximation(DBSSA) register ADC, which is suitable for physiological signal detection, the bypass windows are implemented with dynamic proximity comparator(DPC), DBSSA logic, and sub-DAC, which can sense more kinds of signals, and maintain low power consumption. The 10-bit 100KS/s SAR ADC was fabricated using TSMC 180 nm CMOS process. With a supply voltage of 0.6 V and the Effective Number of Bits (ENOB) is 8.7461-bit, the measured signal-to-noise-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 54.41 and 60.36 dB. The ADC consumes power is 368.089 nW. The figure of merit (FOM) is around 7.67812 fJ/conversion-step and the ADC chip core area is 282.46 µm x 412 µ m.

PA02 A New Improved-V-Squared-Controlled Buck Converter with New-Current-Sensing Techniques Bo-Shan Li, Yuh-Shyan Hwang Department of Electronic Engineering, National Taipei University of Technology,

This paper presents a new improved-V-squared-controlled buck converter with new-current-sensing techniques. The proposed converter achieves fast transient response with new current-sensing and V-squared-controlled techniques. The proposed converter is fabricated with TSMC 0.35𝜇m 2P4M processes. The output load current range is 100~800mA. The load transient response times are about 2.6 𝜇s and 2.1 𝜇s when the load currents are light to heavy and heavy to light, respectively. The total area of the chip is 1.5mm × 1.5 mm. The max power efficiency is 90.8%.

PA03 A 2nd-Order Delta-Sigma-Modulation Buck Converter with Transient-Accelerated-Circuits Hung-Jr Liu, Jiann-Jong Chen Department of Electronic Engineering, National Taipei University of Technology

This paper presented a continuous-time delta-sigma-modulation (CT-DSM) current-mode controlled buck converter with transient-accelerated-circuits (TAC) that features an

integral loop filter with a superiority of oversampling and noise shaping for effective spurious-noise reduction. In addition, the TAC use DCR current-sensing circuit and hysteresis-voltage-controlled (HVC) circuit to speed up the transient response. Then, the proposed buck converter preserves a low spurious noise and fast transient response. The proposed buck converter is fabricated in TSMC 0.18um 1P6M CMOS processes with a chip area of 1.19mm × 1.05mm. The simulation results show that the transient recovery time with TAC is 2.7µs which is 3µs faster than the recovery time without TAC and the undershoot and overshoot voltage is 35mV when the load current changes from 50mA to 500mA and from 500mA to 50mA. The output spectrum with signal to noise ratio is 71dB was obtained across all sampling frequencies. The peak power efficiency is 91.8%, when the load current is 200mA and output voltage is 2.5V.

PA04 A Fast-Transient Response Hysteretic-Controlled Buck Converter with New Current-Sensing Techniques Szu-Hsien Ho, Jiann-Jong Chen Department of Electronic Engineering, National Taipei University of Technology

This paper presented a fast-transient-response hysteretic-controlled buck converter with new current-sensing techniques. This circuit control uses hysteretic control to reduce transient response time and use a new current sensing circuit to improve overall performance. The proposed converter is fabricated with TSMC 0.35𝜇m 2P4M processes. The experimental results show that the maximum efficiency is 91%, when the load current is 200mA and output voltage is 2.5V. The load transient response time is about 2.6𝜇s and 3𝜇s when the load current changes from 50mA to 500mA and from 500mA to 50mA, respectively.

PA05 A Fast-Transient-Response Delta-Sigma-Modulator Buck Converter With Hysteresis-Voltage-Controlled Techniques Tz-Shiuan Tzeng, Jiann-Jong Chen Department of Electronic Engineering, National Taipei University of Technology

A Fast-Transient-Response Second-Order Delta-Sigma-Modulator buck converter with hysteresis-voltage-controlled techniques is proposed. With the proposed control approach, the transient time can be accelerated by roughly 40%. The rail-to-rail OTA generates a current Isense, which replicates the inductor current IL with K times. As Isense flows through the capacitor Csense, it will be converted into Vsense. Then, HVC circuits compares the two terminal voltages of hysteresis comparator to detect the overshoot and undershoot of Vsense. Once Vsense. is detected, the output signal of HVC circuits becomes oppositive to the previous state to conduct MP and MN previously. Besides,Second-Order DSM plays a vital role of mitigating noise-interference and elevating SNR in whole circuits. The proposed converter has been fabricated in TSMC

0.18µm 1P6M CMOS processes with an active area of 1.26mm^2. The post-simulation results show the transient time are 4.2µs and 3.2µs, respectively, when the load current changes between 500mA and 50mA. The peak conversion efficiency is 91.8% while the load current is 300mA.

PA06 An Improved-Hysteresis-Current-Controlled Buck Converter with New Current-Sensing Techniques Shin-Yi Dai, Yuh-Shyan Hwang Department of Electronic Engineering, National Taipei University of Technology

This paper presented an improved-hysteresis-current-controlled buck converter with new current-sensing techniques. This circuit control used hysteresis-current control to achieve fast transient response and use a new current sensing circuit to reduce power consumption and increase the overall system performance. The proposed converter was fabricated with TSMC 0.35𝜇m 2P4M processes. The chip area is 1.5mm×1.5mm. The measured results show the transient response are 2.8µs and 2.5µs when the load current changes from 100mA to 500mA and 500mA to 100mA, respectively. The peak efficiency is 91.6% when the output voltage is 2.5V and the load current is 200mA.

PA07 A Fully Differential Low-Noise Biopotential Sensing Amplifier With Gate-Balanced Pseudo-Resistor Yun-Jie Huang, Yuan-Chuan Wang, Zu-Jia Lo, Sheng-Yu Peng National Taiwan University of Science and Technology

A fully reconfigurable biopotential sensing amplifier utilizing gate-balance pseudo-resistor is presented in this paper. By using the complementary differential pairs, the theoretical limit for the noise efficiency factor of the proposed amplifier is below 2. The equivalent high impedance of pseudo-resistance can be used to set ultra low-frequency corner. A concept proving prototype chip was designed in a 0.18 um CMOS process. With a supply voltage of 1.8 V, the simulated mid-band gain can be select from 40 dB and 50 dB, and input-referred noise is 3.4 and 2.28, and noise efficiency factor (NEF) in these gain settings are 1.58 and 1.8. The simulated common-mode rejection and the supply rejection are above 60 dB.

PA08 An Analog Programmable Multidimensional Radial Basis Function Based Classifier with Programmable Floating-Gate Bump Circuit Ting-Lu Lin,Tzu-Hao Li,Yi-Heng Wu,Sheng-Yu Peng National Taiwan University of Science and Technology

In this paper,propose a new programmable bump circuit of compact analog programmable multidimensional radial basis function (RBF)-based classifier is demonstrated.The probability distribution of each feature in the template is modeled by a Gaussian function, which is realized by the bell-shaped transfer characteristic of the proposed floating gate circuit (we call it a floating gate bump circuit). An array of these circuits constitute a compact multidimensional RBF-based classifier that can easily implement a Gaussian mixture model.With a following WTA circuit, the resultant analog vector quantizer can be applied to nonuniform, as well as uniform, variance scenarios.Use the operating characteristic curve and equal bit error rate to evaluate the performance of the RBFbased classifier and the resulting analog vector quantizer. The proposed method is more energy efficient than the previous digital microprocessor.

PA09 A Resistor-Less High-Precision CMOS Bandgap Voltage Reference Jia-Fong Shih, Yu-Hsiang Wang, and Yung-Hui Chung Department of Electronic and Computer Engineering, National Taiwan University of Science and Technology

This paper presents a resistor-less high-precision CMOS bandgap voltage reference (BGR). To meet the high-precision request, a high-order curvature compensation is applied to correct higher-order nonlinear temperature terms of the emitter-base voltage (VEB). With this nonlinearity correction method, the CTAT voltage VEB can be better linearized over a wide temperature range. Without using resistors, the offset voltage of the BGR output buffer is applied to yield the PTAT voltage. Using the proportional weighted sum of negative temperature coefficient (TC) on VEB and positive TC on VOS, a highly stable bandgap voltage reference can be achieved. The proposed BGR is implemented in 0.18-μm CMOS technology. The active area of the prototype BGR is 300μm×440μm. A minimum TC of 2.5ppm/°C is achieved over a temperature range from −40°C to 85°C. The maximum total current is 26 μA over the supply voltage ranging from 1.6V to 2V. The BGR output is about 996mV with the power supply noise attenuation of −50dB.

PA10 Wearable Wireless Armband Sensor for Ultra-Low Power Consumption System Yi-Da Wu, Shanq-Jang Ruan Department of Electronic and Computer Engineering, National Taiwan University of Science and Technology

The purpose of this study is to implement an ultra-low-power surface EMG acquisition system for measurement. We explore the most power-efficient design solution in an analog circuit. This work uses a Bluetooth Low Energy (BLE) module with System-on-Chip (SoC) in a digital system, appropriately modulate the CPU clock rate, and with an energy-saving method based on a ping-pong buffer mechanism. Finally, the results are displayed after infinite impulse response filter (IIR filter) on cell phone. The results show that the average current of the proposed architecture can be reduced by 92.46% compared to the previous work. In addition, the battery life is 5.66 times longer than the previous operation under continuous wireless connection with the same 300mAh lithium battery.

PA11 A High-performance FPGA Digital-to-Time Converter based on PLL Delay Matrix and Fine-Phase Shift Control Joshua Adiel Wijaya, Poki Chen, Ruei-Ting Wang Department of Electronic and Computer Engineering, National Taiwan University of Science and Technology

Digital-to-Time Converter (DTC), or delay timing generator, has been developed for quite many years for the increasing demand of Internet-of-Things (IoT) and environmental sensors. In the industry, the DTC plays a crucial role in Automatic Test Equipment (ATE) and Built-In Self-Test (BIST) technology. However, formal studies on the DTC design are rarely reported. This study proposes a precise phase division DTC based on phase-locked loop (PLL) delay matrix to further extend FPGA applications into the analog domain. All delay cells in delay matrix are precisely controlled by PLLs so that output phases are uniformly distributed within reference clock period. For concept proof, the proposed DTC based PLL delay matrix is implemented on an Altera Stratix-IV FPGA chip to achieve the resolution up to 5.2ps, while having a low differential nonlinearity (DNL), integral nonlinearity (INL), and high jitter performance of -2.3 to 2.4 LSB, -1.8 to 1.8 LSB, and 2.3 LSB, respectively. Our proposed DTC substantially benefit the development of ATE and BIST.

PA12 Modified Magnitude Detected Converter with Latched-Type Comparator Hsin-Liang Chen1, Yu-Chun Chiu1, and J. S. Chiang2

1Electrical Engineering, Chinese Culture University 2Electrical Engineering, Tamkang University

A magnitude detected converter (MDC) using a low noise two-stage latch-type comparator to replacing the conventional opamp based comparator is proposed. By employing the latch-type comparator and rearranging the decision control circuits, the PVT dependent timing error can be relieved. Besides, the power efficiency can be improved within the low and high speed operations of the MDC. A prototype of 10-bit MDC is designed to operate at 0.04 / 50 MHz with only 36.5 / 210 μW of power dissipations, respectively.

PA13 Low Voltage, Low Process Sensitivity LVDS RX Front-End Tzu-Hao Lin, Hung-Wen Lin Department of Electrical Engineering, Yuan Ze University

Data rate and power efficiency are the key requirements for serial link system. This paper proposes a inverter-based front-end amplification circuit to improve the data rate and power efficiency. A level shifter was inserted to typical inverter to achieve low supply-voltage but high speed operations. The eye diagram of Low voltage I/O was very sensitive to supply voltage and process variation, so the output levels and bandwidth control circuitry were adopted to compensate the performance variation. This paper proposes a common-mode feedback (CMFB) circuit and a differential-mode feedback (DMFB) circuit which provide a bias level above the supply voltage, to maximize the control range while maintain the bandwidth. The proposed front-end was verified in 90nm COMS process under single 0.5V supply voltage, and the simulation results show that the data rate achieve 10Gbps and total current consumption was 5.38mA. With CMFB and DMFB, the amplification circuit provides a 10dB of minimum gain and a 20dB of gain dynamic range.

PA14 A CMOS-MEMS Pressure Sensor with Differential Sensing Electrodes Integrated with Readout Circuits Po-Wei Liao1, Hao-Chiao Hong2 and Yi Chiu2

1Institute of Biomedical Engineering, National Yang Ming Chiao Tung University 2Dept. Electrical and Computer Engr., National Yang Ming Chiao Tung University

This paper reports a CMOS-MEMS capacitive pressure sensor with differential sensing electrodes integrated with an RC oscillator readout circuit in a single chip. The proposed differential sensing electrodes are designed in the back-end-of-line (BEOL) portion in a commercial 0.18µm 1P6M CMOS process. The proposed differential sensing design offers the advantages of sensitivity enhancement and noise reduction compared with other pressure sensors with single sensing elements. A low-power RC oscillator readout circuit is integrated with the sensor on the same chip to reduce noise and power consumption. Measurement results show the proposed sensing capacitors have a pressure sensitivity of 0.72 fF/kPa, the frequency of the readout circuit has a sensitivity of 0.032%/kPa in the pressure range of 50-300 kPa.

PA15 A Sub-Sampling Phase-Locked Loop Using Pulse-Width to Current Conversion Shao-Yu Shu, Ching-Yuan Yang Department of Electrical Engineering, National Chung Hsing University

In this paper, a sub-sampling phase detector (SSPD) and pulse-width to current conversion (PWCC) circuits are adopted to suppress reference frequency spurious tone of frequency synthesizer. The proposed PWCC technique converts the pulse-width of input clock signal into a modulated output current. This characteristic of pulse-width sensing applies to improve the conventional sub-sampling phase detector and charge-pump in phase-lock loop. Continuous and linear output current suppress the reference frequency spur, which results from non-ideal effect of charge-pump. Simulated by 0.18-um CMOS process, the proposed SSPD frequency synthesizer dissipates 20 mW from a 1.8-V power supply. The operation frequency of proposed frequency synthesizer is between 4.7 GHz and 5.35 GHz under the channel width of 10 MHz. The simulated output spurious tone is -57.59 dBm and the in-band phase noise performance is -123.17 dBc/Hz at 1-MHz offset.

PA16 31-33 GHz CMOS PA For Ka-Band Radar System Chih-Yu Chang, Hsiao-Chin Chen National Taiwan University of Science and Technology

A 31-33 GHz CMOS PA is designed and implemented using 90-nm CMOS technology for radar applications in this work. Based on the two stage differential class-AB power amplifier architecture, the PA is realized by using transformers as matching elements to save chip area. Moreover, a neutralization technique is applied to ensure the stability. Consuming the power of 109.8 mW, the PA achieves the output power of 9.93 dBm and the PAE of 6.9 % at 32 GHz for the input power of -7 dBm.

PA17 A V-band Vector Combination Phase Shifter Juo-Chen Chen, Ching-Fong Chen, and Yen-Chung Chiang Department of Electrical Engineering, National Chung Hsing University

In this paper, a vector combination phase shifter designed in a TSMC 90 nm CMOS process technology for V-band applications was proposed. The phase shifter consists of a Lange coupler, 3 balance-to-unbalance converters (baluns) and a vector combiner. Four signals with 90 degree phase difference, i.e. I+, I–, Q+, and Q– generated by a Lange coupler and two baluns are input to the vector combiner. Vector combination technique is able to control the output phase by voltage. Continuous phase shift ranges of 360 degrees have been measured. The chip area was 0.732×0.948 mm2, and the power consumption was 27.6 mW under a 1.2V supply. The measured range of S11 under different control voltage was from –11.88 dB to –6.63 dB. The measured P1dB is 0 dBm. The frequency range for the phase error less than 5 degrees was from 62.5 GHz to 66 GHz.

PA18 A Variable Inductor by Switching Paths and Coupling Coils Yen-Chung Chiang, Juo-Chen Chen, and Chiu-Hsiang Hsu Department of Electrical Engineering, National Chung Hsing University

A variable inductor implemented in the 0.18 m CMOS process technology is proposed in this paper. By using MOS transistors to switch the main coil paths and the mutual coupling coils, a large inductance tuning range with moderate step sizes is achieved. The inductor can achieve inductance values between 300 and 553 pH corresponding to 59.32% inductance variation range and 0.5% to 6.1% fine step size of the switched inductance at 4 GHz frequency.

PA19 A Highly Integrated Power-On-Reset Circuit Design For Multi-Delay and Multi-Voltage Systems Yu-Lung Lo and Wen-Po Lo Department of Electronic Engineering, National Kaohsiung Normal University

A power-on-reset (POR) circuit is extremely important in digital and mixed-signal ICs. It is used to initialize the critical nodes in digital blocks in mixed-signal circuits. Several papers of power-on-reset (POR) circuits have been reported, however, most of them offer the fixed reset time and reset voltage levels. Therefore, this paper proposes a novel multi-delay and multi-level (MDML) POR circuit that can simultaneously reset four output channels with a shared controller. The time-division-multiplexing (TDM) scheme has been applied to the shared controller of this MDML POR and the four-channels POR is greatly integrated in one chip. Based on a 0.18-µm standard CMOS process with a supply voltage of 2 V~1.4 V, the experimental results indicated that the proposed POR has the multi-output voltage from 2 V to 1.4 V and multi-reset time from 245 μs to 661 μs.

PA20 2.4/5.2 GHz Concurrent Band LNA with Noise Cancellation Yu-Chen Cheng, Hsiao-Chin Chen, Chih-Feng Yang National Taiwan University of Science and Technology

A2.4/5.2 GHz concurrent band low noise amplifier is designed for Wi-Fi 6 applications. A feedforward noise canceling technique is applied to the LNA so that the noise of MOSFETs in the primary stage can be reduced. The LNA is fabricated using TSMC 90nm CMOS technology.Consuming the power of 18.37 mW from the 1-V supply,the LNA achieves the NF of 1.9/1.98 dB, the IIP3of -4.06/-0.97 dBm and S21 of 14.56/12.3 dB at 2.4/5.2 GHz.

PA21 An Efficient and Stable CMOS Relaxation Oscillator Hung-Chou Mai and Klaus Yung-Jane Hsu Advanced Silicon Devices and Applications Lab, Institute of Electronics Engineering, National Tsing Hua University

In this paper, an efficient and stable CMOS relaxation oscillator with high power efficiency is presented. Fabricated in a standard 0.18 μm CMOS process, the proposed oscillator with an oscillation frequency of 41 MHz achieves better than ±0.017% voltage sensitivity for a supply change from 1.6 V to 2.0 V and a frequency variation less than ±0.011% for a temperature range from -40 ℃ to 100 ℃. In addition, a 50% duty cycle is realized by single charging/discharging path and a frequency divider.

PA22 High Performance Analog Feedback Second Order DT DSM with SAR Quantizer Hung-Ming Chiu1, Peng-Jhen Lee1, Hsin-Liang Chen2, Jen-Shiun Chiang1 1Electrical Engineering, Tamkang University 2Electrical Engineering, Chinese Culture University

An architecture for audio applications of low area cost and high resolution delta-sigma modulator is proposed in this paper. It is a switched-capacitor modulator that employs a successive approximation register (SAR) quantizer for obtaining a high dynamic range and can operate efficiently. By minimizing its oversampling ratio, the power consumption can be reduced systematically. It also employs a second-order noise shaping topology with a 6-bit SAR quantizer to reach audio dynamic specifications. In addition, a R2R ladder digital-to-analog converter (DAC) is used to share the DAC of the SAR quantizer and feedback of the modulator to relieve the area and power costs. A prototype was implemented by 180-nm 1P6M CMOS process. It could achieve dynamic range of 105dB, SNDR of 93.7dB, and SNR of 103.8dB with bandwidth of 25kHz and power dissipation of 1.25mW. It is also able to reach the state-of-the-art energy efficiency, as demonstrated by a Schreier FoM of 178 dB.

PA23 Hybrid Sturdy MASH-21 Delta-Sigma Modulator Using 1.5 bits Quantizer for Audio Applications Heng Zhang and Chia-Yu Yao Department of Electrical Engineering, National Taiwan University of Science and Technology

This paper presents a hybrid sturdy-MASH-21 (SMASH-21) delta-sigma modulator (DSM) chip design. We employ differential opamps in the hybrid SMASH-21 DSM chip to reduce even-mode harmonics. The sampling rate is 4.608 MHz and the over-sampling ratio is 96. When taking the transient noise in post simulations, the worst case occurs at the SS-0 C corner where the modulator consumes 745 uW of power and achieves a 77.21 dB SNDR, which is equivalent to having 12.5 ENOBs. The chip size is 1.528 x 1.238 mm2.

PA24 A fast settling time asynchronous binary search digital LDO with domino control mechanism Wei-Bing Yang, Shu-Yu Ku and Chun-Wei Wang Advanced Mixed-Operation System (AMOS) Lab, Tamkang University

This paper proposes asynchronous binary search digital low-dropout regulator (ADLDO) with domino control mechanism and the adjustable bidirectional asynchronous loop. The

domino binary search is used to achieve fast settling time. After domino binary search completed, the adjustable bidirectional asynchronous loop goes to fine tracking region. Additionally, the double edge-triggered comparator enhances the detection of load transients. The proposed ADLDO is implemented in TSMC 90nm 1P9M. With VIN=350mV and 50mV dropout, the proposed LDO can support maximum output current of 2.4mA with 99.87% current efficiency and settling time is 61ns. Therefore, the proposed LDO is suitable for fast tracking ultra-low supply voltage applications.

PA25 An Extensive Load Resistor Operation of Wireless Power Transfer System in 13.56MHz Resonant Mode Heng-Ming Hsu and Jian-Kai Liao Department of Electrical Engineering, National Chung Hsing University

The variation of load resistor influences the efficiency of the wireless power transfer (WPT)system dramatically. This study designs the mutual inductance of the resonant coil for achieving high efficiency at the heavy-load period (20 Ohm-50 Ohm) and light-load period (50 Ohm-120 Ohm). A class-E^2 WPT system operated at 13.56MHz is implemented to verify the proposed approach. Measurement shows the efficiency is greater than 76% in a wide range of load resistors (20 Ohm-120 Ohm). The system output power is 20W at a specified load resistor (30 Ohm) which is occurred at a maximal efficiency point.

PA26 A High-Performance Active Full Rectifier for Piezoelectric Vibration Energy Harvesting Systems With Bulk voltage Control Po-Chen Lin, Ching-Yuan Yang Department of Electrical Engineering, National Chung Hsing University

In this paper, we propose a high-performance full-wave-rectifier converter for piezoelectric vibration energy harvesting systems. By replacing the passive diodes with an operational amplifier-controlled active counterpart and adding a switch in par-allel with the transducer, the proposed rectifier solves the dc-offset problem of the comparator-based active diode, minimizes the voltage drop along the conduction path, and extracts more power fromthe transducer, all of which lead to better power extraction and con-version capability. The full-wave-rectifier was implemented in 0.35-μm CMOS process. Compared with the traditional full-wave-rectifier, simulation shows that when input current and frequenzy is same, the Vout of the proposed full-wave-rectifier can be increased from 1.8V to 6.5V and shows 90% power conversion efficiency and81 μW output power, with values corresponding to 1.5 times and3.4 times the values for a conventional full-bridge rectifier

PA27 A Switched-Capacitor Second-Order Sigma-Delta Modulator Hsin-Wei Dong1, Po-Hui Yang1, Chorng-Sii Hwang2

1Department of Electronic Engineering; 2Department of Electrical Engineering, National Yunlin University of Science and Technology

In this paper, an improved internal amplifier topology for the conventional architecture of the second-order sigma-delta modulator is proposed. A two-stage operational amplifier is utilized with a hybrid common-source and common-gate compensation in the second stage. A 16-bit accuracy is achieved while the signal bandwidth is 5 KHz and the oversampling rate is 250. The proposed circuit is designed and simulated with TSMC 0.18 um 1P6M CMOS technology. The post-layout simulation shows that the SNDR is 99.7 dB and the ENOB is 16.65. The power consumption and core area are 3.39 mW and 0.39 mm2, respectively.