Degradation Analysis in SO1 LDMOS Transistors with Steep Retrograde Doping Profile and Source Field Plate

I. Cortks, J. Roig, D. Flores, J. Urresti, S Hidalgo and J. Millin

Centro Nacional de Microelectrhica (CNM-CSIC), Campus UAB, 08 193, Bellaterra, Barcelona (Spain) Tel. (34) 93 594 77 00, Fax. (34) 93 580 14 96, e-mail: ignasi.cortes@cnm.es

Abstract The benefits of implementing a source field plate in RF ultra-thin SO1 Power LDMOS transistors with a retrograde doping profile in the entire drift region is evaluated in this paper in terms of Hot-Carrier Degradation (HCD) and capacitance behaviour. The optimisation of the retrograde doping profile allows the current path to be diverted deep inside the active Silicon layer in such a way that the surface damage originated by hot carriers is attenuated. However, a slight change in the dose implanted into the drift region can deteriorate the performance in terms of HCD and capacitance. Among the well-known benefits, such as better power efficiency and higher reliability, simulation results show that the source field plate (SFP) leads to an improvement of device stability to implanted dose fluctuations in LDMOS transistors with retrograde doping profiles. Moreover, the retrograde doping profile along with the SFP helps to accelerate the depletion process in the drift region, increasing the variation of the gate-drain capacitance (CgJ as a function of the drain voltage and thus improving the RF performance.

1. Introduction The presence of defect centres or traps in

lateral architectures, such as the power LDMOS transistor, is an important drawback since most of the current flows close to the Si/SiOz interface. As a consequence, more interface traps are generated into the high electric field regions. In addition, the probability of electrons being trapped at these defect centres i s enhanced. Besides, the electron mobility is reduced in the channel region due to the carrier scattering and increased HCD [ f ] . The final consequence of these effects is the degradation of critical electrical parameters such as the specific on-state resistance and the transconductance. Two aspects have to be addressed in order to minimise the HCD effect: the maximum current path has to be moved away from high electric field regions and the high impact ionization region has to be pushed deep into the active Silicon area.

The hot carrier degradation (HCD) in power LDMOS

transistors is closely related to the high electric field peak, generally located close to the surface at the body- LDD junction region. Assuming that there is a dependence of the HCD on the lateral electric field, the HCD can be reduced by decrementing the doping concentration at the body-LDD junction region in order to smooth the electric field distribution. Different doping profiles in the channel region, such as lateral asymmetric channel (LAC) [ 2 ] applied to conventional deep submicron MOSFET structures, have been reported in the literature. In that case, a graded body doping from source to drain, implemented via a high tilt implantation process, was used to reduce the lateral electric field at the gate edge and therefore the WCD effect. On the other hand, LDMOS structures with a dummy gate 131 have also been integrated showing a reduction of the HCD effect in the LDD region. This is achieved by the field plate effect of the secondary gate which relaxes the electric field shape at the surface of the LDD region close to the gate edge. An LDMOS with a secondary gate connected to the source has been also proposed in [4] addressed to the further acceleration of the depletion process in the drift region. Hence, the doping concentration in the drift region can be increased with the subsequent reduction of the drift resistance, maintaining the breakdown voltage capability. In the same way, the MOSFET structure proposed in [5] is addressed to minimise the HCD effect moving the maximum current path away from the region where the maximum electric field is reached and pushing the impact ionization region deep into the Silicon active area. In conclusion, different technical solutions have been reported to reduce the HCD effect, such as the buried LDD structure [ M I . Basically, two approaches are envisaged: the creation of a low resistive path deep in the active Silicon layer via a second LDD implantation or the deflection of the electron current towards the bottom of the LDD diffusion at the edge of the gate.

A modified SO1 power LDMOS transistor for RF applications to be integrated in ultra-thin SO1 substrates with a steep retrograde doping profile in the entire drift region and metal source field plate (SFP) on top of the

0-7803-88 10-0/05/$20.00 02005 IEEE.

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bodyLDD region (RDD structure) is proposed in this paper. The structure is analysed in terms of hot-carrier degradation and capacitance comportment. In this sense, the RDD itructure has been numerically studied using 2-D numerical simulators (Silvaco [7] and ISE-TCAD @I) and compared with a conventional uniformly doped drift LDMOS structure (UDD).

Gate length Drift region length '

2. Retrograde Drift Doped Structure A steep retrograde doping profile in the entire drift region was proposed in [9] to diminish the HCD effect in SO1 LDMOS transistors. The reported structure exhibits better electrical performances in terms of trapped electron distribution and transconductance degradation with no relevant modification of the DC characteristics; i.e. breakdown voltage and specific on- resistance, in comparison with a conventional LDMOS structure. The implementation of the steep retrograde profile allows the main current path to be deviated from the surface at the drift region and a slight reduction of the lateral electric field peak in the body/drift region. As a consequence, a smaller impact ionization generation rate is attained at the surface and therefore less hot carriers are created. The main problem of this structure is the unstable behaviour when the implanted dose is slightly increased. We propose to add a metal source field plate in the body/LDD region so that the electric field distribution along the drift region is improved and the electric field at bodyLDD junction [4] is further relaxed. Moreover, the source field plate, also known as second gate structure, helps to the acceleration of the depletion process. Hence, the implanted dose in the drift region can be increased with the inherent reduction of the drift resistance with no significant electric field change in the body-LDD region. These conditions assure better power efficiency and successfully remove the undesired I-V kink effect, maintaining a high breakdown voltage capability. Finally, this structure exhibits good performance in terms of HCD.

3. Device structure and design The analysed SO1 power LDMOS transistor is based on the structure reported in [lo]. The schematic cross- section of the analysed LDMOS structure and a detailed view of the doping profile across the drift region are illustrated in Fig. 1. The main geometrical and technological parameters of this structure are listed i n Table 1. A low doped P-type substrate is used to reduce the output capacitance and to enhance the frequency response whereas the source is tied to the body diffusion to avoid the activation of the parasitic bipolar transistor [ I I]. A drain field plate (DFP) is implemented on top of the LDD diffusion close to the drain whereas a SFP is placed above the gate-LDD region in such a way that a smoother electric field distribution is obtained along the LDD surface.

- Lg 0.8 pm L~~~ 3.5 pm

The proposed structure has two main doping features: the graded channel doping profile and the retrograde

Drain field plate length 49

doping profile in the drift region. Lateral diffusion of the p-type body diffusion under the gate forms the channel region. The doping concentration peak at the edge of the gatelsource p-body region chiefly controls the transistor threshold voltage and is adjusted to obtain a threshold voltage in the range of 1.7 V. The retrograde doping profile in the drift region is implemented with an Arsenic high energy implantation through an ultra-thin thermal oxide. The target was a maximum doping concentration at the interface between the active Silicon layer and the buried oxide and a surface Arsenic concentration in the range of 2 orders of magnitude lower than that of the inner interface. The final values to achieve the steep retrograde profile within a 180 nm active Silicon layer are an Arsenic implantation with a dos: of 2.2~10" cm.* and a energy of 250 Kev through 30 A thin oxide. Once the drift implantation process is completed, a RTA anneal at 1000" C for 10 min. has to be performed to activate the introduced impurities.

L, cf

I . L - < !

0.6 pm

P- substrate I < 7.5 um >

f: T,,

Fig.1. Cross-section of the LDMOS structure under study

Parameters Buried oxide thickness

Gate oxide thickness 40 nm

Table 1. LDMOS structural parameters

4. Simulation results and physical interpretation

A. Hut-Carrier Degradation (HCD)

The final doping profiles across the drift region in UDD and RDD structures are plotted in Fig. 2. As it can be inferred from this figure, the retrograde doping profile of the RDD structure has a minimum doping level at the

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surface of the active Silicon layer, being the maximum concentration level reached at the Silicon-buried oxide interface. On account of this fact the body/drift junction becomes slightly shifted towards the drift. As a consequence, the overlap between gate electrode and LDD diffusion is eliminated, Indeed, the charge interaction between gate and drain terminals is reduced; i.e. a C,, capacitance reduction, as discussed in the next section. In any case, the on-state resistance is lightly increased mainly at low gate voltages,

lEl5 U U.02 U U I 006 0.08 0.10 0.11 0.14 0.16 0.18

Y p i t i a n (p)

Fig. 2. Net doping profile across the drift region for both UDD and RDD SO1 LDMOS structures.

The retrograde doping profile, in the RDD structure, helps to direct the current path along the drift region towards the interior of the active layer. Therefore, the impact ionization generation rate is located deep inside the active layer, thus reducing the possibility of hot carriers to reach the Si-Si02 interface [5 ] . Furthermore, the SFP, in the RDD structure, relaxes the electric field under the body-LDD region and, along with the DFP, provides better linear electric field distribution along the drift region. Hence, the reduction of the interface trap generation and the electric field at the LDD-gate edge helps to decrease de the HCD degradation effect.

The HCD effect is directly related with the total number of free electrons at the Si-Si02 interface. In spite of the conduction path location, electrons generated by impact ionisation will also contribute to degrade the device reliability. The total generation rate of electron-hole pairs by impact ionization not only depends on the electric field distribution but also on the current density. Devices with lateral architecture exhibit a current path mainly concentrated in a narrow region close to the Silicon surface. Hence, the maximum generation by impact ionization will appear at the surface regions where the IateraI electric field peak is also high; i.e. in the channel-drift junction region and in the LDD-drain contact.

different depletions processes, the horizontal depletion at the body-LDD junction and vertical depletions created by the buried oxide at the bottom and the SFP at the top of the drift region, define a funnel region through which current flows from drain to source. Hence, the surface of the drift region will be depleted quickly than the region close to the buried oxide, thus confining the main current path deep inside the drift region. Moreover, the region with the highest impact ionisation rate will be located deep inside the Silicon at the drain-LDD region. Fig. 3 represents the electron density and impact ionisation contours across the active Silicon layer in the RDD structure at the following biasing conditions: V,=2 V and Vd=28 V. Fig 4 shows the lateral electric fie!d distribution along with the impact ionisation generation rate. An improved electric field distribution is achieved in RDD structure due to the SFP action and the lower superficial junction doping level regarding the UDD structure. As a consequence, less hole-electron pairs are generated by impact ionisation along the drift region. This is an important factor in terms of HCD degradation, as explained before.

Thermodynamic simulations have been carrier out to take into account the self-heating effect. Simulation results of electron Joule heat and lattice temperature along the Silicon surface at V,=2 V, V ~ 3 0 V for both UDD and RDD structures are shown in Fig. 5. As it can be seen from this figure, a great difference of electron Joule heat distribution results in the drift region covered by the SFP for both structures is obtained. Keeping in mind that the Joule heat directly depends on the current density and the electric field, the lattice temperature distribution is different in both devices. AI1 these aspects help to reduce the possibility of electrons being trapped in the Si-SiOz interface.

s prstlrm (pro)

Fig. 3 Electron density and impact ionisation contours along gateldrift area in the RDD structure

A SFP is necessary in a retrograde doped drift structure to stabilise the electric field and to improve the power efficiency. On the other hand, thanks to the SFP, the

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3 4 S 6

X pmition (p)

Fig. 4 Lateral electnc field and impact ionisation generation rate along the Silicon surface for both UDD and RDD structures.

Lattinlrmprstum rJwlrhcpl d U D D -UDD --o-RDD * O * RDD

0 1 1 3 1 8 6 1 )dl

E l 0

iw 1Ea

E m IFI e 1" g a

E I- I H 3%

8 3m lmOu $

LI - 3

f: Imo c1 - I W

I O

310

)oo I 0 1 1 3 4 5 6 7

X !"lUon (PI Fig. 5 Electron Joule heat and lattice temperature distribution along the Silicon surface for both UDD and RDD structures.

To confirm the expected reduction of the HCD effect, the device degradation model with the experimental fitting parameters extracted from 1121 has been used. The initial neutral concentration traps ( N,: =lo8 cm-') defined in the middle of the bandgap and the electron trapping cross section (an = 1~10-l~ cm2) specifications have been taken into account. Transient simulations at different time steps under stressed bias conditions have been performed. Under these conditions, more traps are generated and more carriers are trapped at Si/SiOz interface as a function of the electric field value at the surface. Considering the exponential dependence of hot carriers with the electric field value, the device is biased in such a way that the electric field peak is located at the body/LDD region. Therefore, the stressed biasing conditions are Vd=30 V and Vg=2 V. The degradation of UDD and RDD SO1 LDMOS transistors up to lx105 operating seconds is plotted in Fig. 6 . As it can be clearly inferred, the drain current starts to diverge after IO0 seconds showing a 7.7% reduction in the UDD case after lx105 seconds. On the contrary, the RDD structure

only exhibits a reduction of 1.5% at the same timc step. This result is related with the less transconductance degradation in power SO1 LDMOS transistors with a retrograde doping profile and SIT.

I - t . * 4

_n

"e (6)

Fig. 6. Time dependence of the HCD for both UDD and RDD structures.

B. C-V characreristic

In a conventional SO1 LDMOS structure, the feedback capacitance C , is defined as the gatddrift overlap capacitance (Cox) in series with the gatddrift junction capacitance (CJ, as shown in Fig. 7. The CO, capacitance value basically depends on the gate oxide thickness and the LDD doping concentration in the drain contact edge. The C,; capacitance value also depends on the doping concentration and the bodyLDD junction depth [13]. There is another contribution to the CRd capacitance due to the interaction between gate- drain metallic interconnections (Cgdi). In the case of a LDMOS structure with a SIT, this capacitance does not contribute to the C, capacitance value since it is like a Faraday shield which avoids the coupling between gate and drain terminals [ 141. Therefore the total feedback capacitance and the input capacitance in a conventional SO1 LDMOS transistor can be expressed as:

with SFP (2)

Nevertheless the reduction of C,, capacitance value gws with an increase of the Cis, capacitance value due to the added interaction between gate and the metal SFP represented by Cgsi capacitance. Although this effect causes a cutoff frequency reduction, it can be compensated with an appropriate input matching network in power amplifier applications. Fig.7 also shows the junction curvature difference between the UDD structure (continuous line) and the RDD structure

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(discontinuous line). Cgdl

C

N

I Buried oxide I 2 3 i 5 6 7

X position (~JII)

Fig. 7 Cross section of a conventional SO1 LDMOS structure with the capacitance components.

In this section the analysis of the C-V characteristics and the simulation results of RDD and UDD structures are provided. Small-signal AC simulations at lMHz have becn performed in both structures to extract the equivalent capacitances between each pair of electrodes. Substrate and source contacts are connected to the ground .

Keeping in mind that id a SO1 LDMOS with a retrograde doped drift structure the doping concentration at the surface is very IOW, there is no overlap in the LDD/gate edge. Therefore the C,, capacitance does not contribute to the total feedback capacitance. Moreover, the SFP will help to cancel the contribution of the C,,, capacitance. Consequently, the feedback capacitance (CrJ will strongIy depend on the drift region doping concentration. Simulation results concerning capacitances between gate and drain terminals (CrJ as a function of the drain voltage in RDD and UDD SO1 LDMOS structures are represented in Fig.8. Taking into account that the junction capacitance varies with drain voltage while the parasitic capacitance is not affected, the overlap capacitance study can be performed at V s O V. Hence, two versions of the UDD structure have been simulated, one with O.Ipm of gateLDD junction overlap (UDD-OV) and the other one without overlap junction (UDD).

Results in Fig, 8 suggest that the evolution of C,, capacitance as a function of v d r strongly drops in the RDD case in comparison with UDD counterparts. Due to the retrograde doping profile implementation, a non uniform depletion process at the bcdy/LDD junction is observed. This fact and the existence of a SFF allow a quick surface depletion at increasing drain voltage conditions. As a consequence, the C,i capacitance is reduced as if the plates of a parallel capacitance were moving away. Therefore the feedback capacitance in the case of RDD structure goes down with a steeper slope.

IC'

3.6016~ 20 3d UI

v, (v)

Fig. 8 Gate-drain capacitance versus drain voltage for both UDD and RDD structures. The UDD structure is simulated also with a Gate/LDD junction overIap (UDD-OV).

On the other hand, two regions with different slope of the CghVd curves can be distinguished in both structures. The knee observed between the two regions is a direct consequence of the DFP. A superficial electron accumulation is generated at high VdJ in both devices in such a way that de depletion process is slowed down. A previous knee is found in the case of RDD structures in comparison with the UDD case since the surface accuniulates more easily in the RDD structures due to different doping concentration level. At a drain voltage close to 40 V the slope of the C,, curve tends to be zero in the RDD case due to the complete depletion of the drift region at this drain bias.

Differences observed in the c& capacitance values at Vdb=O V in UDD and UDD-OV cases account for the Cox contribution to the total C,, capacitance value. However, results shown in Fig. 8 clearly indicate that the capacitance in the body/LDD junction is slightly higher in RDD structures in comparison with the UDD counterparts despite the much lower surface doping concentration level. Therefore, the junction capacitance has to be considered in all the junction area, according to the results shown in Fig. 8. The higher doping concentration level in the drift area close to the buried oxide in the RDD structure regarding the UDD counterpart, as plotted in Fig. 2, is the cause of this phenomenon.

Finally, simulation results concerning C,, capacitance are also plotted in Fig. 8 to corroborate the influence of the SIT. As stated before, results from Fig. 8 show that the interaction capacitance component between gate and source, when a SFP is implemented, adds a constant value to the total gate source capacitance. Thereby, the SFP is the responsible of this slight capacitance increment.

A detailed study has been performed to corroborate the C,, capacitance comportment. The surface potential

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variation at the gate/drift region is plotted in Fig. 9 at AVp20 m y and V,=0 V for five different drain voltage values (1.6, IO, 20, 30 and 40 V). The results shown in Fig. 9 illdstrate a large surface potential drop in the gatddrift surface region at vcF20 V. Taking into account that the C,, capacitance is defined as the gate charge variation for a given drain potential difference, and the charge distribution at the gate is proportional to the voltage drop in the gate/drift region, the simulation results confirm the capacitance behaviour previously shown in Fig. 8.

2.5 3.0 3s 40 4s

0 0

F 5

I . , . ' ! , , . , . I _I__

13 3J 3.5 1 0 4.5

X Posltlontpm)

Fig. 9 Lateral surface potential variation when Vd changes by 20 mV in UDD and RDD structures operating at Vg=O V and at a drain bias of 1.6, 10, 20, 30 and 40 V.

5. Conclusions

The contribution of implementing a SFP in terms of HCD and capacitance behaviour in ultra-thin SO1 power LDMOS with a steep retrograde doping profile in the drift region is analysed i n this paper. The drift region below the source field plate, close to the body-LDD junction is easily depleted due to the combined action of the SF'P and the retrograde doping profile. Hence, the current path in the channel edge is pushed further away from the interface and the electron concentration at the surface decreases. This fact along with the electric field relaxation causes less generation and occupancy of interface trap density and therefore better reliability. On the other hand the C-V characteristic of RDD LDMOS structures significantly changes with a SFP placed at the LDD region, leading to lower C,, capacitance values.

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