Liboiron-Ladouceur et al. VOL. 3, NO. 8/AUGUST 2011/J. OPT. COMMUN. NETW. A1

A Scalable Space–Time Multi-plane OpticalInterconnection Network Using

Energy-Efficient Enabling Technologies[Invited]

Odile Liboiron-Ladouceur, Pier Giorgio Raponi, Nicola Andriolli, Isabella Cerutti,Mohammed Shafiqul Hai, and Piero Castoldi

Abstract—This paper presents an energy-efficient multi-plane optical interconnection network to interconnect serversin a data center. The novel architecture uses the time domainto individually address each port within a card and the spacedomain to address each card. Optical enabling technologiespassively time-compress serial packets by exploiting thewavelength domain and perform a broadcast-and-select to adestination card with minimum power dissipation. Scalabilityof both the physical layer and the overall power dissipationof the architecture is shown to be enhanced with respectto the existing interconnection network architectures basedon space and wavelength domains. The space–time networkarchitecture is scalable up to 216 ports with space-switchesexhibiting energy efficiency of the order of picojoules per bit,thanks to the self-enabled semiconductor-optical-amplifier-based space-switches.

Index Terms—Computer network performance; Opticalinterconnection; Optical switch; Power consumption.

I. INTRODUCTION

T o support Internet services or large databases, datacenters house large clusters of servers connected through

a networking infrastructure. The number of servers in datacenters is growing steadily to keep pace with the increaseddemand for data and computational performance required, forinstance, by Web searches. Such growth is further jeopardizedby the current trend of tailoring the architectural design ofdata centers in a modular way [1] with a large number oflow-cost commodity servers, rather than expensive high-endservers [2,3]. This trend allows the tasks to be parallelized andthe expected performance to be delivered, which is typicallybelow the peak performance [4]. In typical data centers, theaverage server utilization is about 20–30% [5] (even lower, atabout 5–15%, at the CERN data center [6]) and it is expected toincrease to 30–60% when virtualization is introduced [6]. Along

Manuscript received January 28, 2011; revised April 7, 2011; accepted April29, 2011; published June 20, 2011 (Doc. ID 141934).

Odile Liboiron-Ladouceur (e-mail: odile.liboironladouceur@mcgill.ca) andMohammed Shafiqul Hai are with the Department of Electrical and ComputerEngineering, McGill University, Montreal, Quebec, H3W 2M1 Canada.

Pier Giorgio Raponi, Nicola Andriolli, Isabella Cerutti, and Piero Castoldi arewith the Scuola Superiore Sant’Anna, 56124 Pisa, Italy.

Digital Object Identifier 10.1364/JOCN.3.0000A1

with server size increase, the power drained by the serversis growing even faster. Despite the improvement of servercomputational performance (a factor of three every two years),the energy efficiency of servers is unable to keep up with thesame improvement rate (limited to about doubling every twoyears [7]). Thus the overall power consumption is rising at ayearly rate of about 15–20% [7–9]. In fact, the acquisition costof a server is now lower than the operational cost due to itsvery high energy consumption [8–10].

Scalability and energy efficiency have become the two keyissues in data centers and are imposing tight constraintson the networking infrastructure connecting the numerousservers. Statistics report that about 10–20% of the equipmentbudget [3] and about 5% of the power consumption in datacenters is due to the networking infrastructure [11–13]. Whentaken in absolute terms, the amount of power drained by thenetworking infrastructure is non-trivial and is doomed to growwith the scaling of data centers. Indeed, the scalability with re-spect to the number of interconnected servers (as well as withthe transmission data rate) and the overall power consumptionis stretching the limit of today’s interconnection networksbased on electronics [14]. The challenge is to interconnect alarge number of servers according to dynamically changingcommunication patterns, so that a large amount of bandwidthcan be offered when and where required. This requires thedesign of high throughput and scalable architectures for theinterconnection networks, with an energy consumption limitedand proportional to the utilization of the network [4,15,16].

The introduction of optics in interconnection networks hasbeen proposed to mitigate the issues related to electroniclimitations. In particular, optics has the advantage of offeringlarge bandwidth with low attenuation and crosstalk making itsuitable for communications (i.e., exchange of packets) betweenservers [1,14,17–20]. On the other hand, in interconnectionnetworks based on optics, the architectural design, theselection of optical technologies, and the operating strategiesmust be optimized in order to meet the requirements of powerconsumption [14,17,18,20–23] and scalability [1,23] imposedby the current growth trend in data centers [10]. To overcomethe scalability limitations, multi-plane architectures have beenproposed, such as the space–wavelength architecture [24–26].Multi-plane architectures are organized in cards, each one withmultiple ports, and fit well the modular architecture paradigm

1943-0620/11/0800A1-A11/$15.00 © 2011 Optical Society of America

A2 J. OPT. COMMUN. NETW./VOL. 3, NO. 8/AUGUST 2011 Liboiron-Ladouceur et al.

for data centers [1]. The control of the network is delegatedto a two-step scheduler (TSS) [25]. The TSS addresses theproblem of scheduling packet transmission by splitting theproblem into two subsequent steps. As shown in [25], theadvantage of the TSS approach is the reduction of the problemcomplexity, leading to a reduction in the latency experiencedby the incoming packets in large size networks with respect toa single-step scheduler. In addition, the TSS approach allowsfor the parallelization of the scheduling operations, leading tofaster computation and higher scalability.

This paper proposes an innovative multi-plane architecturefor optical interconnection networks, controlled by the TSSscheduler. The architecture exploits space and time switchingdomains, whereas the wavelength domain provides additionalcapacity to increase the throughput. In this way, each port isequipped with the same laser array, leading to a simplificationof the implementation, compared with architectures withwavelength-dependent ports [24,26].

To overcome the power consumption issue, especially atlow levels of utilization, an all-optical implementation basedon self-enabling semiconductor optical amplifiers (SOAs) isenvisioned for the proposed space–time (ST) architecture.The key features of the self-enabling SOA are the abilityto act simultaneously as a switch and an amplifier, andthe possibility to remain in an idle state when unused.Sharing of functionalities and exploitation of idle mode allowa reduction of the consumed power, especially at low levels ofutilization [26].

The aim of the paper is two-fold: to discuss the STarchitecture with enabling technologies such as integratedpassive devices and self-enabled SOAs, and to assess thescalability, network performance, and power consumptionof the proposed implementation. Performance is comparedwith the space–wavelength architecture [26] and a spacearchitecture (such as the conventional broadcast-and-selectarchitecture [27]) to determine the most suitable architecturefor future data centers.

II. SINGLE- AND MULTI-PLANE ARCHITECTURES

Optical communication systems based on single-modepropagation conventionally make use of the inherent frequencyparallelism through wavelength division multiplexing (WDM).Alternatively, optical interconnection networks can exploit thespace domain or the time domain for switching optical packets.Scalability is typically limited by the switching domain as wellas by the network performance (e.g., the latency experienced bythe packets waiting in the queue). The three possible switchingdomains are shown in Fig. 1(a) with their respective scalabilitylimitations.

Typically, single-plane optical interconnection networksexploit the space domain, such as in broadcast-and-selectarchitectures [27,28]. As the packet is being broadcast, thepower loss can be compensated by the optical amplifiers atthe cost of amplified spontaneous emission (ASE) noise, whichultimately limits the scalability from the minimum opticalsignal-to-noise ratio (OSNR) requirement. For instance, in [26],the binary tree structure of the broadcast-and-select switch

(a)

(b)

Optical SNR

Wavelength

Space

Time

Optical Bandwidth

Time compressionefficiency

N ports

M

M cards

L channels

21 N2

1

Fig. 1. (Color online) (a) Switching domains and their respectivescalability limitations. (b) Switching domains exploited in thespace–time (ST) architecture.

contains amplification stages after a cascade of five powersplitters to maintain the optical signal power. The scalabilityof the single-plane space architecture (S) is found to belimited to 1024 ports due to ASE noise accumulation in theSOA-based space-switch. Note that the wavelength domaincan also be exploited to realize a single-plane interconnectionarchitecture [24]. In such an architecture, the scalabilityis limited by the wavelength tunability in the transmitterslimiting the number of ports to a few tens.

To overcome the scalability limitations imposed by oneswitching domain, multi-plane architectures can be devised,where multiple switching domains are exploited. In multi-plane architectures, ports in a card are addressed using onedomain while cards are addressed using another domain. Anexample is given by the space–wavelength (SW) architecturein [24–26] which exploits the space and wavelength domainsto switch packets among cards and ports, respectively. In [26],the analysis showed that greater throughput is achieved bythe multi-plane SW architecture while exhibiting a reductionof up to 40% of the energy per bit compared with a single-planearchitecture which solely exploits the space domain. Whilethe space–wavelength makes use of the same space-switchstructure, its scalability is enhanced by the wavelength domainand the energy per bit is reduced thanks to the smaller numberof active optical components used for the same throughput withrespect to the single-plane architecture.

An alternative design of multi-plane architectures withbroadcast-and-select switches can be realized by exploitinga third switching domain, i.e., time. However, the time-compression efficiency limits the scalability of this domain.Packets can be compressed in time either by increasing thedata rate per channel (resorting to speed up or complexmodulation formats) or by expanding serial packets in thewavelength domain through wavelength-striped techniques.An architecture based on the latter approach is presented next.

Liboiron-Ladouceur et al. VOL. 3, NO. 8/AUGUST 2011/J. OPT. COMMUN. NETW. A3

III. SPACE–TIME INTERCONNECTION NETWORK

ARCHITECTURE

The space–time architecture consists of M cards, eachsupporting N input ports and N output ports. The space–timearchitecture exploits the space domain to individually switchpackets among cards and the time domain to switch themamong different ports, as sketched in Fig. 1(b). In addition,the wavelength domain is exploited to further increase thethroughput. This is achieved by encoding packets on multiplewavelengths (also referred to as WDM packets) and switchingthem in space and time among ports of different cards. TheWDM packets are switched between input and output ports byan M×M SOA-based switch.

The conventional wavelength-striped process is performedelectronically where the serial packet is partitioned (striped)and mapped to multiple wavelengths such that each wave-length carries a portion of the serial packet. A set ofoptoelectronic components (E/O and O/E) is assigned toeach wavelength, leading to a linear increase of the powerdissipation with the number of wavelengths. Moreover,high-speed electronics for converting the bit sequence of theserial packet into parallel streams would be required. Instead,the wavelength-striped process can be done entirely in theoptical domain using optical filters and delay lines [29].

The optical generation of WDM packets is based on a singleset of optoelectronic components for the signal conversionbetween the electrical and optical domains for all wavelengths.The process of creating and receiving a WDM packet isillustrated in Fig. 2 and can be realized as follows. Considera serial packet whose transmission duration at the selecteddata rate is T. The bits of the serial packet are usedto simultaneously modulate a comb of N optical channels.This can be realized with a single broadband modulatorthat modulates an array of N lasers emitting on differentwavelengths. Then, the passive wavelength-striped mapping(PWM) delays the modulated channels in time by T/N fromeach other and the delayed channels are gated in time togenerate a WDM packet of duration T/N. The serial packetis therefore compressed in time by the number of channels N.

The considered implementation of the ST architecture isshown in Fig. 3. Each input port converts serial packets intotime compressed WDM packets and is equipped with an arrayof N lasers, an external broadband optical modulator (E/O,e.g., Mach–Zehnder modulator), a PWM delaying the WDMchannels, and an SOA performing the gating. The WDM packetis launched through the M×M space-switch interconnection.At the receiving side, each output port performs the oppositeprocess: an SOA performs the gating of the received opticalsignal, a PWM reversely delays the different channels ofthe time compressed WDM packets, then a single broadbandoptical receiver converts the now delayed optical signals into aserial packet (Figs. 2 and 3).

The time domain is exploited by sequentially transmittingthe WDM packets in different time-slots of duration T/N.The N time-slots are then combined to form a time-frameof duration T, as shown in Fig. 2. For 100% utilization,up to N compressed WDM packets from different ports canbe accommodated in a time-frame. Hence, the number of

Broadband E/O Passive wavelength-stripedmapping (PWM)

Time-slot packet

M × M

Time-slot packetPassive wavelength-striped mapping (reversed delay)

Broadband O/E

...

Por

t out

,1

Por

t out

,N

Por

t out

,1

Por

t out

,N

Time-slot T/N

Time-frame TSerial packet

Serial packet

T

T

T

T/N

Tim

e ga

ted

by S

OA

Tim

e ga

ted

by S

OA

T/N

Packets in M × M

...

Fig. 2. (Color online) Time compressed WDM packets in a cardthrough PWM.

wavelengths, responsible for the compression factor, mustcorrespond to the number of ports. In this architecture,each time-slot of a time-frame is assigned to a specificport of the output card. In other words, a WDM packetat the k-th input port Portin,k of the h-th card (with k =1, . . . , N and h = 1, . . . , M) destined to the n-th output portPortout,n of any given output card m (with n = 1, . . . , Nand m = 1, . . . , M) is transmitted in the n-th (n = 1, . . . , N)time-slot (Fig. 2). Because the time-slot gating is fixed atthe transmitting side, a cross-point [30] is necessary. Thecross-point on each card connects the input buffer of eachport Portin,k to each modulator input Inn (with k,n =1, . . . , N). The configuration is performed at each time-frame Tbased on the intra-card scheduler decisions. The gated WDMpackets are then multiplexed together at the card by an N:1coupler. Then, the WDM packet crosses an M×M space-switchinterconnection. At the receiving side, a 1:N splitter broadcaststhe routed packet to the PWM of each output port and an SOAgate selects the time-slot corresponding to the output port.

A. Inter-Card and Intra-Card Schedulers

The presented space–wavelength interconnection networkis non-blocking [30], i.e., at each time-frame it is possible toswitch up to MN packets from every input port to distinctoutput ports, and the switching configuration can be modifiedat each time-frame. The switching configurations and packetselection are dynamically decided by the schedulers.

At each time-frame, the intra-card and inter-card schedulersselect and schedule the packets to be switched, according tothe TSS framework described in [25]. In particular, at eachtime-frame, the intra-card scheduler running on each cardmaps the N input buffers to the N time-slots (i.e., to theN output ports). The mapping must ensure that each bufferis assigned to a different time-slot to avoid collisions. Themapping can be performed by solving a weighted matchingproblem, based solely on buffer information related to thecorresponding card. Once solved, the intra-card scheduler

A4 J. OPT. COMMUN. NETW./VOL. 3, NO. 8/AUGUST 2011 Liboiron-Ladouceur et al.

interconnectionM × M

1 × M

1 × M

Por

t ou,

t1P

ort o

ut,N

Por

t out

,1P

ort o

u,tN

O/E

O/E

O/E

O/E

PWM

PWM

PWM

PWM

PWM

PWM

PWM

PWM

Gatet = 0

Gatet = 0

Gatet = T(1-1/N)

Gatet = T(1-1/N)

Gatet = 0

Gatet = 0

Gatet = T(1-1/N)

Gatet = T(1-1/N)

1:NM:1

M:1 1:N

N:1

N:1

Card 1 of M

Card M of M

Card 1 of M

Card M of M

o1

oMiM

i1

Inter-cardscheduler

Intra-cardscheduler

Intra-cardscheduler

E/O

E/O

E/O

E/O

Cross-point

Cross-point

N chan

N chan

N chan

N chan

Portin,N

Portin,1

Portin,N

Portin,1

InN

InN

In1

In1

Fig. 3. (Color online) Space–time interconnection network architecture for M cards and N ports.

is responsible for setting the cross-point switch at eachtime-frame.

Based on the decisions of the intra-card schedulers, theinter-card scheduler selects the output card for each time-sloton each card. The selection must ensure that each output porton any card is receiving at most one WDM packet. The selectioncan be performed by solving N weighted matching problemsin parallel (i.e., one for each output port) every time-frame.Once solved, the inter-card scheduler controls the M×Mspace-switch interconnection by setting the N configurations,one for each time-slot.

Notice that the scheduling problem for the proposedarchitecture can be solved also by a unique single-stepscheduler. However, in [25] it is demonstrated that the TSShas a superior scalability in terms of computational complexitywith respect to the classical single-step scheduler. Moreover,when practical scheduling algorithms are used with realistictraffic, the suboptimality of the TSS is counterbalanced by theperformance degradation of the single-step scheduler for veryhigh port counts, leading to an overall advantage in using theTSS compared with a single-step scheduler [25].

IV. ST ARCHITECTURE IMPLEMENTATION

The implementation of the PWM and the M×Mspace-switch interconnection is discussed to devise theenabling optical technologies that are most suitable for theirlow propagation loss, optical bandwidth, power efficiency,and integrability. Based on recent developments related to100 gigabit Ethernet technology, the line rate is assumedto be 50 Gb/s and the optical modulation format to benon-return-to-zero on–off keying (NRZ-OOK) [31].

A. Passive Wavelength-Striped Mapping

The low power enabling subsystem is the PWM which isshown in Fig. 4. In the PWM, each wavelength channel needs

to be first filtered then delayed in time. The challenge andprice to pay in performing the mapping in the optical domainis power loss due to longer propagation. A power-efficientimplementation has been experimentally demonstrated withfiber-based components [29], where the wavelength-stripedprocess was achieved using passive optical components suchas filters and fiber delay lines (FDLs). While fiber-basedimplementation is viable, it becomes impractical and bulkywhen considering delays as long as the serial packet length(e.g., delaying by 2048 bits at 50 Gb/s requires 8 m of fiber).Hence, an integrated solution with propagation losses aslow as possible becomes necessary. A suitable technology isthe silica-based material that allows waveguide delays [32].The total loss of waveguide delay is strongly dependent onthe layout efficiency. Propagation losses for single-mode ribwaveguides have been reported as low as 3 dB per meter fora 2 mm bend radius [33]. Filtering is achieved using a latticestructure made of Mach–Zehnder interferometers (MZIs) tofilter each wavelength. The lattice structure has one input andconsists of a binary tree with stages of MZIs for filtering theWDM channels (e.g., three stages for eight WDM channels).The free spectral range (FSR) of the first stage is set to separatethe even from the odd labeled channels (λ2, λ4, λ6, λ8 fromλ1, λ3, λ5, λ7). With a channel separation of 400 GHz, thefirst stage MZI is designed with an FSR of 800 GHz. Thesecond stage MZIs are designed with an FSR that is fourtimes the channel separation to filter λ2, λ6 from λ4, λ8,and λ1, λ5 from λ3, λ7. The four MZIs in the third stageshave an FSR of 3200 GHz to individually filter each channel.Between the MZI stages, appropriate delays are inserted toperform the wavelength-striped mapping as shown in Fig. 4.Note that other optical technologies, such as microrings andAWG, would not be suitable in this design configuration due tohigh loss. For microring resonators, large FSRs are achievablewith small radius leading to higher loss in the resonance cavity.The AWG approach incurs overall greater loss due to the delayrequirements. For these reasons, the MZI approach is selectedas it enables large FSRs with limited loss.

Liboiron-Ladouceur et al. VOL. 3, NO. 8/AUGUST 2011/J. OPT. COMMUN. NETW. A5

λ1 to λ8

E/O MZI

MZI

MZI

MZI

MZI

MZI

MZIN:1N:1

N:1N:1

O/E

MZI

MZI

MZI

MZI

MZI

MZI

MZI

Seri

al p

acke

t (T

) Se

rial

pac

ket

(T)

8:1

AW

G

TX_PWM

RX_PWM

FSR = 2ΔλFSR = 4Δλ

FSR = 4Δλ

8:1 AW

G

SOAgate

SOAgate

λ1 to λ8

λ1 λ2 λ3 λ4 λ5 λ6 λ7 λ8

λ1 λ2 λ3 λ4 λ5 λ6 λ7 λ8

M × M

FSR = 8Δλ

FSR = 8Δλ

FSR = 8Δλ

FSR = 8Δλ

λ6, Δt = 0

λ2, Δt = T/N

λ8, Δt = 2 T/N

λ4, Δt = 3 T/N

λ3, Δt = 4 T/N

λ7, Δt = 5 T/N

λ5, Δt = 7 T/N

λ1, Δt = 6 T/N

λ1, Δt = T/N

λ7, Δt = 2 T/N

λ3, Δt = 3 T/N

λ4, Δt = 4 T/N

λ8, Δt = 5 T/N

λ6, Δt = 7 T/N

λ2, Δt = 6 T/N

λ5, Δt = 0Spectral response of the TX-PWM

Spectral response of the RX-PWM

Opt

ical

pow

er (

a.u.

)O

ptic

al p

ower

(a.

u.)

5 dB/div.

5 dB/div.

193 193.5 1934 194.5 195 195.5 196Frequency (in THz)

193.5 1934 194.5 195 195.5

Frequency (in THz)193 196

Fig. 4. (Color online) PWM performing the time-compression of the serial packet at the transmitting card and time-expansion at the receivingcard.

Each MZI uses multimode interference (MMI) couplers forminimal loss: the estimated insertion loss per MZI is 1 dBbased on recent developments presented in [34]. Time delayscorresponding to a multiple of the time-slot are appropriatelyintegrated within the lattice structure (Fig. 4). Once delayed,the channels are multiplexed using a silica-based arrayedwaveguide grating (AWG) with an estimated insertion loss of5 dB [35,36]. An SOA is used to generate the WDM packet bygating in time the optical signal as shown in Fig. 2. The gatingis performed on the optical signal at the output of the AWG bythe SOA, which is electrically pumped with a pulse of widthT/N. The timing of the gating pulse with the incoming WDMpacket is controlled by the intra-card scheduler (Fig. 4). Thegating SOA also plays the important role of optical amplifier tocompensate for the optical power loss in the PWM.

The implementation approach of the PWM has a strongeffect on its scalability in terms of port number as certainwavelength channels experience greater insertion loss. For apacket sub-slot of 16 ns (T/N) with a total serial packet lengthof 128 ns (800 Bytes at 50 Gb/s) and N = 8, the maximuminsertion loss difference in the PWM is 10.5 dB betweentwo channels (Fig. 4). Each 16 ns delay induces a 1.5 dBloss. To ensure physical layer scalability of the SOA-basedinterconnect, the laser sources are pre-compensated to obtainequal power for each channel of the WDM packet beinglaunched in the M×M interconnection. At the destination card,the loss difference between channels is reversed, e.g., channelλ6 will experience the least amount of loss in the PWM atthe receiving side (RX-PWM) since it experienced the mostloss in the PWM at the transmitting side (TX-PWM). Inthe RX-PWM, the maximum loss difference remains 10.5 dBbetween the channels, which can be compensated or convertedusing an optical receiver with large dynamic range. In thisproposed configuration, the PWM can be implemented withoutan amplification stage and is estimated to have a footprint ofapproximately 21 cm2. For a greater number of ports the total

insertion loss needs to be compensated with the inclusion ofSOAs in the PWM, which are envisioned to be flip-chip ontothe planar integrated circuit [37].

B. Energy-Efficient M×M Space-Switch Interconnection

As shown in Fig. 3, the considered architecture for the M×Mspace-switch interconnection consists of a broadcast-and-selectimplementation with M switches 1×M controlled by the inter-card scheduler and M couplers M:1. Each 1×M space-switchis a binary tree structure with SOAs, while each M:1 coupleris another binary tree structure with SOAs, as shown inFig. 5. The figure indicates also a possible implementationthat is achieved by connecting the 1×M space-switches placedon M vertical input layers to the M:1 couplers placed on Mhorizontal output layers. The wiring can still be cumbersomeas a number of connections equal to M2 is required for aspace–wavelength network with an overall number of inputports MN. However, such a number of connections is N2

times smaller than the number of connections required bya single-stage interconnection network based only on such aspace-switch with the same number of ports, i.e., MN.

The SOAs on the terminal branches of the 1×M space-switchact both as amplifiers and as switches that may enable orblock the passage of the optical signal, as decided by theinter-card scheduler. The SOAs on the output of the M:1coupler are required for amplification purposes. Moreover,additional stages of SOAs are required every five splittingstages (in both the 1×M space-switch and the M:1 coupler) tocompensate for the power loss introduced by the splitters.

In Fig. 3, the inter-card scheduler decides that the k-th inputport ik should be connected to the n-th output port on duringa given time-slot. For an energy-efficient implementation, onlythe SOAs in the path from the input port ik to the output port

A6 J. OPT. COMMUN. NETW./VOL. 3, NO. 8/AUGUST 2011 Liboiron-Ladouceur et al.

i1

i2

i3

iM

o1

oM-2

oM-1

oM

Fig. 5. (Color online) Illustration of the M×M space-switchinterconnection comprised of 1×M space-switches and M:1.

on are enabled, while the unused SOAs are idle, dissipatingminimum power. The state of SOAs in the 1×M switches iscontrolled by the inter-card scheduler. On the other hand, theM:1 couplers are not controlled by the inter-card scheduler;therefore the power minimization is accomplished thanks toa self-enabling mechanism.

The working principle of the self-enabled SOA is depictedin Fig. 6. A small amount (e.g., 10%) of the optical powerof the incoming optical packets is converted to an electricalsignal with a pulse width equal to the propagating packetlength. The converted electrical signal is the input of acurrent driver injecting carriers (Ipump) in the SOA activeregion to provide the necessary gain to the input packet.SOAs used as switches have been demonstrated to switchin the sub-nanosecond range [38–40] and can be used toswitch packets in broadcast-and-select space-switches [26–28].Despite the high switching speed capability, a guard timemust be introduced for each time-slot. The duration of theguard time depends on the rising time of the enabled SOA.Faster switching time can be achieved with a higher biascurrent used in the idle state as long as it is below the SOAtransparency condition [41,42]. However, such a bias currentalso negatively affects the extinction ratio [43]; hence there isa tradeoff between the switching speed, the extinction ratio,and the power dissipation of the SOA when idle.

V. PERFORMANCE ANALYSIS

The performance of the ST architecture is evaluatedand compared with the space–wavelength (SW) architecturepresented in [26] and a single-plane space architecture (S)discussed in Section II. The metrics of interest in theassessment are the physical layer scalability, the networkperformance, and the power consumption.

A. Scalability

The scalability in size of the ST architecture is determinedby the limitation of the switching domains, as shown in

O/E

SOA

Ipump

Fig. 6. (Color online) Energy-efficient self-enabled SOA.

Fig. 1(a). The maximum number of cards that the networkcan support is constrained by the optical signal-to-noiseratio (OSNR) degradation experienced by the WDM packetswhen traversing the M×M space-switch interconnection. Thephysical layer analysis has been done using commercial opticalsystem software (OptiSystem). The SOA has a noise figureof 8.6 dB and an output saturation power of 15.6 dBm [44].The physical layer analysis accounts for both saturationpower and ASE noise accumulation from the SOA devicesin the datapath of the WDM packet. At a modulation rateof 50 Gb/s and 8 ports per card, the bit-error rate is lowerthan 10−9 for M up to 8192 cards for a total of 216 ports.The scalability to 8192 cards is four times higher than thescalability of the SW architecture and eight times higherthan the scalability of the S architecture [26]. The maximumnumber of ports per card (N) that the network can supportis constrained by the wavelength-striped technique used forpacket time-compression. Since the time-compression is basedon WDM, N is limited by the maximum number of wavelengthsthat can be used in the C band with an adequate physical layerperformance. While a large port count is possible, eight portsare chosen in the proposed architecture as no amplification isnecessary in the PWM.

Greater throughput can be achieved through the use ofcomplex modulation formats. By encoding more bits persymbols as in 100 Gb/s differential quadrature phase shiftkeying (DPQSK), the maximum throughput can be increased(by a factor of 2 in the case of DPQSK) without any changes tothe network architecture as the interconnection is transparentto the data rate and modulation format. By using more complexmodulation formats, the energy consumption increases due tothe more complex optical modulators (e.g., nested modulators)but in a linear way with the overall number of ports.

B. Network Performance

The network performance of the ST architecture is drivenby the performance of the intra-card and inter-card scheduleralgorithms and affects both the throughput of the network andthe queuing delay experienced by the packets in the inputbuffers. The schedulers avoid packet collisions and are ableto ensure the delivery of all the packets to the output ports,leading to 100% throughput [25]. Therefore the level of loadalso corresponds to the effective network utilization as packetsare transmitted between interconnected cards. The maximumthroughput of the ST network is MN/T packets per second.However, such a theoretical value is difficult to achieve due tothe necessity of introducing a guard time for each time-slot.

Liboiron-Ladouceur et al. VOL. 3, NO. 8/AUGUST 2011/J. OPT. COMMUN. NETW. A7

Assuming a guard-time duration of kT/N seconds, where k isa ratio normalized to the WDM packet duration, the time-slotand the time-frame durations increase to T/N(1+k) and T(1+k), respectively, and the maximum throughput would drop toMN/[T(1+k)] with a relative performance loss of k/(1+k).

The queuing delay is evaluated here to assess whetherthe limited scalability of the number of ports per card(i.e., N ≤ 8) imposed by the physical layer is detrimental. Twoconfigurations of the interconnection network are considered.Both configurations have the same maximum throughput, i.e.,the same number of total input ports (MN = 4096 and MN =8192). The simulations are performed using the maximalmatching algorithm iSLIP [45] in the second step of theTSS [25]. The packets are generated according to an ON/OFFMarkov modulated model, with a mean ON duration equal to32 packets and with uniform distribution on the destinations(i.e., output ports and cards).

Figure 7 shows how the queuing delay is affected by thevarying number of ports per card, N, without consideringthe scalability limitation imposed by the physical layer.Independently of the considered loads, the queuing delayimproves when increasing N from 2 ports up to reach aminimum whose value is load dependent. Such behavior can beexplained as follows: when N is low (i.e., with a small numberof time-slots), it is more probable that all the packets storedin different input buffers of a card are destined for the sameoutput port, i.e., must be transmitted in the same time-slot.Thus, multiple time-frames are necessary to accommodatethem, leading to an increased delay. Increasing the number ofports mitigates this problem since the probability of findinga maximal matching (and thus sending one packet for eachtime-slot) improves. When the number of ports per card isfurther increased, the behavior of the queuing delay dependson the load. For medium loads (e.g., 0.5 in the figure), thequeuing delay is almost constant. As the load increases(e.g., 0.8 and 0.9), the delay performance degrades with N. Athigh loads the comparison of the delay performance for theconfigurations with MN = 4096 and MN = 8192 ports showsthat the delay difference is minimal and mainly experiencedfor high values of N. Such differences and the degradation inperformance for large N depend on iSLIP behavior at highloads. In fact, in these conditions, iSLIP is known to havepoor performance for small size matching problems [45]. Inthe plot, the problem size (in number of cards M) decreaseswhen passing from MN = 8192 to 4096 for a fixed N and whenmoving along the x-axis (i.e., increasing N with fixed MN).

In summary, the delay performance indicates that a lowvalue of N (ranging from 4 to 16) is preferable as it ensuresa minimal delay for high loads (with N = 8 being theoptimal value) and a limited delay at medium–low loads. Thescalability limitation of up to N = 8 ports per card imposed byphysical layer performance is in fact leading to better delayperformance at high loads and good performance at mediumand low loads.

C. Energy Consumption

The energy consumption of the M×M space-switch intercon-nection and the overall ST architecture is evaluated keeping in

1

102

3

0 16 32 48 64 80 96 112 128

Ports per card (N)

load = 0.5

load = 0.8

load = 0.9MN = 4096

MN = 8192

10

10

Que

uing

del

ay [

pack

ets]

Fig. 7. (Color online) Queuing delay versus number of ports.

consideration the power consumptions of the optical devices inactive and idle modes. The devices contributing to the powerdrainage are laser arrays (8×200 mW [46]), modulators anddrivers (225 mW), SOAs (5 mW when idle, 455 mW whenenabled [44,47]), and receivers (250 mW). The overall powerconsumption per bit/s (energy per bit) of the ST architectureis compared with the power consumption of the SW and Sarchitectures, as a function of the network utilization.

When the network utilization increases, a large numberof packets are switched and therefore a large number ofoptical devices are active and drain power. In particular, it isassumed that the SOAs in the M×M space-switch are enabledwhen WDM packets need to be switched, or idle otherwise.Therefore, the average power consumption of the SOA islinearly increasing with the average network utilization. Also,it is assumed that the receivers, the modulators, and thedrivers drain more power when modulating. More specifically,the power consumption of the modulator increases from225 mW to 300 mW when utilized. The increase in powerconsumption of the receiver is negligible (1 mW). Finally, thelaser arrays are assumed to be always on, independently ofthe level of network utilization. As a result, the average powerdrained by SOAs is more utilization dependent than the otherdevices.

The energy per bit of the SOA-based M×M space-switchinterconnection is shown in Fig. 8 for different numbersof interconnected cards M. The results for M = 32 cards(solid lines in the figure) show an energy per bit of a fewpicojoules and are similar to previous works on SOA-basedspace-switches [48]. As the network utilization increases, theenergy per bit is almost constant or decreasing. A utilization-independent energy per bit means that the energy efficiencyis optimal and that the number of active SOAs increaseslinearly with the network utilization. In the consideredM×M space-switch interconnection with broadcast-and-selectarchitecture, the SOA used for amplification at the outputstage must always be active. This is why their energy per bitimproves with the network utilization. In addition, the amountof power associated with the SOAs in idle mode decreaseswith the network utilization, leading to an improvement ofthe energy efficiency at a high level of utilization. The figure

A8 J. OPT. COMMUN. NETW./VOL. 3, NO. 8/AUGUST 2011 Liboiron-Ladouceur et al.

-12

10 -11

10 -10

-9

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

8192 × 81921024 × 102432 × 32

10

10Jo

ules

per

bit

0.1 1

Network utilization

5 mW idle0.5 mW idle

Fig. 8. (Color online) Energy per bit for the SOA-based M×Mspace-switch interconnection for 5 mW and 0.5 mW power dissipationof the SOA in idle mode.

also shows that the energy consumption is affected by theswitch size M, since the number of SOA devices increases asthe interconnection scales. The increase in the total number ofSOAs with M2 explains the increase of energy per bit for largerspace-switch sizes. The number of active SOAs scales linearlywith M; therefore the increase in power consumption is mainlydue to the idle SOAs. In fact, there is a significant drop of theenergy per bit when the idle power of the SOAs (due to thedrained bias current) is reduced to 10% (from 5 mW to 0.5 mW).For large space-switch sizes, the drop in energy consumptionis almost one order of magnitude. SOA devices with their idlemode consuming close to zero power (0.5 mW, dashed linesin the figure) would enable low energy per bit of the order ofpicojoules per bit for interconnection network sizes up to 1024cards. Technological progress and innovations suggest that nocurrent could be used in the idle mode and a switching time inthe range of nanoseconds would be possible [48].

The energy per bit of the SW interconnection network isquantified by adding the energy consumption of the M×Mspace-switch interconnection to the energy consumption of thelaser arrays, the receivers, the modulators, and the drivers.The energy per bit is evaluated as a function of the networkutilization in Fig. 9 for different sizes M×N of the networkarchitecture and it is compared with S and ST architectures.

As discussed in Subsection V.A, the ST architecture scalesup to 8192×8. In contrast, the S and SW architecturesscale up to 1024×1 and 512×8, respectively, as derivedin [26], primarily limited by the physical layer. For allthree architectures, the energy consumption decreases at highnetwork utilization. This reduction is only in part due to thebehavior of the energy consumption of the M×M space-switchinterconnection (Fig. 8). The main reason for the reductionis due to the energy consumption of the laser arrays thatis constant independently of the network utilization, makingthe network more power-efficient at high utilization levels.The use of self-enabling technology and SOAs with low poweridle mode allows compensation for the power dissipation ofthe laser arrays. The figure shows also that the single-planearchitecture (S) consumes more energy per bit than themulti-plane architectures (ST and SW). When comparing the

10-10

10-9

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Joul

es p

er b

it

1024 × 1 (S)128 × 8 (ST)128 × 8 (SW)512 × 8 (ST)512 × 8 (SW)

1024 × 8 (ST)1024 × 8 (SW)2048 × 8 (ST)8192 × 8 (ST)

0.1 1

Network utilization

Fig. 9. (Color online) Energy per bit of the space–time (ST)architecture compared with the space–wavelength (SW) and thesingle-plane (S) architectures for various network sizes M×N (idleSOA dissipates 5 mW).

three architectures with the same overall number of ports(i.e., 1024), the 1024×1 single-plane architecture (S) consumesmore energy per bit than the 128×8 multi-plane architectures(ST and SW). The energy effectiveness of the multi-planearchitectures also holds when increasing their port count. Or,in other words, for the same energy per bit (corresponding tothe energy per bit of the 1024×1 S) the SW architecture canbe designed with an 8-times higher port count and the STarchitecture can be designed with a 64-times higher port count.Among the multi-plane architectures, the SW architectureis more energy efficient than ST only when the number ofcards is low (i.e., M = 128 or lower). Interestingly, the energyconsumption of the ST architecture increases more slowlywith the network size and thus is more energy efficient thanSW when M increases further. The reason for the betterscalability is mainly due to the different sizes and complexitiesof the space-switches: the ST architecture requires an M×Mspace-switch that can be realized with M switches 1×Mand M couplers M:1, whereas the SW architecture requiresNM×M space-switches (and couplers) per card, leading to MNswitches (and couplers). Thus, the number of switches andcouplers in ST architecture is reduced by a factor of N withrespect to the SW architecture. This makes the ST architecturenot only more scalable in size but also in energy consumption.

VI. CONCLUSION

This paper presented an innovative and energy-efficientarchitecture for optical interconnection networks, based onspace and time domains to switch packets between cardsand ports, respectively. Space switching is achieved by takingadvantage of self-enabled SOAs. Time switching requires time-compression of the packets and is achieved by transmitting thepacket bits in parallel on the different wavelengths to generateWDM packets. The energy efficiency is improved by setting orself-enabling SOAs to idle when unused and by exploiting atotally passive technique for generating WDM packets using awavelength-striped approach.

Liboiron-Ladouceur et al. VOL. 3, NO. 8/AUGUST 2011/J. OPT. COMMUN. NETW. A9

The study on the feasibility of the proposed architecturereveals some interesting strengths of the space–time archi-tecture. The architecture can be implemented by using therecent progress on silica-based technology to integrate theoptical devices on a silicon substrate. Although the passivewavelength-striped implementation is challenging and limitsthe maximum number of wavelengths (and thus of portsper card) to eight, such a number is found to be idealfrom the network performance point of view. In addition,the ST architecture benefits from the known advantages ofmulti-plane architectures, namely, higher scalability in size,better network performance, and lower power consumption.The ST architecture outperforms the other multi-planearchitecture (i.e., space–wavelength architecture) in terms ofscalability in size and power, as the number of switches andcouplers required for space switching is reduced by a factorequal to the number of cards. The energy efficiency, the highstability of the power consumption with network size, and thesuperior scalability in size make the ST architecture a goodcandidate for overcoming these issues in future data centers.

ACKNOWLEDGMENTS

The work described in this paper was carried out with supportin part by the National Sciences and Engineering ResearchCouncil of Canada (NSERC), le Fonds québécois de recherchesur la nature et la technologie (FQRNT), as well as bythe Italian Ministry of Foreign Affairs, Directorate-Generalfor Country Promotion, through the high-relevance bilateralproject “Réseaux Optiques D’INterconnexions extensibles àhaute efficacité énergétique (RODIN).”

REFERENCES

[1] N. Farrington, G. Porter, S. Radhakrishnan, H. H. Bazzaz,V. Subramanya, Y. Fainman, G. Papen, and A. Vahdat, “Helios:a hybrid electrical/optical switch architecture for modular datacenters,” Comput. Commun. Rev., vol. 40, pp. 339–350, Aug. 2010.

[2] L. Barroso, J. Dean, and U. Holzle, “Web search for a planet:the Google cluster architecture,” IEEE Micro, vol. 23, no. 2,pp. 22–28, Mar./Apr. 2003.

[3] A. Greenberg, P. Lahiri, D. A. Maltz, P. Patel, and S. Sen-gupta, “Towards a next generation data center architecture:scalability and commoditization,” in Proc. of the ACM Workshopon Programmable Routers for Extensible Services of Tomorrow(PRESTO ’08), 2008, pp. 57–62.

[4] L. Barroso and U. Holzle, “The case for energy-proportionalcomputing,” Computer, vol. 40, no. 12, pp. 33–37, Dec. 2007.

[5] D. Meisner, B. T. Gold, and T. F. Wenisch, “PowerNap: elimi-nating server idle power,” in Proc. of the 14th Int. Conf. on Ar-chitectural Support for Programming Languages and OperatingSystems (ASPLOS ’09), 2009, pp. 205–216.

[6] Intel Xeon Processor Data Center Optimization and CERN open-labs, “Reducing data center energy consumption,” Intel XeonProcessor White Paper, 2008.

[7] K. G. Brill, “The invisible crisis in the data center: the economicmeltdown of Moore’s law,” White Paper, Uptime Institute, 2007.

[8] J. Humphreys and J. Scaramella, “The impact of power andcooling on data center infrastructure,” Market Research Report,IDC, 2006.

[9] C. L. Belady, “In the data center, power and coolingcosts more than the IT equipment it supports,”Electronics Cooling, Feb. 2007 [Online]. Available:http://www.electronics-cooling.com/2007/02/in-the-data-center-power-and-cooling-costs-more-than-the-it-equipment-it-supports/.

[10] P. Pepeljugoski, J. Kash, F. Doany, D. Kuchta, L. Schares,C. Schow, M. Taubenblatt, B. Offrein, and A. Benner, “Towardsexaflop servers and supercomputers: the roadmap for lowerpower and higher density optical interconnects,” in 36th Eu-ropean Conf. on Optical Communication (ECOC), Sept. 2010,pp. 1–14.

[11] Energy Star Program, Report to congress on server and datacenter energy efficiency: Public law 109-431, US EnvironmentalProtection Agency, 2007.

[12] S. Pelle, D. Meisner, T. F. Wenisch, and J. W. VanGilder, “Un-derstanding and abstracting total data center power,” in Proc.Workshop on Energy Efficient Design (WEED), 2009.

[13] J. G. Koomey, “Worldwide electricity used in data centers,”Environ. Res. Lett., vol. 3, no. 3, pp. 1–8, 2008.

[14] D. A. B. Miller, “Device requirements for optical interconnectsto silicon chips,” Proc. IEEE, vol. 97, no. 7, pp. 1166–1185, July2009.

[15] V. Soteriou and L.-S. Peh, “Exploring the design space ofself-regulating power-aware on/off interconnection networks,”IEEE Trans. Parallel Distrib. Syst., vol. 18, no. 3, pp. 393–408,Mar. 2007.

[16] D. Abts, M. R. Marty, P. M. Wells, P. Klausler, and H. Liu, “En-ergy proportional datacenter networks,” in Proc. of 37th Annu.Int. Symp. Computer Architecture (ISCA ’10), 2010, pp. 338–347.

[17] H. Cho, P. Kapur, and K. Saraswat, “Power comparison betweenhigh-speed electrical and optical interconnects for interchip com-munication,” J. Lightwave Technol., vol. 22, no. 9, pp. 2021–2033,Sept. 2004.

[18] A. Benner, “Cost-effective optics: enabling the exascaleroadmap,” in 17th IEEE Symp. on High PerformanceInterconnects (HOTI), Aug. 2009, pp. 133–137.

[19] D. A. B. Miller, “Rationale and challenges for optical intercon-nects to electronic chips,” Proc. IEEE, vol. 88, no. 6, pp. 728–749,June 2000.

[20] X. Chen, L.-S. Peh, G.-Y. Wei, Y.-K. Huang, and P. Prucnal,“Exploring the design space of power-aware opto-electronic net-worked systems,” in Proc. Int. Symp. High-Performance Com-puter Architecture, Feb. 2005, pp. 120–131.

[21] R. S. Tucker, “Green optical communications—part II: Energylimitations in networks,” IEEE J. Sel. Top. Quantum Electron.,vol. 17, no. 2, pp. 261–274, Mar./Apr. 2011.

[22] R. S. Tucker, “The role of optics and electronics in high-capacityrouters,” J. Lightwave Technol., vol. 24, no. 12, pp. 4655–4673,Dec. 2006.

[23] E. Bonetto, D. Cuda, G. A. G. Castillo, and F. Neri, “The role ofarrayed waveguide gratings in energy-efficient optical switchingarchitectures,” in Optical Fiber Communication Conf. and Ex-hibit (OFC), 2010, OWY4.

[24] R. Gaudino, G. Castillo, F. Neri, and J. Finochietto, “Can simpleoptical switching fabrics scale to terabit per second switch capac-ities?” J. Opt. Commun. Netw., vol. 1, no. 3, pp. B56–B69, Aug.2009.

[25] P. G. Raponi, N. Andriolli, I. Cerutti, and P. Castoldi, “Two-stepscheduling framework for space–wavelength modular opti-cal interconnection networks,” IET Commun., vol. 4, no. 18,pp. 2155–2165, Dec. 2010.

A10 J. OPT. COMMUN. NETW./VOL. 3, NO. 8/AUGUST 2011 Liboiron-Ladouceur et al.

[26] O. Liboiron-Ladouceur, I. Cerutti, P. G. Raponi, N. Andriolli, andP. Castoldi, “Energy-efficient design of a scalable optical multi-plane interconnection architecture,” IEEE J. Sel. Top. QuantumElectron., vol. 17, no. 2, pp. 377–383, Mar./Apr. 2011.

[27] T. Lin, K. Williams, R. Penty, I. White, and M. Glick, “Capacityscaling in a multihost wavelength-striped SOA-based switchfabric,” J. Lightwave Technol., vol. 25, no. 3, pp. 655–663, Mar.2007.

[28] R. Hemenway, R. Grzybowski, C. Minkenberg, and R. Luijten,“Optical-packet-switched interconnect for supercomputer appli-cations,” J. Opt. Netw., vol. 3, no. 12, pp. 900–913, Dec. 2004.

[29] O. Liboiron-Ladouceur, H. Wang, A. S. Garg, and K. Bergman,“Low-power, transparent optical network interface for highbandwidth off-chip interconnects,” Opt. Express, vol. 17, no. 8,pp. 6550–6561, Apr. 2009.

[30] W. Dally and B. Towles, Principles and Practices of Intercon-nection Networks. Morgan Kaufmann, San Francisco, CA, USA,2003.

[31] M. Moller, “High-speed electronic circuits for 100 Gb/s transportnetworks,” in Optical Fiber Communication Conf. and Exhibit(OFC), Mar. 2010, OThC6.

[32] J. LeGrange, J. Simsarian, P. Bernasconi, L. Buhl, J. Gripp,and D. Neilson, “Demonstration of an integrated buffer for anall-optical packet router,” IEEE Photon. Technol. Lett., vol. 21,no. 12, pp. 781–783, June 2009.

[33] J. Bauters, M. Heck, D. John, M.-C. Tien, A. Leinse, R. Heide-man, D. Blumenthal, and J. Bowers, “Ultra-low loss silica-basedwaveguides with millimeter bend radius,” in 36th European Conf.on Optical Communication (ECOC), Sept. 2010.

[34] K. Jinguji and T. Yasui, “Synthesis of one-input M-output op-tical FIR lattice circuits,” J. Lightwave Technol., vol. 26, no. 7,pp. 853–866, Apr. 2008.

[35] S. Kakehashi, H. Hasegawa, K.-i. Sato, O. Moriwaki, andS. Kamei, “Analysis and development of fixed and variablewaveband MUX/DEMUX utilizing AWG routing functions,” J.Lightwave Technol., vol. 27, no. 1, pp. 30–40, Jan. 2009.

[36] J. Ito and H. Tsuda, “Small bend structures using trenchesfilled with low-refractive index material for miniaturizing silicaplanar lightwave circuits,” J. Lightwave Technol., vol. 27, no. 6,pp. 786–790, Mar. 2009.

[37] G. Maxwell, A. Poustie, C. Ford, M. Harlow, P. Townley, M. Nield,T. Lealman, S. Oliver, L. Rivers, and R. Waller, “Hybrid in-tegration of monolithic semiconductor optical amplifier arraysusing passive assembly,” in Proc. 55th Electronic Componentsand Technology Conf., May/June 2005, vol. 2, pp. 1349–1352.

[38] C. Gallep and E. Conforti, “Reduction of semiconductor opti-cal amplifier switching times by preimpulse step-injected cur-rent technique,” IEEE Photon. Technol. Lett., vol. 14, no. 7,pp. 902–904, July 2002.

[39] O. Liboiron-Ladouceur and K. Bergman, “Optimization of aswitching node for optical multistage interconnection networks,”IEEE Photon. Technol. Lett., vol. 19, no. 20, pp. 1658–1660, Oct.2007.

[40] O. Liboiron-Ladouceur, A. Shacham, B. Small, B. Lee, H. Wang,C. Lai, A. Biberman, and K. Bergman, “The data vortex opticalpacket switched interconnection network,” J. Lightwave Technol.,vol. 26, no. 13, pp. 1777–1789, July 2008.

[41] C. Tai and W. Way, “Dynamic range and switching speed lim-itations of an N×N optical packet switch based on low-gainsemiconductor optical amplifiers,” J. Lightwave Technol., vol. 14,no. 4, pp. 525–533, Apr. 1996.

[42] E. Burmeister and J. Bowers, “Integrated gate matrix switch foroptical packet buffering,” IEEE Photon. Technol. Lett., vol. 18,no. 1, pp. 103–105, Jan. 2006.

[43] A. Ehrhardt, M. Eiselt, G. Grossopf, L. Kuller, R. Ludwig,W. Pieper, R. Schnabel, and H. Weber, “Semiconductor laser am-plifier as optical switching gate,” J. Lightwave Technol., vol. 11,no. 8, pp. 1287–1295, Aug. 1993.

[44] S. Tanaka, S.-H. Jeong, S. Yamazaki, A. Uetake, S. Tomabechi,M. Ekawa, and K. Morito, “Monolithically integrated 8:1 SOAgate switch with large extinction ratio and wide input powerdynamic range,” IEEE J. Quantum Electron., vol. 45, no. 9,pp. 1155–1162, Sept. 2009.

[45] N. McKeown, “The iSLIP scheduling algorithm for input-queuedswitches,” IEEE/ACM Trans. Netw., vol. 7, no. 2, pp. 188–201,Apr. 1999.

[46] H. Zhu, X. Xu, H. Wang, D. Kong, S. Liang, L. Zhao, and W. Wang,“The fabrication of eight-channel DFB laser array using sampledgratings,” IEEE Photon. Technol. Lett., vol. 22, no. 5, pp. 353–355,Mar. 2010.

[47] N. Sahri, D. Prieto, S. Silvestre, D. Keller, F. Pommerau, M. Re-naud, O. Rofidal, A. Dupas, F. Dorgeuille, and D. Chiaroni, “Ahighly integrated 32-SOA gates optoelectronic module suitablefor IP multi-terabit optical packet routers,” in Optical FiberCommunication Conf. and Exhibit (OFC), 2001, vol. 4, PD32.

[48] A. Albores-Mejia, F. Gomez-Agis, H. Dorren, X. Leijtens, T. deVries, Y.-S. Oei, M. Heck, R. Notzel, D. Robbins, M. Smit, andK. Williams, “Monolithic multistage optoelectronic switch circuitrouting 160 Gb/s line-rate data,” J. Lightwave Technol., vol. 28,no. 20, pp. 2984–2992, Oct. 2010.

Odile Liboiron-Ladouceur (M’95) receivedher B.Eng. degree in electrical engineeringfrom McGill University, Montréal, QC, Canada,in 1995 and her M.S. and Ph.D. degrees inelectrical engineering from Columbia Univer-sity, New York, in 2003 and 2007, respec-tively. Her doctoral research work focusedon the physical layer of optical interconnec-tion networks for high-performance computing.In 2007, Dr. Liboiron-Ladouceur received a

post-doctoral fellowship from the Natural Sciences and EngineeringResearch Council of Canada. She is currently an Assistant Professorin the Electrical and Computer Engineering Department at McGillUniversity. Her research interests include energy-efficient photonicinterconnects for high-performance optical systems. She is the authoror co-author of over 40 papers in peer-reviewed journals andconferences.

Pier Giorgio Raponi received his Laureadegree (B.Eng.) and his Laurea Specialisticadegree (M.S.), both in telecommunicationsengineering, from the University of Pisa in2004 and 2009, respectively. He was anundergraduate student at Scuola SuperioreSant’Anna in Pisa from 2001 to 2008 wherehe received a Diploma degree in 2004 withhonors. He is currently a Ph.D. student atScuola Superiore Sant’Anna, in the Centre of

Excellence for Information and Communication Engineering (CEIICP).His research interests include fast switching architectures, schedulingalgorithms and design and analysis of packet-switched opticalnetworks and nodes.

Liboiron-Ladouceur et al. VOL. 3, NO. 8/AUGUST 2011/J. OPT. COMMUN. NETW. A11

Nicola Andriolli received his Laurea degreein telecommunications engineering from theUniversity of Pisa, Pisa, Italy, in 2002, andhis Diploma and Ph.D. degrees from ScuolaSuperiore Sant’Anna, Pisa, in 2003 and 2006,respectively. He was a visiting student atBudapest University of Technology and Eco-nomics (BUTE), Budapest, Hungary, and atthe Department of Communications, Opticsand Materials of the Technical University of

Denmark (COM DTU), Copenhagen, Denmark, and he was a visitingtrainee at the National Institute of Information and CommunicationsTechnology (NICT), Tokyo, Japan. He is currently an AssistantProfessor at Scuola Superiore Sant’Anna. His research interestsinclude network modeling and simulation, QoS and fault tolerance inoptical networks, generalized multi-protocol label switching (GMPLS)architecture, and optical packet switching.

Isabella Cerutti holds a Ph.D. and a Laureadegree in electrical engineering from theUniversity of Texas at Dallas, USA (2002) andfrom the Politecnico di Torino, Italy (1998),respectively. From 2002 to 2006, she was aPost-doctoral Research Associate at the Uni-versity of Texas at Dallas and then at ScuolaSuperiore Sant’Anna, Italy. She is currentlyan Assistant Professor at Scuola SuperioreSant’Anna. She has co-authored more than 50

publications in international journals and conference proceedings.Her research interests include performance evaluation and design ofoptical and wireless networks, with special emphasis on the energyefficiency.

Mohammed Shafiqul Hai receivedhis B.Sc. degree in electrical and electronicengineering from Bangladesh University of En-gineering and Technology, Dhaka, Bangladesh,in 2007. He is currently pursuing his Mastersat the Department of Electrical and ComputerEngineering at McGill University, Montreal,Canada. His research interests include model-ing and characterization of CMOS compatiblecompact nanophotonic devices on silicon on

insulator platforms and components for next generation optical fiberand RF communication.

Piero Castoldi (M’97) received his MastersDegree from the University of Bologna, Italy,in 1991 and his Ph.D. degree in informationtechnology from the University of Parma, Italy,in 1996. He is currently an Associate Professorat Scuola Superiore Sant’Anna, Pisa, Italy,where he is Area Leader of the “Networksand Services” area. Since January 2005 hehas also been the Director of the CNITNational Laboratory of Photonic Networks. His

recent research interests cover reliability, switching paradigms, andcontrol for optical networks, including application-network cooperationmechanisms. He is the author of more than 170 publicationsin international journals and conference proceedings. During theacademic year 1996/97 he was a Visiting Post-doc Researcher at theDepartment of Electrical Engineering of Princeton University, USA.He was also at Princeton during the summers of 1999 and 2000 as aVisiting Professor. From December 1997 until February 2001 he wasAssistant Professor at the Faculty of Engineering of the University ofParma.