1114 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 3, NO. 7, JULY 2013

3-D Stacking of Ultrathin Chip Packages: AnInnovative Packaging and Interconnection

TechnologySwarnakamal Priyabadini, Student Member, IEEE, Tom Sterken,

Luc Van Hoorebeke, and Jan Vanfleteren, Member, IEEE

Abstract— In order to increase the functionality of electronicdevices, while reducing the overall size and weight of the elec-tronic chip packages, electronic chip packages can be combinedinto a 3-D assembly. In this field, we present a technologyfor stacking multiple chip packages, resulting in total volumealmost equal to that of a single bare die. The technology isbased on batch-processed ultrathin chip packages (UTCPs) with afine pitch metal fan-out. Package-on-package technology enablesstacking of UTCPs by vacuum lamination, followed by through-hole interconnection technology for making contacts to the metalfan-out of the embedded UTCPs within the stack. The individualchip packages can be tested before stacking.

Index Terms— 3-D stacking, EEPROM memory die stacking,multi ultrathin chip package (UTCP), through-hole (TH)interconnection, vacuum lamination.

I. INTRODUCTION

THE GROWING demand for portable electronic devices isthe driving force behind the development of high-density

interconnection (HDI) technology. 3-D stacking of ultrathinchip packages (UTCPs) is one of these HDI technologies. Thispaper describes an approach to produce miniaturized modularpackages by using UTCP [1]–[3], package-on-package (PoP)[4], [5], and through-hole (TH) microvia [6], [7] technologies.UTCP technology is a board-level packaging concept, basedon embedding of ultrathin chips (chip thickness ∼20 μm)within two 20-μm-thick spin-on polyimide layers resulting ina thin flexible chip package with a thickness of ∼50 μm [3].The use of the PoP concept [4]–[5] enables stacking offour sheets of such chip packages by vacuum lamination.This process is similar to the printed circuit board (PCB)manufacturing process, which is a cheap and fast way ofproducing such stacks. Package-to-package interconnections

Manuscript received August 6, 2012; revised October 29, 2012; acceptedNovember 27, 2012. Date of publication January 14, 2013; date of currentversion July 2, 2013. This work was supported in part by EU throughTIPS Project under Contract FP7-224535. Recommended for publication byAssociate Editor L. Daniel upon evaluation of reviewers’ comments.

S. Priyabadini, T. Sterken, and J. Vanfleteren are with the Center forMicrosystems Technology (affiliated with IMEC and Ghent University),Department of Electronics and Information Systems, Ghent University,Ghent B-9000, Belgium (e-mail: swarnakamal.priyabadini@ugent.be;tom.sterken@ugent.be; jan.vanfleteren@ugent.be).

L. Van Hoorebeke is with the UGCT-Department of Physics and Astron-omy, Ghent University, Faculty of Sciences, Ghent 9000, Belgium (e-mail:Luc.VanHoorebeke@ugent.be).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TCPMT.2012.2234830

are made by laser drilling of TH vias (THV) [6]–[8] inthe outer contact pads of the stacked packages, followed bymetallization of these THVs by Cu electroless deposition andelectroplating [6]–[7]. Top- and bottom-side Cu patterningfollowed by dicing produces individual chip stacks with a totalthickness of 300 μm, embedding four thin dies within it.

A brief introduction to this technology with some prelimi-nary results was presented by Priyabadini et al. [9]. This paperdescribes the whole flow process in producing stacked UTCPs,subsequent results after each process with implementation ofthis technology in producing stacked EEPROM die packages.Additionally, failure analysis and scope of further developmentin this technology for future application have been explainedin great detail.

II. UTCP CONCEPT

The UTCP technology is a chip embedding technologywhich includes thinning down of the active componentto ∼20 μm and subsequent embedding within two spin-on polyimide layers (∼20 μm each). In this process, thebase layer (polyimide) is spun and cured on a rigid car-rier (glass). The ultrathin dies are picked and placed onan adhesive material (e.g., BCB) which is spin-coated onthe cured bottom polyimide layer and cured during thechip bonding process. Finally, the chips are fully embeddedby spinning and curing a top polyimide layer. The con-nection to the outer world is made by opening microviason the contact pads of the embedded chips. This can berealized by laser drilling, dry etching, or photolithography(when photosensitive polyimide is used). Metallization isdone by sputter deposition of TiW (50 nm)/Cu (1 μm)as a seed layer, followed by the electroplating of copper upto a thickness of ∼5 μm. The patterning of metal is done bya wet-etching process in combination with lithography. Thewhole flow process is reported by many of the researchers ofour group in past couple of years [1]–[3], [17]–[19].

III. UTCP STACKING CONCEPT

An overview of the flow process for the stacked UTCPtechnology is shown in Fig. 1. The base materials for theproduction of stacks are UTCPs with identical or differingfan-out patterns. From cost point of view, production ofmultiple UTCPs on a single panel is mandatory for achieving3-D integration of chip packages by stacking technology and

2156-3950/$31.00 © 2013 IEEE

PRIYABADINI et al.: 3-D STACKING OF UTCPs: PACKAGING AND INTERCONNECTION TECHNOLOGY 1115

Step 1. Production of individual sheets of MultipleUTCPs

Step 3. After stacking of all layers by vacuum lamination technology

Step 5. Dicing of individual stacks by laser cutting after top and bottom side metal patterning

Step 4. Through hole drilling on contact pads of the embedded packages by laser ablation, followed by metallizing them by electroless/ electroplated Cu deposition

Step 2. Individual sheets of UTCPs and extra copper flexes at top and bottom with adhesive films in between

Fig. 1. Process flow for UTCP Stacking.

precise placement of chips on a base substrate is one of theimportant steps which can affect the package production yield.After testing the yield, these packages can be released easilyfrom the carrier and stacked together with thin adhesive layersin-between by vacuum lamination technology. For top andbottom metallization layers, two extra Cu flexes are laminatedon both sides of the stacks. Interconnection within individualpackages happens by making THs on the outer contact padsof the stacked UTCPs, followed by an electroless/electroplatedcopper deposition.

The different materials used for building the stacks are givennext with their inbuilt physical and mechanical properties(as per the data sheet) to make the overall module moredurable and robust.

1) PI 2611: Base material for UTCP production [10].2) Pyralux LF100 (DuPont) of thickness 25 μm: Adhesive

material [11] for PoP bonding.3) Upilex foil SR 1410 from UBE Inc. with 25 μm

polyimide/9-μm copper [12]: As top layer of the UTCPstack.

4) 9-μm-thick Cu flex (TW-YE) from the circuit foil [13]:As a bottom layer of the UTCP stack.

A. Multi UTCP Fabrication, Testing, and Release

These multi UTCPs are fabricated on a 6 square glasssubstrate with 500-nm-thick thermally evaporated KCl (salt) as

Fig. 2. Layout for alignment holes on UTCP sheets (left), size of each hole(right).

a release layer [3]. After processing, the electrical connectivityand/or functionality of the UTCPs can be tested on the fan-out metallization, in order to create a mapping of functionalpackaged chips on each substrate. This process makes it easyto sort out the nonfunctional stacks before starting the stackingprocess. For the mechanical alignment of the PoP duringlamination, four pin holes are made on each sheet of UTCPsby the YAG laser. Additionally, laser cutting at the edges ofeach sheet is performed for easy release of the UTCP sheetfrom its glass carrier. Fig. 2 shows the layout for this lasercutting process.

1116 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 3, NO. 7, JULY 2013

TABLE I

LASER PARAMETERS FOR UTCP RELEASE PROCESS

Laser Laser Speed Ablated Surface

355 nmYAG,

500 mWPower

2.5 mm/s Making holes onPI (30 μm)-Cu (7 μm) surface

5 mm/s Cutting the PI (30 μm)

Fig. 3. Multi UTCP sheet release.

The laser parameters used for making holes and cutting theedges are tabulated in Table I.

The release of the multi UTCP sheets from the carrieris realized by soaking the samples in deionized water. Thecuts made at the edges of the UTCP sheet enable waterpenetration under the package. Due to the hygroscopic natureof the salt situated in-between the carrier and the UTCP sheets,the water is absorbed underneath the polyimide film, and thesalt gets dissolved. This effect ensures an easy release of theUTCP package sheets. This whole process was described byWang et al. [3]. Fig. 3 shows the individual UTCP sheetrelease process by soaking it in deionized water.

B. Vacuum Lamination Process

In order to improve the adhesion of the acrylic adhesive(LF 100) on the conductive copper lines on UTCPs withinthe stack, it is mandatory to prepare the copper surface priorto lamination. H2O2-based wet chemical treatment roughensthe surface and also creates an oxide containing group on thecopper surface which makes it beneficial for its adhesion withacrylic material during lamination process.

Sheets of 25-μm-thick Pyralux LF100 adhesive are usedin-between each UTCP sheet for realizing a stable bond, aswell as between the UTCP sheets and additional flex (topand bottom) layers (Step 2 of Fig. 1). This Pyralux LF100sheet is a proprietary B-staged modified acrylic adhesive andit is used primarily to bond flexible inner layers or rigid caplayers in multilayer lamination. Prior to lamination, the LF100is patterned according to the pattern shown in Fig. 2, usinglaser ablation. Finally all UTCP, adhesive and metal layersare placed on a dedicated lamination plate and held in placeby mechanical pin holes at the four edges to avoid shiftingduring the lamination process (Fig. 4, top). The laminationprocess is similar to a standard PCB lamination process.

Release foil

Press padRelease foil

Press pad Separator plate

Press book

Separator plate

(a)

(b)

Fig. 4. Top: multi UTCP panel (180-chip packages on a single panel)on alignment tool plates for stacking. Bottom: schematic cross section oflamination stack build-up.

Fig. 5. Temperature and pressure cycle during vacuum lamination process.

During lamination, the stack of functional layers is sandwichedbetween press pads, separator plates, and Teflon foils, asindicated in Fig. 4. The press pad, a soft material (Senpad),and the steel separator plates provide an even distribution ofthe pressure during lamination. The Teflon foil is used as arelease liner to protect the laminated stack of UTCPs.

A good adhesion at the interface of the LF 100 layer andpolyimide (PI 2611) has been verified by peel tests. Themeasured peeling strength is 1.2 N/mm or higher.

The accuracy of the alignment between the different layerswas verified after lamination with a layer-to-layer shift of20 μm in maximum. As the landing pads for the vias in thistechnology have a radius of 100 μm or higher, this shift isnegligible. The process parameters are optimized for gettinguniform thickness of the adhesive layer within the stack. Thelamination profile with graphical illustration is given in Fig. 5.

PRIYABADINI et al.: 3-D STACKING OF UTCPs: PACKAGING AND INTERCONNECTION TECHNOLOGY 1117

P1

P2

P3

P4

(a)

(b)

Fig. 6. Cross-sectional pictures of stack of four packages (P1–4) of totalthickness (a) ∼300 μm in the chip area and (b) ∼280 μm outside the chiparea.

1) Vacuum is drawn and maintained at 2 m bar.2) The adhesive starts melting at 90 °C and a low pressure

(known as kiss pressure) of 50 N/cm2 is applied for20 min.

3) Heating rate is fixed at 5 °C/min and a full pressure of250 N/cm2 is applied when the adhesive starts flowingat 130 °C.

4) The adhesive is then cures at 195 °C for 90 min.5) Finally cooling down to room temperature at the rate of

5 °C/min.

The photograph in Fig. 6 illustrates a cross section of fourstacked packages. It can be observed that the adhesive layerthickness is different within the chip packages (∼13 μm, top)and on the remaining parts of the stack (∼24 μm, bottom).By application of pressure during the flow process, the liq-uefied adhesive flows away from the chip region, where thesingle UTCP layers are thicker. This phenomenon reduces theoverall thickness variation of the stacked package to ∼20 μm.

C. Laser Drilling for Making Vias

After the lamination step, the interconnection within eachlayer of the UTCPs can be established by using TH inter-connection technology, which includes via formation and viaplating afterward. The most common via processing approachfor multilayered flexes is laser ablation technology. It is the

(a) (b)

Fig. 7. TH drilling process by laser trepanning method of (a) side view and(b) top view.

Fig. 8. Misalignment problem (120 μm shifting): TH is not at the center ofstack of contact pads problem.

cleanest and fastest material removal process that uses local-ized thermal energy caused by stimulated radiation. Nd:YAGlasers are more suitable for this particular application in gettingstructures with fine pitch than their infrared counterparts(CO2 laser). Also, the YAG laser can be frequency multipliedso that it can emit radiations from near IR to UV and it isfaster than excimer laser; therefore it is more versatile.

In our process, the THV of diameter 200 μm was realizedby using a frequency-tripled NdYAG laser (Gaussian beam).This Gaussian beam has the advantage of having a uniformprofile which favors drilling through higher thickness flex withminimum focus problem. As the via dimension (200 μm) ismuch higher compared to the laser spot size (25 μm), a lasertrepanning method (Fig. 7) is used for cutting the TH out fromthe stack by moving the laser spot in a circular orbit.

This laser ablation is a critical process which has thefollowing issues and is shown pictorially in Figs. 8–10.

1) Misalignment Issue (Fig. 8): Due to CTE mismatchbetween the polyimide 2611(3 ppm/°C) and the carrier mater-ial (glass, 8.7 ppm/°C), it has been observed (both experimen-tally and from simulation) that the fully cured polyimide hasa reproducible linear shrinkage of ∼0.2% and that leads tothe deformation in UTCP sheets when they are fabricated on

1118 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 3, NO. 7, JULY 2013

Fig. 9. Focusing problem: via could not be cut through the stack.

large substrates (e.g., 4” or 6” glass carriers). Also, the samedeformation is retained within the stack after lamination. Thisresults in misplacing the THV. This deformation needs to betaken into account during the design phase.

2) Focusing Problem (Fig. 9): As the stack itself is flexible,it stays nonflat on the carrier during the drilling process. Thisresults in incomplete drilling through the stack due to lack offocusing at certain points.

3) Undercutting Within the Stack (Fig. 10): The inhomo-geneous thermal conductivity of each underlying layer andthe shape of the laser beam influence the temperature andas a result the amount of ablated material. This impliesthat the laser parameters (pulses at a place, power) have tobe optimized to minimize the local heating/melting of thedifferent layers which could lead to undercutting. Fig. 10shows that LF100 is sensitive to undercutting.

It has been reported that laser pulses with uniform energiescan be realized either by shorter duration of the pulse accom-panied by higher peak power, or by longer pulse duration withlower peak power [8]. In the optimization of the laser drillingprocess, first the total number of pulses at one spot and thelaser power were optimized for drilling the TH out of a stackof a specified thickness (usually 300 μm). Optimized laserdrilling parameters for this process are given next.

1) Laser power (E) = 500 mW.2) Pulse repetition rate ( f ) = 10 kHz.3) Spot size of the YAG laser (d) = 25 μm.4) Pulses at a place (n1) = 10.5) Number of places per round (n2) = 3.14*D/d (here

D = TH diameter = 200 μm) = 25.6) Pulses per round (n3) = n1* n2 = 250.7) Total pulses at a place (n4) = 400 (set for stack of

300–400-μm thickness).8) Total round (n5) = n4/n1 = 40.9) Total pulses to drill one TH (N) = n2* n5 = 10 000.

10) Round per second (R) = f /n3 (input parameters fortrepanning) = 40.

To minimize the undercutting of LF 100 within the stack, thelocal heating effect during laser processing was investigated.Instead of giving the needed total number of pulses (n4) = 400at once, it is divided into shorter “salvos” (n1) of ten pulseseach at a certain spot. As the trepanning process allows the

PI 2611

Cu

LF 100

Fig. 10. Undercutting problem: Acrylic material (LF100) melting out underthe polyimide layer due to thermal effect.

Fig. 11. Cross-sectional view of the TH drilled with optimized laserparameters (Power 500 mW, frequency 10 kHz, Energy ∼500 mJ, andtime ∼1 s).

rotation of the laser to make a circle of desired TH dimension(here, D = 200 μm), the total pulses at a place were deliveredby making a number of rotations n5 = 40. By choosing avery small n1 value, the rotation speed (R) increases whichdoes not add much difference to the heating effect. After someintensive tests by varying the laser power and the number ofpulses at a place per “salvo,” a uniform TH profile (as shownin Fig. 11) was realized on the stack with the following set ofparameters.

The energy of 1 pulse of laser with power 500 mW andpulse repetition rate 10 kHz is calculated to be 50 μmJ.Assuming a spot size of the YAG laser equal to 25 μm, thelaser fluence (�) can be derived as 10.19 J/cm2. If the totalpulses (n4) given at a point for making the TH is 400, theeffective fluence (�eff) can be calculated as 4076 J/cm2. Thelaser pulse energy used and the time taken in drilling one THof 200-μm diameter on a stack of thickness ∼300 μm are502.4 mJ and 1 s, respectively.

D. Desmear

During the cross-sectional analysis of laser ablated TH,some organic debris on the TH wall has been observed whichis formed by melting of the acrylic layers due to thermal effect.The quickest, cleanest, and most reliable way to desmearacrylic adhesive-based THs in the flex is plasma etching.Metal debris has not been observed so far during this analysis.If present, that can be removed by wet processes, e.g., Cumicroetching before TH plating.

PRIYABADINI et al.: 3-D STACKING OF UTCPs: PACKAGING AND INTERCONNECTION TECHNOLOGY 1119

TABLE II

REACTIVE ION ETCHING PARAMETERS FOR DESMEAR PROCESS

Step Power (W) Pressure(mTorr)

Gas FlowRate

(sccm)Duration (min)

1 150 100CHF3: 5,O2: 20

2

2 150 100 O2: 25 1

As reported by DuPont electronics [14], the first step with aCHF3/O2 gas mixture in an RIE chamber performs the etchingof debris and the second step is a pure oxygen burn processin which the fluorine-bound organics on the hole wall getremoved. The etching of debris was done by a plasma ThermBatchtop reactive-ion etching (RIE) machine which can dryetch thin layers at room temperature. The process variablesthat influence adhesive etch back are radio frequency power,gas mixture composition, gas flow rate (sccm), are chamberPressure (mTorr). After repeated tests, the RIE parameterswere optimized (as tabulated next) for getting debris-free THs.This two-step RIE exposure was done both from the top sideand the bottom side of the stack.

E. Metallization

The requirement of HDI includes a highly efficient platedTHs without corner cracks which may appear during later ther-mal reliability tests. Electro-deposited copper is the preferredmethod for plating the laser drilled THs in order to provide anelectrical connection between internal and external conductivepatterns in the stacked UTCPs. For this application, a completeplating line was designed which comprises a cleaning andCu micro etching step, followed by initial metallization ofthe surface and THs by electroless copper depositing and asubsequent electrolytic copper plating step.

Electroless copper deposits a very thin (∼2–4 μm), fragilecoating of pure copper over the entire surface of the panel.This includes the drilled TH walls and external surfaces (topand bottom sides of the stack). Electroplating then proceededto increase the thickness of the copper to a final valueof 10–12 μm. The cross-section of the plated through holeindicating electroless and electroplated Cu thickness is citedin Fig. 12.

F. Patterning and Dicing

The final copper patterning is done on both the top andbottom sides of the stack protecting the plated TH and somefine conductive lines on the stack. Riston FX920 (20-μm-thicknegative dry film resist from DuPont Electronic Technology)is laminated on both sides of the whole stack using a dryfilm laminator machine at a temperature 120 °C with a speedof 0.85 m/min. Photopatterning was done on both sides of thestack by illuminating the laminated stack by UV exposure withan energy of 60 mJ/cm2, followed by peeling the protectivelayer from the resist and developing it in 0.8% Na2CO3solution. For better adhesion of the resist on the coppersurface, a postdevelopment curing step can be introduced

Inner layer Cu ~7µm

(a)

(b)

Fig. 12. (a) Plated TH. (b) Close view showing electroless and electroplatedCu thickness.

either by a baking cycle (at 120 °C in an air convection ovenfor 10–15 min) or by UV exposure (100–150 mJ/cm2).

After developing, the exposed Cu layer from both top andbottom sides of the stack is etched by a Cu-spray etchingprocess in a CuCl2•2H2O + HCl solution at 55 °C. This is auniform etching process, used by almost all PCB manufactur-ing industries. Finally, the resist stripping was done by stirringthe stack in 3% NaOH solution (55 °C) for 3 min.

To protect the conductive parts from corrosion, a soldermask can be applied which can cover the whole stack exceptthe contact pads on the module. These contact pads canbe plated with electroless Ni/Au to keep the Cu free fromoxidation.

The final process is dicing of individual stacks from thewhole panel which can be done by laser cutting by using thesame set of parameters used for making the THs.

IV. EEPROM STACK DESIGN

The basic design rules for the stacked UTCP are adoptedfrom the PoP technology and THV technology used in PCBmanufacturing industries. The top layer contains easily solder-able outer contact pads for testing. Under the framework ofthe EU-funded project thin interconnected packaged stacks, theaim is to produce a stack of four dies within the same volumeas a single EEPROM die. This can be used as a replacementof a single die in a hearing aid device having fourfold memorycapacity, compared to a single memory chip device.

A. Chip Design

The EEPROM chips are commercially available memorydies of size 2005 × 3525 μm with eight contact pads per

1120 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 3, NO. 7, JULY 2013

Layout3 Layout4

Layout2Layout1

Fig. 13. Four different layouts for packaging EEPROM dies as UTCPs.

chip pad size 103 × 103 μm. The aluminum finished contactpads are bumped with 5-μm-thick electroless plating of Ni/Auwhich is a standard process offered by PacTech [15]. The sub-sequent thinning and dicing are handled by Disco who offers adicing-by-grinding process especially suited for ultrathin dies(∼20 μm) [16].

B. Package Design

The I/O limits of the stacked package are restricted by thefollowing considerations.

1) The pitch of the contact pads on the chip is limitedby the etching technology used to pattern the coppermetallization [1], [2]; pitch values down to 80 μm areachievable without yield loss.

2) The number of I/Os is limited by the area which istaken by the fan-out, based on the sizes of the THV,the landing pad area, and track-to-track spacing.

3) The parameters mentioned in the previous considerationare limited by the package-to-package shift during thelamination process.

4) Laser ablation and the subsequent plating processes limitthe size of the THV which can be realized.

Considering these limitations, the design was made for theproduction of multiple UTCPs (18 rows and 10 columns) on asingle panel (6” substrate) to reduce cost of production. Eachof the single UTCP packages has six I/Os (two on one side and4 on the other side) of size 500 μm diameter and conductivelines of width 115 μm. Four different layouts were designed(as shown in Fig. 13) for the four different UTCPs to bestacked afterward.

C. Stack Design

As per the stacking flow process described in Fig. 1,patterning of top and bottom layers is the final processing step.The top layer used here is the exact copy of the design madefor layout 4 (top most layer with contact pads for testing).The bottom layer design is made only to protect the PTH andsome extra copper at the bottom side of the stack to make itmore thermally stable.

D. EEPROM Stack

The whole process was realized in producing stacks contain-ing four EEPROM dies of size 5.45 mm × 2.56 mm × 300 μm

(a)

(b)

Fig. 14. (a) Close view of Multiple UTCPs (this is picture only for package 1)fabricated on a single panel. (b) 3-D view of EEPROM stack (4 dies withtotal stack thickness of 300 μm).

(a)

(b)

Fig. 15. (a) X-ray CT scan picture of one stacked UTCP showing conductivelines within the stack. (b) Coss-section of the four plated THs indicated onone side of the same stack.

which is almost equivalent to the size of a bare silicon die.Fig. 14 shows a close view of embedded EEPROM dies andthe interconnection pattern for package 1 (before release fromthe glass substrate) and the 3-D view of the diced stack.

Fig. 15 shows the X-ray CT scan picture of the stack whichis reconstructed from the 2-D pictures taken at different anglesby rotating the stack. This gives the cross-sectional view ofthe plated TH and all conductive lines within the stack.

E. Characterization

The connectivity of the chip packages is verified by check-ing the functionality of ESD pad protection diodes on the chipsby two-point measurement set-up. If the chip pads are wellconnected to the outside world, a typical diode impedance

PRIYABADINI et al.: 3-D STACKING OF UTCPs: PACKAGING AND INTERCONNECTION TECHNOLOGY 1121

-0,05

-0,04

-0,03

-0,02

-0,01

0,00

0,01

-1,00 0,00 1,00 2,00 3,00

Cur

rent

(A

)

Voltage (v)

S1

S2

S3

S4

S5

S6

S7

S8

S9

S10

S11

P1

P2P4

P5

P6

P1. GndP2. VccP3. SDAP4. CLKP5. WCP6. Gnd

P3

S1-S4 = Functional stacks

S5-S11 = Non-functional stacks

Fig. 16. Top side view of the EEPROM stack with external contact points(top picture) with graphical representation of the two-point connectivity testresult, measured at the points P1: ground and P2: Vcc of 11 stacks (S1–S11).

characteristic between the functional pads and the groundpads is measured. The I–V characteristics shown in Fig. 16were drawn from this measurement result with P1:ground andP2: Vcc as the contact points on the stack. The current wasmeasured within the voltage range of −1 V to +3 V for allthe stacks. Out of 11 stacks (as in the plot), only S1–S4 wereproven to be functional and rest were nonfunctional as thecurrent raises with voltage after 1 V which indicates shorts inthe circuit.

The average single-chip packaging yield per each layout ofUTCPs was 85%. Problems in thin chip handling during chipplacement (high pressure) and copper routing at the nonflatedge of the package are the main reasons for this minor lossin yield. However, consequences on yield loss of the individuallayers become more severe when these layers are stackedto form the four-chip EEPROM stack. With the assumptionthat inclusion of a single nonfunctional package within astack makes the whole module nonfunctional, the expectedstack yield was calculated to be 46%. The schematic diagramillustrating the influence of single UTCP packaging yield onstack yield is shown in Fig. 17. Although in this examplein each sheet there are only 1–3 defective UTCP packageson a total of 30, this will result in 9 defective stacks (on atotal of 30).

After the complete stacking process, the yield per batch ofstack turns out to be 7% only, which is very low comparedto the effort. During failure analysis, cracks at certain parts ofchip were observed (Fig. 18). These cracks were suspected to

Fig. 17. Schematics of batch stacking. Red color symbolizes nonfunctionalUTCPs per each layer of packages allowing to determinate the yield afterstacking.

Crack on Chip

Bottom PI

Top PI

Cu

Adhesive LF100

Bottom PI of UTCP sheet

Fig. 18. Thin die cracking found during failure analysis of the stacks of chippackages.

be the main failure cause of those stacks. This defect couldhave been introduced in any of the following processing steps:by applying pressure during chip placement or during the stacklamination process.

Additionally, air inclusion under the chip during thin chipplacement is risky for further processing as it can expandduring subsequent high-temperature processes leaving minorcracks on the flexible chips. As the UTCP itself has an in-built risk of nonuniform package thickness due to chip height,when pressure is applied at the adhesive flow stage duringthe lamination process, the liquefied glue on the top of chippackage squeezes out from the chip area leaving a very thinlayer on the top of the chip (Fig. 18). This results in anonuniform pressure distribution on the overall surface of theembedded packages during the lamination process which couldbe a reason for chip cracking. To overcome this problem ofpressure nonuniformity, all the layers to be laminated have tobe flat enough to reduce the risk of die cracking. This canbe achieved by use of flat UTCPs by spinning an extra layerof polyimide. This additional polyimide layer has a thicknesswhich is the same as the thinned dies in-between the baseand top layers of the chip packages [2], [19]. The embeddingcapability in standard flexible printed circuits of individualflat UTCPs has already been demonstrated by IMEC in thepast couple of years [17]–[19]. A recent development in thistechnology confirms 95% production yield by 3-D-integratingthis flat UTCP in standard flexible circuit boards [19].

1122 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 3, NO. 7, JULY 2013

V. CONCLUSION

A new generation 3-D packaging technology was discussedin this paper. The stack of four dies was so thin that it couldreplace a single bare silicon die of similar volume. Manyoptimization test runs were performed to obtain this batch ofstacked UTCPs. There is still room to improve the yield byusing proper thin-die bonding technology. In addition, a stackof flat UTCPs can give better yield because a uniform pressuredistribution on the packages during lamination process canbe obtained. This cannot be achieved by using conventionalUTCPs (nonflat). Tests are currently ongoing for the produc-tion of stacked flat UTCP. Reliability and thermomechanicalbehavior of the thin stacks also have to be verified in nearfuture. Further developments in the process and results willbe reported in subsequent papers.

REFERENCES

[1] W. Christiaens, E. Bosman, and J. Vanfleteren, “UTCP: A novelpolyimide-based ultra-thin chip packaging technology,” IEEE Trans.Compon. Packag. Technol., vol. 33, no. 4, pp. 754–760, Dec. 2010.

[2] J. Govaerts, E. Bosman, W. Christiaens, and J. Vanfleteren, “Fine-pitchcapabilities of the flat ultrathin chip packaging,” IEEE Trans. Adv.Packag., vol. 33, no. 1, pp. 72–78, Feb. 2010.

[3] L. Wang, T. Sterken, M. Cauwe, D. Cuypers, and J. Vanfleteren,“Fabrication and characterization of flexible ultrathin chip packageusing photosensitive polyimide,” IEEE Trans. Compon., Packag. Manuf.Technol., vol. 2, no. 7, pp. 1099–1106, Jul. 2012.

[4] A. Geczy and Z. Illyefalvi-Vitez, “Package-on-package—review on apromising packaging technology,” in Proc. 33rd Int. Spring SeminarElectron. Technol., 2010, pp. 117–122.

[5] P. Sun, V. Leung, D. Yang, R. Lou, D. Shi, and T. Chung, “Develop-ment of a new package-on-package (PoP) structure for next-generationportable electronics,” in Proc. Electron. Compon. Technol. Conf., 2010,pp. 1957–1963.

[6] T. Braun, K.-F. Becker, S. Voges, T. Thomas, R. Kahle, V. Bader,J. Bauer, K. Piefke, R. Krüger, R. Aschenbrenner, and K.-D. Lang,“Through mold vias for stacking of mold embedded packages,” in Proc.Electron. Compon. Technol. Conf., 2011, pp. 48–54.

[7] T. Braun, K.-F. Becker, K. Piefke, S. Voges, T. Thomas, M. Topper,T. Fischer, R. Kahle, V. Bader, J. Bauer, R. Aschenbrenner, and K.-D.Lang, “3D stacking approaches for mold embedded packages,” in Proc.Microelectron. Packag. Conf., 2011, pp. 1–8.

[8] Z. Illyefalvi-Vitez, “Laser processing of adhesives and polymeric mate-rials for microelectronics packaging applications,” in Proc. 4th Int. Conf.Adhes. Join. Coat. Technol. Electron. Manuf., 2000, pp. 289–295.

[9] S. Priyabadini, A. Gielen, K. Dhaenens, W. Christiaens, S. Van Put,G. Kunkel, A. E. Petersen, and J. Vanfleteren, “3D-stacking of UTCPsas a module miniaturization technology,” in Proc. 44th Int. Symp.Microelectron., 2011, pp. 463–468.

[10] HD Microsystem. (2011). PI2611, Louisville, KY [Online]. Available:http://hdmicrosystems.com/HDMicroSystems/en_US/index.html

[11] Pyralux LF. (2010) [Online]. Available: http://www2.dupont.com/MCM/en_US/index.html

[12] UBE America Inc. (2011). SR 1410, New York [Online]. Available:http://www.ube.com/index_US.php

[13] TW-YE. (2009) [Online]. Available: http://circuitfoil.com/[14] Electronic Flexible Printed Circuit Processing Guide, DuPont, Wilm-

ington, DE, 1995.[15] Standard Ni/Au Bumping Process. Pac Tech, Nauen, Germany [Online].

Available: http://www.pactech.de/index.php?option=com_content&view=article&id=34&Itemid=74

[16] Wafer Thinning and Dicing Services. DISCO, Tokyo, Japan, [Online].Available: http://www.disco.co.jp/eg/solution/charged/index.html

[17] J. Govaerts, W. Christiaens, E. Bosman, and J. Vanfleteren, “Fabricationprocesses for embedding thin chips in flat flexible substrates,” IEEETrans. Adv. Packag., vol. 32, no. 1, pp. 77–83, Feb. 2009.

[18] J. Govaerts, W. Christiaens, E. Bosman, and J. Vanfleteren, “Multiplechip integration for flat flexible electronics,” in Proc. 7th IEEE Conf.Polymers Adhes. Microelectron. Photon., Aug. 2008, pp. 1–5.

[19] T. Sterken, M. O. de Beeck, F. Vermeiren, T. Torfs, L. Wang, S.Priyabadini, K. Dhaenens, D. Cuypers, and J. Vanfleteren, “High yieldembedding of 30 μm thin chips in a flexible PCB using a photopattern-able polyimide based ultra-thin chip package (UTCP),” in Proc. 45thInt. Symp. Microelectron., Sep. 2012, pp. 940–945.

Swarnakamal Priyabadini (S’12) received theMaster of Science degree in physics from UtkalUniversity, Bhubaneswar, India, and the Master ofTechnology (M.Tech.) degree in solid state materialsfrom the Indian Institute of Technology Delhi, NewDelhi, India, in 2007 and 2009, respectively. She didher M.Tech. Project from Walter Schottky Institute,Technical University of Munich, Munich, Germany,under DAAD Fellowship Program from September2008 to May 2009. She is currently pursuing thePh.D. degree with the Center for Microsystems

Technology Group (CMST), Ghent University-Interuniversity Microelectron-ics Center, Ghent, Belgium, on the topic ’3D stacking of ultrathin chips andchip packages’.

Tom Sterken received the Masters degree inmicroelectronics engineering from Ghent University,Ghent, Belgium, in 2001, and the Ph.D. degreein MEMS technology from Catholique University,Leuven, Belgium, in 2001 and 2009, respectively.

He joined IMEC as a Project Engineer, where heworked on the design, modeling, and fabricationof miniature power generators based on MEMStechnology. He is currently with the Center forMicrosystems Technology Group, Ghent University,where he is working on ultrathin chip packaging and

stretchable electronics.

Luc Van Hoorebeke received the Licentiate degreein physics and the Ph.D. degree in physics degreefrom Ghent University, Ghent, Belgium, in 1985 and1991, respectively.

He was a Researcher with the Belgian NuclearResearch Centre, Boeretang, Belgium, from 1993 to1994, working in positron annihilation spectroscopy.Afterwards, he was with Ghent University as a Post-Doctoral Fellow with the Research Foundation -Flanders in experimental nucleon structure physics.In 2003, he became a Professor in physics with the

Department of Physics and Astronomy, Ghent University, and also becamethe Head of the Radiation Physics Research Group. In 2006, he cofoundedthe Centre for X-Ray Tomography, Ghent University. His current researchinterests include high resolution X-ray tomography.

Jan Vanfleteren (M’01) received the Ph.D. degreein electronic engineering from Ghent University,Ghent, Belgium, in 1987.

He is currently a Senior Engineer with the Cen-ter for Microsystems Technology Group (CMST),Ghent University-Interuniversity MicroelectronicsCenter, Ghent, and is involved in the developmentof novel interconnection, assembly, and polymermicrosystem technologies, especially for wearableand implantable electronics, biomedical, microflu-idics, cell culturing, and tissue engineering appli-

cations. He is a Project Manager at CMST, where he has long-standingexperience in coordination and cooperation in EC-funded projects. In 2004,he became a part-time Professor with Ghent University. He is the co-authorof over 200 papers in international journals and conferences. He holds 14patents and patent applications.

Prof. Vanfleteren is a member of the International Microelectronics andPackaging Society and the Materials Research Society.