System-wide Power Management for Real-Time Systems - Inria

System-wide PowerManagement for Real-TimeSystems

Roberto Medina and Liliana [email protected]

RTSOPS

I Reactive embeddedsystems

I Time constraints

I Battery powered

Challenges

I ↗ functionalities

I ↗ autonomy

I ↘ SWaP

I COTS

Context and motivation

2

Dynamic Voltage and Frequency Scaling (DVFS)

I ↘ voltage → ↘ frequency → ↗ execution time.

I Derive a proper speed to meet deadlines.

Dynamic Power Management (DPM)

I CPUs have low-power states, barely consuming energy.

I Know when system can be put into this low-power state.

Energy management for RT systems

3

Classic real-time task model: τi ,Ci ,Ti ,Di .

I Proportional to frequency? i.e. Ci/s

I Linux GRUB-PA, DRA, AGR...

I Fixed + frequency-dependent parts? i.e. Cfixi + C var

i /sI FAST, Aydin et al. 2006...

Execution time

4


How does Ci evolve w.r.t. frequency?

I Proportional to frequency? i.e. Ci/s

I Linux GRUB-PA, DRA, AGR...



Execution time

4


How does Ci evolve w.r.t. frequency?

I Proportional to frequency? i.e. Ci/sI Linux GRUB-PA, DRA, AGR...



Execution time

4

I Run TACLeBench tests on isolation,i.e. one core = one benchmark.

I Perform 500 consecutive runs of the application.

I Processor speed set to min or max.

I Measure execution time and CPU cycles.I Platforms:

1. Intel i7-8650U, Linux 5.1.16, L1-L3 caches, 800MHz -2100Mhz, DDR4 1200MHz.

2. ARM Cortex A-53, Linux 4.19.56, L1-L2 caches, 600MHz- 1400MHz, LPDDR2 500MHz.

Experimental setup

5

2 2.1 2.2 2.3 2.4 2.5 2.6

adpcm decadpcm enc

ammunitioncjpeg transupp

cjpeg wrbmpdijkstra

epic

fmrefgsm decgsm enc

h264 dechuff enc

mpeg2

ndespetrinet

rijndael decrijndael enc

statematesusan

I Theoretical speedup never reached.I Ci not proportional to CPU frequency.

Execution time (Intel i7-8650U)

6

0.88 0.9 0.92 0.94 0.96 0.98 1 1.02

adpcm decadpcm enc


cjpeg wrbmpdijkstra

epic

fmrefgsm decgsm enc

h264 dechuff enc

mpeg2

ndespetrinet


statematesusan

I > 1→ less cycles spent in the processor XI Generally programs spend additional cycles waiting for

the bus and memory (slower).

CPU Cycles (Intel i7-8650U)

7

1.9 2 2.1 2.2 2.3

adpcm decadpcm enc


cjpeg wrbmpdijkstra

epic

fmrefgsm decgsm enc

h264 dechuff enc

mpeg2

ndespetrinet


statematesusan

Execution time (ARM Cortex A-53)

8

0.85 0.9 0.95 1

adpcm decadpcm enc


cjpeg wrbmpdijkstra

epic

fmrefgsm decgsm enc

h264 dechuff enc

mpeg2

ndespetrinet


statematesusan

CPU Cycles (ARM Cortex A-53)

9

I Tasks have different behaviors benefiting more or less onprocessor speed.

I Ci is not proportional to CPU frequency.I Bus and memory need to be considered.

I Model with a fixed part seems ok, but...I Requires a deep knowledge about the program and

architecture.

Takeaway messages

10

τi =

(Ci =

(2 3 8

0.5 0.3 0.2

),Ti ,Di

)I RTA can guarantee a DMP for the system.

I Systems have a degree of schedulability with a highutilization rate (U ≥ 1).

I ↗ functionalities.

Probabilistic RT systems

11

How does the pET change w.r.t. CPU frequency?

Cfi =

(? ? ? ?? ? ? ?

)

I Not proportional to processor speed.

I Obtain information about memory instructions (e.g.FAST) very time consuming.

I Difficult to predict on COTS.

Open problems: Frequency scaling and pET (1/2)

12

Figure: dijkstra @ 1400MHz


13

Figure: dijkstra @ 600MHz


14

Can probabilistic RT system benefit from DVFS?

We ran experiments where the actual execution timefollows a normal or uniform probability distributionfunction.

“Power-Aware Scheduling for Periodic Real-Time Tasks”Aydin et al., IEEE Transactions on Computers, 2004

I More precise distribution to know when to be aggressive.


15

I Memory energy consumption is significant (∼20-25%)

1

Can DVFS be exploited at a memory level?

1“Memory power management via dynamic voltage/frequency scaling”, David et al, 8th ACMinternational conference on Autonomic computing. 2011

Open problems: memory frequency scaling (1/2)

16

1

How does the pET change w.r.t. memory frequency?

I Tasks less affected by memory accesses → scale downmemory frequency.

1“Memory power management via dynamic voltage/frequency scaling”, David et al, 8th ACMinternational conference on Autonomic computing. 2011

Open problems: memory frequency scaling (2/2)

17

Thank you

Any question?

System-wide Power Management for Real-Time Systems - Inria

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