Laterally amalgamated DUal Material GAte Concave (L-DUMGAC) MOSFET for ULSI

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www.elsevier.com/locate/mee

Microelectronic Engineering 85 (2008) 566–576

Laterally amalgamated DUal Material GAte Concave(L-DUMGAC) MOSFET for ULSI

Rishu Chaujar a, Ravneet Kaur a, Manoj Saxena b, Mridula Gupta a, R.S. Gupta a,*

a Semiconductor Devices Research Laboratory, Department of Electronic Science, University of Delhi, South Campus, New Delhi 110 021, Indiab Department of Electronics, Deen Dayal Upadhyaya College, University of Delhi, Karampura, New Delhi 110 015, India

Received 31 January 2007; received in revised form 27 August 2007; accepted 23 October 2007Available online 30 October 2007

Abstract

In this paper, a novel structure: Laterally amalgamated DUal Material GAte Concave (L-DUMGAC) MOSFET is proposed. Theeffectiveness of L-DUMGAC MOSFET design was examined by comparing Single Material Gate (SMG) Concave devices with L-DUM-GAC devices of various gate length ratios, Negative Junction Depths (NJDs) and metal gate work functions, and it was found thatL-DUMGAC exhibits significant enhancement in device characteristics in terms of device efficiency, intrinsic gain, early voltage andthe switching characteristics. With the enhancement in device integration technology, the structure offers new opportunities for realizinghigh performance in the future ULSI production.� 2007 Elsevier B.V. All rights reserved.

Keywords: ATLAS-3D; Concave MOSFET; DMG; Device efficiency; Early voltage; Intrinsic gain

1. Introduction

Enhancement in device integration technology requiresrapid scaling of device dimensions to achieve higher speedsand packing densities. As the device miniaturization trendcontinues, the MOSFET dimensions have advanced intosub-100 nm era, paving the way to various critical issuessuch as short channel effects (SCEs), punchthrough cur-rent, threshold voltage roll-off and hence, resulting indevice performance degradation. Concave/grooved gateMOSFETs are considered as one of the promising candi-dates for suppressing SCEs and improving the hot carrierimmunity; and thus the device reliability [1–6]. In thisstructure, two potential barriers are formed at the concavecorners due to high density of electric field lines. Improve-ment in SCEs is mainly attributed to the formation of these

0167-9317/$ - see front matter � 2007 Elsevier B.V. All rights reserved.doi:10.1016/j.mee.2007.10.002

* Corresponding author. Tel.: +91 011 24115580; fax: +91 01124110606.

E-mail addresses: [email protected] (R. Chaujar), [email protected] (R. Kaur), [email protected](M. Saxena), [email protected] (R.S. Gupta).

potential barriers. However, carriers in the channel requirehigher energy to surmount these potential barriers, whichlimits carrier transport efficiency and hence, current drivingcapability of the device and transconductance. In order tosurmount the problems and further improve the ION/IOFF

ratio, laterally amalgamated DUal Material GAte Concave(L-DUMGAC) MOSFET, as shown in Fig. 1, is proposed.The step potential profile, due to gate electrodes of differentmetal work functions [7–11], ensures reduction in DIBLand enhancement of carrier transport efficiency and deviceefficiency (gm/Ids).

In this paper, the electrical characteristics of L-DUM-GAC are compared with SMG Concave MOSFETs interms of surface potential, Vth, DIBL, Sub-ThresholdSwing (S), drain current, transconductance, device effi-ciency gm/Ids, ION/IOFF, early voltage, VEA = Ids/gd andintrinsic gain (Av). In the first section, an analytical modelis developed for the proposed structure and a close proxim-ity of the modeled data with the simulated results authen-ticates our model. The second section investigates thedevice characteristics using ATLAS 3D [12], in terms oftransconductance, DIBL, Sub-Threshold Swing (S), device

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Fig. 1. Schematic structure of Concave MOSFET with L-DUMGAC configuration. Channel length (L) = 50 nm, effective channel length(LEFF) = L + 2(tox + NJD), device width (W) = 1 lm, groove depth (d) = 100 nm, L1 = L2 = 25 nm, NA = 1 · 1017 cm�3, tox = 4 nm, eox = 3.9. Workfunction (UM1) = 4.77 V for SMG and for DMG, (UM1) = 4.77 V and (UM2) = 4.4 V/4.10 V. (b) Schematic representation interpreting the corner effectapproximation.

R. Chaujar et al. / Microelectronic Engineering 85 (2008) 566–576 567

efficiency, ION/IOFF, early voltage, and intrinsic gain with(a) different Negative Junction Depths (NJDs), (b) differentmetal gate work functions, (c) same effective lengths and(d) same electrical lengths of the two devices. In our study,we adopt the hydrodynamic energy transport model, whichcan simulate the non-local transport phenomenon [13].

2. Model formulation

2.1. Two-dimensional potential analysis

A schematic structure of L-DUMGAC MOSFET isshown in Fig. 1. The lengths of metal gates M1 and M2is L1 and L2, respectively. The source/drain (S/D) regionsare rectangular and uniformly doped at 1020 cm�3. Thechannel doping concentration NA is also uniform. Thedevice characteristics were simulated using the ATLASdevice simulator [12]. Assuming the impurity density inthe channel region to be uniform, the potential distributionU(x,y) in silicon film can be given as [14]

o2Uðx; yÞox2

þ o2Uðx; yÞoy2

¼ qN A

esi

for 0 < x < LEFF and

ðd þ toxÞ < y < ðd þ tox þ Y DÞ ð1Þwhere eSi is the dielectric constant of silicon, q is the elec-tronic charge, NA is the substrate doping density, d is thegroove depth, YD is the depletion layer thickness.

LEFF is the effective channel length which is given by [2]

LEFF ¼ Lþ 2ðNJDþ toxÞ ð2Þwhere L is the gate length; NJD is the negative junctiondepth and tox is the gate-oxide thickness.

Basic assumption: We have approximated the cornereffect in concave structure with an assumption, as shown

in Fig. 1(b). In our analysis, the corners have beensmoothed out in such a way that i, ii, iii (marked inFig. 1(b)) are all equivalent to tox leading to an underesti-mation of the position of the corner by De. It is found thatif De/LEFF < 5%, the analytical model results are in closeproximity to the simulated results. In our analysis, forNJD = 10 nm with gate lengths varying from L = 100 nmto 50 nm, the error De/LEFF varies from 3% to 5%; andfor NJD = 30 nm with gate lengths varying fromL = 100 nm to 50 nm, the error De/LEFF varies from 2%to 3%. In case of gate lengths less than 50 nm, De/LEFF

becomes greater than 5% and hence the corner effects inmodeling cannot be ignored.

In our analysis, the Poisson’s equation has been eval-uated in the substrate depletion layer where the channelis virtually depleted of mobile charge carriers. Thus, thepotential distribution in the channel, before the onset ofstrong inversion is governed by the Poisson’s equation[15,16] as mentioned by Eq. (1). The Poisson’s equationhas been considered in the weak inversion region andnot in the strong inversion region. This is because ifthere are any significant mobile charges present in thechannel, Poisson’s equation becomes non-linear and cou-ples to the continuity equation. Although this problemcan be solved by numerical simulations, they can offeronly isolated data points and hence do not offer a suit-able basis for device models. An analytical solution,however, is necessary to explicate the trends in devicebehaviour. Restricting the view to the sub-thresholdregime makes the solution tractable because Poisson’sequation is then linear and decoupled from the continu-ity equation.

The depletion layer thickness, YD is approximately givenby

-0.4

-0.2

0

0.2

0.4

0.6

0.8

0 0.2 0.4 0.6 0.8 1

Normalized Position Along The y-direction

Ver

tical

Pot

entia

l (V

)

METAL OXIDE SEMICONDUCTOR

Vgs=0.0VVds=0.0VL=50nmd=100nm

ΦM1 =4.7V

Φ M2 =4.1VΦ M2 =4.4VΦ M2 =4.7V

Fig. 2(a). Simulated vertical potential profile along the depth (y-direction)for L-DUMGAC MOSFET explaining the flat-band voltage for threedifferent UM2 for W = 1 lm, d = 100 nm. The cutline has been drawn atthe middle of the M2 gate.

568 R. Chaujar et al. / Microelectronic Engineering 85 (2008) 566–576

Y D ¼ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi2 � esi

q � NA

� 1:5UF

sð3Þ

where UF is the Fermi potential.The potential profile in the vertical direction can be

approximated by a simple cubic function as [8]

Uðx; yÞ ¼ USðx; d þ toxÞ þX3

i¼1

CiðxÞyi ð4Þ

where US(x,d + tox) is the surface potential and Ci(x)(i = 1,2,3) is an arbitrary coefficient which is a function ofx only. As mentioned by Suzuki [15] and Toyabe and Asai[16], a three order or a cubic polynomial potential profilehas been assumed in the vertical direction for bulk MOS-FETs as in this case. It cannot be approximated by a linearor a quadratic function of y near the drain end. This is be-cause the potential distribution is a concave curve similarto the depletion layer potential distribution in the middleof the channel, while it is convex near the drain end whenthe drain bias is larger than the gate bias. Thus, based onthis observation, a cubic polynomial potential profile hasbeen considered in the vertical direction for this structure.

In SMG Concave MOSFET, the gate is made up of onlyone material, i.e. M1 having a work function UM1, but inthe L-DUMGAC structure, we have two different materi-als with work functions UM1 and UM2, respectively. Inthe present analysis, the channel region has been dividedinto two parts, in which the potential under M1 and M2can be represented as

U1ðx; yÞ ¼ US1ðx; d þ toxÞ þX3

i¼1

Ci1ðxÞyi

for 0 < x < L1EFF; ðd þ toxÞ < y < ðd þ tox þ Y DÞ ð5Þ

U2ðx; yÞ ¼ US2ðx; d þ toxÞ þX3

i¼1

Ci2ðxÞyi

for L1EFF < x < ðL1EFF þ L2EFFÞ;ðd þ toxÞ < y < ðd þ tox þ Y DÞ ð6Þ

where L1EFF = L1 + (NJD + tox), L2EFF = L2 + (NJD +tox), US1(x,d + tox) and US2(x,d + tox) are surface poten-tials under regions M1 and M2, and Ci1(x) and Ci2(x) arethe corresponding arbitrary coefficients. These surfacepotentials depends on the effective gate voltages, which inturn, are dependent on the flat-band voltages. These flat-band voltages come into being as a result of different metalgate work functions as shown in Fig. 2(a). The flat-bandvoltages for two gates would, thus, be different, resultingin different effective gate voltages; and hence, different sur-face potentials under the two different material gates amal-gamated laterally. Moreover, the dependence of surfacepotential on the work functions of the metal gates signifiesthat we can tune the surface potential and threshold volt-age of MOSFETs.

The Poisson equation is solved separately under the tworegions (M1 and M2) using the following boundaryconditions:

1. Electric flux at the gate-oxide/Si interface is continuousfor both the metal gates. Thus

oU1ðx; yÞoy

¼ V G1 � US1ðx; yÞctox

at 0 < x < L1EFF and y ¼ d þ tox ð7ÞoU2ðx; yÞ

oy¼ V G2 � US2ðx; yÞ

ctox

at L1EFF < x < LEFF and y ¼ d þ tox ð8Þ

where VG1 = Vgs � VFB1 and VG2 = Vgs � VFB2 whereVgs is the gate-to-source voltage, VFB1 and VFB2 arethe flat-band voltages. c is defined as

c ¼ esi

eox

ð9Þ

where eox is the permittivity of SiO2. Since in general,the metal and the semiconductor have different workfunctions, this difference causes band bending. In theMOS structure, electrons will flow from the metal tothe semiconductor or vice versa until a potential is builtup between the two, which will counterbalance the dif-ference in their work functions [17]. Thus, there is a var-iation in electrostatic potential from one region toanother resulting in band bending in the interior ofthe structure. Since metal is an equipotential region,no band bending occurs there as is clear fromFig. 2(a). Therefore, the energy bands bend in the oxideand the semiconductor. To compensate for this bandbending, flat-band voltage is considered, which is simplythe work function difference that causes band bending.Once the bands have become flat at the surface, a homo-geneous effect of the applied bias could be observed onthe device behaviour. This flat-band voltage, as is clearfrom Fig. 2(a), changes with the change in the metalgate work function, with the semiconductor work func-


tion being a constant. Thus, for a consistent effect of theapplied bias on the device behaviour, band bendingneeds to be compensated. This is done by incorporatingthe effect of Vfb in the applied gate bias and so the effec-tive gate potentials, VG1 and VG2 are the applied gatebias minus the flat-band voltage corresponding to met-als M1 and M2, respectively. The flat-band voltage is of-ten used as a reference voltage and is an important MOSdevice parameter.

2. Surface potential at the interface of two dissimilar met-als is continuous:

U1ðx; yÞ ¼ U2ðx; yÞ at x ¼ L1EFF and y ¼ d þ tox ð10Þ3. Electric flux at the interface of two dissimilar metals is

continuous:

oU1ðx;yÞox

¼ oU2ðx;yÞox

at x¼ L1EFF and y ¼ dþ tox ð11Þ

The potential distribution in the substrate depends uponthe effective gate potentials i.e. Vgs � Vfb whereVfb = UM � US. Although the channel is uniformlydoped, due to lateral dissimilar gate electrode configura-tion, Vfb of region I is different from region II, therebyleading to different effective gate to source potentialsðV 0gsÞ. That is why potential and electric field inside thesubstrate along the channel is modulated from region Ito region II. The solution, however, is within the domain0 < x < LEFF and (d + tox) < y < (d + tox + YD). In thisdomain, there are two sub-domains namely region Iwhere 0 < x < L1EFF and d + tox < y < d + tox + YD

and region II where L1EFF < x < LEFF and d + tox <y < d + tox + YD specifying regions under M1 and M2,respectively. Potential and electric field are continuousinside each of the individual sub-domains. However, atthe interface of two dissimilar metal gates i.e. M1 andM2, there is a step potential profile. In order to modelit, the potential and electric field of the two sub-domainshave been matched at the interface only i.e. at x = L1EFF.Hence, for 0 < x < L1EFF and d + tox < y < d + tox +YD, channel potential is U1(x,y); and for L1EFF < x

< LEFF and d + tox < y < d + tox + YD, channel poten-tial is U2(x,y).

4. Potential at the depletion edge is VSUB:

U1ðx; yÞ ¼ U2ðx; yÞ ¼ V SUB at 0 < x < LEFF and

y ¼ d þ tox þ Y D ð12Þ

where VSUB is the substrate bias.5. Electric field at the depletion edge is zero:

oU1ðx; yÞoy

¼ oU2ðx; yÞoy

¼ 0 at 0 < x < LEFF and

y ¼ d þ tox þ Y D ð13Þ

6. Potential at the source end is

U1ðx;yÞ¼ V bi¼US1ðx;dþ toxÞ at x¼ 0 and 0< y< dþ tox

ð14Þwhere Vbi is the built-in voltage.

7. Potential at the drain end is

U2ðx; yÞ ¼ V bi þ V ds ¼ US2ðx; d þ toxÞ at

x ¼ L1EFF þ L2EFF and 0 < y < d þ tox ð15Þ

where Vds is the applied drain-to-source bias.

The constants in (5) and (6) can be found from theboundary conditions (7)–(15) and on substituting their val-ues in (5) and (6), we get

U1ðx; yÞ

¼ US1ðx;d þ toxÞ þ ðV G1� V SUBÞ ��2

A� 4Y D

AB� 6

B

� ��

� ðV G1�US1ðx;d þ toxÞÞ

� 2Y D

Aþ 4A2� 8C

c � toxB

�� 3A2þ 6C

c � tox �B

�� y

þ ðV G1� V SUBÞ �1

A2� 4

AB

� �� ðV G1�US1ðx;d þ toxÞÞ

�

� 1

A2� 2A2þ 4C

ABC

� �� y2 þ ðV G1 � V SUBÞ �

2

A2B

� ��

þ ðV G1�US1ðx;d þ toxÞÞ �A2� 2C

A2BC

� �� y3 ð16Þ

U2ðx; yÞ

¼ US2ðx;d þ toxÞ þ ðV G2� V SUBÞ ��2

A� 4Y D

AB� 6

B

� ��

� ðV G2�US2ðx;d þ toxÞÞ

� 2Y D

Aþ 4A2� 8C

c � toxB� 3A2þ 6C

c � tox �B

� �� y

þ ðV G2� V SUBÞ �1

A2� 4

AB

� �� ðV G2�US2ðx;d þ toxÞÞ

�

� 1

A2� 2A2þ 4C

ABC

� �� y2 þ ðV G2 � V SUBÞ �

2

A2B

� ��

þ ðV G2�US2ðx;d þ toxÞÞ �A2� 2C

A2BC

� �� y3 ð17Þ

where

A ¼ d þ tox þ Y D

B ¼ Y D � 2d � 2tox

C ¼ ctoxY D

ð18Þ

The surface potentials US1(x,d + tox) and US2(x,d + tox)under regions M1 and M2 can be obtained by substituting(16) and (17) into (1).

2.2. Threshold voltage (Vth)

The threshold voltage of the short channel MOSFET isdefined as the gate-to-source voltage at which the minimum


surface potential in the channel US1ðxmin; d þ toxÞ equals2UF where UF represents the Fermi potential [17]. WithDMG architecture, due to the existence of metal gates,M1 and M2, with different work functions, the surfacepotential minima is solely determined by M1 i.e. the metalgate with higher work function. Thus, substitutingUS1ðxmin; d þ toxÞ ¼ 2UF and Vgs = Vth in the expressionfor surface potential under region M1, gives an expressionfor threshold voltage. The position of minimum surfacepotential xmin lies under the first metal gate (or the controlgate) M1 and can be evaluated by solving

o

oxUS1ðx; d þ toxÞ

��x¼xmin

¼ 0 ð19Þ

Electric field along the channel is made equal to zero inorder to determine the position of minimum surface poten-tial, xmin and to evaluate the minimum surface potential,US1ðxmin; d þ toxÞ. This minimum surface potential has beenutilized in the determination of threshold voltage of thedevice.

2.3. Drain current model

The threshold voltage for two different regions ofL-DUMGAC MOSFET is different due to the differencein the metal work functions. Since the work function ofmetal gate M1 is higher in the dual material structure,the drain current depends on region 1. The drain currentin the linear region is given by [18],

IdLIN ¼ ln � W � Cox �V gs � V th � V ds

2

� �� V ds

LEFF 1þ V ds

LEFF �ECRIT

� ð20Þ

where ECRIT is the critical electric field given byECRIT ¼ 2�vSAT

ln, Cox is the effective oxide capacitance given

by Cox ¼ eox

toxand ln is the electron mobility extracted from

device simulations [12] using the concentration-dependentlow field mobility (CONMOB) model and the parallel elec-tric field dependence (FLDMOB) models. The drain cur-rent in the saturation region is given by [19,20]

IdSAT ¼ W � Cox � vSAT � ðV gs � V th � V dSATÞ ð21Þwhere VdSAT is the saturation drain-to-source bias given by

V dSAT ¼ V gs�V th

1þ V gs�V thLEFF �ECRIT

� .

3. Analytical and simulation results and discussion

In order to gain an insight into the effectiveness ofL-DUMGAC MOSFET design, the SMG Concave andL-DUMGAC devices of various L1/L2 ratios, NJDs andmetal gate work functions are studied; and the results arepresented in terms of various parameters such as deviceefficiency, intrinsic gain, VEA, etc.

3.1. Analog and digital performance metrics

In order to fairly analyze the analog and digital perfor-mances, all devices are optimized to have the same thresh-old voltage i.e. 0.3 V and comparisons are then made togive a fair insight into the effectiveness of L-DUMGACdesign. The first section of Table 1 predicts the thresholdvoltages and DIBL values without any device optimization,where the devices have the same substrate doping density,NA. It is clear from the table that L-DUMGAC has lowerthreshold voltage and DIBL values than SMG concaveMOSFET. However, in the second section of the tablei.e. the section titled ‘‘After Device Optimization forVth = 0.3 V’’, devices are optimized, by modulating thesubstrate doping density, to have the same threshold volt-age, thereby providing design optimization of L-DUM-GAC MOSFET in terms of ION/IOFF and Sub-ThresholdSlope, S, giving NJD variation, work function variation,electrical channel length variation and effective channellength variation. Further, this section of the table predictsa significantly higher ION/IOFF and a lower Sub-ThresholdSlope, S of the proposed L-DUMGAC MOSFET in com-parison to SMG concave edifying its effectiveness in theswitching applications. A percentage increment (%D) vary-ing from 3% to 77% in terms of ION/IOFF and S has beenobtained for different design configurations of L-DUM-GAC MOSFET over its SMG counterpart in terms ofNJD, L and UM2. Higher the ION/IOFF ratio and lowerthe Sub-Threshold Slope, better are the switching andturn-on characteristics of the device. The results clearlyexhibit a good performance enhancement of L-DUMGACover SMG thereby proving its efficacy for high-speed digi-tal and switching applications. Fig. 2(b) shows the varia-tion of surface potential with the normalized channelposition for L-DUMGAC and SMG Concave MOSFETs.The step potential profile exhibited by L-DUMGAC, dueto different work functions of two metal gates, screensregion under M1 from drain potential variations. The drainbias, thus, has a very diminutive effect on the drain current;thereby reducing DIBL, as is reflected from Table 1 as well.Fig. 3 shows the variation of surface potential with the nor-malized channel position for different combinations of con-trol gate and screening gate lengths, L1 and L2,respectively; maintaining the total gate length constant.The figure clearly reflects a shift in the position of mini-mum surface potential towards the source, as L1 is reduced;thereby shifting the step potential profile towards thesource resulting in DIBL reduction. Fig. 4 depicts the elec-tric field distribution along the channel for different valuesof gate lengths L1 and L2, keeping the total gate length con-stant. As L1 reduces, the peak electric field position movestowards the source, thereby enhancing the carrier transportefficiency and hence, the switching speed of the device.Fig. 4 (Inset) shows the variation of electric field alongthe channel for different gate lengths, L. It is clear fromthe figure that as the device miniaturization trend contin-ues, the electric field peak moves towards the source; thus,

Table 1Summary of the simulated parameters extracted for SMG Concave MOSFET and L-DUMGAC structures

UM = 4.7 V(SMG Concave) L = 50 nm

SMGConcaveMOSFET

L-DUMGAC MOSFET OM1 = 4.7 V;OM2 = 4.1 V; L1 = L2 = 25 nm

DIBL (mV/V) @Vds = 1.0 V andVds = 0.1 V

NJD = 10 nm 352.127 234.061NJD = 30 nm 544.180 401.817

Vth (V) NJD = 10 nm 0.574 0.471NJD = 30 nm 0.741 0.675

After device optimization for Vth = 0.3 V

L = 50 nmUM = 4.7 V

L = 50 nmL1 = L2 = 25 nmUM1 = 4.7 V

L = 100 nmL1 = L2 = 50 nmUM1 = 4.7 V

L = 75 nm, L1 = 50 nm;L2 = 25 nmUM1 = 4.7 V

UM2 = 4.1 V %D UM2 = 4.4 V UM2 = 4.1 V %D UM2 = 4.4 V UM2 = 4.1 V %D UM2 = 4.4 V

ION/IOFF NJD = 10 nm 13,500 14,700 8.9 13,600 24,000 77.7 18,100 22,300 65.2 19,000NJD = 30 nm 22,600 23,900 5.8 18,700 28,100 24.3 21,400 24,100 6.7 20,800

S (mV/dec) NJD = 10 nm 95.29 92.19 3.4 97.4 84.36 13.0 85.01 84.93 12.2 85.64NJD = 30 nm 83.27 81.12 2.7 89.1 76.91 8.3 79.7 80.91 2.9 81.09

Vds = 0.5 V, NA = 1 · 1017 cm�3, W = 1 lm, d = 100 nm, tox = 4 nm, eox = 3.9, work function (UM) = 4.77 V for SMG and for DMG, (UM1) = 4.77 Vand (UM2) = 4.10 V/4.4 V.

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0 0.2 0.4 0.6 0.8 1

Normalized Position Along The Channel

Cha

nnel

Pot

entia

l (V

)

ModelSimulated, L1/L2=1:3Simulated, L1/L2= 1:1

Simulated, L1/L2=3:1

L-DUM GAC: L=50nm

M1=4.7V

M2=4.1VNJD=30nm

ΦΦ

Fig. 3. Surface potential variation with the normalized channel positionfor L-DUMGAC MOSFET for different combinations of gate length L1

and L2 of M1 and M2, respectively, keeping the sum (L1 + L2) constant.W = 1 lm, d = 100 nm, Vds = 0.2 V and Vgs = 0.1 V.

-0.1

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0 0.2 0.4 0.6 0.8 1

Normalized Position Along The Channel

Cha

nnel

Pot

entia

l (V

)

Simulated, L-DUM GAC

Simulated, SMG Concave

Model

SMG Concave: L=50nm

M1=4.7VL-DUM GAC: L=50nm

L1: L2= 1:1

M1=4.7V

M2=4.1V

NJD=30nmΦ

ΦΦ

Fig. 2(b). Surface potential variation with the normalized channelposition for L-DUMGAC and SMG Concave MOSFET for W = 1 lm,d = 100 nm, Vds = 0.2 V and Vgs = 0.1 V.


increasing the device speed. Hence, scaled devices are fas-ter. Fig. 5(a) gives the threshold voltage variation with gatelength for L-DUMGAC and SMG Concave MOSFET andreflects that L-DUMGAC MOSFET exhibits a lowerthreshold voltage in comparison to its conventional coun-terpart. The threshold voltage is set by the doping andwork functions in long channel devices. However, in shortchannel devices, in addition to these parameters, the lengthof the control gate also determine the threshold voltage asis clear from Fig. 5(b). A close matching between the ana-lytical and simulated results validates the model. As L1

increases keeping L2 the same, threshold voltage increasesdue to reduction in the device’s on current as is discussedby Long et al. [7]. With the proper control over controlgate length, threshold voltage will not be sensitive to justthe gate length; which is a desirable feature in deep-submi-cron technology.

3.1.1. Drain and transconductance characteristicsFig. 6(a) shows the drain characteristics of L-DUM-

GAC devices and SMG for same electrical length (i.e.

0.66

0.68

0.7

0.72

0.74

L2=25nmd=100nm

Vds=0.2V

Vds=0.5V

L-DUMGAC MOSFET

ld V

olta

ge, V

th (V

)


L(SMG) = [L(L-DUMGAC) = L1 + L2 = 50 nm]) andsame effective length (i.e. L(SMG) = L1 = 50 nm and dif-ferent screening gate length, L2’s). As L1 increases keepingL2 the same, the threshold voltage increases, therebydegrading the saturation current. However, as L2 increaseskeeping L (=L1 + L2) same, the electric field peak movestowards the source as is clear from Fig. 4, thereby enhanc-ing carrier transport efficiency and hence, the drain currentdriving capability. Further, as NJD increases, the potential

-3

-2

-1

0

1

2

3

4

5

0 20 40 60 80 100

Position Along The Channel (nm)

Ele

ctri

c F

ield

(|E

|x 1

0 5

V/c

m)

Simulated, L1/L2=1:3Simulated, L1/L2=1:1

Simulated, L1/L2=3:1

L-DUMGAC: L=100nm

M1 =4.7V

M2 =4.1VNJD=30nm

-3

-2

-1

0

1

2

0 20 40 60 80 100

Position Along The Channel (nm)

L-DUM GAC: L1/L2=1:1

M1 =4.7V

M2 =4.1VNJD=30nm

L=100nmL=50nmEle

ctri

c F

ield

E

x 1

0 5

V/c

m)Φ

Φ

ΦΦ

(

Fig. 4. Simulated electric field variation with channel position forL-DUMGAC MOSFET for different combinations of gate length L1

and L2 of M1 and M2, respectively, keeping the sum (L1 + L2) constant.W = 1 lm, d = 100 nm, Vds = 0.2 V and Vgs = 0.1 V. (Inset) Simulatedelectric field variation with channel position for L-DUMGAC MOSFETfor different gate lengths. W = 1 lm, d = 100 nm, Vds = 0.2 V andVgs = 0.1 V. Inset: Simulated electric field variation with channel positionfor L-DUMGAC MOSFET for different gate lengths. W = 1 lm,d = 100 nm, Vds = 0.2 V and Vgs = 0.1 V.

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

40 50 60 70 80 90 100 110

Gate Length,L (nm)

Thr

esho

ld V

olta

ge, V

th (V

)

ModelSimulated, SMG Concave Simulated, L-DUM GAC

NJD=30nm

SMG Concave: M1=4.7VL-DUM GAC : L1: L2=1:1

M1=4.7V

M2=4.1V

Φ

ΦΦ

Fig. 5(a). Threshold voltage variation with gate length for L-DUMGACand SMG Concave MOSFET. W = 1 lm, d = 100 nm and Vds = 0.2 V.

0.6

0.62

0.64

20 40 60 80

Length of Control Gate, L1 (nm)

NJD=30nm

ΦM1=4.7V

ΦM2=4.1VLine: ModelSymbols: Simulated

Thr

esho

Fig. 5(b). Threshold voltage variation with control gate length, L1, forL-DUMGAC MOSFET.

barrier at the corner increases resulting in carrier velocityreduction, which degrades current driving capability asshown in Fig. 6(b). Fig. 6(b) also reflects that with increas-ing work function difference between two metal gates (i.e.by reducing the work function of screening gate, UM2),threshold voltage increases for the same L1/L2 (control gatelength/screening gate length for L-DUMGAC) ratio andhence, degrades the driving current. A close propinquityof the analytical results with the simulated data validatesour model.

Fig. 7 shows the transconductance characteristics ofL-DUMGAC devices and SMG for same electrical lengthand same effective length. In order to make the L-DUM-GAC device characteristics enhancement, in comparisonto SMG Concave MOSFET, more comprehensible, thevariation of transconductance gm with the gate-to-sourcebias, Vgs has been demonstrated. Results clearly reveal thatL-DUMGAC MOSFET has a higher transconductance incomparison to SMG Concave MOSFET and hence, ahigher device efficiency and intrinsic gain.

It clearly reflects that a higher transconductance isexhibited by L-DUMGAC with different length configura-tions, in comparison to its conventional counterpart,proving the proposed device better. The screening gatelength, however, does not make any contribution to theeffective channel length. This is because the effective chan-nel length is described as the effective linear region lengthin the channel potential profile of MOSFETs [5]. In con-ventional SMG MOSFETs, the effective linear regionlength decreases continuously as the drain bias increases.However, in the DMG architecture, the control gatelength is the effective linear region length, that remainsunchanged with the drain bias variations. This is due tothe fact that in L-DUMGAC device, the drain bias vari-ations are not absorbed under the control gate region, M1but under screening gate region, M2, i.e. M1 region is

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0 0.2 0.4 0.6 0.8 1

Gate to Source Voltage, Vgs (V)

Tra

nsco

nduc

tanc

e, g

m (

mS

)

Hollow Symbol : SMG ConcaveL=50nmΦ M1 = 4.7 V

Solid Symbol : L-DUM GAC L=1 00 nm ; L1 : L2 = 1 : 1 L=75 nm ; L1 : L2 = 2 : 1 L=50 nm ; L1 : L2 = 1 : 1

Φ M1 = 4.7 V ; ΦM2 = 4.1 V

NJD=10 nm

Vth = 0.3 V

Fig. 7. Simulated transconductance, gm variation with drain to sourcevoltage, Vgs for L-DUMGAC and SMG Concave MOSFET for differentgate lengths for device width, W = 1 lm and Vds = 0.5 V.

0.00

0.09

0.18

0.27

0.36

0.45

0 0.3 0.6 0.9 1.2 1.5

Drain to Source Voltage, Vds (V)


Dra

in C

urre

nt,

I ds

(mA

/m

)


Solid Symbol : L-DUM GACL=1 00 nm ; L1 : L2 = 1 : 1L=75 nm ; L1 : L2 = 2 : 1 L=50 nm ; L1 : L2 = 1 : 1

Φ M1 = 4.7 V ; Φ M2 = 4.1 V

NJD= 10nm

MODEL

0.00

0.09

0.18

0.27

0.36

0.45

0 0.3 0.6 0.9 1.2 1.5

NJD=30nm


Solid Symbol : L-DUM GACL=100 nm ; L1 : L2 = 1 : 1 (__) Φ M1 = 4.7 V ; Φ M2 = 4.1 V(---) Φ M1 = 4.7 V ; Φ M2 = 4.4 V

NJD=10 nm

μD

rain

Cur

rent

, I d

s(m

A/

m)

μ

Fig. 6. Drain current, Ids variation with drain to source voltage, Vds for L-DUMGAC and SMG Concave MOSFET for device width, W = 1 lmand Vgs = 1.5 V. (a) Device length variation. (b) NJD and metal gate workfunction variation.


screened from drain bias variations resulting in a steppotential profile. The channel, however, is inverted underboth the gates but, since M1 region mainly reflects the lin-ear region and M2 region does not maintain any linearitydue to absorption of drain bias variations, the screeninggate length does not contribute to the effective length.Transconductance (dIds/dVgs) is higher if the drain currentshows enhancement due to the improved gate control.However, if the device exhibits a weak gate control, themagnitude of the drain current can still be higher dueto the effect of drain bias. This effect is, however, notdesirable as it reflects the DIBL effect. Thus, a higherdriving current and a lower transconductance in SMGreflects poor gate control over the channel and an increasein the DIBL.

3.1.2. Device efficiency, intrinsic gain and early voltage

Device efficiency is described in terms of gm/Ids where gm

and Ids, which otherwise, simply defines the device trans-conductance and drain current ,respectively, can also beinterpreted in a different way. In this paper, it has beeninterpreted such that gm represents the amplification pro-vided by the device and drain current represents the energydissipated to achieve this amplification. Its ratio, hence,defines the device efficiency [21,22] which is found to exhi-bit significant enhancement in L-DUMGAC MOSFET ascompared to SMG Concave MOSFET. Since lower draincurrent represents lower energy dissipation required toachieve amplification, when used as an amplifier, this inturns leads to an increased device efficiency i.e. gm/Ids ratioas shown in Fig. 8(a) and (b). gm/Ids ratio can also beviewed as the quality factor of the device, since the trans-conductance represents the amplification delivered by thedevice, and the drain current represents the power dissi-pated to obtain that amplification [21]. Higher the gm/Ids

ratio, higher is the device efficiency. The maximum voltagegain of a MOSFET is obtained when the value of gm/Ids islargest. The largest value of gm/Ids appears in the weakinversion regime for MOSFETs.

Fig. 8(a) shows that for same electrical length, gm/Ids ofL-DUMGAC is marginally superior to SMG. However,for the same effective length, gm/Ids of L-DUMGAC exhib-its significant enhancement in comparison to SMG, as L1

increases. Comparisons with L-DUMGAC MOSFET of75 nm gate length were carried out in order to show theircharacteristics, when they have the same effective gatelength. The control gate length (or the length of M1 region)determines the effective gate length, where there is no effectof drain bias variations as these are absorbed under thescreening gate, M2. Further, comparisons with L-DUM-

0.00E+00

3.00E+01

6.00E+01

9.00E+01

0 0.2 0.4 0.6 0.8 1


Dev

ice

Eff

icie

ncy,

g m

/I ds

(V-1

)

Vth = 0.3 V


Solid Symbol : L-DUM GACL=1 00 nm ; L1 : L2 = 1 : 1L=75 nm ; L1 : L2 = 2 : 1 L=50 nm ; L1 : L2 = 1 : 1

Φ M1 = 4.7 V ; Φ M2 = 4.1 V

NJD=1 0 nm

0.00E+00

3.00E+01

6.00E+01

9.00E+01

1.20E+02

0 0.2 0.4 0.6 0.8 1


Dev

ice

Eff

icie

ncy,

g m

/I ds

(V-1

)


Solid Symbol : L-DUM GACL=100 nm ; L1 : L2 = 1 : 1 (__) Φ M1 = 4.7 V ; Φ M2 = 4.1 V(---) Φ M1 = 4.7 V ; Φ M2 = 4.4 V

NJD=1 0 nm

Vth = 0.3 V

NJD=30nm

Fig. 8. Simulated device efficiency, gm/Ids versus gate to source voltage,Vgs characteristics for L-DUMGAC and SMG Concave MOSFETfor device width, W = 1 lm and Vds = 0.5 V. (a) Device length variation.(b) NJD and metal gate work function variation.

0.00

20.00

40.00

60.00

80.00

100.00

120.00

0 0.2 0.4 0.6 0.8 1

0 0.2 0.4 0.6 0.8 1


Intr

insi

c G

ain,

AV

= g

m/g

d


Solid Symbol : L-DUM GAC L=1 00 nm ; L1 : L2 = 1 : 1L=75 nm ; L1 : L2 = 2 : 1 L=50 nm ; L1 : L2 = 1 : 1

Φ M1 = 4.7 V ; Φ M2 = 4.1 V

NJD= 10nm

Vth = 0.3 V

0.00

20.00

40.00

60.00

80.00

100.00

120.00

140.00

160.00

180.00

200.00


Intr

insi

c G

ain,

AV

= g

m/g

d


Solid Symbol : L-DUM GACL=1 00 nm ; L1 : L2 = 1 : 1 (__) Φ M1 = 4.7 V ; Φ M2 = 4.1 V(---) Φ M1 = 4.7 V ; Φ M2 = 4.4 V

NJD = 1 0nm

NJD=30nm

Vth = 0.3 V

Fig. 9. Simulated intrinsic gain, gm/gd versus gate to source voltage, Vgs

characteristics for L-DUMGAC and SMG Concave MOSFET for devicewidth, W = 1 lm and Vds = 0.5 V. (a) Device length variation. (b) NJDand metal gate work function variation.


GAC MOSFET of 100 nm gate length were carried out inorder to illustrate the impact of screening gate length var-iation on the device characteristics, when they have thesame effective gate lengths.

Table 1 also illustrates that the two structures with thesame electrical length gives comparable performance interms of S and ION/IOFF ratio. This is attributed to thefact that as L1 increases keeping L2 same, electric fieldpeak moves towards the drain, thereby degrading draincurrent driving capability and hence, enhancing the deviceefficiency as is clear from Fig. 8(a). Again, as the workfunction difference of the two gate materials increases,the threshold voltage increases, thereby degrading drivingcurrent, but at the same time, increasing the work func-tion difference improves gate control over the channel,thereby enhancing the device efficiency as shown in

Fig. 8(b). Fig. 8(b) also indicates that as NJD increases,device efficiency increases due to driving current degrada-tion. Lower driving current (or lower carrier transportefficiency), on the other hand, lowers the device cut-offfrequency, on-current and transconductance, therebydegrading the device features for ULSI technology. Car-rier transport efficiency is related to the average carriertransport velocity travelling through the channel, whichis associated with the electric field distribution along thechannel. With DMG architecture, the electric field inthe channel is enhanced, becomes more uniform and theelectrons near the source are accelerated more rapidly,thereby increasing the average electron velocity in thechannel and hence, the carrier transport efficiency. Highercarrier transport efficiency has the advantages of a higherdriving current and higher cut-off frequency of the device.


A trade-off can, thus, be made as per the device applica-tions in the semiconductor technology. Further, highergm/Ids reflects higher Av provided by the device, whenused as an amplifier, as is depicted from Fig. 9(a) and(b). Fig. 9(a) and (b) clearly indicates that L-DUMGACMOSFET exhibits superior performance as compared toSMG Concave MOSFET, in terms of Av and hence pro-vides good figure of merit values, higher gm and lowerdrain conductance, gd, which are generally desired.L-DUMGAC MOSFET also exhibits good turn-on char-acteristics in comparison to SMG Concave MOSFET asis clear from Table 1. Fig. 10(a) and (b) further reflectsa higher VEA exhibited by L-DUMGAC devices in com-parison to SMG Concave due to reduced drain conduc-

0

0.5

1

1.5

2

2.5

3

0 0.2 0.4 0.6 0.8 1


Ear

ly V

olta

ge,

VE

A=

I ds/

g d (

V)

Hollow Symbol : SMG Concave L=50nm

Φ M1 = 4.7 V

Solid Symbol : L-DUM GAC L=1 00 nm ; L1 : L2 = 1 : 1 L=75 nm ; L1 : L2 = 2 : 1 L=50 nm ; L1 : L2 = 1 : 1

Φ M1 = 4.7 V ; Φ M2 = 4.1 V

NJD = 1 0nm

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5


Ear

ly V

olta

ge,

VE

A=

I ds/

g d(V

)


Solid Symbol : L-DUM GACL=1 00 nm ; L1 : L2 = 1 : 1 (__) Φ M1 = 4.7 V ; Φ M2 = 4.1 V(---) Φ M1 = 4.7 V ; Φ M2 = 4.4 V

NJD = 10nm

NJD=30nm

0 0.2 0.4 0.6 0.8 1

Fig. 10. Simulated early voltage, Ids/gd variation with drain to sourcevoltage, Vds for L-DUMGAC and SMG Concave MOSFET for devicewidth, W = 1 lm and Vgs = 0.5 V. (a) Device length variation. (b) NJDand metal gate work function variation.

tance. Increased work function difference between themetal gate electrodes favours gm enhancement and gd

reduction and thus, larger values of voltage gain and earlyvoltage are obtained. However, with reduction in L2 keep-ing L1 same, VEA decreases significantly owing to increasein drain conductance; an outcome of screening effect deg-radation due to weaker gate control. For the same electri-cal length, even though gm increases, the improvementobserved is curtailed by the relative increment in drainconductance. Hence, deterioration in VEA and gm/gd hasbeen observed for same electrical length of 50 nm. Fromthe results obtained, it is observed that with L1/L2 = 1and same effective length with a higher NJD, a significantenhancement in terms of S, ION/IOFF, device efficiency,early voltage and hence, the intrinsic gain of the device,is obtained in comparison to all other device structureconfigurations. Although, the proposed device L-DUM-GAC has marginally lower drain current than SMG, itis counterbalanced by higher transconductance (improvedgate control), higher device efficiency and higher devicegain for high-speed digital, switching and analog applica-tions. Thus, it can be concluded from Table 1, Figs. 8–10that L-DUMGAC with same effective length as SMGConcave and L1/L2 = 1 is most beneficial for VLSI circuitrealization. Thus, by gate material engineering, NJD vari-ations and gate length variations, the desirable effects interms of Vth roll off and other SCEs related behaviourscould be realized.

4. Conclusions

In this paper, a new structure, L-DUMGAC MOSFET,is proposed, analyzed and investigated using ATLAS 3Ddevice simulator. Our work fairly compares the analogand digital performances of L-DUMGAC and SMG Con-cave MOSFET. It is clear from the analytical model andsimulation results that L-DUMGAC MOSFET exhibitssignificant device characteristics enhancement in compari-son to its conventional SMG Concave counterpart. Forlow power-low voltage analog circuit applications, highearly voltage (VEA) and hence, intrinsic gain are the impor-tant design parameters. The proposed structure minimizesSCEs, DIBL and enhances (a) device efficiency, (b) intrinsicgain, (c) early voltage and (d) ION/IOFF ratio in comparisonto SMG Concave MOSFET and hence, presents its appli-cability for high-speed digital, switching and analogapplications.

Acknowledgements

Authors are grateful to Defence Research and Develop-ment Organization (DRDO), Ministry of Defence, Gov-ernment of India and one of the authors (Rishu Chaujar)is grateful to University Grants Commission (UGC) forproviding the necessary financial assistance to carry outthis research work.


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Laterally amalgamated DUal Material GAte Concave (L-DUMGAC) MOSFET for ULSI

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