Embedded wafer level packages with laterally placed and vertically stacked thin dies

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Embedded Wafer Level Packages with Laterally Placed and Vertically Stacked Thin Dies

Gaurav Sharma, Vempati Srinivas Rao, Aditya Kumar, Nandar Su, Lim Ying Ying, Khong Chee Houe, Sharon Lim, Vasarla Nagendra Sekhar, Ranjan Rajoo, Vaidyanathan Kripesh and John H. Lau*

Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research) 11 Science Park Road, Singapore 117685

E-mail: [email protected], Phone: + 65 67705440 *Now with Hong Kong University of Science & Technology

Abstract Two embedded micro wafer level packages (EMWLP)

with (1) laterally placed and (2) vertically stacked thin dies are designed and developed. 3D stacking of thin dies is illustrated as progressive miniaturization driver for multi-chip EMWLP. Both the developed packages have dimensions of 10mm × 10mm × 0.4mm and solder ball pitch of 0.4mm. As part of the work several key processes like thin die stacking, 8 inch wafer encapsulation using compression molding, low temperature dielectric with processing temperature less than 200 C have been developed. The developed EMWLP components successfully pass 1000 air to air thermal cycling (-40 to 125 C), unbiased highly accelerated stress testing (HAST) and moisture sensitivity level (MSL3) tests. Developed EMWLP also show good board level TC (> 1000 cycles) and drop test reliability results. Integration of thin film passives like inductors and capacitors are also demonstrated on EMWLP platform. Developed thin film passives show a higher Q factor when compared to passives on high resistivity silicon platform. Thermo-mechanical simulation studies on developed EMWLP demonstrate that systemic control over die, RDL and package thicknesses can lead to designs with improved mechanical reliability.

Introduction Today consumer electronics comprise 50 % of the total

integrated circuit revenue [1]. Hand held consumer electronics mandate small form factor and footprint area electronic packages. In consumer electronic applications, like cell phone, passives constitute 80 % of components. In cell phones, passives occupy 80 % of circuit board area and contribute 70 % of product assembly cost [1]. Thin film passives integrated with- in the package redistribution layer structure can replace discrete integrated passive devices (IPD) which can lead to progressively miniaturized mobile phone packages. System in Package is a packaging technology platform that enables integration of more than one active electronic component of different functionality plus thin film passives and other devices like MEMS or optical components [1]. Embedded Micro Wafer Level Package is a packaging technology that enables development of low form factor multi-die packages [2]. Multi-die EMWLP combined with thin film passives integration can provide SiP solutions.

In addition to providing SiP solutions EMWLP technology also possesses several advantages over the conventional wafer level packages (WLP). EMWLP provides multi-die packaging solution where as WLP is restricted to a single die. EMWLP process flow is known good die (KGD) based which, results in better wafer level yields in packaging. EMWLP also leads to fan out interconnect fabrication which,

unlike in WLP, can exceed the die foot print area [3]. In WLP high pin count devices can be achieved by increasing the silicon chip size. However, increasing chip size is a large cost adder in the front end. In EMWLP the mold compound material can be used for fabrication of fan out interconnects which is a much more economical way for increasing pin count. In microelectronic developments the shrinkage of pitches and pads at the chip/package interface is much faster than the shrinkage at the package/board interface which leads to the “interconnect gap” problem in packaging [1]. EMWLP provides a cost economical way to increase the package/board pin count thus addressing the “interconnect gap” problem.

In literature, some EMWLP configurations have been reported. Keser et al have reported a chip embedding technology named as redistributed chip package (RCP) where in complete radio-in-package using RCP was demonstrated [4]. Brunnbauer et al have demonstrated a single chip embedded device technology solution [3, 5]. Kripesh et al have shown fabrication and process flow results on a 3D stacked embedded wafer level package with three thin die stacking [6].

In this study two multi-chips EMWLP with (1) laterally placed and (2) vertically stacked thin dies have been designed and developed. The developed multi-die packages have dimensions of 10 mm × 10 mm × 0.4mm and solder ball pitch of 0.4 mm. EMWLP with laterally placed dies and vertically stacked dies have 206 and 350 I/O respectively. As part of this study key processes like wafer thinning with copper pillars, wafer level compression molding, thin die stacking and low temperature dielectric processes have been developed. Several materials like mold compounds with different coefficients of thermal expansion (CTE) and filler contents, molding tapes, dicing die attach films, low temperature dielectric materials have been evaluated and the associated processes are optimized. The entire package fabrication is carried out using wafer level front end processes. The developed packages demonstrate good temperature cycling, MSL3, HAST and drop test reliability results. Thin film passives fabrication on EMWLP platform is also demonstrated. Simulation of thermo-mechanical reliability of EMWLP test vehicles shows that systemic control over package design parameters like die, RDL and package thickness can provide design guidelines to improve mechanical reliability of EMWLP being developed.

Mechanical Modeling & Design of EMWLP Simulation of thermo-mechanical reliability of fabricated test vehicles was carried out using finite element analysis. Figure 1 shows the FEA models for two EMWLP configurations. The environmental condition for the temperature cycle test

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was set at between -40 C to 125 C and run continuously for five cycles. Creep energy strain density (W) which is also known as plastic work is the parameter that is used to compute the number of cycles to failure [7]. For both the test vehicles it is found that joint failure is predicted to occur between solder ball and substrate. The predicted solder joint to fail first is the solder ball joint that is closest to the die. This is attributed to the die edge affect which arises due to high local CTE mismatch adjacent to the die [8]. For both the above test vehicles W plot predicts almost similar number of cycles to solder joint failure. Hence detailed investigation of package design parameter variation on package reliability is carried out for only EMWLP test vehicle 1. RDL, dielectric and package thicknesses were varied to investigate their effect on the package reliability. The RDL is modeled as copper metal and the thickness is varied from 3 to 15 m, which leads to a 25 % decrease in W at the first solder joint failure and hence improves the reliability of the packages. On the other hand when the dielectric thickness was increased from 8 to 20 m it leads to a 50 % increase in W thus reducing the reliability of the packages. A decrease in package thickness also leads to decrease in W thus improving the reliability of the packages. Thinner packages are relatively more flexible and hence lead to less strain on the solder ball joint during thermal cycling thus improving the reliability of the package [8]. Based on the modeling results low dielectric and relatively higher RDL layer thicknesses are chosen in package design and fabrication.

Mold compound

Solder bump FR-4 board

5x5x0.3mm dieRDL + dielectric layer

Copper pad on dieMold compound


5x5x0.3mm dieRDL + dielectric layer

Copper pad on die

Die attach7x7x0.3mm die

Copper posts

5x5x0.1mm die


RDL + dielectric layer

Die attach7x7x0.3mm die

Copper posts

5x5x0.1mm die


RDL + dielectric layer

Figure 1: Finite element analysis models for thermo-mechanical modeling for EMWLP (top) test vehicle 1 and (bottom) test vehicle 2

Process Flow Figure 2 (a) and (b) show a schematic of the EMWLP that

are being developed. In figure 2 (a) package schematic multi-chip integration is achieved by lateral placement of dies. In figure 2 (b) package schematic multi- chip integration is achieved by 3D stacking. To reduce the overall thickness of the package thin dies are fabricated and packaged. For the EMWLP with laterally placed dies the two fabricated die sizes are 5 mm × 5 mm × 0.3 mm and 1.5 mm × 1.2 mm × 0.3 mm. For the EMWLP with stacked dies the die sizes are 5 mm × 5 mm × 0.1 mm & 7 mm × 7 mm × 0.3 mm. For stacked die package copper pillars are electroplated to enable 3D stacking and I/O formation. The interconnects from both chips of the stacked module are brought to the same plane

Figure 2: Schematic showing the EMWLP with (a) laterally placed and (b) vertically stacked dies. In (a) chip 1 and chip 2 are 5 mm × 5 mm × 0.3 mm and 1.5 mm × 1.2 mm × 0.3 mm respectively. In (b) chip 1 and chip 2 are 5 mm × 5 mm × 0.1 mm and 7 mm × 7 mm × 0.3 mm respectively. The dimensions of both package components are 10 mm × 10 mm × 0.4 mm. using different heights of copper pillar interconnects on different chips. Figure 3 shows an overview of the chip wafer fabrication process. As shown in proces steps (I) and (II) the basic die layout comprises of aluminum daisy chain structure passivated with SiO2. For EMWLP with laterally placed dies the die wafers are back grinded to thickness of 300 um. As shown in process steps (III) and (IV) for EMWLP with vertically stacked dies the 5 mm × 5 mm & 7 mm × 7 mm die wafers are electroplated with copper pillars of different heights and then are back grinded to the required thicknesses of 100 um and 300 um respectively. The copper pillar heights and chip thicknesses are decided by package design requirements. Figure 4 shows an overview of the EMWLP fabrication process. Process steps (I) and (II) are only required for EMWLP with vertically stacked dies. (I) The 5 mm thin die wafer is laminated with Dicing Die Attach Film (DDAF) and then diced. (II) The 7 mm thin die wafer is diced separately and the 5 mm dies are stacked on top of the 7 mm dies. (III) The dies and die stacks are then picked and placed on a two adhesive layer moulding tape using wafer level pick and place process. For EMWLP with laterally placed dies the thin wafer die is singulated and dies are then picked and placed on a molding tape. To achieve robust pick and place and wafer moulding process the back side of the moulding tape is laminated on to a silicon support wafer. The molding tape features thermo- release properties, which allows removal of tape after molding. (IV) Pick and place process is followed by wafer level compression molding. The compression molding process is optimized for wafer warpage by using different granular mold compound materials that have different filler contents and CTE. (V) After compression molding the support wafer and dicing ring support are removed. This is followed by post mold cure of the mold compound wafer. (VI) For EMWLP with vertically stacked

Chip 1 Chip 2

Mold compound

(a)

Logic Chip Chip 2

Chip 1 Dicing Die Attach Film

(b)

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dies mold wafer grinding is employed to expose the copper pillars. For EMWLP with laterally placed dies this step is not required since molding tape removal exposes the chip I/O pads on which RDL can be fabricated. (VII) Wafer molding is followed by redistribution layer processing to fabricate the fan out interconnects. Since the molded wafer decomposes at temperatures > 200 C low temperature dielectric process is developed. Two low temperature dielectric materials from separate manufacturers are evaluated that have processing

Figure 3: Process flow for chip wafer fabrication. (I) Thermal SiO2 growth and aluminum deposition and patterning for daisy chain fabrication. (II) SiO2 deposition and patterning for daisy chain passivation. (III) Copper seed layer deposition and dry film lamination and patterning. (IV) Copper pillar electroplating and wafer back grinding.

Figure 4: Overview of the EMWLP fabrication process. (I) Lamination of DDAF on small die & singulation. (II) 3D stacking of small die on big die. (III) Wafer level pick & place of dies on support wafer which is laminated with molding tape. (IV) Wafer level compression molding. (V) Removal of molding tape and support wafer. (VI) Grinding of mold compound wafer to expose copper pillars. (VII) RDL fabrication & solder ball placement.

temperature ranging from 160-200 C. The RDL process is followed by conventional solder ball placement process. The EMWLP are then assembled on Printed Circuit Board, & reflowed.

The package components are subjected to air to air thermal cycling (-40 to 125C), MSL3 and HAST tests. The package components assembled on PCB also undergo air to air thermal cycling (-40 to 125C) and drop tests. Reliability assessment is carried out using daisy chain resistance and chain continuity measurements. Scanning acoustic microscopy is employed to assess delamination and voids in EMWLP.

EMWLP with Laterally Placed Thin Dies Figure 5 below shows 8 inch mold wafer with two

adjacent embedded thin dies. Excellent wafer warpage control during wafer molding can be achieved. Different granular mold compounds that have different coefficients of thermal expansion ranging from 8 to 20 ppm are evaluated as molding materials. The molding temperature is also varied from 125 to 175 C to evaluate its affect on wafer mold-ability and warpage. The lowest CTE mold compound and a molding temperature of 150C yields best mold-ability and warpage results. Figure 6 shows a magnified view of the embedded dies in the mold compound. The two adjacent dies have dimensions of 5 mm × 5 mm and 1.5 mm × 1.2 mm.

Figure 5: 8 inch mold compound wafer with laterally placed thin dies that are embedded in mold compound

After the wafer molding process a two layer redistribution layer is fabricated on the mold compound wafer. For fabrication of RDL layer on the mold compound low temperature dielectric materials having processing temperature of 160 – 200 C are utilized. The adhesion strength of dielectric materials is evaluated using tape peel tests. The RDL stack comprises of dielectric/copper/dielectric/Under Bump Metallization (UBM) layers. Ti/Cu layers are used as UBM. To achieve thick Cu layer electroplated copper is used. Figure 7 shows an individual package component with fabricated RDL. Figure 8 (a) and 7 (b) show an individual package component after the solder ball attach process. The lead free solder ball composition in weight % is Sn - 1.0 Ag – 0.1 Cu –In – 0.04 Ni. The peak reflow temperature used during the reflow

Molding tape

Dicing ring

Support wafer

(I)

(III)

(II)

(VI)

(VII)

(IV) (V)

(I) (II)

(III) (IV)


Figure 6: Laterally placed thin dies after wafer level molding process. The small and big dies have dimensions of 1.5 mm × 1.2 mm and 5 mm × 5 mm respectively.

Figure 7: EMWLP component with laterally placed dies after the redistribution layer process.

profile is 245C and the dwell time above 220C eutectic temperature is 40 seconds. The package components are made to undergo air to air thermal cycling from -40 to 125C. Daisy chain continuity measurements show no failure after 1000 cycles. The package components also successfully pass the unbiased highly accelerated stress test at 130C, 85 % relative humidity for 96 hours and moisture sensitivity level 3 (MSL3) test at 260C reflow. Scanning acoustic microscopy in both through and surface scan mode shows no RDL delamination or voids in the package components after TC, HAST and MSL3 tests. Figure 9 shows a single package component being assembled on the PCB. The package components assembled on board are then subjected to drop tests based on JESD22-B111 standard. Daisy chain continuity measurements on the assembled package qualify the package to pass > 30 drops. The package components assembled on board are also being subjected to air to air -40 to 125C thermal cycling. However, it is determined that underfill is necessary to achieve good board level TC reliability. Underfill NAMICS XS8410-73C is employed and the samples have passed 1000 cycles with out any failure.

(a)

(b) Figure 8: (a) EMWLP component after solder ball

placement. (b) A close up view of I/O pads on chip after solder ball placement process.

EMWLP with Vertically Stacked Dies For developing the EMWLP with vertically stacked dies some of the key processes that were developed are: thinning of wafers that had electroplated copper pillars. Uniform electroplated copper pillar heights and suitable back grinding tape is required to ensure that wafer thinning can be completed with-out wafer breakage during the wafer back grinding process. Uniform electroplating is achieved by using low current density electroplating and rack type wafer electroplating cell configuration. Copper pillars during wafer thinning are protected using UV curable Adwill E-8320 back grinding tape. As shown in figure 4 on EMWLP process flow, die stacking is achieved using dicing die attach films. The DDAF is laminated onto the small die and then diced. Dicing feed and speed are optimized to achieve minimum chipping of silicon die and whisker formation in the DDAF. The smaller 5 mm die is then stacked on top of the 7 mm die. Figure 10 shows a stacked structure with the two thin dies. During the stacking process the bond force, bond time and bond temperature parameters are optimized to achieve void free and uniform bond line DDAF thickness. For DDAF A bond temperature of 120 C, bond force 2.5 Kg and bond time of 1

Mold compound


Figure 9: Shows a single EMWLP assembled on the printed circuit board. EMWLP has two embedded dies.

second leads to void free and uniform bond line thickness die attachment. For DDAF B the optimum bond temperature, bond force and bond time are 130 C, 2.5 Kg and 3 seconds respectively. Since the DDAF becomes an integral part of EMWLP with stacked dies the DDAF is qualified to pass the HAST and MSL3, TC tests. DDAF A and B also demonstrate good shear strength of 2 2.4 Kg/mm2 before and after the MSL3 and HAST tests. The two die stack is then placed on a molding tape using wafer level pick and place processes. The molding tape has adhesive on both the sides. One side adhesive is of thermal release type that leads to drastic drop in adhesive strength when heated to a certain temperature. Thus after the molding process the molded wafer with embedded dies can easily be removed using the thermal release method. The other side adhesive is pressure sensitive type which is used to attach a support wafer during molding. After carrying out pick and place of the die stack on the molding tape with the support wafer the wafer undergoes compression molding process. Molding is carried out using granular mold compounds that have different filler contents and coefficients of thermal expansion. Wafer warpage and die shift are two major problems encountered during the wafer molding process. The lowest CTE mold compound leads to both reductions in warpage and die shift. We have evaluated different grades of molding tapes that have different thermal release temperatures and adhesive strengths. The thermal release temperatures range from 120 to 200C. The highest thermal release temperature molding tape has highest associated adhesive strength. Using the highest adhesive strength tape leads to reduction in die shift during the wafer molding process. Reducing the molding temperature also

Figure 10: Two thin stacked dies with copper pillars. Stacking is achieved using dicing die attach film. The top and the bottom dies have dimensions as 5mm × 5mm × 0.1mm and 7mm × 7mm × 0.3mm respectively. The DDAF has bond line thickness of 0.025mm.

Figure 11: Vertically stacked dies after mold wafer grinding process to expose the copper pillars. Three rows of copper pillars from the inner die and one row of copper pillar from outer die are visible. leads to reduction in die shift during wafer molding. Molding temperatures ranging from 125 to 175C were evaluated. 150 C molding temperature was found to reduce die shift and also lead to excellent mold-ability. After the molding and tape release process post mold cure is carried out. For EMWLP with vertically stacked dies mold wafer grinding is carried out to expose the copper pillars. Figure 11 shows two dies embedded inside the mold compound with the exposed copper pillars. After exposing the copper pillars RDL is fabricated on the copper pillar structure. Figure 12 shows the RDL fabricated on the two dies that are embedded inside the mold compound. Reliability assessment of EMWLP with vertically stacked dies is currently undergoing.

Mold compound


Figure 12: EMWLP component with vertically stacked dies after the RDL layers have been fabricated.

Thin Film Passives on EMWLP Platform Thin film passives were fabricated on EMWLP platform.

Figure 13 shows an inductor and capacitor fabricated on mold compound wafer. The passives have a stack up structure of four layers namely: metal 1 (5m) / dielectric 1 (5m) / metal 2 (8m) / dielectric 2 (2m). Copper is used as the metal in the stack up. A low temperature dielectric with dielectric constant of 2.6 and loss tangent of 0.003 is used for fabrication of thin film passives. The substrate mold compound wafer has loss tangent and dielectric constant values of 0.009 and 4.3 respectively. The mold compound wafer thickness is 500 micron. The usage of such low loss materials in passive fabrication leads to superior electrical performance when compared to passives fabricated on high resistivity silicon wafers. For similar inductance values the inductors demonstrate a 100 % improvement in Q factor over inductors fabricated on high resistivity silicon wafers.

(a) (b) Figure 13: An (a) inductor and (b) capacitor fabricated on

the mold compound wafer. Conclusions & Recommendations EMWLP with laterally placed and vertically stacked dies are designed and developed as part of this study. The entire package fabrication has been carried out using wafer level front end silicon manufacturing technologies. Some of the important results are summarized as following: (1) For successful EMWLP fabrication the most critical

process is wafer level molding, which was optimized in this study.

(2) The developed EMWLP components are demonstrated to have passed HAST, MSL3, drop and temperature cycling (1000 cycles) tests.

(3) Thin film passives integration employing low temperature dielectrics on EMWLP platform is also successfully demonstrated.

(4) The fabricated passives demonstrate superior electrical performance when compared to passives fabricated on high resistivity silicon, which can be attributed to low electrical loss properties of dielectric and mold compound materials.

(5) It is shown that the developed EMWLP platform can not only integrates multiple dies but also thin film passives thus enabling a SiP solution.

(6) The EMWLP with 3D chip stacking demonstrates the potential of 3D stacking based EMWLP as a driver for progressive package miniaturization.

(7) The low electrical loss properties of the developed EMWLP system in this study would enable applications of EMWLP in high frequency applications.

(8) Thermo-mechanical reliability modeling using finite element analysis demonstrates that systemic control over die, RDL and package thicknesses can lead to package designs with improved mechanical reliability.

(9) Following material and process combinations are recommended for the achievement of low warpage and die shift during wafer level molding: (a) low CTE mold compound (b) moderate molding temperature of 150°C, and (c) high adhesive strength molding tape.

Acknowledgments The authors would like to gratefully acknowledge funding

for this work by industry consortium members under the 9th Electronic Package Research Consortium the members of which are Asahi Glass Co. Ltd, ASM Technology Singapore Pte Ltd, Hynix Semiconductor Inc., Infineon Technologies Asia Pacific Pte Ltd, Ibiden Singapore Pte Ltd, Kinergy Limited, Nitto Denko (Singapore) Pte Ltd, NXP Semiconductors, Samsung Electro-Mechanics Co Ltd, Sumitomo Bakelite Singapore Pte Ltd, Victrex PLC and the Institute of Materials Research & Engineering.

Special thanks to Sumitomo Bakelite for mold compound and dielectric materials, Ashai Glass Company for dielectric materials and Nitto Denko for mold compound and molding tape materials support to our technology development efforts.

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Breakthrough for Advanced Packaging,”Proc 57thElectronic Components and Technology Conf, Reno, NV, May. 2007, pp. 286-291.

3. Brunnbauer, M, “An Embedded Device Technology Based on a Molded Reconfigured Wafer,” Proc 56th Electronic Components and Technology Conf, San Diego, CA, May. 2006, pp. 547-551

4. Keser, B, “Advanced Packaging : The Redistributed Chip Package,” IEEE Trans Adv Pckg, Vol. 31, No. 1 (2008) pp 39-43.


5. Brunnbauer, M, “Embedded Wafer Level Ball Grid Array (eWLB),” Proc 8th Electronics Packaging Technology Conf, Singapore, Dec. 2006, pp. 1-5.

6. Kripesh, V, “Design and Development of a Multi-Die Embedded Wafer Level Package,” Proc 58th Electronic Components and Technology Conf, Orlando, FL, May. 2008, pp. 1544-1549.

7. Syed, A, “Accumulated creep strain and energy density based thermal fatigue life prediction models for SnAgCu solder joints,” Proc 54th Electronic Components and Technology Conf, Las Vegas, NV, Feb. 2004, pp. 737-746.

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Embedded wafer level packages with laterally placed and vertically stacked thin dies

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