Large-Capacity Compact Optical Buffer Based on InP Integrated Phased-Array Switch and Coiled Fiber...

396 JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. 29, NO. 4, FEBRUARY 15, 2011

Large-Capacity Compact Optical Buffer Basedon InP Integrated Phased-Array Switch and

Coiled Fiber Delay LinesTakuo Tanemura, Member, IEEE, Ibrahim Murat Soganci, Student Member, IEEE, Tomofumi Oyama,

Takaharu Ohyama, Shinji Mino, Senior Member, IEEE, Kevin A. Williams, Member, IEEE,Nicola Calabretta, Member, IEEE, H. J. S. Dorren, Member, IEEE, and Yoshiaki Nakano, Member, IEEE

Abstract—Optical buffering has been one of the major technicalchallenges in realizing optical packet switching (OPS) routers.While fiber-delay-line-based (FDL) buffers are the most practicaland realistic solution to offer useful amount of capacity, the bulki-ness of long FDLs and optical switches has been the main obstacleto practical implementation. This paper demonstrates a compactoptical buffer with up to 750-ns capacity and 50-ns temporalresolution by using an InP integrated 1 16 optical phased-arrayswitch and compact FDL module based on thin-cladding highlynonlinear fiber (HNLF). Owing to the high mode confinementinside HNLF, 15 fibers with the total length of 1.2 km are coiledonto a single bobbin with a coin-sized footprint without increasingthe propagation loss. At the interface between the InP switch andFDLs, a pitch-converting silica planar-lightwave circuit chip is em-ployed to achieve 16-port simultaneous uniform interconnection.Using the developed module, variable optical buffering experimentis demonstrated, where the packet intervals are expanded from 20to 70 ns successfully.

Index Terms—Fiber delay lines (FDL), integrated photonic cir-cuits, optical buffers, optical packet switching (OPS).

I. INTRODUCTION

O PTICAL packet switching (OPS) has been consideredas a potentially attractive approach in realizing future

power-efficient scalable photonic networking [1]–[3]. In OPSnetworks, high-capacity data packets are buffered and switchedin the optical domain without power-consuming optical–elec-tronic–optical conversion. One of the major technical challengesin building an OPS router is the lack of optical buffer with suffi-cient performance, which is essential to resolve contention and

Manuscript received July 18, 2010; revised October 29, 2010; accepted De-cember 09, 2010. Date of publication December 23, 2010; date of current ver-sion February 02, 2011. This work was supported in part by the Grant-in Aid forScientific Research (S) under Grant 20226008 and in part by the Japan Societyfor the Promotion of Science.

T. Tanemura, I. M. Soganci, T. Oyama, and Y. Nakano are with the ResearchCenter for Advanced Science and Technology, University of Tokyo, Tokyo 153-8904, Japan (e-mail: [email protected]).

T. Ohyama and S. Mino are with NTT Photonics Laboratories, NTT Corpo-ration, Atsugi 243-0198, Japan.

K. A. Williams, N. Calabretta, and H. J. S. Dorren are with the COBRA Re-search Institute, Eindhoven University of Technology, Eindhoven 5600 MB, TheNetherlands.

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org

Digital Object Identifier 10.1109/JLT.2010.2102338

congestion of colliding packets having a same destination port[3]–[5].

A widely used rule-of-thumb for electronic router suggeststhat the buffer size needs to be equal to the bitrate-delay-productof the link. This can lead to a buffer size as large as 1 GB fora 40-Gb/s link, which is unrealistically large to realize all-op-tically. However, it has been shown recently that with a smallsacrifice in link throughput, the required buffer size can be re-duced to as small as 10 to 20 packets [6], [7]. These findingshave opened new opportunities for optical buffers as a poten-tially useful solution.

Various types of optical buffer have been considered anddemonstrated to date, including slow-light devices based onsemiconductor optical amplifiers [8], coupled ring resonators[9], [10], and photonic crystals [11]. Although significantimprovements have been made over the years on these tech-nologies, they suffer from limited time-bandwidth product,large optical loss, and/or large power consumption, which makethem impractical for the near future solution [12].

Currently, the most practical and realistic approach is to useoptical delay lines combined with fast optical switches, eitherin a serial, parallel, or recirculating loop configuration. Thesetypes of buffer are particularly attractive in terms of broadoptical bandwidth, low noise, and low power consumption,which are nearly insensitive to the delay time. They have beenimplemented successfully using either integrated waveguides[13]–[15] or optical fibers [16], [17]. While the former is advan-tageous in terms of small footprint and potential integrabilitywith optical switches, the maximum amount of delay is usuallylimited to around 100 ns due to the footprint and propagationloss of the waveguide. Although they should be useful forintrapacket synchronization, the capacity is still insufficientfor interpacket buffering. On the other hand, the latter schemebased on fiber delay lines (FDLs) can offer sufficiently largeamount of delay with low insertion loss [18]–[20], but thebulkinesses of FDLs and switches have hindered practicalimplementation. In [16], e.g., 16 bundles of standard FDLsare used in combination with cascades of commercial 1 8PLZT switches. Miniaturization of both FDL and switchis mandatory to realize a practical FDL-based optical buffer.At the same time, efficient multiport interconnection betweenlarge-scale integrated switch and FDLs is essential forcompact packaging.

In this paper, we report a compact variable optical bufferwith a large storage capacity up to 750 ns with 50-ns time

0733-8724/$26.00 © 2011 IEEE

TANEMURA et al.: LARGE-CAPACITY COMPACT OPTICAL BUFFER BASED ON INP INTEGRATED PHASED-ARRAY SWITCH AND COILED FIBER DELAY LINES 397

Fig. 1. Schematic of single-stage variable optical buffer with double (a) andsingle (b) switch configurations. (a) Double switch configuration, (b) singleswitch configuration.

resolution (16 channel), using a monolithic InP 1 16 switchand a compact FDL module. By using high-index-contrasthighly nonlinear fiber (HNLF) with 60- m-thin cladding [21],15 FDLs with total length of 1.2 km are coiled onto a singlecompact bobbin. For the interface between the switch andFDLs, a pitch-converting silica planar-lightwave circuit (PLC)is newly developed, which enables efficient coupling of thelight out from 16 output ports of the InP switch simultaneously.Using the module, variable optical buffering experiment isdemonstrated, where the packet intervals are expanded from 20to 70 ns successfully.

In Section II, we describe the configuration of entire bufferunit and explain details of its key components: an InP inte-grated 1 16 switch, silica PLC interface chip, and compactFDL module. Then in Section III, we present the results on op-tical buffering experiment. Discussion on the effect of coherentcrosstalk is given in Section IV. Finally, the paper is summa-rized in Section V.

II. OPTICAL BUFFER BASED ON FIBER DELAY LINES

Fig. 1 shows the single-stage variable all-optical buffer unitwith two different configurations. The double-switch configura-tion, as shown in Fig. 1(a), consists of a fast optical switch,

FDLs with linearly increasing length, and another op-tical switch. When a packet arrives, the and switchesselect the appropriate optical path for each packet, where it ex-periences different temporal delay.

Alternatively, one of the switches can be replaced with a pas-sive coupler, as shown in Fig. 1(b). This clearly has an ad-vantage in terms of simplified configuration and reduction ofrequired number of switches. On the other hand, inherent op-tical loss at the passive coupler and reduction of extinction ratiocompared with the double-switch configuration may become

the drawback in case of large . Due to the limitation of ex-perimental equipments, however, we demonstrate this simpli-fied single-switch configuration in this paper. The significanceof using the double-switch configuration will be discussed inSection IV.

It has been shown that the buffer size should be at least10–20 packets to achieve sufficient throughput of over 0.8 [6],[7]. Given that majority of IP packets carry 1024 bytes of data(ignoring the acknowledgement packets of 40 bytes) [20], thelength of each packet would be around 41 ns if, e.g., we assumea bitrate of 200 Gb/s. This leads to a calculation that the buffershould have a maximum storage time of around 410 to 820 nswith a resolution of 41 ns. These values would double if weassume the bitrate of 100 Gb/s. In any case, significant amountof delay time is required, and currently, this is only possible byusing long FDLs. In order to realize sufficiently large storagecapacity in a small footprint, we propose to employ 15 ultra-thin-cladding HNLFs for the FDLs and a monolithic InP 1 16switch to select the optical path among them.

In the following, we describe the details of the three key ele-ments consisting the buffer: an InP 1 16 switch, 16-port silicaPLC interface chip, and compact FDL module.

A. InP Optical Phased-Array 1 16 Switch

The layout of 1 16 InP phased-array switch is shown inFig. 2(a). Input light is dispersed spatially at the first star cou-pler and directed to 24 arrayed phase shifters. By changing thephase linearly (with modulo ) across the array, we can dy-namically control the destination port at the second star couplerwith the reconfiguration time of several nanoseconds [22], [23].Since 1 16 switching is achieved using a single phase-shiftingstage, we expect a potential advantage in terms of footprintand optical insertion loss when increasing the port count fur-ther [24]. Moreover, the antisymmetric waveguide design withconstant optical path lengths among the arrayed waveguides as-sures broadband wavelength-insensitive operation covering theentire -band [23], which makes it particularly attractive forwavelength-division-multiplexed (WDM) [25] or optical-time-domain-multiplexed (OTDM) packet switching [26] with arbi-trary modulation format.

The cross sections at the phase shifter and passive sectionare shown schematically in Fig. 2(b). The entire chip has anidentical p-i-n InP/InGaAsP heterojunction epitaxial structuregrown by single metal–organic vapor phase epitaxy (MOVPE).The guiding layer is 500-nm-thick undoped bulk InGaAsPthat has a photoluminescence peak at a wavelength of 1.3 m(Q1.3). By injecting current into this InGaAsP core layer,efficient phase modulation is achieved through band-fillingand free-carrier plasma effects. The waveguide width is set to3.5 m at the phase shifters and 2 m at the passive wave-guide sections, which is laterally tapered to 5 m at the inputand output interfaces. The waveguides were fabricated bysingle-step shallow reactive ion etching, followed by standardplanarization and electrodes patterning techniques. The dimen-sions of fabricated switch are 4.1 mm 2.6 mm.

The fabricated device demonstrated static switching with anaverage extinction ratio of 18.6 dB, on-chip loss below 7 dB, andwavelength dependence of less than 0.8 dB in the entire -band(1530–1565 nm). The rise and fall times (10%–90%) were 11.0


Fig. 2. Layout (a) and cross section schematic (b) of 1 � 16 optical-phased array switch with 24 phase shifters. The switch dimensions are4.1 mm� 2.6 mm.

and 5.4 ns, respectively, which included the dynamic responseof the driver circuit. More information about the switching char-acteristics has been reported in [23].

B. 16-Port Silica PLC Interface Chip

In order to couple light out from all 16 ports of the switch si-multaneously, we developed a silica–PLC interface chip, whichconnects the 30- m-pitch InP switch output to a commerciallyavailable 127- m-pitch 16-port fiber array. We should note thatit is also possible to expand the output pitch of InP switch to 127

m, which would eliminate the need for such an interface cir-cuit. In this case, however, the footprint of InP switch increasessignificantly, resulting in higher cost and optical insertion lossof the entire module. Owing to the mature PLC technology andless-expensive silica material, we expect that this hybrid archi-tecture should be a cost-effective approach to multiport couplingof large-scale InP switches.

The layout and structure of PLC circuit are shown schemat-ically in Fig. 3 . We employed an embedded silica waveguidestructure with high refractive index contrast of 2.5%, corethickness of 3.5 m, and width of 4.5 m. For the ease of align-ment, the waveguide was laterally tapered to 6.5 m at the in-terface to InP switch.

Fig. 4 shows the fiber-to-fiber loss of all 16 outputs of the 116 switch, measured using the PLC pitch converter to couple

all outputs simultaneously (dots). For comparison, we also plotthe results obtained using a lensed fiber, where each output portwas coupled and optimized independently (circles). The lossdifference between these two cases is plotted with triangles. Theexcess coupling loss of PLC from that of lensed fiber is keptbelow 2.3 dB with a maximum deviation of 0.9 dB among all16 ports, indicating that simultaneous and uniform coupling is

Fig. 3. Schematic of the silica-PLC pitch converting circuit. Chip size is14 mm� 7 mm. At the interface, waveguide width is tapered laterally from 4.5to 6.5 �m for the ease of alignment.

Fig. 4. Fiber-to-fiber loss of all 16 outputs of the 1 � 16 switch module mea-sured using the 16-port PLC pitch converter (dots). The results are comparedwith those obtained using a lensed fiber (circles), where each output port is cou-pled and optimized separately.

achieved. From a separate measurement, we estimate the cou-pling loss between the lensed fiber and InP waveguide to bearound 5 dB, which implies that the coupling loss between thePLC and InP should be around 7 to 8 dB. (It should be notedthat the input facet of switch was accidently damaged duringthe measurement, so that the absolute value of loss, as shown inFig. 4, has increased by more than 10 dB from those reported inour previous publications [23], [26].) The coupling loss may bereduced further by applying antireflection coating and verticalspot-size converters at both interfaces.

C. Compact FDL Module Using Thin-Cladding HNLFs

In order to realize sufficiently large storage capacity in a smallfootprint, we employ ultrathin-cladding HNLFs for the FDLs.Owing to the highly confined optical mode in the HNLF, theouter cladding could be thinned down to a diameter of 60 m.As a result, we could coil the fibers onto a compact bobbin with abending radius as small as 7.5 mm without inducing mechanicaldamage and optical loss [21].

To achieve the temporal resolution of 50 ns and buffering sizeof 16 packets, 15 fibers with the lengths ofm lengths (total lengths of 1.2 km) were coiled onto a singlebobbin. The schematic and photograph of the module are shownin Fig. 5. The dimensions are 40 mm in diameter and 20 mmin height, and 15 input/output fibers are fed out from the topside. Table I shows the basic optical properties of coiled FDLs.Fiber-to-fiber losses for the 15 FDLs range from 0.4 to 0.9 dB,


Fig. 5. Schematic and photograph of the coiled FDL module. 15 HNLFs witha total length of 1.2 km is coiled onto a single compact bobbin. The bobbin sizeis 40 mm (diameter) � 20 mm (height).

TABLE IPROPERTIES OF COILED FDLS

which include the splicing losses at the both ends. Although thenonlinear coefficient is higher (13 W km ) than a standardsingle-mode fiber, nonlinear effects should be negligible for thefiber length of 150 m, as long as optical peak power is lowerthan 1 W, which is the case for practical implementation.

It should also be noted that the FDLs used in this experi-ment exhibited relatively large chromatic dispersion ofps/nm/km. With the maximum delay length of 150 m, the al-lowable serial bitrate is calculated to be around 172 Gb/s for anon-return-to-zero OOK format [27]. We, therefore, assume toemploy wavelength-multiplexed packet format [25] to achievebitrates of 200 Gb/s and higher. At the same time, it is possibleto fabricate thin-cladding FDLs with lower chromatic disper-sion [21] to allow higher serial bitrate.

III. OPTICAL BUFFERING EXPERIMENT

A packet switching experiment was carried out to test variableoptical buffering function using our modules. The experimentalsetup is shown in Fig. 6. Due to the limitation of the setup,the simple single-switch configuration depicted in Fig. 1(b) wasdemonstrated, where an passive coupler was employedat the output. Also, for simplicity, optical label recognition andprocessing [25 ], [26] were not demonstrated in this experiment.

At the transmitter, a periodic series of 16 optical packets with10-Gb/s payload (PRBS7), 30-ns duration, and 20-ns guard time(shown in the inset of Fig. 6) was generated by using two-stageLiNbO (LN) modulators. The first modulator (LN1) generateda continuous train of 10-Gb/s PRBS packets having 30-ns du-ration and 20-ns guard time, while the second modulator (LN2)was used to gate bursts of 16 packets. The guard time of 20ns was chosen to accommodate the 11-ns response time of the

Fig. 6. Setup for optical buffering experiment. 16 packet trains with 30-ns du-ration and 20-ns guard time are generated and input to the buffer. LD: laserdiode, PPG: pulse-pattern generator, FG: function generator, PC: polarizationcontroller.

switch and timing jitter caused at the driving circuit. The packettrain was amplified, aligned to TE polarization state, and in-jected into the buffer. A 4-bit digital control signal was inputto the switch driver to reconfigure the switch path within the20-ns guard time. The output packets from the FDLs were com-bined using a 16 1 passive coupler and sent to the receiverfor characterization. In order to equalize the residual nonunifor-mity of the output power among ports, variable optical attenu-ation (VOA) was applied by bending some of the fiber pigtailswith a small bending radius. In future, this power equalizationmay be achieved in a more controlled manner by adjusting thesplicing condition of each FDL or by intentionally detuning thedriving conditions of the switch.

Fig. 7(a) shows the optical waveforms at the input, respec-tive output ports of the switch (Port 1–16), and output of the16 1 passive coupler. In this particular scenario, 16 packetsare forwarded sequentially to respective output ports to experi-ence different delays. As a result, the packet intervals of 20 nsat the input are expanded successfully to 70 ns after the buffer,and the maximum delay of 750 ns is achieved with the 150-mFDL. A bursty packet traffic at the input is thus shaped into amore uniform traffic pattern at the output.

Due to the insufficient extinction ratio of the switch, theresidual components in the neighboring packets (after tempo-rally shifted by FDLs) combine coherently at the output couplerand cause signal degradation. This is observed explicitly inFig. 7(b), which displays the magnified eye diagrams at theedge (Packet #1) and center (Packet #9) of the output packetstream. While clear waveform is obtained at the edge (#1),where there is no crosstalk from other packets, it is distortedseriously at the center (#9), where the crosstalk componentsfrom all other 15 ports interfere coherently. The effect of thiscrosstalk is discussed in the next section.

IV. DISCUSSION ON CROSSTALK IMPAIRMENTS

It is important to investigate the impairments caused byresidual crosstalk and derive the required extinction ratio of the

switch. Under a practical condition of sufficiently largeextinction ratio, the dominant term of noise at the receiver is thesignal-crosstalk beat noise, where the relative intensity noise(RIN) is described as [28]

(1)


Fig. 7. Packet waveforms observed at the input, 16 output ports of the switch(P1-16), and buffer output (a) with magnified views of Packet #1 and #9 (b).

Here, is the average extinction ratio of theswitch, where and are the output power in the

ON and OFF states, respectively. We assume that switching effi-ciencies to all ports are equalized by the VOAs, so that crosstalkfrom each FDL arm combines with an equal degree at the output.Note that corresponds to the inverse of crosstalk ratio pa-rameter defined in [28 ]. In (1), is multiplexed by thetraffic load to account for the fact that the proba-bility of having crosstalk from neighboring packet slots is pro-portional to the load. In addition, it is further multiplexed byanother factor of , assuming the mark ratio of the data tobe . Finally, accounts for the polarization averaging ef-fect. Since we employ nonpolarization maintaining FDLs withlengths sufficiently longer than the beat length, the polarizationstates of interfering packets should be distributed randomly overthe Poincaré sphere. In such a case, we can assume .

If the decision threshold is optimized in the presence ofcrosstalk, the power penalty to achieve specific bit-error-rate(BER) at the receiver is expressed as [28]

(2)

where is linked to the BER as

(3)

In Fig. 8, we plot (2) as a function of for the case of, and under different values

Fig. 8. Calculated power penalty at BER of �� , induced by coherentcrosstalks with increasing traffic load �� . Single-switchconfiguration [see Fig. 1(b)] is assumed to emulate the experiment.

Fig. 9. Required extinction ratio of each �� switch to achieve power penaltyof less than 2 dB �� . The double switching configuration [see Fig. 1(a)]is assumed. The required extinction ratio simply doubles in case of the singleswitch configuration [see Fig. 1(b)].

of load . The penalty increases rapidly and approaches infinityat dB for , indicating that noise floor arises inthe BER curve. It is obvious from Fig. 8 that error-free opera-tion is impossible even at a low traffic load of 0.4 with the 1 16switch having an average extinction ratio of 18.6 dB, which wasused in our experiment.

One approach to solve this problem is to replace the passivecoupler at the output to another switch, as described

in Fig. 1(a). In this case, the total extinction ratio doubles to37.2 dB. Fig. 8 reveals that this should be sufficient to achievea BER of with a power penalty of less than 1 dB.

To allow multihop transmission of optical packets, we needhigher extinction ratio. The total RIN in (1) should simply bemultiplied by the number of hops . Fig. 9 shows the re-quired extinction ratio of each switch to achieve the powerpenalty of less than 2 dB as a function of . Weassume the double switch configuration [see Fig. 1(a)], but therequired extinction ratio is simply doubled (in dB) in the caseof single switch [see Fig. 1(b)]. From Fig. 9, in order to achieve20 hops with and , e.g., the extinction ratio ofeach 1 16 switch should be at least 20.3 dB at BER of .This value should be within the reach with further optimizationof array design and driving condition of the switch. Moreover,if we employ forward-error-correction (FEC) and allow BER


of , the required extinction ratio drops down to 17.5 dB,which is already in the attainable range with current devices.

V. CONCLUSION

We have demonstrated a variable optical buffer with up to750-ns storage capacity and 50-ns temporal resolution usinga monolithically integrated InP optical phased-array 1 16switch and a compact FDL module. By using HNLF with60- m thin cladding, 15 FDLs with total length of 1.2 kmwere coiled onto a single coin-sized compact bobbin. At theinterface between the InP switch and FDLs, a pitch-convertingsilica PLC chip was employed to achieve 16-port simultaneousuniform interconnection. We have theoretically shown thatmultihop transmission should be feasible by using the doubleswitch configuration with another 16 1 switch at the output.Owing to the broad bandwidth of the switch, PLC, and FDLs,the module should be applicable to high-speed optical packetswith WDM or OTDM payloads encoded by arbitrary modula-tion format.

ACKNOWLEDGMENT

The first author would like to thank M. Takahashi,R. Sugizaki, and T. Yagi of Furukawa Electric Companyfor providing the fiber-delay-line module.

REFERENCES

[1] S. J. B. Yoo, “Optical packet and burst switching technologies forthe future photonic internet,” J. Lightw. Technol., vol. 24, no. 12, pp.4468–4492, Dec. 2006.

[2] R. S. Tucker, “The role of optics and electronics in high-capacityrouters,” J. Lightw. Technol., vol. 24, no. 12, pp. 4655–4673, Dec.2006.

[3] H. J. S. Dorren, N. Calabretta , and O. Raz, “Scaling all-optical packetrouters: How much buffering is required?,” J. Opt. Netw., vol. 7, no.11, pp. 936–946, Nov. 2008.

[4] D. K. Hunter, “Buffering in optical packet switches,” J. Lightw.Technol., vol. 16, no. 12, pp. 2081–2094, Dec. 1998.

[5] E. F. Burmeister, D. J. Blumenthal, and J. E. Bowers, “A comparison ofoptical buffering technologies,” Opt. Switch. Netw., vol. 5, pp. 10–18,2008.

[6] M. Enachescu, Y. Ganjali , A. Goel, and N. McKeown, “Part III:Routers with very small buffers,” ACM Comput. Commun. Rev., vol.35, no. 3, pp. 79–82, 2005.

[7] N. Beheshti, Y. Ganjali, R. Rajaduray, D. Blumenthal, and N. McK-eown, “Buffer sizing in all-optical packet switches,” presented at theOpt. Fiber Commun. Conf., Anaheim, CA, 2006, Paper OThF8, un-published.

[8] C. J. Chang-Hasnain and S. L. Chuang, “Slow and fast light in semicon-ductor quantum-well and quantum-dot devices,” J. Lightw. Technol.,vol. 24, no. 12, pp. 4642–4654, Dec. 2006.

[9] F. N. Xia, L. Sekaric , and Y. Vlasov, “Ultracompact optical buffers ona silicon chip,” Nature Photon., vol. 1, no. 1, pp. 65–71, Jan. 2007.

[10] N. K. Fontaine, J. Yang , Z. Pan, S. Chu, W. Chen, B. E. Little, and S. J.B. Yoo, “Continuously tunable optical buffering at 40 gb/s for opticalpacket switching networks,” J. Lightw. Technol., vol. 26, no. 23, pp.3776–3783, Dec. 2008.

[11] M. Davanco, A. M. Xing , J. Raring, E. L. Hu, and D. J. Blumenthal, “Detailed characterization of slow and dispersive propagation near amini-stop-band of an inp photonic crystal waveguide,” Opt. Express,vol. 13, pp. 4931–4938, 2005.

[12] R. S. Tucker, “Capabilities and limitations of slow light optical buffers:Searching for the killer application,” in Proc. Conf. Lasers Electro-Opt., Baltimore, MD, May 2009, pp. 1–, Paper JTuB1.

[13] H. Park, J. P. Mack, D. J. Blumenthal, and J. E. Bowers, “An inte-grated recirculating optical buffer,” Opt. Express, vol. 16, no. 15, pp.11124–11131, Jul. 2008.

[14] J. P. Mack, E. F. Burmeister , H. N. Poulsen, B. Stamenic, J. E. Bowers,and D. J. Blumenthal, “Synchronously loaded optical packet buffer,”IEEE Photon. Technol. Lett., vol. 20, no. 21, pp. 1757–1759, Nov.2008.

[15] J. D. LeGrange, J. E. Simsarian , P. Bernasconi, L. Buhl, J. Gripp,and D. T. Neilson, “Demonstration of an integrated buffer for an all-optical packet router,” IEEE Photon. Technol. Lett., vol. 21, no. 12, pp.781–783, Jun. 2009.

[16] H. Furukawa, H. Harai, N. Wada, N. Takezawa, K. Nashimoto, andT. Miyazaki, “A 31-FDL buffer based on trees of 1� 8 PLZT opticalswitches,” in Proc. Eur. Conf. Opt. Commun., Sep. 2006, pp. 1–2, PaperTu4.6.5.

[17] E. F. Burmeister, J. P. Mack, H. N. Poulsen, J. Klamkin, L. A. Col-dren, D. J. Blumenthal, and J. E. Bowers, “SOA gate array recircu-lating buffer with fiber delay loop,” Opt. Express, vol. 16, no. 12, pp.8451–8456, Jun. 9, 2008.

[18] N. Ogashiwa, H. Harai , N. Wada, S. Kubota, and Y. Shinoda, “Multi-stage fiber delay line buffer in photonic packet switch for asynchro-nously arriving variable-length packets,” IEICE Trans. Commun., vol.E88-B, no. 1, pp. 258–265, Jan. 2005.

[19] H. Yang and S. J. B. Yoo , “All-optical variable buffering strategiesand switch fabric architectures for future all-optical data routers,” J.Lightw. Technol., vol. 23, no. 10, pp. 3321–3330, Oct. 2005.

[20] G. Das, R. S. Tucker , C. Leckie, and K. Hinton, “Multiple-input single-output FIFO optical buffers with controllable fractional delay lines,”Opt. Express, vol. 16, no. 26, pp. 21849–21864, Dec. 2008.

[21] M. Takahashi, Y. Mimura , J. Hiroishi, M. Tadakuma, R. Sugizaki,M. Sakano, and T. Yagi, “Investigation of a downsized silica highlynonlinear fiber,” J. Lightw. Technol., vol. 25, no. 8, pp. 2103–2107,Aug. 2007.

[22] T. Tanemura, M. Takenaka, A. Al Amin, K. Takeda, T. Shioda, M.Sugiyama, and Y. Nakano, “InP/InGaAsP integrated 1� 5 opticalswitch using arrayed phase shifters,” IEEE Photon. Technol. Lett., vol.20, no. 12, pp. 1063–1065, Jun. 2008.

[23] I. M. Soganci, T. Tanemura , K. A. Williams, N. Calabretta, T. de Vries,E. Smalbrugge, M. K. Smit, H. J. S. Dorren, and Y. Nakano, “Monolith-ically integrated InP 1� 16 optical switch with wavelength-insensitiveoperation,” IEEE Photon. Technol. Lett., vol. 22, no. 3, pp. 143–145,Feb. 2010.

[24] T. Tanemura and Y. Nakano , “Design and scalability analysis of op-tical phased-array 1�� switch on planar lightwave circuit,” IEICEElectron. Exp., vol. 5, no. 16, pp. 603–609, Aug. 2008.

[25] T. Tanemura, K. Takeda , and Y. Nakano, “Wavelength-multiplexedoptical packet switching using InP phased-array switch,” Opt. Express,vol. 17, no. 11, pp. 9454–9459, May 2009.

[26] I. M. Soganci, N. Calabretta , T. Tanemura, W. Wang, O. Raz, K.Higuchi, K. A. Williams, T. de Vries, H. J. S. Dorren, and Y. Nakano,“160-Gb/s optical packet switching subsystem with a monolithic op-tical phased-array switch,” IEEE Photon. Technol. Lett., vol. 22, no.11, pp. 817–819, Jun. 2010.

[27] A. F. Elrefaie, R. E. Wagner , D. A. Atlas, and D. G. Daut, “Chromaticdispersion limitations in coherent lightwave transmission systems,” J.Lightw. Technol., vol. 6, no. 5, pp. 704–709, May 1988.

[28] H. Takahashi, K. Oda , and H. Toba, “Impact of crosstalk in an arrayed-waveguide multiplexer on� �� optical interconnection,” J. Lightw.Technol., vol. 14, no. 6, pp. 1097–1105, Jun. 1996.

Takuo Tanemura (S’02–M’06) received the B.E., M.Sc., and Ph.D. degrees inelectronic engineering, all from the University of Tokyo, Japan, in 2001, 2003,and 2006, respectively.

In 2006, he joined the Department of Electronic Engineering, the Universityof Tokyo and moved to the Research Center for Advanced Science and Tech-nology, University of Tokyo, in 2007, where he is currently a Lecturer. SinceMarch 2010, he has been a Visiting Scholar at Ginzton Laboratory, StanfordUniversity. His research interests include semiconductor photonic integratedcircuits, photonic switching networks, and optical interconnection.

Dr. Tanemura is a member of the Institute of Electronics, Information andCommunication Engineers of Japan. He was the recipient of the 2005 IEEEPhotonics Society Graduate Student Fellowships and the Ericsson Young Sci-entist Award 2006.


Ibrahim Murat Soganci (S’01) received the B.S. and M.S. degrees fromBilkent University, Ankara, Turkey, in 2005 and 2007, respectively, both inelectrical and electronics engineering. He is currently working toward thePh.D. degree at the Electronics Engineering Department, University of Tokyo,Tokyo, Japan.

During his M.S. thesis, he was engaged in research on the utilization of semi-conductor and metal nanoparticles for improved performance of optoelectronicdevices. His current research interests include integrated optical space switchesand their applications in large-capacity optical packet switching networks.

Mr. Soganci was awarded the IEEE Photonics Society 2010 Graduate StudentFellowship in addition to several scholarships by Japanese Ministry of Educa-tion, Global Center of Excellence in Electronics at the University of Tokyo, theScientific Research Foundation of Turkey, Bilkent University, and Turkish Min-istry of Education.

Tomofumi Oyama received the B.Sc. degree in electronic engineering fromTohoku University, Japan, in 2009. Since April 2009, he has been a graduatestudent of the Department of Electronic Engineering, Graduate School of Engi-neering, University of Tokyo.

His current research interests include InP photonic switching devices.

Takaharu Ohyama received the B.E. degree from Kyusyu Institute of Tech-nology, Fukuoka, in 1992, and the M.E. degree from Kyusyu University,Fukuoka, in 1994.

In 1994, he joined NTT Opto-Electoronics Laboratories, NTT Corporation,Atsugi, Japan, where he is currently with NTT Photonics Laboratories, andwhere he has been engaged in research on hybrid integration in silica-basedplanar lightwave circuits and semiconductor devices.

Mr. Ohyama is a member of the Institute of Electronics, Information andCommunication Engineers of Japan.

Shinji Mino (S’88–M’96–SM’09) received the B.Sc. degree in chemistry fromWaseda University, Tokyo, in 1986, and the M.Sc., and Ph.D. degrees in chem-istry and electronic engineering from Tokyo University, Tokyo, in 1988 and1996, respectively.

In 1988, he joined NTT Opto-Electronics Laboratories, NTT Corporation,Atsugi, Japan, where he is currently a Group Leader in the Photonic Integra-tion Laboratory, NTT Photonic Laboratories, and where he has been engagedin research on garnet film for waveguide-type isolator devices. From 1993 to2003, he was engaged in research on the hybrid integration of various activeoptical devices and electronic ICs, focusing particularly on the use of high-fre-quency circuits in silica planar lightwave circuits (PLCs). From 2006 to 2008,he was involved in the research and development of novel functional photoniccomponents for PLC-free-space optic modules using liquid crystal, and since2008, he has been engaged in research on PLC hybrid-integration technologyrelated to LiNbO modulators, and photodiodes for use in high-speed coherenttransmitters and receivers. His research interests include various types of PLChybrid integration with respect to optical active devices and electronic ICs, suchas liquid crystal devices, LiNbO modulators, and optical semiconductor de-vices, such as photodiodes, laser diodes, and modulators.

Dr. Mino is a Senior Member of the IEEE Lasers and Electro-Optics Society,the Institute of Electronics, Information and Communication Engineers, and amember of the Japan Society of Applied Physics.

Kevin A. Williams (M’00) received the B.Eng. degree in electrical engineeringfrom the University of Sheffield, Sheffield, U.K., in 1991, and the Ph.D. degreein physics from the University of Bath, Bath, U.K., in 1995.

He was awarded a Royal Society University research fellowship at the Uni-versity of Bristol, Bristol, U.K., in 1996, and moved to the University of Cam-bridge, Cambridge, U.K., in 2001, where he was a Lecturer and a Fellow atChurchill College. In 2006, he was awarded a Marie Curie Chair at the Eind-hoven University of Technology, where he is currently with COBRA ResearchInstitute, The Netherlands. His research interests include the design, realization,and demonstration of high-speed integrated photonic circuits.

Nicola Calabretta (M’04) received the Bachelor’s and M.S. degrees in telecom-munications engineering, both from Politecnico di Torino, Turin, Italy, in 1995and 1999, respectively, and the Ph.D. degree from COBRA Research Institute,Eindhoven University of Technology, Eindhoven, The Netherlands, in 2004.

In 1995, he visited the RAI Research Center (Italian broadcasting television),Turin, Italy. From 2004 to 2007, he was a Researcher at the Scuola SuperioreSant’Anna University, Pisa, Italy. He is currently with COBRA Research Insti-tute, Eindhoven University of Technology, Eindhoven, The Netherlands. He isa coauthor of more than 120 papers published in international journals and con-ference proceedings. He holds three patents. His current research interests in-clude all-optical signal processing for optical packet switching, semiconductoroptical amplifier, all-optical wavelength conversion and regeneration, and ad-vanced modulation formats for optical packet switching.

Dr. Calabretta is a Referee for several journals of the IEEE and the Institutionof Electrical Engineers, and the Optical Society of America.

H. J. S. Dorren (M’09) received the M.Sc. and Ph.D. degrees from UtrechtUniversity, Utrecht, the Netherlands, in 1991 and 1995, respectively.

In 1996, he joined Eindhoven University of Technology, Eindhoven, theNetherlands, where he is currently a Full Professor and the Scientific Directorof the COBRA Research Institute. In 2002, he was also a Visiting Researcherat the National Institute of Industrial Science and Technology, Tsukuba, Japan.He is a coauthor of more than 250 journal papers and conference proceedings.His research interests include optical packet switching, digital optical signalprocessing, and ultrafast photonics.

Prof. Dorren was an Associate Editor for the IEEE JOURNAL OF QUANTUM

ELECTRONICS during 2005–2009.

Yoshiaki Nakano (S’81–M’87) received the B.E., M.S., and Ph.D. degrees inelectronic engineering, all from the University of Tokyo, Japan, in 1982, 1984,and 1987, respectively.

In 1984, he spent a year at the University of California, Berkeley, as an ex-change student. In 1987, he joined the Department of Electronic Engineering,University of Tokyo, where he became an Associate Professor in 1992, a Pro-fessor in 2000, and the Department Head in 2001. He moved to the ResearchCenter for Advanced Science and Technology, University of Tokyo, in 2002,where he became the Director General in 2010 and a Professor. He is also withthe Department of Electronic Engineering, School of Engineering, the Univer-sity of Tokyo. In 1992, he was a Visiting Associate Professor at the Universityof California, Santa Barbara. He is the author or coauthor of more than 250 ref-ereed journal publications and more than 500 international conference papers.He holds 40 patents. His research interests include physics and fabrication tech-nologies of semiconductor distributed feedback lasers, semiconductor opticalmodulators/switches, monolithically-integrated photonic circuits, and high-ef-ficiency heterostructure solar cells.

Dr. Nakano is a Fellow of the Institute of Electronics, Information, andCommunication Engineers (IEICE), Japan Society of Applied Physics (JSAP),a member of the IEEE Electron Device Society, and the Optical Society ofAmerica. He was an elected member of the Board of Governors of IEEE Laserand Electro-Optics Society; a member of the Board of Directors of the JSAP,the Editor-in-Chief of the Applied Physics Express, and the Japanese Journal ofApplied Physics; and a member of the Board of Directors of the Japan Instituteof Electronics Packaging. He is currently the Chairman of the OptoelectronicsTechnology Trend Research Committee of the Optoelectronics Industry andTechnology Development Association (OITDA), and the Chairman of the Op-tical Interconnect Standardization Committee of Japan Electronics Packagingand Circuits Association. He served as the Project Leader of the JapaneseNational Project on “Photonic Networking Technology” organized by theMinistry of Economy, Trading, and Industry (METI), and as the Project Leaderof SORST Program on “Non-Reciprocal Semiconductor Digital PhotonicIntegrated Circuits and their Applications to Photonic Networking” sponsoredby Japan Science and Technology Corporation. He is currently the ProjectLeader of the METI National R&D Project on “Post-Silicon Solar Cells forUltraHigh Efficiencies.” He is the recipient of the 1987 Shinohara MemorialPrize from the IEICE, the 1991 Optics Paper Award from the JSAP, the 1997Marubun Science Prize, the 2007 Ichimura Prize, the 2007 IEICE ElectronicsSociety Award, and the 2007 Sakurai Medal from the OITDA. He was alsothe recipient of the Prime Minister Award in Collaborative Research betweenAcademia and Industry in 2007.

Large-Capacity Compact Optical Buffer Based on InP Integrated Phased-Array Switch and Coiled Fiber...

Documents

Transcript of Large-Capacity Compact Optical Buffer Based on InP Integrated Phased-Array Switch and Coiled Fiber...