IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 30, NO. 3, AUGUST 2007 377

A Novel Design Structure for WLCSP With HighReliability, Low Cost, and Ease of Fabrication

Shu-Ming Chang, Chih-Yuan Cheng, Li-Cheng Shen, Kuo-Ning Chiang, Senior Member, IEEE, Yu-Jiau Hwang,Yu-Fang Chen, Cheng-Ta Ko, and Kuo-Chyuan Chen

Abstract—Wafer level chip scale packaging (WLCSP) has someadvantages, such as real die size packaging, high electrical per-formance, and low manufacturing cost. However, because the me-chanical reliability of a large die can not be guaranteed due tothe coefficient of thermal expansion (CTE) mismatch between sil-icon and organic printed circuit board (PCB), WLCSP technologyis still not fully accepted. We have developed a new solder jointprotection-WLCSP (SJP-WLCSP) structure with a delaminationlayer interposed between the top layer of the chip and the bottominsulating layer of the metal redistribution traces. The stress on thesolder joints can be released by the cracks forming in the delami-nation layer, which protects the solder joints from cracking. Sincethe cracking of the delamination layer is irrelevant to the electricalcircuits of the packaging, the packaged integrated circuits (IC) de-vice remains functional. One of the possibilities for processing theSJP-WLCSP was implemented and validated successfully in theSiLK-wafer samples. The board level packaging samples, using thedaisy chain resistance measurement passed 1000 cycles of the tem-perature cycling testing.

Index Terms—Delamination layer, memory, wafer level chipscale packaging (WLCSP).

I. INTRODUCTION

BECAUSE of the thermal expansion mismatch between thesilicon chip and the organic printed circuit board (PCB)

(3 silicon versus 14–16 for FR-4), underfillencapsulation is usually needed to ensure solder joint reliabilityfor the flip-chip type package. However, the underfill operationincreases the manufacturing cost and reduces the throughput. Inaddition, reworking an underfilled chip on PCB is very difficult.At the same time, the pitch and size of the pads are very smalland put a great demand on the supporting PCB. High-densityPCBs are commonly available, but at a higher cost. Therefore,the wafer level chip scale packaging (WLCSP) class of pack-aging provides a solution to these problems. The use of metalto redistribute the fine-pitch pads on the chip to larger-pitcharea-arrayed pads on the PCB is one of the features of mostWLCSP structures [1]. The first redistributing technology usingtwo polyimide dielectric layers and one metal layer to redis-

Manuscript received May 19, 2006; revised December 7, 2006.S.-M. Chang, C.-Y. Cheng, L.-C. Shen, Y.-J. Hwang, Y.-F. Chen, C.-T. Ko,

and K.-C. Chen are with the Packaging Technology Division, EOL/ITRI, 0R100EOL/ITRI/ 195-4, Hsinchu 310, Taiwan, R.O.C. (e-mail: SMChang@itri.org.tw).

K.-N. Chiang is with the Advanced Microsystem Packaging and Nano-Mechanics Research Laboratory, Department of Power Mechanical Engi-neering, National Tsing Hua University, Hsinchu 30043, Taiwan, R.O.C.

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TADVP.2007.901773

tribute peripheral pads on a silicon die to an area array of padswith larger pad size and pitch was reported by Chanchani et al.[2]. It not only facilitates die testing to obtain “known gooddie,” but also allows cost-effective flip chip assembly using stan-dard surface mount equipment and processes. WLCSP has someadvantages, such as low cost, high performance, and minimalpackaging size. The packaging and interconnection are fabri-cated on the entire wafer prior to dicing, and no underfill isused in most cases. With the reduction in package mass relativeto the solder joint strength, WLCSP is expected to have bettershock and vibration resistance, particularly in drop tests wherequite a few chip scale packaging (CSP) packages have failedand required underfill to reinforce their mechanical strength inboard connection [3]. Therefore, after the packaging processes,the bare die can be mounted directly onto the PCB substrate.Since there is no underfill used for WLCSP assemblies, thesolder joints are subject to very large shear stresses resultingin cracks being formed inside the solder joints due to the largecoefficient of thermal expansion (CTE) mismatch between sil-icon chip and organic PCB. For larger die sizes or distanceto the neutral point (DNP), the solder joints suffer more shearstrains [4]. Therefore, many techniques have been developed torelease shear stresses in the solder joints due to the large CTEmismatch between the silicon chip and the FR-4 PCB, espe-cially for the large die application with WLCSP technology.These technologies can be roughly divided according to threemajor features. One is the use of a soft stress buffer layer (evenair gaps) which are formed under the solder bumps to releasethe shear stress in the solder joints [5]–[8]. Another one of thefeatures was developed by the Fujitsu Company by forminghigh copper posts to increase the gap between the chip andthe PCB in order to reduce the shear stress in the solder joints[9]. The larger gap enhances the mechanical reliability. Thethird feature involves extending the wire bonding technologyso that microsprings are formed as a joint for the electrical cir-cuit between the silicon chip and the FR-4 substrate [10]. Thisspring easily releases any mechanical stresses. However, someissues remain to be improved before these technologies can beconsidered for widespread use. For the technologies using astress buffer layer, only a few materials with low Young’s mod-ulus were developed, and the degree of softness and the thick-ness of the stress buffer layer are related closely to the me-chanical reliability. The other methods that were proposed usemore complex processes in order to get better mechanical reli-ability, but they come with higher production cost. Therefore, anovel solder joint protection-WLCSP (SJP-WLCSP) architec-ture without stress buffer layer, and just using standard semi-conductor integrated circuits (IC) processing technology is pro-

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378 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 30, NO. 3, AUGUST 2007

Fig. 1. Schematic cross-sectional structures for (a) a WLCSP with solder jointcracking, (b) SJP-WLCSP, and (c) the mechanism of stress release in the SJP-WLCSP.

posed and validated. This paper presents the SJP-WLCSP struc-ture which is designed to protect the solder joints from cracking,and also explains the integration of the processes and the resultsof the temperature cycling testing.

II. STRUCTURE

The SJP-WLCSP is a new concept developed to releasethe shear stress in the solder joints due to the CTE mismatchbetween silicon chip and organic PCB. In traditional WLCSPstructures, the solder joints are the weakest part of the diemounted on the organic PCB, with the solder joints sufferingmost of the shear stress. Cracks are easily formed inside thesolder joints in order to release the stress from the large CTEmismatch during the temperature cycling testing. A schematiccross-sectional structure is shown in Fig. 1(a). Cracking of thesolder joints will break the electrical circuits and result in thefailure of the IC device. The basic idea behind the SJP-WLCSPis to form a delamination layer interposed between the bottominsulation layer of the metal redistribution traces and the toplayer of the silicon chip. A schematic cross-sectional structureof the SJP-WLCSP is shown in Fig. 1(b). Instead of the solderjoints, the delamination layer will be the weakest part of theSJP-WLCSP structure after assembly. This delamination layerwill delaminate or crack in order to release the shear stresscaused by the CTE mismatch between the silicon chip and theorganic PCB when the shear stress of the solder joints overloadsduring the temperature cycling testing. The fracturing of the

Fig. 2. Diagram for the testing chip layout.

delamination layer will not damage any of the electrical circuitsof the packaging structure. As a result, the stress of the solderjoints can be released easily through the forming of cracks in thedelamination layer, and the IC devices remain functional. Theschematic cross-sectional structure of the SJP-WLCSP afterthe cracking of the delamination layer is shown in Fig. 1(c).

A dynamic random access memory (DRAM) with a chip sizeof 14.280 mm 6.850 mm was chosen to be the test vehicle.The contact solder pads of this dummy memory die were 116 area array with a pitch of 0.8 mm. The electrical circuit of thewhole device was designed as a daisy chain, so as to allow in situmeasurement of the resistance during the accelerated tempera-ture cycling testing. A diagram of the chip layout is shown inFig. 2.

III. PROCESSES

Six-inch wafers were spin-coated with various materials asa top layer of the dummy wafers, respectively. The commonmaterials used as the insulating layer of metal traces, such aspolyimide (PI-wafer) and low-k SiLK (SiLK-wafer) materialswere chosen as the coatings. Then, a delamination layer wasformed on the surface of the top layer using metal sputtering,photolithography, and etching. According to previous reports[11], [12], the adhesion strength between metal and some low-kmaterials such as SiLK was found to have poor adhesion nat-urally. On the other hand, the adhesive strength between metaland some insulating materials can be weakened further if thestep of plasma etching was removed. This is based on the mech-anism that a step of plasma treatment on the surface of polymerlayer can make the surface rougher prior to metallization andenhance the adhesion strength between them [13], [14]. There-fore, a thin metal layer of titanium collocated with polyimide orSiLK material was chosen to validate if the idea of SJP-WLCSPwas workable at the first phase of the experiments. The thick-ness of the metal layer was about 0.1 . After the delami-nation layer was formed, photopatternable polyimide materialused as the bottom insulating layer (BIL) for the metal redis-tribution traces was spin coated on the wafer and defined. Thethickness of the bottom insulating layer was about 5 . Thenext step was a Ti/Cu/Ni/Au redistribution layer (RDL) formedby Ti/Cu sputtering, Ni electroplating followed by immersion inAu. The Ti/Cu/Ni/Au thin film redistribution layer was chosenfor its ability to produce both the redistribution trace as wellas the under bump metalization (UBM) in one thin film layer.The reliability of this system has been well characterized for itsresistance to solder diffusion [7], [15]. Subsequently, the top in-sulating layer (TIL) of the metal redistribution traces was spin

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CHANG et al.: A NOVEL DESIGN STRUCTURE FOR WLCSP WITH HIGH RELIABILITY, LOW COST, AND EASE OF FABRICATION 379

Fig. 3. Processing flow chart for SJP-WLCSP.

TABLE ISPECIFICATION OF THE DRAM TEST VEHICLE FOR SJP-WLCSP

coated and defined with the same material as for the BIL to formthe area-array solder pads with a diameter 340 on the chips.The polyimide material for the BIL and the TIL, HD-4001, wasprovided by HD MicroSystems (Taipei, Taiwan, R.O.C.). Forthe WLCSP application, HD-4001 was chosen for the dielec-tric layers because it had been tested earlier and passed the re-liability tests, including the precondition level 1 and pressurecooker tests following the JEDEC standards [7]. In addition, itcan be photopatterned and it is easily processed. Solder ballsof 63/37 SnPb with a diameter of 0.4 were used as thesolder joints. A standard ball attachment process of flux, ballplacement and reflow was used for attaching the solder balls.Finally, the chips were assembled on the FR-4 PCB with highTg (glass transition temperature) using a standard SMT processafter wafer dicing. The flow chart of the entire process is shownin Fig. 3. Table I lists the specification of the DRAM test vehiclein detail for the SJP-WLCSP. Fig. 4(a) and (b) shows the im-ages of the dummy DRAM chips before assembly on the organicFR-4 PCB. The finished dummy dual in-line memory modules(DIMMs) were then plugged in the motherboards with an elec-trical connection to the in situ resistance measurement system.The image of the DIMMs plugged in a motherboard is shown inFig. 5.

Fig. 4. Images of the dummy DRAM chips with the SJP-WLCSP structure.

Fig. 5. Image of a motherboard plugged in the DIMMs for in situ resistancemeasurement.

Fig. 6. Cross-sectional SEM images of a SiLK-wafer sample after soldering.

Temperature cycling testing is the biggest challenge for diesusing the WLCSP technology. It must be noted here that mostof the materials we used, such as HD-4001 polyimide for theBIL and TIL, and the Ti/Cu/Ni/Au metal traces, already passedthe other items of the reliability tests [7]. Therefore, tempera-ture cycling testing between -40 and 125 for the boardlevel packaging will be the major reliability testing item re-ported in this paper. The accelerated temperature cycling testingwas based on the JEDEC standard.

IV. RESULTS AND DISCUSSION

Fig. 6(a) and (b) shows the cross-sectional scanning electronmicroscope (SEM) images of a SiLK-wafer sample after sol-dering. It is evident that the delamination layer, the titaniumthin film, was still well adhered to the top layer of the chipand the BIL. The average height of the solder bumps is about330 . Shear testing of the solder bumps was first to be usedto test if the idea of SJP-WLCSP was workable. The top viewimages of the PI- and SiLK-wafer samples, after shear testing

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380 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 30, NO. 3, AUGUST 2007

Fig. 7. Top view images for (a) the PI-wafer sample and (b) the SiLK-wafersample after shear testing of the solder bumps.

of the solder bumps are shown in Fig. 7(a) and (b), respec-tively. Two different fracture modes in the PI-wafer sampleswere found. One was an interface fracture along the delamina-tion layer. It was the preferred fracture type for our experimentaldesign. However, another fracture mode with a ductile fracturethrough the solder ball was also found. This fracture mode, usu-ally seen in previous WLCSP structures [5], [7], [8] was notthe desired mode for the SJP-WLCSP since it went against ourdesign concept of releasing the stress caused from the CTE mis-match between silicon chip and FR-4 board. However, only onekind of fracture mode was found in the SiLK-wafer samples.The fracture interface was identified to be the interface betweenthe SiLK top layer of the silicon chip and the titanium delami-nating layer. The average shear strength of the PI-wafer and theSiLK-wafer samples are 196.6 and 122.0 gm, respectively. Al-though, the PI-wafer samples were not suitable for further tem-perature cycling testing due to the ductile fractures through thesolder ball, which were contrary to the designed mechanism ofthe SJP-WLCSP. However, in order to compare the results withthe SiLK-wafer samples after temperature cycling testing, westill did the same reliability testing for the PI-wafer samples.

Fig. 8(a) and (b) shows the cross-sectional SEM images ofa SiLK-wafer sample across the position – , as shown inFig. 2 after 1000 cycles of the temperature cycling testing forboard level packaging. It clearly shows that the shear stress ofthe solder joints, due to the CTE mismatch between silicon chipand FR-4 PCB, was released by the forming of a crack in thespecially designed titanium delamination layer instead of insidethe solder joints. No cracks were found in the solder joints. Fromthe results of the in situ resistance measurement system withdaisy chain monitoring, no obvious change was found for theresistance. Therefore, the cracks forming in the delaminationlayer did not influence the electrical performance for the SJP-WLCSP samples. Fig. 9(a) and (b) shows the cross-sectionalSEM images of a SiLK-wafer sample across the position B–B’,as shown in Fig. 2 after 1000 cycles of the temperature cyclingtesting for board level packaging. It can be seen that the crackstopped propagating at the end of the delamination layer.

On the other hand, for the PI-wafer samples, testing samplesstarted to fail due to the opening of the electrical circuits withdaisy chain monitoring. The mean lifetime of the sampleswas about 150 cycles of -40 to 125 temperature cy-cling testing. The cross-sectional SEM images of a PI-wafersample after 1000 temperature cycling testing are shown inFigs. 10(a) and (b). The difference with the SiLK-wafer sam-ples was that cracks were found in some of the solder joints

with a normal failure mode as was observed in most of theWLCSP structures after temperature cycling testing. For thePI-wafer samples, solder joint cracking was due to the factthat the adhesion strength between the titanium delaminationlayer and the BIL or polyimide top layer of Si chip was stilltoo strong in some of the solder bumps of the die as a resultof the shear testing of the solder bumps. Consequently, thesesolder joints were still the weakest part of the SJP-WLCSP.We tried to weaken the adhesion strength of the interfacebetween the polyimide top layer of the chip and the titaniumdelamination layer by changing the depositing condition of thetitanium metal thin film on the polyimide surface. However, auniform adhesion strength at the polyimide/titanium interfacewas still not obtained. Therefore, if even only one of the solderjoints was the weakest part within the die, it would cause thesample to fail after temperature cycling testing with daisy chaindesign. Polyimide is a material usually used in chip scale pack-aging as the insulting layer for metal traces.So, most of themwere added with a promoter to enhance the adhesion strengthbetween the metal traces and itself [16]. Therefore, a weakadhesion strength between metal thin film and polyimide couldbe obtained by removing the promoter in the application for thebottom insulating layer (BIL) of RDL or the top layer of siliconchip. Besides the metals, there should be many other materialssuitable as a delamination layer with properties suitable for theSJP-WLCSP structure.

This experiment would like to validate the design idea of re-leasing the shear stress of the solder joints for the SJP-WLCSPat the initial stage. Therefore, only one of the possibilities wasimplemented and reported in this paper. The stress release of thesolder joints due to the CTE mismatch between silicon chip andorganic FR-4 PCB can be validated successfully in the SiLK-wafer samples. Because simple and standard IC processing stepswere used for the entire production of SJP-WLCSP, its fabri-cation is very easy. As to the cost of manufacturing; since nospecial materials and processing tools are used, the fabricationcosts are low. In this paper, the mechanism of stress releasefor SJP-WLCSP simply uses a delamination layer interposedbetween the top layer of the wafer and the bottom insulatinglayer of the metal redistribution traces under the solder bumps.A small crack formed in the delamination layer easily releasesthe shear stress of the solder joints. Therefore, the SJP-WLCSPstructure can protect the solder joints from cracking and avoidthe failure of samples due to the electrical opening up of solderjoints. In addition, due to the shear stress in the solder jointscan be reduced significantly by the small cracks formed in thedelamination layer. The Ti/Cu/Ni/Au interconnections withinthe dielectric layer materials are repeatedly flexed during thechanges in temperature, as shown in Fig. 1(c). Therefore, themechanical reliability of SJP-WLCSP could be independent ofthe size of the solder bumps and the Young’s modulus of thestress buffer materials used. The SJP-WLCSP structure has ahigh potential to be applied to electrical devices with a largedie size and high pin counts. From previous literature [17], it isalso known that the simplest WLCSP structure without any spe-cial design for enhancing the mechanical reliability can be usedfor a small die size with . The WLCSP struc-ture just uses a two layer dielectric system of BCB materials

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CHANG et al.: A NOVEL DESIGN STRUCTURE FOR WLCSP WITH HIGH RELIABILITY, LOW COST, AND EASE OF FABRICATION 381

Fig. 8. Cross-sectional SEM images of a SiLK-wafer sample across position A�A , as shown in Fig. 2 after temperature cycling testing.

Fig. 9. Cross-sectional SEM images of a SiLK-wafer sample across position B� B , as shown in Fig. 2 after temperature cycling testing.

Fig. 10. Cross-sectional SEM images of a PI-wafer sample after temperature cycle testing.

and a thin TiW/Cu/Ni/Au metal redistribution layer. Therefore,a hybrid structure with a delamination layer or not in a die canalso be implemented for a large die size application. This hybridstructure will enhance the attached strength of the die mountedon the FR-4 PCB. However, the strength of the die attachmentwas found to be good even with all of the bumps having theSJP-WLCSP structure in a die.

V. CONCLUSION

A novel SJP-WLCSP technology with high reliability, lowcost, and easy fabrication was implemented and validated suc-cessfully in the SiLK-wafer samples. The mechanism for stressrelease of solder joints due to the large mismatch between sil-icon chip and organic FR-4 PCB simply used a delaminationlayer interposed between the top layer of the silicon chip andthe bottom insulating layer of the metal redistribution traces.Instead of the solder bumps, the delamination layer will be theweakest part of the SJP-WLCSP after assembly. The shear stressof the solder joints can be released easily by the cracks that formin the delamination layer, and these cracks will not result in anydamage to the electrical performance of the IC devices.

From the cross-sectional SEM analysis, the images of the newSJP-WLCSP structure show that the mechanism designed to re-lease the shear stress of the solder joints due to the CTE mis-match between silicon chip and FR-4 PCB works very well onthe SiLK-wafer samples. Even after 1000 cycles of temperaturecycling testing for the board level packaging, samples with daisychain resistance measurement in the in situ monitoring systemcan pass the temperature cycling testing. On the other hand, themean lifetime of temperature cycling testing for PI-wafer sam-ples was only about 150 cycles. From the results of the sheartesting of the solder bumps for the PI-wafer samples, the uni-formity of the fracture mode was related to the low lifetime ofthe temperature cycling testing. Not only was the fracture at thedelaminating layer found, but the ductile fracture through thesolder balls was seen as well.

Because the Ti/Cu/Ni/Au interconnections within the dielec-tric layer materials are repeatedly flexed during the changes intemperature after the cracks formed in the delamination layer.The mechanical reliability of SJP-WLCSP could be irrelevantto the size of the solder bumps and the Young’s modulus of thestress buffer materials used. Therefore, the SJP-WLCSP struc-

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382 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 30, NO. 3, AUGUST 2007

ture will have great potential to be applied to electrical deviceswith a large die size and high pin counts.

ACKNOWLEDGMENT

The authors would like to thank the Ministry of the EconomicAffairs (MOEA), Taiwan, R.O.C., for performing this project.S.-M. Chang would like to thank the Dow Chemical Companyin Taiwan for providing the low-k materials and wafers in thisexperiment.

REFERENCES

[1] J. H. Lau, S. H. Pan, and C. Chang, “A new thermal-fatigue life pre-diction model for Wafer Level Chip Scale Package (WLCSP) solderjoints,” J. Electron. Packag., vol. 124, pp. 212–220, Sep. 2002.

[2] R. Chanchani, K. Treece, and P. Dressendorfer, “A new mini Ball GridArray (mBGA) multichip module technology,” Int. J. MicrocircuitsElectron. Packag., vol. 18, no. 3, pp. 185–192, 1995.

[3] W. Koh, “Memory device packaging-from leadframe packages towafer level packages,” in Proc. HDP’04, 2004, pp. 21–24.

[4] J. H. Lau, Low Cost Flip Chip Technologies: For DCA, WLCSP, andPBGA Assemblies. New York: McGraw-Hill, 2000, pp. 324–329.

[5] A. Kazama et al., “Development of low-cost and highly reliable waferprocess package,” in Proc. 51st Electron. Compon. Technol. Conf., Or-lando, FL, May 2001, pp. 40–46.

[6] M. S. Bakir et al., “Sea of leads ultra high-density compliant wafer-level packaging technology,” in Proc. 52nd Electron. Compon. Technol.Conf., San Diego, CA, May 2002, pp. 1087–1094.

[7] W. C. Lo et al., “The development of enhanced wafer level packaging,”in Proc 4th Electron. Packag. Technol. Conf, Singapore, Dec. 2002, pp.218–222.

[8] G. Gardner et al., “Integration of a low stress phtopatternable siliconeinto a wafer level package,” in Proc. 54th Electron. Compon. Technol.Conf., Las Vegas, NV, Jun. 2004, pp. 170–174.

[9] J. H. Lau and S. W. Ricky Lee, Chip Scale Package, CSP: Design, Ma-terials, Processes, and Applications. Singapore: McGraw-Hill, 1999,pp. 487–494.

[10] J. H. Lau, Low Cost Flip Chip Technologies: For DCA, WLCSP, andPBGA Assemblies. New York: McGraw-Hill, 2000, pp. 344–348.

[11] L. L. Mercado, C. G. Oldberg, S. M. Kuo, T. Y. Lee, and S. K. Pozder,“Analysis of flip-chip packaging challenges on copper/low-k intercon-nects,” IEEE Trans. Device Mater. Rel., vol. 3, no. 4, pp. 111–118, Dec.2003.

[12] M. R. Miller and P. S. Ho, “Interfacial adhesion study for copper/silkinterconnects in flip-chip packages,” in Proc. 51st IEEE CPMT Elec-tron. Compon. Technol. Conf., Orlando, FL, 2001, pp. 965–970.

[13] R. Chanchani, K. Treece, and P. Dressendorfer, “Mini Ball GridArray (mBGA) assembly on MCM-L boards,” in Proc. 1997 Electron.Compon. Technol. Conf., pp. 656–663.

[14] E. Kondoh, “Material characterization of Cu(Ti)-polyimide thin filmstacks,” Thin Solid Films, vol. 359, pp. 255–260, 2000.

[15] S. M. Chang et al., “Investigation of electroplating Ni UBM for Pb-freesolders,” in Proc 53rd Electron. Compon. Technol. Conf, New Orleans,LA., May 2003, pp. 1209–1214.

[16] E. Perfecto et al., “Evaluation of Cu capping alternatives for poly-imide-Cu MCM-D,” in Proc. 51st IEEE CPMT Electron. Compon.Technol. Conf., Orlando, FL, 2001, pp. 1187–1192.

[17] P. Garrou, “Wafer Level Chip Scale Packaging (WLCSP): Anoverview,” IEEE Trans. Adv. Packag., vol. 23, no. 2, pp. 198–205,May 2000.

Shu-Ming Chang received the Ph.D. degree in ma-terials science and engineering from the Tsing HuaUniversity, Hsin-chu, Taiwan, in 2000.

After receiving the Ph.D. degree, he joined thePackaging Process Technology Division, Electronicsand Optoelectronics Research Laboratories (EOL),Industrial Technology Research Institute (ITRI),Taiwan. His research interests are the interfacialreactions of various thin films integration and failuremodes analysis after reliability tests. He is a DeputyProject Manager and responsible for the projects of

advanced wafer-lever CSP, 3-D packaging, thin film passive devices integration.

Chih-Yuan Cheng received B.S. and M.S. degreesin mechanical engineering from National TaiwanUniversity, Taipei, Taiwan, in 2001 and 2003,respectively.

He currently works as a Package Design Engineerin Thermal and Structure Design Technology De-partment, Electronics and Optoelectronics ResearchLaboratories, Industrial Technology Research Insti-tute (ITRI), Taiwan. His expertise lies in the field ofelectronic packaging and experienced in optimumpackaging design, solder joint reliability evaluation,

accelerated life testing, failure mode analysis, material mechanical propertytesting, and finite element analysis.

Li-Cheng Shen received his B.S., M.S., and Ph.D.degrees from the Department of Electrical andControl Engineering, Nation Chiao-Tung University,Taiwan, in 1992, 1994, and 1998, respectively.

In 1998, he joined the Packaging Process Tech-nology Division, Electronics and OptoelectronicsResearch Laboratories (EOL), Industrial TechnologyResearch Institute (ITRI), Taiwan, involving flip-chipbumping, 3-D packaging, wafer-level chip scalepackaging (WL-CSP), opto-electronic packaging,flexible electronics, electro-optical circuit board,

assembly, and system in package (SiP) using embedded actives technologies[chip-in-substrate package (CiSP)]. He is now the Department Manager of theDepartment of Assembly and Reliability Technology, Package TechnologyDivision, Electronics and Opto-electronics Research Laboratory, ITRI.

Kuo-Ning Chiang (M’04–SM’05) received thePh.D. degree from the Georgia Institute of Tech-nology, Atlanta.

He has published more than 200 journal/con-ference papers in the area of computational solidmechanics, electronic/optical packaging, MEMS,and nano-technology. He holds five U.S. and 24Taiwan MEMS/Electronic Packaging Devicespatents. He is the Associate Editor of the Journal ofMechanics.

Prof. Chiang is the Associate Editor of the IEEETRANSACTIONS OF COMPONENTS AND PACKAGING TECHNOLOGY. He waselected as the ASME Fellow in 2004. He is the Secretary General of ASMETaiwan section and the President of International Microelectronics and Pack-aging Society Taiwan Chapter (IMAPS Taiwan).

Yu-Jiau Hwang received the M.S. degree from the Ta Hwa Institute of Tech-nology, Taiwan, R.O.C.

She works at the Packaging Process Technology Division, Electronics andOptoelectronic Research Laboratories (EOL), Industrial Technology ResearchInstitute (ITRI), Taiwan. She joins some projects involving flip-chip bumping,3-D packaging, wafer-level chip scale packaging (WLCSP). She is now an En-gineer and responsible for the development of photoresist processes.

Yu-Fang Chen received the B.S. degree from the De-partment of Information Management, Ta Hwa Insti-tute of Technology, Taiwan, R.O.C., in 2002.

She works at the Packaging Process TechnologyDivision, Electronics and Optoelectronic ResearchLaboratories (EOL), Industrial Technology ResearchInstitute (ITRI), Taiwan. She is now an AssistantEngineer and supports the development of ad-vanced packaging technologies such as fine pitchflip-chip bumping, wafer-level chip scale packaging(WLCSP), and 3-D packaging.

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CHANG et al.: A NOVEL DESIGN STRUCTURE FOR WLCSP WITH HIGH RELIABILITY, LOW COST, AND EASE OF FABRICATION 383

Cheng-Ta Ko received the M.S. degree in chem-ical engineering from National Taiwan University,Taiwan, R.O.C., in 2002.

Since 2002, he has served in the Electronicsand Optoelectronic Research Laboratories (EOL),Industrial Technology Research Institute (ITRI),as a member of the Packaging Technology Di-vision. The focus of his work is electroplating,electroless plating, vacuum lamination, and processdevelopment of advanced package technology.His research interests also include build-up tech-

nology, wafer-level packaging, embedded active device packaging, and SiPtechnologies.

Kuo-Chyuan Chen received the B.S. degree fromthe Department of Physics, Tamkang University,Taiwan, R.O.C.

He is with the Packaging Process TechnologyDivision, Electronics and Optoelectronic ResearchLaboratories (EOL), Industrial Technology Re-search Institute (ITRI), Taiwan. He is an Engineerand responsible for the development of printingand soldering technologies applied for fine pitchflip-chip bumping, wafer-level chip scale packaging(WL-CSP), flexible electronics, and SiP using

embedded passives technologies.

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