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\/UOOD^ ^OS-
DATE DUE
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RESERVE THESIS 00A.68 SIM
6/1308815d
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A Local Area Network Using
Spread Spectrum Techniques
A Thesis submitted for examination for the
Degree of Master of Engineering (Electrical)
By
A. L. Simcock
BSc(Hons) (Electronics)
University of Kent at Canterbury,
Canterbury.
England.
Department of Electrical and Electronic Engineering,
Footscray Institute of Technology,
Victoria, Australia.
December, 1988
Table of Contents
Table of Contents i
List of Figures vii
List of Tables xi
Acknowledgements xii
Abstract xiii
1 INTRODUCTION 1
1.1 Summary 1
1.2 The Emergence of Local Area Networks 2
1.3 Spread Spectrum in LANs 3
1.4 Literature Survey and Existing Systems 5
1.4.1 System A 5
1.4.2 System B 6
1.4.3 System C 7
1.4.4 System D 7
1.5 Autocorrelation, Crosscorrelation and Orthogonality 8
1.6 Features Required in CDMA Codes 10
1.7 Maximal Length Sequences 11
1.8 Basic Spread Spectrum Theory 13
1.9 Multiple Access in a Spread Spectrum System 19
2 OUTLINE OF THE RESEARCH 23
2.1 Summary 23
2.2 Design Aims 23
2.3 Spread Spectrum vs Current Networks 24
2.4 System Specifications 25
CODES IN A CDMA SYSTEM 29
3.1 Summary 29
3.2 Coding Scheme Selection 29
3.2.1 Scheme A - Segments of Long m-sequences 30
3.2.2 Scheme B - Different m-sequences of the Same Length 30
3.2.3 Scheme C - Gold Codes 31
3.2.4 Scheme D - Phase Shifted Versions of a Single m-sequence 32
3.2.5 Scheme F - Modified Maximal Length Sequences 34
3.3 System Timing Concepts 37
3.4 Sliding Correlator 41
3.5 Collision Mechanisms and Characteristics 42
HARDWARE 43
4.1 Summary 43
4.2 Overview of Development Requirements 43
4.3 Brief Overview of Hardware 44
4.3.1 Microprocessor Control Circuit - Board M 44
4.3.2 Host Interface - Board M 48
4.3.3 Synchronisation Circuit - Board P 48
4.3.4 Clock Recovery - Board M 48
4.3.5 Transmitter Line Driver - Board P 48
4.3.6 Code Select - Board P 49
4.3.7 A/D Converter - Board M 49
4.3.8 Receiver Sliding Correlator and Demodulator - Board M 49
4.3.9 Transmitter Sliding Correlator and Demodulator - Board P 50
4.3.10 Data Generator/Receiver - Board P 50
4.4 Detailed Hardware Description 50
4.4.1 Microprocessor Control Circuit 50
4.4.2 Host Interface 52
4.4.3 Synchronisation Circuits 52
4.4.3.1 Performance Tests on the Sync Circuit 61
4.4.4 Clock Recovery 63
4.4.5 Transmitter Line Driver 67
4.4.6 Code Select 72
4.4.7 Analogue to Digital Converter (ADC) 72
4.4.8 Receiver 74
4.4.8.1 The Sliding Correlator 74
4.4.8.2 The Analogue Multiplier 76
4.4.8.3 Integrate and Dump 79
4.4.9 Transmitter 79
4.4.10 Data Generator/Receiver 81
5 HARDWARE FUNCTIONAL TESTING 83
5.1 Summary 83
5.2 Bit Error Rate (BER) Test 83
5.3 Sliding Correlator Test 89
5.4 Collision Detection Tests 91
5.4.1 Test 1 Additive interference (overlap < 1 bit) 91
5.4.2 Test 2 Additive interference (1 bit < overlap < 2 bits) 93
5.4.3 Test 3 Destructive interference (overlap < 1 bit) 93
5.4.4 Test 4 Destructive interference (1 bit < overlap <2 bits) 96
6 THROUGHPUT MODEL 101
6.1 Summary 101
6.2 Theoretical Throughput 101
6.3 Simulation of Throughput 110
7 SOFTWARE AND SYSTEM TESTING 116
7.1 Summary 116
7.2 Overview of Control Software 116
III
7.3 Control of the Spread Spectrum Interface 117
7.3.1 Inputs 117
7.3.2 Outputs 118
7.4 ADLC Control 120
7.4.1 Receiver Control 121
7.4.2 Transmitter Control 122
7.5 Connection Testing 122
7.6 Throughput Performance Testing 124
7.6.1 Test Configuration and General Procedures 124
7.6.2 Test Results 127
7.6.2.1 Test#1 Peak Channel Occupancy - no collisions 127
7.6.2.2 Test #2 Throughput - with collisions 130
7.6.2.3 Test #3 Short (Pseudo random) Re-scheduling Times 131
7.7 Analysis of System Performance 136
CONCLUSIONS 137
8.1 Discussion of the Project 137
8.2 Comparison With Other Networks 140
8.3 Suggestions for Future Work 142
Bibliography 144
Appendices
A CIRCUIT DIAGRAMS 150
A.I Summary 150
B ERROR GENERATOR 157
B.I Summary 157
IV
B.2 The Requirements 157
B.3 Circuit Description 158
B.4 Circuit Testing and Discussion of Results 166
B.4.1 Test#1 167
B.4.2 Test #2 173
B.4.3 Test #3 175
B.4.4 Tests #4 to #8 175
B.4.5 Tests #9 and #10 182
B.4.6 Tests #11 and #12 182
B.5 Appendix B Conclusions 189
C THE ANALOGUE MULTIPLIER 191
C.I Summary 191
C.2 Theory of Operation 191
C.3 Level Shifting 195
C.4 Analogue Multiplier Design Procedure 196
C.5 Level Shifter Design 199
D PROGRAM - CSMA/CD SIMULATOR 202
D.I Summary 202
D.2 Brief Outline of the Program 202
PROGRAM LISTING 204
E MICROPROCESSOR PROGRAM 209
E.I Summary 209
PROGRAM LISTING 210
F PROGRAM - TRAFFIC GENERATOR 231
F.I Summary 231
F.2 Poisson & Normal Distribution Characteristics 231
F.2.1 Normal (Gaussian) 231
F.2.2 Poisson 232
F.3 The "Random" Programs 233
F.3.1 Normal Distribution Numbers 233
F.3.2 Poisson Number Program 234
F.4 The Traffic Program 234
PROGRAM LISTING 238
PUBLICATIONS 242
G.I Summary 242
VI
List of Figures
Figure Title Page
1 Maximal Length Sequence Generator 12
2 Single Channel Direct Sequence System 14
3 Relationship Between Chip and Data Signals 15
4 Spectral Occupancy of Signals 18
5 Multiple Access Concept 20
6 Typical Transmitter Waveforms 21
7 Network Bus Structure 26
8 Autocorrelation Function of a 1023 Bit MLS 33
9 "Modified" MLS Address Code Generation 35
10 Autocorrelation Function of "Modified" 1024 Bit MLS 36
11 System Delay and Timing Aspects 38
12a Overall System Block Diagram 45
12b Photograph of Microprocessor Board 46
12c Photograph of Peripheral Board 47
13 Microprocessor Control Circuit - Block Diagram 51
14 Memory Map for Microprocessor Control Circuit 53
15 V.I.A. Control Signal Pin Connections 54
16 Sync Circuit and Code Select - Block Diagram 55
17 Timing Diagram For Sync Circuit 57
18 Schematic Diagram for Synchronisation Circuit 58
19 Sync Dropout vs Error Rate 62
20 Cycles to Regain Sync vs Error Rate 64
21 Clock Recovery/Generator - Block Diagram 65
22 Timing for Clock Recovery 66
23 Transmitter Line Driver - Block Diagram 69
24 Line Driver - Circuit Schematic 71
VII
Figure Title Page
25 A to D Converter Circuit - Block Diagram 73
26 Receiver Circuit - Block Diagram 75
27 Sliding Correlator - Block Diagram 77
28 Analogue Multiplier - Block Diagram 78
29 Integrate and Dump Circuit and Timing Diagram 80
30 Transmitter Circuit - Block Diagram 82
31 Bit Error Rate Test Hardware Configuration 84
32 White Noise Generation 85
33a Photograph of Band Limited Spectrum 86
33b Photograph of Single Transmitter Spectrum 86
33c Photograph of Noise -i- Multi-Transmitters Spectrum 88
33d Photograph of Received Signal / Recovered Data 88
34 Bit Error Rate vs S/N Ratio 90
35 Correlation With Delayed Signals 92
36 Correlation of Additive Signals - Less Than 1 Bit Delay 94
37 Correlation of Additive Signals - Greater Than 1 Bit Delay 95
38 Correlation of Destructive Signals - Less Than 1 Bit Delay 97
39 Positive and Negative Correlation - Less Than 1 Bit Delay 98
40 Correlation of Destructive Signals - Greater Than 1 Bit Delay 99
41 Positive and Negative Correlation - Greater Than 1 Bit Delay 100
42 Channel Transmission Characteristics 104
43 Throughput vs Offered Traffic 107
44 Comparison of Throughput Characteristics 109
45 Theoretical and Simulated Throughput 113
46 Number of Collisions vs Offered Traffic 115
47 Hardware Configuration for Performance Tests 125
48 System Throughput - No Interference 129
49 System Throughput - With Interference Generator 132
VIII
Figure Title Page
50 System Throughput - Alternative Protocol (small random rescheduling) 134
A1 Microprocessor Board (M) - sheet 1 of 2 151
A2 Microprocessor Board (M) - sheet 2 of 2 152
A3 Peripheral Board (P) - sheet 1 of 3 153
A4 Peripheral Board (P) - sheet 2 of 3 154
A5 Peripheral Board (P) - sheet 3 of 3 155
B1 Block Diagram for Error Generator 159
B2 Circuit Diagram for Error Generator - Board 1 162
B3 Circuit Diagram for Error Generator - Board 2 163
B4 Test Circuits A and C 168
B5 Test Circuits D,E and F 169
B6 Test Circuits G,H,I and J 170
B7 Distribution of All Errors (A). F = 1 MHz. R = 1 in 10 171
B8 Distribution of Any Error (B). F = lMHz. R = 1 in 10 174
B9 Distribution of 1 Bit Errors (C). F = iMHz. R = 1 in 10 176
B10 Distribution of 2 Bit Errors (D). F = 1MHz. R = 1 in 10 177
B11 Distribution of 3 Bit Errors (E). F = 1 MHz. R = 1 in 10 178
B12 Distribution of 4 Bit Errors (F). F = 1 MHz. R = 1 in 10 179
B13 Distribution of 5 Bit Errors (G). F = 1MHz. R = 1 in 10 180
B14 Distribution of 6 Bit Errors (H). F = 1MHz. R = 1 in 10 181
B15 Distribution of Separate Error Occurrences 183
B16 Multi-Bit Error Characteristics 184
B17 Distribution of All Errors (A). F = lOKHz. R = 1 in 10 185
B18 Distribution of All Errors (A). F = lOOKHz. R = 1 in 10 186
B19 Distribution of All Errors (A). F = IMHz. R = 1 in 100 187
B20 Distribution of All Errors (A). F = IMHz. R = 1 in 1000 188
IX
Figure Title Page
Cl Circuit Schematic of the Analogue Multiplier 192
C2 Internal Schematic of the RSI 495 193
F1 Probability Distribution Normal (Gaussian) Characteristics 235
F2 Probability Distribution Poisson Characteristics 236
List of Tables
Table Title Page
1 System Timing and Delays 40
2 Peak Throughput as a Function of Vulnerable Period 108
3 Peak Throughput as a Function of System Model 110
4 Simulated and Theoretical Throughput Figures 112
5 Measured Peak Throughput - no interference 128
6 Measured Throughput - with interference 132
7 Alternative Protocol Throughput - short re-scheduling delay 135
B1 Error Generator PROM Details 164
B2 Error Generator Board 1 - Chip List 165
B3 Error Generator Board 2 - Chip List 166
B4 Error Generator Test Circuit Definitions 172
XI
Acknowledgements
This research project was supported by a grant from the Australian Telecommunications and Electronics
Research Board (ATERB).
The project was supervised by Dr. C. naRanong and Mr. P. Leung, for whose advice and support I am
grateful.
My warm thanks are extended to many people, in particular:-
My wife, Moira, for typing this thesis
My friends and colleagues at F.I.T., for their help and encouragement
Mr. F. Hayward, for laying-out the printed circuit boards
+ Mr. R. Ives, Mr. M. Dow, Mr. M. Faulkner and Mr. J. MacLeod, for their many informative
discussions
Dr. R. Malyniak and Dr. A. Kalam for their support, proof reading and criticism of this thesis.
XII
Abstract
Local Area Networks (LANs) have become fairly common in recent years. This thesis considers the
application of Spread Spectrum (SB) communication techniques to the implementation of a LAN.
Basic SS techniques are described and a model of a LAN using these techniques is developed. The major
difference between this LAN and most other l-AN implementations is that in this system many nodes (or
stations) may transmit concurrently. The primary feature of this model is the ability to distinguish between
transmissions intended for different users by the address code used to modulate the data. This is called
Code Division Multiple Access (CDMA). The properties of the codes, allocated to each node in the
network, are of paramount importance in a CDMA system. Several code allocation schemes are
considered in order to find one with the most suitable properties. System timing and synchronisation
concepts are also considered, since they, together with the code allocation scheme selected, determine
the characteristics of the system.
The hardware designed to implement and control network functions is described. Tests carried out to
verify the operation of the Independent hardware modules are also detailed. The ability of the system to
synchronise and transmit data in the presence of noise is tested, prior to complete system testing and
throughput measurement.
CDMA is used to separate information on different channels but there is still the need to consider possible
contention within a channel. A Carrier Sense Multiple Access with Collision Detection (CSMA/CD)
mechanism is used for this purpose. A theoretical model of a suitable mechanism is developed and
simulated. The theoretical and simulated results are compared and used to predict the results expected
from the hardware. Finally the system's traffic handling characteristics are tested and the results
compared with those predicted. System flexibility is investigated by programming an alternative protocol
into each node and again examining the throughput characteristics.
XIII
This thesis concludes with a discussion of the major features highlighted by this development project.
Theoretical, simulated and actual measured results are also compared. Cost and certain system
performance parameters are compared with those of a more conventional CSMA/CD network, such as
Ethernet. Possible system enhancements and avenues for future work are then discussed.
XIV
1 INTRODUCTION
1.1 Summary
This thesis contains the description of the research carried out towards the production of a Local Area
Network (LAN) based on Spread Spectrum (SS) techniques [1]. The concept of using Spread Spectrum
techniques is attractive since simultaneous transmissions by several users is possible, using a Code
Division Multiple Access (CDMA) mechanism.
The evolution of the requirement, a brief introduction to the essential theory and a precis of the
contemporary Spread Spectrum LAN research projects are all outlined in chapter 1. An outline of the
project design criteria and system specifications are included in chapter 2. The choice of code generation
and distribution is crucial to the performance of a CDMA system. Chapter 3 briefly outlines the different
coding schemes considered before a final choice was made. After considering several schemes, a
synchronised system was adopted as an appropriate code allocation scheme. Timing and code related
matters are inseperable in a synchronised system; because of this, aspects of code recognition and
collision detection and certain system timing concepts are also described in chapter 3.
Chapter 4 describes the hardware required to generate the codes and meet the timing requirements etc
outlined in previous chapter. Photographs of the two printed circuit boards are also included to aid
description. Where individual circuit modules have been tested in isolation the tests descriptions are
included with the details of the hardware of that particular module. Multi-module and integration tests are,
however, detailed separately in chapter 5. Since the hardware is described in terms of the individual circuit
modules the complete circuit diagrams, for each of the two boards which constitute a system node, are
included in appendices rather than the main section of the text.
Chapter 1 Page 1
The hardware described in chapters 4 and 5 represents the physical components of the system; it is the
software which controls the hardware, however, in which the higher level system protocols are embedded.
Theoretical and simulation models of channel throughput were developed in order to predict system
performance before the control software was written. These models are described in chapter 6. The control
software and the tests carried out to verify system performance parameters are described in chapter 7.
A discussion of system performance parameters and ideas for further research are included with an overall
evaluation of the research project in the conclusions section, chapter 8.
The aim of this thesis is to describe the main points of the research carried out towards the development
of a Spread Spectrum LAN. For this reason all of the control, test and peripheral programs which were
written are included as appendices rather than in the main body of the text. Details of special purpose test
equipment, photographs of the circuit boards and complete circuit diagrams are also included as
appendices.
1.2 The Emergence of Local Area Networks
The advent of the microprocessor has had a significant impact on society. The substantial reduction in
the cost of computing power has resulted in the widescale use of computers for all kinds of data
manipulation and storage. Magnetic storage devices such as floppy disks have, to some extent, replaced
paper as a means of intra and inter company data transfer. Local Area Networks (LANs) were primarily
developed to allow the sharing of expensive resources, but their development has also allowed the sharing
of data between interested parties without the need to manually transport disks, paper tapes etc. The
expanding need for data communication channels in L^Ns has increased the pressure on the available
transmission bandwidth. This has led to developments in two broad areas : the extension of the usable
spectrum through the use of even higher frequency carriers and the development of complex networking
and multiple access algorithms.
Chapter 1 Page 2
The ever increasing use of LANs has brought with it two problems with respect to the protection of data.
First it is necessary to protect the data against interference, be it deliberate or othenA/ise, in orderto ensure
delivery of correct information to the correct user. Second, as more proprietory information is appearing
on data bases, it is becoming increasingly necessary to protect the information against prying or
interception. Society has, indeed, become information conscious to the extent that the acquisition and
protection of data has become an industry in its own right.
SS techniques, which were originally developed in the mid 1950s [2] for military use as a means of
providing a jam resistant communication link, have only recently been considered seriously in a
commercial or civilian environment [3]. Areas of interest include mobile radio, radio telephony, amateur
radio and satellite communications [4].
13 Spread Spectrum in LANs
The adaptation of SS techniques to the development of a LAN appears to offer some advantages in the
areas of concern mentioned above. Its well known interference rejection capabilities [5] could be used to
advantage in allowing the system to work in an environment where electrical interference might be a
problem and where the use of alternatives such as fibre optic cables might not be appropriate[6,7]. SS
systems, by their very nature, also offer possible benefits [2,8,9] in the area of data privacy.
One definition of SS [5] which adequately reflects the major characteristics of this technique is as follows:-
"Spread Spectrum is a means of transmission in which the signal oc
cupies a bandwidth in excess of the minimum necessary to send the in
formation. The band spreading is accomplished by means of a code
which is independent of the data. A synchronised version of the same
Chapter 1 Page 3
code is then used at the receiver in order to despread the signal and
facilitate data recovery."
What this definition means is that the data is modulated with the spreading code and that, through a
correlation process, the receiver restores the signal to its normal bandwidth and, in doing so, it enhances
the desired signal while substantially reducing the effects of interference and noise. Overall, the
communication channel capacity is not "wasted" because with a suitable selection of spreading codes
(having low crosscorrelation properties) several nodes may simultaneously transmit messages over the
same channel, with low, predictable, interference between nodes.
A LAN, where multiple nodes use a single communication channel - one pair at a time, is a prime candidate
for the application of SS techniques. By using CDMA techniques, alternatively called Spread Spectrum
Multiple Access (SSMA), it is possible to have several multi-pair communications in progress
simultaneously [10,11]. Being inherently multi-user, CDMA techniques have the potential to increase the
network's throughput, under conditions of heavy usage, by allowing many pairs of nodes to communicate
simultaneously, thus reducing contentions.
The three primary methods of spreading the data transmissions are [5,12]:-
Direct Sequence - in which the data is directly modulated with a fast pseudo random code
sequence.
Frequency Hopping - in which the carrier which is modulating the data is caused to hop from
one frequency to another in a pseudo random manner.
Chapter 1 Page 4
Time Hopping - in which the time channel allocated to a particular transmission is changed
in a pseudo random manner.
1.4 Literature Survey and Existing Systems
A survey of literature revealed many papers on Spread Spectrum techniques and many more on Local
Area Networks, but only four papers which described research which combined both [13-16]. Several
more papers relating to one of the four existing research projects were published subsequently. These
papers described the project at various stages of its development, the most recent [17] was used as a
reference. The projects described were at various stages of completion, varying from systems which had
been extensively tested to those which had been simulated, but for which no hardware had been built.
The characteristics of each system in brief are as follows:-
1.4.1 System A [13 and 17]
Smythe and Spracklen [13] describe their SS LAN system, and the software simulations used to test it, in
general terms. Spracklen et. al. [17], however, give a much more comprehensive descnption of the system.
The system, called SPREADNET, is a bus topology system which is connected via fibre optics, and is
aimed specifically towards military applications, in this network, which can be up to 2 km. in length, as
many as 150 users can be accommodated. Direct sequence modulation is used and encoded data is
transmitted in baseband at 100 M bits/sec. Each node controller uses a 12 MHz MC68000 microprocessor.
A source code address allocation scheme is used, where the receiver must be informed which
demodulation code to use. Upon receipt of a packet for transmission the node controller requests a virtual
communications channel ie. requests address codes to be used for the transmission. The management
Chapter 1 Page 5
system then informs the transmitter and receiver of the choice of codes. Contentions are avoided by this
elaborate network management interchange before logical code to physical device mapping is achieved.
All codes allocated in this manner are encrypted before delivery and are protected by a two key
cryptographic algorithm in conjunction with the Data Encryption Standard (DES). Dynamically allocated
codes are also used by the individual node controllers to transmit network management information
around the system.
Synchronisation is achieved by means of polarity coincidence correlators, and digital correlation is
performed continuously to overcome tracking problems. Modulation and demodulation are handled by
dedicated hardware (custom programmed logic arrays), and a sliding correlator is used in conjunction
with polarity coincidence correlation for data recovery.
1.4.2 System B [14]
System B was developed, to investigate network efficiency and performance criteria and compare them
with the classic Frequency Division Multiple Access (FDMA) ALOHA type of network. The system is cable
connected, and used "uplink' and "downlink' separation of transmission and reception paths interfaced
via a "Repeater and Sync generator". Bus topology and direct sequence (DS) modulation are used. Bit
synchronisation is achieved via a sophisticated mechanism whereby the Repeater and Sync generator
periodically interrupts traffic to inject sync information for each user. This must be done with sufficient
frequency so that the local clocks do not drift by more than one chip bit period between updates.
The system is designed to accommodate voice and data. Voice or data bits are transmitted in packets.
Different processing gains are used in the system, and data is modulated using a variable number, between
64 and 512, of chip bits per data bit, whereas a processing gain of 167 is used for voice traffic. This gives
an effective modulated data rate of 10.9 MHz for voice traffic of 64 kHz. Bits of each packet, either voice
Chapter 1 Page 6
or data, are modulo 2 added to the direct address code sequence. The resulting binary array then balance
modulates a high frequency carrier which is transmitted in the uplink direction. The Multiple Access
protocol is via point to point CDMA, with the destination address being used, but no code allocation details
are included.
1.43 System C [15]
This system utilises what the designers call "a non-processed fibre optics bus", where non-processed is
defined as supressing the entire command and address part of the bus. A distributed star topology is used
to implement the bus, which is capable of supporting up to 25 users. Distributed 5 port optical couplers
are used to allow a bus do be developed which does not use handshaking or a master-slave configuration.
Fibre optic interconnections are used and modulation takes the form of Frequency Hopping superimposed
upon a Direct Sequence modulated data signal. 15 frequencies with a separation of 15 MHz centred on
155 MHz are used for the frequency hopping component, and a processing gain of 127 is used for the
direct sequence part. Surface wave acoustic convolvers centred on 155 MHz are used for synchronisation.
1.4.4 System D [16]
For this system a fibre optic connected ring network and a separate synchronisation bus are used. Both
synchronous and asynchronous data is catered for in the system.Node addresses are cyclically bit shifted
versions of the one m-sequence. The sync signal sent from the Sync Node is also a bit shifted m-sequence.
The system employs dual phase locked loops for synshronisation demodulation and data separation.
Each receiver removes its own modulated data signal from the received signal, so node #2 would see
the same signal as node #1 minus any transmission addressed to node #1 . This prevents the transmission
Chapter 1 Page 7
for node #1 from recirculating in the system. Each node conducts an "in-channel" busy test before
transmitting. When a node is transmitting it switches its receiver and transmitter m-sequence generators
to the destination address. This ensures that no collisions can occur in that channel as the node would
remove from any signal any component modulated with the same address code. It does, however, mean
that a node may not transmit and receive at the same time.
The research described in these papers appeared to be concentrating on the high speed, extremely
sophisticated end of possible applications. Considerable use was made of custom designed VLSI devices,
multiple high speed correlators etc. Network management, sophisticated synchronisation, layered SS
techniques, encryption and dynamic address code allocation were some of the other advanced features
of the systems referenced. Three of the systems used, or proposed using, fibre optic interconnections
and only one used cables. This concentration on the "high end" of possible applications left considerable
scope for the development of a SS LAN which could find applications where the advanced features
described above might not be appropriate (see System Specifications, section 2.4) and systems such as
those described above may be too complicated.
1.5 Autocorrelation, Crosscorrelation and Orthogonality
The correlation between two signals gives an indication of the similarity between the signals, as a function
of the time displacement (T). The crosscorrelation between two signals v(t) and w(t) is defined by the
scalar product shown below [18]
RVW(T) = <v(t) ,w(t-T)> (1)
Chapter 1 Page 8
Thus, if the correlation value is high the signals have a marked degree of similarity; and if the correla
tion value is very low the signals are essentially dissimilar. The autocorrelation function is defined as
the correlation of a signal v(t) with a time displaced version of itself v(t-T) and is given by:-
R W ( T ) = RV(T) = <v(t),v(t-T)> (2)
If |RV(T) I is large then the inference is that v(t) is very similar (proportional) to ±v(t) for that particular
value of T . Conversely if RV(T) = 0 then, at that particular value of T, v(t) and v(t-T) are said to be
orthogonal.
For a signal z(t) which is a summation of two signals v(t) and w(t), such that 2(t) = v(t) + w(t), the
correlation with one signal v(t) would be given by
RZV(T) = RV(T) + RWV(T) (3)
and if the component signals are orthogonal at this particular value of T ie. if
RVW(T) = RWV(T) = 0 (4)
then
Chapter 1 Page 9
RZV(T) = RV(T) (5)
This extraction of a single correlation function from a signal which is the summation of two or more signals
is the basis upon which CDMA relies.
1.6 Features Required in CDMA Codes
In a CDMA system where one node is distinguished from another by means of the code used to modulate
its data, the selection and allocation of codes is of prime importance. The address codes used must have
certain properties [5,8] i.e. they:-
i) must be easy to generate.
ii) have randomness properties.
ill) have selectable length (long) periods.
iv) must be deterministic i.e. can be synchronised.
v) must be orthogonal
and if the code is intended to impart any substantial degree of encryption they must also be:-
Chapter 1 Page 10
vi) difficult to reconstruct from a short segment.
It can be seen that properties i), iv) and vi) are somewhat contradictory since, if it is simple, deterministic
and easy to synchronise for the intended receiver, it will probably prove to be relatively easy for an
interceptor to "break" the code. Since, however, cryptographic integrity is not a primary requisite of this
work, property vl) may be omitted thus opening the way to use codes which have only the first five
properties.
1.7 IMaximal Length Sequences
The most commonly used type of code which meets these five basic properties is the Maximal Length
Sequence (MLS or m-sequence). The normal method of generating these codes is using Linear
Feedback Shift Registers (LFSR) as illustrated in Figure la. For a code to be a maximal length code it
must have a length, N, which is equal to 2"-1, where n is the number of shift register stages in the generator.
Tables are available [19] which show the feedback taps necessary to generate m-sequences for up to 34
shift register stages. In an m-sequence all binary n-tuples, except the all zero state, are present. By
setting the initial contents of the shift registers to 0001 the pattern shown as code Cx in Figure 1 b would
result. This pattern repeats after 2^-1 = 15 bits. Figure 1 b also shows code Cy which is the result of
cyclically shifting code Cx by 1 bit such that Cxk = Cyk-i where k represents the bit position.
The signals v(t) and w(t) in section 1.5 were continuous signals. The autocorrelation and crosscorrelation
functions do, however, have a direct translation into discrete pseudo random signals such as
m-sequences. By defining the ± 1 sequence Cx'k = 1-2Cxk (where Cxk = 0,1 - see Figure 1 b) then
the autocorrelation function is defined as
RCX'(T) = 1 Cx'kCx'k-T (6) 1
Chapter 1 Page 11
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This is the Periodic Autocorrelation of the m-sequence taken over the length, N, of the sequence, and
T is in whole bit increments. [5]
The Periodic Crosscorrelation of two sequences Cx' and Cy' would similarly be given by
RCx'Cy' = S Cx'kCy'k (7) 1
which is a bit by bit summation of the number of bits in code Cx' which are the same as those in code Cy'
over the length, N, of the codes. The periodic autocorrelation and crosscorrelation functions are of
extreme importance when considering SS systems.
1.8 Basic Spread Spectrum Theory
This research project uses the Direct Sequence method of data spreading, and the description will
concentrate on this aspect. The pseudo random binary sequence used to spread the data is also
commonly known as the "Chip" sequence. Figure 2 illustrates a conceptual model of a single channel
direct sequence system. In this system the chip sequence is used directly to modulate the data in
baseband.
Each data bit d(t), as illustrated in Figure 3, of energy Eb and duration T, may be represented by [5]
d(t) = ± V(Eb/T) (8)
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This one dimensional data bit is multiplied by a two level ± 1 chip sequence, C'(t), running at a frequency
of fc chips/sec, ie. a total of fcT chips per data bit. The resultant sequence d (t)C' (t) is then a fcT dimensional
signal. The relationship between the data and chip signals is shown in Figure 3
The ratio of the dimensionality of the chip sequence to the data is called the "Processing Gain", and is
defined as :-
Processing Gain = Gp = Bss (9)
BD
Where Bss = Bandwidth of the SS Signal and BD = Bandwidth of the Data Signal
The numerical value of the processing gain is an indication of a power improvement factor, which a
receiver, possessing a copy of the transmitter's chip sequence, can achieve by a process of correlation.
The processing gain gives an indication of the interference rejection capability [5].
If the "chipped data" signal, d(t)C'(t), is transmitted in the presence of an interfering signal J(t), the
received signal would be
r(t) = d(t)C'(t) + J{t) 0 < t < T (10)
At the receiver the correlation process is carried out by multiplying the received signal, r(t), with the same
chip sequence used to encode the transmitted data, and then integrating the result over a period T to
produce a decision variable U, where
Chapter 1 Page 16
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U = V(Eb/T) r(t)C'(t) dt (11) 0
From equation (11) it can be determined whether + V(Eb/T) or - \/(Eb/T) was sent, depending on
whether U is positive or negative. The integrand in equation (11) may then be expanded as follows
„2 r(t)C(t) = d(t)C"^(t) + J(t)C'(t) (12)
And, since C'(t) = ±1 ( .-. C'^(t) = 1), the above equation may be rewritten as
r(t)C'(t) = d(t) + J(t)C'(t) (13)
With suitable filtering the high frequency component J(t)C'(t) may be removed and the original data signal,
d(t), recovered.
This fact can be illustrated by inspection of the the spectral occupancy of the signals shown in Figure 4,
where the power spectral densities of the data signal, d(t), and the spread data signal, d(t)C'(t), are
sketched. The data signal may be extracted by using a filter with a bandwidth of fd Hz. The fraction of
power due to the interfering signal which can pass through this filter is then 1/fcT. Thus the data can have
an effective power advantage over the interfering signal of n = fcT, i.e. the processing gain, defined in
equation (9) above.
Chapter 1 Page 17
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In equation (13) the jamming signal J(t) may be an external interference signal, eg. nearby high voltage
equipment, and/or it may be interference from other transmitting nodes. The rejection of the other nodes
transmissions as noise depends upon the orthogonality of the codes [20] used for spreading each node's
data.
1.9 Multiple Access in a Spread Spectrum System
The concept of simultaneous multi-access is illustrated in Figure 5. This diagram shows a number of
transmitting nodes (n) and a single receiver (node #x) (where 1 < x < n). At each transmitter the data
bit, dn(t), is modulated with an address code, Cn'(t), to form the output, Sn(t), such that
Sn(t) = Cn'(t)dn(t) (14)
The signal from each transmitter is then "added into" the transmission medium as illustrated in Figure 6,
to produce a total transmission signal T(t) of the form
T(t) = si(t) + S2(t) + S3(t) + Sn(t) (15)
n 2 Sn(t) (16) 1
The transmission medium may be subjected to external noise or interference, J(t), which would then result
in a received signal of the form
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Chapter 1 Page 21
r(t) = T(t)-h J(t) (17)
At the receiver the received signal, r(t), is demodulated by multiplying with the address code for that node,
Cx'(*). and, from equation (11)
r(t)Cx'(t) = dx(t) + I " Sn(t)Cx'(t) + i Sn(t)Cx'(t) + J(t)Cx'(t) (18) 1 x + 1
By suitable filtering the data signal, dx(t), may be extracted from all of the other components indicated in
equation (18). In this manner any receiver may extract its own data from all of the other signals which
have been simultaneously combined onto the network, ie. the receiver may access its own data by using
CDMA.
Chapter 1 Page 22
2 OUTLINE OF THE RESEARCH
2.1 Summary
Chapter 2 outlines the aims of this research project and the the breakdown of the overall task into smaller
packages with identifiable milestones. A brief description of the potential advantages of SS technology in
a network situation is then given. Finally, the system's network specifications are detailed.
2.2 Design Aims
The primary aim of this research is to produce a LAN using SS techniques, and to evaluate some of the
performance parameters of the system produced. The project should use either twisted pair or parallel
pair cables as the interconnection medium in order to maintain the simplicity of the design. The overall
network should use standard, off the shelf, components wherever possible.
In order to satisfy these requirements the research was divided into separate sections :-
Selection of appropriate coding sequences.
Development of timing, synchronisation and decoding philosophies for these sequences.
• Transmission of a synchronising sequence, and subsequent clock recovery.
Chapter 2 Page 23
Development of a d riving technique suitable to ensure that the connection or disconnection of a station
(or a number of stations) would not substantially affect the electrical characteristics of the network.
Design of data recovery hardware.
• Design of microprocessor control circuit for the system.
Investigation Into the hardware and software protocol structure to fulfil the requirements of the lower
levels of the International Standards Organisation (ISO) seven layer model.
Demonstration of concurrent transmissions.
23 Spread Spectrum vs Current Networks
Current bus and ring LAN topologies typified by Ethernet and Cambridge ring [21,22] respectively employ
some form of (asynchronous) time division multiplexing. This may be in the (more or less) fixed
compartment format of Cambridge Ring or the "packet message" type format of Ethernet. Whichever
system is used, any node wishing to access the network must wait until a time when no other users are
transmitting. The node will then transmit at a high frequency in the order of 10 MBits/sec into the system.
The overall effect is that each node emits bursts of data at high bit rates for relatively short periods, and
then remains dormant for a much longer period.
Special chip sets (e.g. Intel 82586), capable of this high speed "bursty" type of transmission have been
developed thus easing the designer's problem but still leaving a requirement for high speed storage to
allow the node processor time to assimilate the data. In systems such as these, even nodes requiring
Chapter 2 Page 24
very modest data rates of a few bits per second would need to be able to accommodate these high speed
transmissions.
In a SS system, however, the node would only need to be able to cater for a data rate much more modest
than the 10 M bits/sec of Ethernet. This reduces the need for specialised high speed or customised devices
at each node and increases the use of standard, commercially available, components [23]. This may well
allowa L^N to be used In areas, hitherto considered unsuitable, because the cost component outweighed
the possible advantages.
2.4 System Specifications
The primary specifications of the system are as follows :-
. The system will use a bus topology as shown in Figure 7, with separate Data/Network and
Synchronisation lines.
. The node interconnections will be via twisted pair or parallel pair wires for simplicity and ease of
connection/disconnection. The cable is terminated with an appropriate resistance at both ends in
order to minimise mismatches and reflections. Using this mechanism means that connections may
be made at any point in the system with "Tap-in" connectors and not only at discrete intervals as
would be the case with a fibre optic system (requiring optical couplers) or a co- axial system (requiring
"T pieces). It means, furthermore, that in orderto accommodate a new node there would be no need
to break the line to insert an optical coupler or "T' piece If a conveniently situated connection point
was not already available.
Chapter 2 Page 25
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High impedance current drivers will be used to interface onto the network line, thus ensuring minimum
perturbation to overall network traffic when nodes connect or disconnect.
. These drivers are not necessary for the synchronisation line. One node (eg. node #1) acts as the
sync transmitter and all other nodes use the transmission on the sync line to recover clock and code
synchronisation information. The overall synchronisation means that all data may be transmitted in a
synchronous, rather than an asynchronous, format. This has significant implications in the choice of
code allocation scheme and in the implementation of the system timing and data recovery sections
(as shown in chapters 3 and 4).
. The system will use the point to point communication protocol. Each node will be allocated its own
chip sequence, or spreading code, which will act as an address for that node; thus if node #1 wishes
to transmit to node #2 then node #1 will modulate its data with the chip sequence for node #2.
Hence the transmitter of each node must be able to modulate its data with any recipient's address
code. In this manner simultaneously multi-pair transmissions are allowed with transmission channels
being identified by the codes being used to modulate the data, ie. CDMA. It is obvious, however, that
no two nodes may simultaneously transmit to the same recipient, otherwise a collision would occur.
The multiple access features reduce the probability of collisions occurring but do not eliminate them
totally.
A Carrier Sense Multiple Access with Collision Detection, (CSMA/CD), type of protocol will be used
to detect and resolve intra-channel collisions. Each transmitter will have a built-in demodulator to
pre-check for traffic in the desired channel and to continuously check for collisions whilst transmitting.
Each node, therefore, requires two demodulators - one for monitoring the channel for its own received
messages and the other for collision avoidance and detection. The first demodulator works exclusively
with its own address code whereas the code used in the second is selectable. Further to the code
allocation scheme, it was decided that the code length (the number of chip bits per data bit, ie. the
processing gain, Gp) should be in the order of 1000. This number was chosen because there is a
Chapter 2 Page 27
rule of thumb which indicates that the number of potential users is approximately 10% of the
processing gain [5]. This would allow a system possibly capable of supporting up to 100 users.
Chapter 2 Page 28
3 CODES AND SYSTEM TIMING
3.1 Summary
Chapter 3 outlines the properties required of the codes in a CDMA system. A brief description of each
coding scheme considered is given. This is followed by a description of the important timing characteristics
of the system.
3.2 Coding Scheme Selection
Several possible generation and allocation schemes were considered before one was finally chosen. The
properties of major concern were :-
Simplicity of generation and synchronisation.
Crosscorrelation between members of the code set.
The first three schemes considered (schemes A, B and C) were designed to allow the network to be
operated asynchronously, ie. the data bits from each user do not have to coincide. The other two schemes
considered (schemes D and E) were designed for synchronous system operation, where data bits from
every user have a fixed start time.
Chapter 3 Page 29
3.2.1 Scheme A - Segments of Long m-sequences
In this scheme the concept was to allocate to each node a segment of M bits of a much longer code of
length N. Every node would generate the same long MLS, each node would then be identified by the
segment of this long code allocated to it. The crosscorrelation between these segments transmitted
simultaneously would determine the interference between one transmission and another.
Lindholm [24] found, in his consideration of the moments of the distribution of weights of M-tuples of
MLSs, that this type of system gave more predictable crosscorrelation values as M tends towards N. This
figures would, in the limit, result In the full code length N being used and in fact producing the
autocorrelation function of the MLS. For this reason this scheme was not considered further.
3.2.2 Scheme B - Different m-sequences of the Same Length
This scheme considered the use of different m-sequences. Each node would be allocated a series of tap
settings which would be used to produce a different m-sequence. Each m-sequence would be of identical
length since shift registers of the same length would be used in each node. Producing m-sequences in
this manner is a relatively straight-fonA^ard procedure and tables of polynomials for the production of such
sequences are readily available [19]. Some sequences do, however, require many taps to produce, and
since each transmitter must be able to transmit to any receiver, this implies that each node must have
sophisticated hardware in orderto produce any code allocated.
The crosscorrelation between sequences produced by Linear Feedback Shift Registers (LFSRs) of the
same length but with different tappings was considered. A problem arises with this scheme in that there
are only 60 m-sequences of length 1023 which can be produced. Within this 60 limit the maximum number
in any Maximally Connected Set * is only 3 indicating that the crosscorrelation between sequences could
be as high as 38% [20], unless extreme care is exercised in the selection of sequences allocated. The
Chapter 3 Page 30
number of codes available for allocation under this scheme would, therefore, restrict the number of users
to 60. This, coupled with the level of correlation interference indicated above, was considered significant
enough to prevent further investigation of this scheme.
*Note A maximally connected set is one in which all members of the set act as part of a preferred
pair with any other member of the set [20]. A preferred pair is a pair of m-sequences of period N = 2"-1
which has a "3 valued" crosscorrelation function where the peak magnitude of the crosscorrelation is
given by [27]:-
,2(n + i ) /2^. , for n odd
|2(n+^;/^ +1 for n even n = mod 4 (19)
For N = 1023 the maximum crosscorrelation for a preferred pair is 65, and the three correlation values
are -65, -1 and +63. (Note the peak value 65 is given by 2^^°+^^^^+1).
3.2.3 Scheme C - Gold Codes
The third scheme considered the use of GOLD codes allocated to each node. Gold codes are a class of
periodic sequences which provide larger sets of sequences with predictable crosscorrelation properties
[20,25]. A set of Gold sequences of period N = 2"-1 consists of N -»-2 sequences. The adoption of this
scheme would, however, require each sequence generator to have a 20 bit shift register, to generate the
1023 bit codes. Two such registers would be required to cater for the fixed receiver and the switchable
transmitter. The transmitter stage would also require a method of pre-setting the LSFR with the required
seed in order to generate the particular Gold code required. The correlation between members of the
Gold Code set is the same as that between the preferred pairs of m-sequences used to generate them
[20] (see also equation (19) above). Although there would be sufficient members of the Gold Code set,
the correlation values offer no improvement over the scheme considered above.
Chapter 3 Page 31
3.2.4 Scheme D - Phase Shifted Versions of a Single m-sequence
Taking advantage of the fact that the whole system could be synchronised means that a code allocation
scheme, using MLSs, could be devised such that the codes allocated would not be produced by different
shift registers, rather that a single m-sequence would be used throughout and each node would be
allocated a phase or bit shifted version of the same sequence. The crosscorrelation between codes of
each node would then become the autocorrelation of the single code. Codes allocated on this phase
shifted basis would have the following format:-
Cn-1'k = Cn'k-s (20)
n indicates the nth code and s is the separation factor, ie. the phase shift between successive codes.
Using separate synchronisation and data lines means that the synchronisation overhead could be kept
to a minimum by using phase zero of the network's m-sequence as the synchronisation pattern. Locking
to the sync code automatically synchronises the address codes which are phase shifted versions of the
same sequence.
With this scheme, however, each user injects approximately 0.1 % error in the correlation process of every
other user. This may be explained by inspection of the autocorrelation function of a m-sequence as shown
in Figure 8 and by consideration of the autocorrelation value of a two level m-sequence, Cx', which, from
equation (6), is given by [5]
|RCx'(t)| N T = 0, N, 2N,
-1 otherwise (21)
Chapter 3 Page 32
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It can be seen that for zero phase shift the correlation is equivalent to the length of the code (i.e. 1023 in
this case) and that for all other phase shift positions the correlation is -1 . This residual -1 effect from every
code being simultaneously transmitted causes this decrease in the correlation output at the receiver. It
is obviously unsatisfactory to have this progressive level of interference caused by other users, and
directly proportional to the number of these other users. These observations are supported by the findings
of Hasegawa, Hirosaki and Sawai [16] in their performance analysis of a fibre optics system.
This scheme has two basic drawbacks, firstly the cross channel interference inherent in m-sequences and
secondly the fact that the code length Is an odd number, 1023. A more suitable code would be a binary
multiple in length, generators and correlators etc. could then use binary counters directly, and would have
ideal 'Iwo valued" autocorrelation values of 0 and N, where N = 1024 in this case. This being the case
it was decided to attempt to modify the m-sequences to eliminate this residual interference effect inherent
in the m-sequences.
3.2.5 Scheme E - Modified Maximal Length Sequences
This scheme uses "Modified" Maximal Length Sequences. Each node is allocated one of these Modified
MLSs, which is essentially a MLS cyclically bit shifted within its 1023 bit length, refer also to Figure lb,
with an additional binary zero transmitted as bit 1024. This address code generation concept is illustrated
in Figure 10. Because of this extra logic zero ail codes produce an additional correlation factor of"-(-1"
when compared to the m-sequence value shown in equation (21). This modification to the MLS produces
a code with the ideal 1024, 0 crosscorrelation characteristics illustrated in Figure 9. The correlation values
produced by code members of this system will then be given by :-
|RmCx'(t)| N + 1 T = 0, N, 2N,
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Chapter 3 Page 34
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33 System Timing Concepts
This section gives a description of the important timing characteristics of the system. Physical network
dimensions and delay features are also considered. Since the code allocation scheme is so intimately
involved with system timing, those aspects of timing important to code allocation are also described.
Timing and code allocation are vital to data recovery, and for this reason the recovery of data from
transmissions subjected to delays is also considered.
As previously noted, this system allows a node to be connected at any point along the interconnection
medium. Node #1 is the station transmitting the synchronisation code (ie. phase zero of the system's
"Modified" MLS) onto the sync line, and this node is connected in the centre of both the Data and Sync
transmission lines. The overall configuration may be represented as shown in Figure 11. The
synchronisation information travels in both directions, along the Sync line, towards nodes #2 and #5,
which are assumed to be at the ends of the transmission lines. Both transmission lines are terminated in
an appropriate resistance to minimise reflections. The clock timing lines in Figure 11 show an example
of possible system delays where the Sync signal takes 1 bit period to reach nodes #2 and #5. At a Chip
rate of 1.2288 MHz (ie. 1200 Hz data rate multiplied by the 1024 processing gain) this 1 bit delay represents
one Chip Bit clock period, Tc = 813.8 ns. This represents a distance of 244 metres from node #1 to
node #2 or node #5, or a total distance from node #2 to node #5 of 488 metres.
Since node #1 is the synchronisation transmitter it represents the system time reference zero (Tref) and
it is this time reference which is used to to generate the synchronisation code (Cref'k), which is the zero
phase of the system coding sequence. This signal takes 1 bit period to arrive at node #2. Node #2 locks
onto this as a reference to absolute system time zero. Node #2 has therefore, a time reference, Tref-1, or
1 bit delayed from the system norm. Node #5 is, similariy, 1 bit delayed, and nodes #3 and #4 are each
1/2 bit delayed.
Chapter 3 Page 37
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If node #1 transmits a message to node #2 using a code which has a separation factor, s, of 2 (ie. Cref'k-2)
it will arrive 1 bit delayed at node #2 (ie. it should look like Cref'k-3), but since node #2 has a relative time
reference which is also 1 bit delayed the two delays will cancel and the transmission will appear to node
#2 to be using code Cref'k-2 . Thus, the code which appears as Cref'k-3 with respect to system time
reference, Tref will appear as Cref'k-2 with respect to node #2's time reference of Tref-i.
If, on the other hand, node #2 transmits to node # 1 , the timing reference of node #2 (Tref-i) used to
select the transmission address code will mean that any address code selected (eg. one subjected to a
separation factor, s, of x, which produces code Cref'k-x) will appear 1 bit delayed (as Cref'k-(x+i)) with
respect to node#1's time reference, Tref. The transmission from node #2 will also be subject to a
propagation delay of 1 bit before reaching node # 1 . The transmission would, therefore, appear to be
using code Cref'k-(x+2) with respect to node #1'stime reference of Tref, ie. the transmission code appears
to have a separation factor of x + 2 as far as node #1 is concerned. In this case the time reference delay
Is added to the data propagation delay to produce this effective delay of 2 bits. Table 1 lists examples
from Figure 11 to explain the situation. In this table column A is the transmitting node, column B is the
receiving node and column C is the total delay as seen by the receiver. This delay is made up of timing
reference delay plus data propagation delay. The calculation of the effective delay for the first two rows
in this table, ie. node #1 to node #2 and node #2 to node # 1 , is shown above. These delays are with
reference to the receiver's own timing reference.
Chapter 3 Page 39
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It can be seen that the relative delay is dependent on the respective positions of the nodes in the system.
One way of overcoming the difficulties posed by these position dependent delays would be to allocate
fixed positions to each node and measure all time delays etc. and then provide a look-up table to each
node so that suitable compensation could be made. This solution detracts from the flexibility of the
system, but could be used to match the transmitting node's ID with the delay characteristics in the look-up
table in order to provide a means of verifying the transmitter's identity. This would be an attractive
proposition if security was a major requirement of the system. Another solution is to adopt a code
allocation scheme such that codes allocated to each node are selected using a separation factor, s, which
is greater than the maximum accumulation of delays in the system.
le s > maximum system delay
Chapter 3 Page 40
Since the maximum system delay is dependent on the length of the transmission lines used, ie. between
node #2 and node #5 in the example shown In Figure 11, the maximum delay can be calculated when
the code allocations are being made. In this way no valid code, no matter what delays it is subjected to,
could possibly mimic any other valid code.
3,4 Sliding Correlator
The fact that transmissions are subject to different propagation delays implies that the receiver must be
able to detect its own messages at any point in a time window, with delays up to the maximum propagation
delay in the system. With the two bit delay used in the example above, it means that a receiver expecting
to demodulate a transmission using code Cx'k must be able to demodulate in the range Cx'k to Cx'k-2.
To this end each receiver incorporates a "Sliding Correlator" with which it can scan across this 2 bit
window looking for its own data. If no such transmission is present the correlation should be zero across
the whole 2 bit window and the search process can begin again, if a valid transmission is present the
receiver should be able to determine the delay at which the correlation peaks and use this delay factor
throughout the transmission, as the delay will remain constant.
Up to this point all aspects of code allocation and modulation/demodulation had been considered in the
light of whole bit delays between codes. This is, obviously, impractical in a real system as the delay is
node placement dependent, and the nodes may be positioned at any point along the transmission line.
The sliding correlator designed for the system is capable, therefore, of delaying the local correlating code
in increments, v, of 1/16th of a bit upto a maximum of 2 bits. The local correlating code thus takes the
form:-
Cx'k-v (23)
Chapter 3 Page 41
If the received and local codes are separated by more than 1 full bit the correaltion will be 0. As the delay
between the correlating codes reduces the correlation will increase uniformly towards a peak of 1024, as
shown in Figure 10.
3,5 Collision Mechanisms and Characteristics
Having seen that the output of the integrator is dependent on the relative partial chip bit overiap of the
transmitter and the receiver, it is important to consider the possible situation surrounding collisions. A
collision would occur when two transmitters simultaneously use the same destination address code. For
positively colliding transmissions the effect would be to simulate a received signal where the energy of
the data bit being encoded varies between V(Eb/T) and V(2Eb/T), depending on the relative overiap of
the two signals with the local correlating code. The result will be to produce a decision variable with a
value between U and 2U, referto equation (11). For negatively colliding signals, ie. subtractive interference,
the value of the decision variable will be in the range 0 to U. For collisions involving more than two
transmissions, the value of the decision variable may be extrapolated from the relative polarities and
overiaps of the colliding signals.
The node should, therefore, be capable of making a decision based on the magnitude of the actual final
value of the decision variable, and not just on the fact that a prescribed threshold has been reached. The
shape of the correlator output (ie. the value of the decision variable) will not follow the characteristic
inverted cone, illustrated in Figure 10, across the 2 bit sliding correlator window when colliding signals
are present. The node should, therefore, be capable of using this information when deciding whether a
collision has occurred.
Chapter 3 Page 42
4 HARDWARE
4,1 Summary
This chapter describes the hardware which has been developed for the project. The description of the
hardware will commence with afunctional description of the major building blocks (and their interactions)
which make up the complete circuit. This will be followed by a description of the individual circuits in block
diagram format, before each circuit is described in detail. The report is designed in this manner in order
that an overall understanding of the operation of the hardware may be obtained, unobscured by the detail
necessary to describe some of the more unique aspects of the circuits designed.
4.2 Overview of Development Requirements
It was decided to produce 3 system nodes. This number allows the simultaneous communication and
interference rejection concepts to be adequately demonstrated, thus satisfying the design aims of the
project.The system is housed in a modular 19 inch rack. A printed circuit backplane, designed for 64 way
indirect edge connectors, is connected to the lower connector slot of the two available. Double or single
Eurocard boards may be used in this system. The indirect edge connectors used are "a" and "c" contact
2 x 32 way units. During the development stages individual circuits were wire wrapped onto single or
double Eurocards. Double Eurocard sized printed circuits were designed for sub sections which had
been developed and tested. Each node of the mature system is made up of two printed circuit boards of
double Eurocard size. For development purposes up to four complete nodes can be housed in the rack.
Power requirements for the whole development system are as follows :-
+ 5 volts at 4 amps, ± 12 volts at 200 ma., and -5 volts at 100 ma.
Chapter 4 Page 43
The need to design modules to be able to be used with different node addresses, and to be controlled via
the same backplane has resulted in the need for some degree of flexibility in backplane pin allocation.
Individually wire wrapping the upper connectors allowed this flexibility. This is necessary in the
development environment, where several nodes must be accomodated together in the single 19 inch
chassis, but is not a feature of a "production" node.
43 Brief Overview of Hardware
Figure 12a shows a block diagram layout of the circuits necessary to perform all of the functions required
in this Spread Spectrum LAN. The individual sections are dispersed between two boards, designated the
"Microprocessor" and "Peripheral" boards, M and P for short, although the microprocessor board
contains peripheral as well as microprocessor components. Each individual circuit is identified as being
on board M or board P. Figures 12b and 12c are photographs of the completed Microprocessor and
Peripheral boards respectively. Figure 12a also identifies which board houses each circuit module. Signals
common to all nodes are transmitted via a commercial printed circuit backplane on the lower of the two
edge connectors, and intra node control takes place via individual wire wrapped connections on the upper
edge connector. Complete circuit diagrams of the two circuit boards are included at Appendix A for
reference.
4.3.1 Microprocessor Control Circuit - Board M
This is the central control and decision making component in each node unit. This section is responsible
for storage of information in transit to and from the network and is also responsible for controlling the
implementation of the LAN protocols.
Chapter 4 Page 44
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Chapter 4 Page 46
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Chapter 4 Page 47
43.2 Host Interface - Board M
The host may be an active bi-directional device such as a computer system, or a relatively passive, mainly
receiver device such as a printer unit. The task of this unit is, however, the same; information received
from the transmission medium must be transferred to the host device in a manner suitable for that device,
and information must be accepted from the host for subsequent transfer, via the spread spectrum network,
to some desired receiver.
4.3.3 Synchronisation Circuit - Board P
This circuit maintains node synchronisation from a sync signal (Address Code 0 is used for this purpose)
transmitted on the sync line. This synchronisation is essential since reference to time frame 0 is necessary
in order to be able to generate different address codes for the transmitter and to detect information
encoded with the node's own address code.
4.3.4 Clock Recovery - Board M
The clock recovery circuit uses the signal on the sync line to extract timing information in order to correct
any drift in the local clock circuits.
4.3.5 Transmitter Line Driver - Board P
This circuit is the high impedence line driver used to transmit modulated data onto the transmission
medium by adding it to the signals already present. A high impedence driver is necessary to ensure
isolation for concurrently transmitting nodes.
Chapter 4 Page 48
43.6 Code Select - Board P
This circuit selects the address code to be used to modulate the transmitter's data, ie. the circuit selects
the destination for each transmission.
4.3.7 A/D Converter - Board M
This section incorporates an A/D converter and an analogue multiplexer, to allow the A/D converter to be
used for two separate inputs. The A/D circuit is used to analyse data obtained from scanning across the
possible 2 bit delay window by the receiver whilst looking for transmissions intended for this particular
node. It is also used by the transmitter to search for transmissions modulated with the intended
destination's code, i.e. a channel occupancy check. The control circuit can select which signal is used
as input to the A/D. This selection allows the transmitter to monitor its own transmissions and to ensure
no collisions occur during transmission.
4.3.8 Receiver Sliding Correlator and Demodulator - Board M
This section allows the node to search, across the allowable 2 bit delay window, for transmissions
modulated with the receiver address code, Up to 32 measurements can be made in 1 /16th bit increments
across the window. Each measurement is the correlation over 1024 chip bits, i.e. the periodic correlation.
The correlation value is then sampled and held whilst waiting to be used by the A/D converter. The
microprocessor control circuit may then make a decision as to the presence or absence of a valid
transmission, with or without collisions, as proposed in section 3.5.
Chapter 4 Page 49
4.3.9 Transmitter Sliding Correlator and Demodulator - Board P
This section enables the transmitter to search, across the allowable 2 bit delay window, for existing
transmissions modulated with the intended recipient's address code. In this manner a Carrier Sense
Multiple Access with Collision Detection (CSMA/CD) type of protocol may be adopted to resolve intra
channel contentions. The circuit may also be used to monitor traffic during transmissions in order to
detect any possible collisions, thus performing the "CD" part of the above protocol.
4.3.10 Data Generator/Receiver - Board P
This circuit performs the necessary second level protocol generation such as frame creation, flag insertion,
frame check sequence, etc. It is also used to check the received data for these same protocol features.
4.4 Detailed Hardware Description
In this part of the report the Individual circuits are described in greater detail. Initially, the functional blocks
of each circuit will be explained and then the unique and/or less commonplace parts of the circuit will be
examined in more detail. The report is designed in this manner to avoid unnecessary description of
standard circuits or techniques.
4.4.1 Microprocessor Control Circuit
The functional block diagram for this circuit is shown in Figure 13. The circuit is based on a Motorola MC
6809 microprocessor operating at a clock frequency of 1 MHz. The two asynchronous serial interface
devices are included (SY 6551), primarily to support the development exercise as only one will be needed
in the mature system. Two parallel input/output devices (SY 6522) are included, giving 32 programmable
Chapter 4 Page 50
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Chapter 4 Page 51
input/output lines. The circuit is designed with 8K x 8 of EPROM (2764) and 8K x 8 static RAM (6164),
which is expendable to 16Kx8. The memory map of the system is included as Figure 14. Figures 13 and
14 also show the Serial Data Generator/Receiver, which uses an Advanced Data Link Contoller (ADLC -
MC 6854), to be part of the controller circuit, but its use will be considered separately in the Data
Generator/Receiver section. The description of the actual use of the components in this circuit will be
better illustrated when either the controller software or the individual circuit being controlled are described.
The connections between the controller and the circuits being controlled are through the parallel input
output devices (VIAs). Figure 15 is a list of the control signals and an identification of the circuits to which
they relate.
4.4.2 Host Interface
The host interface is, essentially, a part of the microprocessor control circuit but is identified separately
since it interfaces to the host machine rather than the "personality" circuits which comprise the Spread
Spectrum l_AN node. The interface uses an Asynchronous Communications Interface Adapter (ACIA)
operating to the V24 format. The device may be programmed to suit the number of data and stop bits,
parity etc. required by the host computer. Messages may then be buffered in the node's RAM whilst
awaiting transmission into the network
4.4.3 Synchronisation Circuits
Figure 16 shows the synchronisation, and closely associated code selection circuitry. For simplicity of
generation, the modified MLSs, which form the address codes, are stored in a Read Only Memory. The
reference (or synchronisation) code is stored in data bit 0 of 1024 consecutive memory locations with bits
1 to 7 being used for 7 other node address codes. For the demonstration system this number is more
than adequate.
Chapter 4 Page 52
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Chapter 4 Page 54
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The locally generated synchronisation code is compared with the signal on the sync line in the comparator
section. It is possible that all 1024 phases of the local sync code must be tried before it matches with the
sync line signal. During the search operation each phase is tested for 32 bits. If 20 consecutive bits are
matched then code synchronisation is assumed and the circuit reverts to the "In Sync" mode and the
"In/Out Sync" indicator set accordingly. If, after 32 bits, the matching criterion is not met then the ROM
Address Modify circuit is activated. This circuit removes one clock pulse from the clock driving the ROM
Address Generator circuit, thus effectively stepping the locally generated code one phase backwards with
respect to the sync line reference signal. 32 bits of this phase are then tested, as described above.
The criteria for recognising loss of sync, when the circuit was already in the In Sync mode, differ from the
criteria used when the circuit was previously "Out of Sync". When already In Sync it is assumed that
errors on the synchronistion line are possible and are in fact more probable than a total loss of sync. This
being the case the comparator circuit remains on the formerly "in sync phase" for 128 bits looking for 20
consecutive matches. Whenever 20 consecutive matches are found the counter circuit is reset and the
sync indicator set to In Sync. If, after 128 bits of testing, 20 consecutive matching bits not are found the
sync indicator is changed to Out of Sync and the "Sync Search" mode is entered. Figure 17 is a timing
diagram of some of the more important waveforms in this circuit, and Figure 18 is a circuit schematic for
the sync circuit.
The waveforms in Figure 17 are related to test points on the circuit schematic. In Figure 17 waveform A
is the clock and waveform B is the ouput of the 20 bit comparator (showing no valid 20 bit comparison),
and waveform C is the output of the search counter circuit. When a count of 32 is reached waveform C
goes to a logic 1 causing the address modify waveforms D and E to be generated. These waveforms
are NANDed together to form the address modify clock enable signal, F, which is used to gate the clock
signal, G, used to generate ROM addresses. The loss of a clock edge in this manner causes the output
of the ROM to be altered by 1 bit in phase relationship with the reference signal on the sync line. 32 bits
of the new phase are than compared with this reference signal.
Chapter 4 Page 56
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Chapter 4 Page 58
The second part of Figure 17 shows the acquisition of a valid 20 bit comparison. After a number of bits
have been compared (23 is only used as an example) a sequence of 20 consecutive bits in agreement
are found and the comparator output goes to a logic 1. This causes the counter to be reset to 0 and remain
in this reset condition whilst the comparator output remains at a logic 1. If for some reason, phase
synchronisation is lost (as shown in the third part of Figure 17) the comparator output returns to a logic
0 and the counter is re-enabled. After 32 bits the address modify clock enable circuitry is not activated,
however, as the circuit was previously in an In Sync condition. If a valid comparison is not found within
128 bits, however, the clock enable circuitry is enabled and one bit removed from the clock to the ROM
address generator circuit, and the whole circuit reverts to the Sync Search mode.
It can be seen that, if the comparator circuit requires 20 valid bits from 32, one error in 32 may cause a
valid phase not to be recognised as phase 0, as the error may make 20 bit comparison impossible before
the next phase is tested. Thus a 3% error rate could, apparantly, cause a complete failure to find sync.
The situation is not quite as bad as this in practice since any 20 consecutive valid bits out of 32 would be
sufficient to find sync, and in burst error conditions this could correspond to an effective error rate of 11
in 32 or 34.4%. When the circuit is already in sync, however, finding 20 error free bits out of 128 is a
much simpler task and, if they are uniformly spread, the circuit could withstand 6 errrors within the 128
bits and still find a valid 20 bit comparison. Thus an error rate of 1 in 20 or 5% is unlikely to cause loss
of sync problems. If the errors occur In bursts, then any burst sequence which permitted 20 error free
bits in 128 would, again, not interfere with the circuit remaining in synchronisation. The circuit could,
therefore, in theory withstand 107 errors within any 128 bit window and still not lose sync. This
corresponds to an error rate of 83.6%.
Having estimated that the circuit should be able to find synchronisation in an error environment of between
3 and 34%, and that the circuit should be able to retain this synchronisation in an error environment of
between 5 and 83%, it was thought necessary to investigate the circuit's error rejection characteristics
more thoroughly.
Chapter 4 Page 59
The worst case time to find sync, from recognition of loss of sync, should be the time to test 32 bits for
1023 non-valid sync phases and then 20 bits of the valid reference phase 0. The worst case time is
therefore:-
1023 X 32 X Tc -f- (20xTc) = 32756 xTc
= 26.7 ms
where Tc = 1/(1.2288x10^) = 814 ns.
In order to test the performance of the synchronisation system in the presence of errors It was necessary
to use an error generator which could be programmed to produce the error rate required, and which could
be synchronised with the clock rate of the synchronisation sequence. No such device was available and
so one had to be designed, built and tested. As this error generator is not, exactly, part of the mainstream
research of this project the details of its contruction and testing are included at Appendix B rather than in
the main text; but since it was designed specifically for this project, the description is comprehensive. A
brief summary of the device is as follows:-
The error rate is programmable between 1x10"® and 9 x 10"\ The output is either an error signal
or, if data is injected at the input, a data signal which includes generated errors. The input and
output are TTL compatible. In order to synchronise to a particular data rate, the generator
requires a data clock input, which is also TTL compatible. The data clock rate may vary between
1 Hz and 1.5 MHz. Error insertion can be turned off and on with one switch, therefore constant
connection and reconnection of the data signal is not necessary. The error rate quoted is the
average, long term, error rate and includes multiple bit errors ie. when 3 consecutive bits are in
Chapter 4 Page 60
error this counts as 3 errors rather than a single error. The output of the error generator
approximates to a Gaussian distribution based on the preset rate selected, as can be seen from
Appendix B,
4.4.3.1 Performance Tests on the Sync Circuit
Using the error generator described briefly above, errors were injected into the signal on the
synchronisation line. The error rate was increased from 1% and the In/Out Sync indicator
monitored to determine whether the circuit had lost sync and failed to re-find sync within the
allowed 128 bits. As the error rate was increased, from 1%, no sync dropouts were encountered
until 10% error rate had been reached. From this point 10 readings were taken at error rates
between 10% and 90%. The number of sync dropouts vs the error rate is plotted in Figure 19. It
can be seen from this graph that the maintenance of synchronisation was not a problem, even
with error rates as high as 30%. From this point dropouts increased until they became a serious
problem above 50% errors and from 60% errors the circuit could not reliably stay in sync. These
figures match closely with the predicted figures and indicate that the circuit will, indeed, maintain
synchronisation in an extremely error prone environment.
Having proven the circuit's ability to retain synchronisation It was then necessary to determine
the circuit's ability to achieve synchronisation in an error prone environment. For these tests the
error generator was used as described above and an additional test circuit to force sync loss was
also used. This circuit removed a clock pulse from the ROM Address generator input, causing
an incorrect phase to be tested thus ensuring sync dropout. This method of generating sync
dropout causes the next phase to be injected into the comparator circuit thus ensuring sync
dropout and also requiring all 1023 alternate phases to be tested before the reference phase 0
was again tested. In this manner the the time taken to regain sync may be used as an indicator
to determine the circuit's resynchronisation characteristics. A counter/timer was used to measure
the time the circuit then took to regain synchronisation. The counter/timer was started by the
In/Out Sync indicator falling from logic 1 to logic 0 and stopped by the sync achieved signal ie.
a 0 to 1 transition on the In/Out Sync indicator.
Chapter 4 Page 61
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Chapter 4 Page 62
Tests began with an error rate of 1% which was increased in 1% steps. 10 measurements were
taken at each error rate. In the absence of errors the circuit should regain synchronisation within
26.7ms, as shown previously. If the circuit failed to find sync on the first pass, thus requiring all
1024 phases to be re-tested, the time taken to achieve sync would be two cycles ie. approximately
54 ms. All test figures are, therefore, normalised to the 26.7 ms cycle and given as the number
of cycles required before sync is achieved. Figure 20 shows a graph of 'Ihe average number of
cycles required to regain synchronisation" vs "error rate". It can be seen that below 7% the
circuit found synchronisation on the first pass every time and that after this point the number of
passes required increased rather rapidly. Having found sync, however, it is very unlikely that the
circuit would lose sync again, as sync loss below 30% error rate was extremely rare. The
performance criterion for the successful operation of this circuit must, therefore, be its ability to
find synchronisation reliably at the first attempt in an environment with an error rate as high as
7%. Since this is a very high error rate, the circuit was considered suitable for use to synchronise
the Spread Spectrum LAN.
4.4.4 Clock Recovery
The basic circuit functions in the clock recovery circuit are shown in Figure 21. Figure 22 shows timing
diagrams for this circuit with the waveforms corresponding to the test points indicated in Figure 21. In
keeping with the overall design aims of the project, i.e. keep the design simple and to use standard
components wherever possible , the circuit does not employ sophisticated phase locked loops as may
be expected.
In order to provide the ability to step the sliding correlator in 1/16th bit intervals it is necessary to locally
generate a frequency of 16 times that used to produce the synchronisation data sequence. A local crystal
controlled oscillator operating at 19.6608 MHz (i.e. 16x1.2288 MHz) is used for this purpose. The output
of this local oscillator. A, is used to clock a divide by 16 circuit, the output of which acts as a locally
generated 1.2288 MHz chip rate clock, B. The signal, C, on the sync line is input to a pulse generator
such that every transition, whether it be positive or negative edge, causes a narrow pulse, D, to be
Chapter 4 Page 63
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Chapter 4 Page 64
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Chapter 4 Page 66
generated. These pulses are used to reset the divide by 16 counter such that the output, i.e. the locally
generated 1.2288 MHz clock, is synchronised with the synchronisation signal on the sync line. The output
of the divide by 16 circuit is, therefore, subject to jitter of up to 1/16th of a bit caused by any frequency
differences between the local oscillator and that of the sync transmitter. Within the limits of this 1/16th bit
jitter the local and reference clocks are thereby locked in phase and frequency.
To produce the clock necessary to create the 1/16th bit steps required forthe sliding correlator the locally
generated 1.2288 MHz clock is input as a data signal to a 16 bit serial-in parallel-out shift register clocked
by the high speed local oscillator. The data outputs, E , F, G, of this shift register thus represent the
1.2288 MHz clock delayed in 1/16th bit increments. The 16 outputs of the shift register are then input to
a 16 to 1 data selector/multiplexer and the delayed version of the 1.2288 MHz required, H, may then be
obtained at the output by selecting which input is to be connected to the output. Two seperate data
selectors are used to provide independently selectable signals suitable for the transmitter and receiver
sliding correlators.
4.4.5 Transmitter Line Driver
Each node must be able to add its signal to those already be present on the data transmission line. To
this end it is obvious that the transmitter line driver must not load the output of every other transmitter.
The multiple access concept used in this network was described in section 1.9. The block diagram for the
functional layout is shown in Figure 5. In order not to load other node's transmissions, and so as to
approach (as far as possible) the idealised multiple transmission characteristics shown in Figure 6, each
transmitter incorporates a high impedance current driver output stage.
Before the driver stage could be designed it was necessary to consider the properties of the transmission
line chosen for this development model. For simplicity of connection and disconnection Balanced Twin
Feeder with the following characteristics was used :-
Chapter 4 Page 67
Clear polythene insulation
Cores are 7 x 0.25 mm plain copper stranded
Dim 9.7 mm X 1.8 mm
Characteristic impedance 300 n
Capacitance 13.2 pF/m
+ Attenuation per 10 metres 0.12 dB at 10 MHz & 1.68 dB at 1000 MHz
For development purposes, a 100 metre drum of this cable was used, as an interconnection medium. This
is terminated at both ends in the characteristic impedance in orderto minimise mismatches and reflections.
The block diagram of the circuit designed to interface to this transmission line is shown in Figure 23. It
was decided that the circuit should act as a constant current source (as near ideal as possible). In order
to transform the 1 and 0 level binary into a two level, ± 1, signal the driver should be able to source and
sink current. If, for example, the circuit were to source current to represent a logic 1 and remain passive
for the logic 0 signal, it would be Impossible for a logic 0 signal to have the desired effect, or Indeed to
be detected in the presence of any logic 1 signal, ie. the system would be performing a logical OR function
rather than ADDING signals. For this reason, it was decided to represent a logic 1 by adding 1 "unit"
voltage to the existing voltage on the transmission line and to represent a logic 0 by subtracting 1 "unit"
voltage from the existing voltage. This is brought about by sourcing or sinking current at an appropriate
rate.
Chapter 4 Page 68
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Since this circuit would always be either sourcing or sinking current it was necessary to include an enable
input so that both source and sink circuits could be disabled. And, as the driver present a high impedance
interface to the transmission line, this means that the node may be electrically disconnected from the
network.
A schematic diagram of the driver circuit is shown in Figure 24. The circuit makes considerable use of
"CURRENT MIRRORS" to create the effect of an ideal current source. The current mirror M2 is the current
reference shown in Figure 23. Current flowing in the left hand transistor is determined by the 10ka variable
resistor, P6, this current is reflected in the right hand transistor which is connected to the enable section.
This 10kn variable resistor is used to set the reference current and hence the value of the "unit" voltage.
The value selected for the unit voltage must be considered when selecting the scale factor for the multiplier
(section 4.4.8.2) and the input amplitude adjustment for the integrate and dump (section 4.4.8.3). The
enable section is made up of two identical NPN transistors. The right hand transistor is biased at 2.1 volts,
determined by the three diode drops. The enable, TCA 17 in Figure 23, is an input to comparator CI . If
the enable input is greater than 2.1 volts then TR5 will be on and current will flow in M1. If, however, the
enable input Is less than 2.1 volts then TR8 will be on and current to M2 will all be supplied by TR8 and
no current will flow in M l . M1 is also a current mirror, if the enable input is greater than 2.1 volts then, as
stated, all of the current for M2 will flow through TR5 and thus this current will be reflected down to M3.
M3 and comparator C2 make up the data section. TR14 is biased like TR8 at 2.1 volts so that if the data
input is greater than 2.1 volts then TR11 will be on and TR14 off, hence all of M3's current will flow through
TR11. A data input greater than 2.1 volts represents a binary one and current must be sourced on to the
line. This is done by M4, the current flowing in TR11 is reflected by M4 and is sourced onto the line,
causing the line voltage to increase by 1 unit voltage.
If the data input is less than 2.1 volts (i.e. binary zero) then TR11 will be off and all of M3's current will flow
through TR14. This current will be reflected by M5 and then by M6 which will draw the same current off
the line, (i.e. sink the reference current) causing the line voltage to decrease by 1 unit voltage.
Chapter 4 Page 70
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Diodes D13 and D14 are used to ensure current does not flow the wrong way when the particular section
is not in use. If the enable Is off, ie. 2.1 volts, then no current will be reflected into M3 and hence M4, M5,
and M6. Transistors TR13and TR18 will both be off and the circuit will present a high impedance interface
to the network.
4.4.6 Code Select
Because of the nature of the code synchronisation and generation, the code selection circuit is greatly
dependent on the sync circuit and is shown included in Figure 16 with the sync circuit. The ROM is
pre-programmed with the synchronisation plus seven other address codes. The synchronisation code is
programmed into the bit Do position of the ROM and the other bits Di to D7 give the, already synchronised,
address codes used for demonstration system testing. The outputs from the ROM are all latched, to
remove ROM address-generation-caused glitches. Three select lines from the microprocessor control
circuit are used to select any one of the remaining seven codes to act as a destination address. The local
address code is extracted after latching, but prior to the selection circuit.
4.4.7 Analogue to Digital Converter (ADC)
The analogue to digital converter circuit contains much more than the name implies. Figure 25 shows a
block diagram of this circuit. The analogue to digital converter is, actually, multiplexed between the
transmitter and receiver circuits, the selection being made by the microprocessor control circuit using a
single select line. In orderto maintain the value of the signal, to be converted until the converter is available
the signal must firstly be sampled and the value of the sample held until it has been used. Seperate sample
and hold circuits are incorporated into the transmitter and receiver circuits. Commercial LF398 sample
and hold ICs are used in conjunction with a 14053 analogue multiplexer. The analogue to digital converter
is an eight bit ADC 800 device. With reference voltages of ± 5 volts the full scale value of $00 represents
+ 5 volts, $80 represents 0 volts and $FF represents -5 volts (where $ signifies hexadecimal notation).
When rationalised these values equate to 0 to ±5 volts being represented by 0 to ±128 (decimal)
Chapter 4 Page 72
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respectively. The input to this circuit is from the output stage of the integrate and dump filter in the
transmitter or receiver circuit (see Figure 26). The sample and hold circuit uses the inverted 1200 Hz data
clock as its tracking and holding clock, as indicated in Figure 25. This gives 416 j^s for the sample and
hold IC to track the output of the integrate and dump filter (of either the receiver or the transmitter). This
substantial amount of time ensures that expensive fast tracking sample and hold devices are not
necessary. The remaining 416 |xs in the hold period is then available for the microprocessor to select
and process the ADC value. The clock which the ADC uses for its conversions is the 1.2288 MHz divided
by 2. This gives a clock rate of 614.4 kHz. The maximum conversion time (quoted as 40 clock cycles) is,
therefore, 65.1 |xs.
4.4.8 Receiver
Figure 26 is a block diagram of the receiver circuit. The receiver may be considered as 3 sections for
description purposes:-
The Sliding Correlator
ii) The Analogue Multiplier
ill) The Integrate and Dump Filter
4.4.8.1 The Sliding Correlator
Figure 27 is a block diagram of the sliding correlator. This circuit uses the output of the clock
selection circuitry in the clock recovery section (see Figure 21) to re-time the address code
selected to be used for demodulation and data recovery purposes. This address code may be
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the node's own code (if this is the receiver sliding correlator) or the code being used for
transmission (if this is the transmitter sliding correlator). One of 16 seperate 1.2288 MHz clock
phases may be used to clock the first "D" type flip flop, and thus re-time the address code in 1/16th
bit increments over a whole bit position. For delays in excess of a single bit the address code is
passed through a second D type giving a 2 bit total delay available. Four select bits are used to
select the clock delay phase and a fifth is used to select < 1 bit or > 1 bit delay. In this way the
whole 2 bit window required for the sliding correlator function may be generated giving 32 x 1 /16th
bit correlator sample positions.
4.4.8.2 The Analogue Multiplier
The major component of this section is the RS 1495 Analogue Multiplier IC. Figure 28 shows a
basic block diagram of the functional components of this circuit. The full calculation of parameters
for the use of this device is shown in Appendix C. The inputs into the RS 1495 for the two signals
to be multiplied are designated VY and Vx. The received signal, r(t), is connected to VY and the
local code, Cx'(t) is connected to Vx. as shown in Figure 28. The two signals are multiplied
together in order to facilitate data recovery as shown in equation (18) in section 1.9.
Since the modulating address code, Cx'(t), is a ± 1 signal, then remultiplying by the same code
will give Cx'^ which will always be + 1 . This -f-1 value will be integrated over the full 1024 bits
which represent a data bit, thus reproducing the original data bit. The multiplication Cx'(t) Cy'(t)
(where Cy'(t) represents any other address code) will, on average, produce as many +1 values
as it would -1 values over the 1024 bits, thus cancelling each other out and producing no
accumulated value at the output of the integrate and dump filter. Separate X and Y offset
adjustments are available on the RS1495, to remove any DC components, and a scale factor
adjustment is also available, allowing the multiplication output to be adjusted to suit power supply
limitations and line signal voltage parameters etc. A separate level shifter circuit (made up of a
LF741 operational amplifier) is included which also transforms the balanced output signal into a
single line output signal. This output signal may then be level shifted, using an output offset
Chapter 4 Page 76
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adjustment, in order to remove any residual DC offset before the signal is presented to the
integrate and dump filter.
4.4.8.3 Integrate and Dump
A block diagram of this circuit, with appropriate timing waveforms, is included in Figure 29. The
integrator consists of a LF741 operational amplifier in an integrator configuration with a serial
input resistor and a feedback capacitor. The values of the components are chosen so as to ensure
linear integration over a data bit period of 833 jis. The input amplitude adjustment allows the
value of the integrated output to be chosen within the range ± 1 to ±10 volts. The standard
integration value was selected to be ±2.5 volts. This is set to give half scale readings on the
Analogue to Digital converter, thus leaving the range between ± (2.5 to 5 volts) available for
collision detection. The integrator output value is held, in the Sample and Hold circuit, on the
rising edge of the 1200 Hz data clock. One bit of the address code clock later (1.2288 MHz) a
pulse one clock bit wide is generated which causes the integrator output to be reset to zero by
discharging the integrator capacitor using FET switches. This dumping of the previous value
ensures no residual or carry over effect from one data bit to the next.
Besides routing the integrator output to the ADC circuit, so that any collisions may be detected
on an individual bit basis, the signal is also input to a comparator and voltage translation circuit
to reproduce a digital signal representing the logic 1 or the logic 0 value of the, now decoded,
data bit. This digital signal is then clocked into the data generator/receiver section for byte and
protocol evaluation etc.
4.4.9 Transmitter
Figure 30 shows a block diagram of the transmitter circuit. The circuit is, in fact, a collection of circuits
previously described. The address code to be used for transmission, i.e. the destination's code, is selected
and a replicated receiver used to pre-check for existing transmissions which are using this code, i.e. a
Chapter 4 Page 79
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channel occupancy check. If no existing transmissions are detected over the full 2 bit window, which is
available using the sliding correlator, then the output from the data generator is multiplied with the selected
address code before being routed to the transmitter line driver for injection into the transmission medium.
The transmission medium is also constantly monitored by demodulating using the destination's address
code to ensure correct, collision free, transmission of the required data. The transmitter may, thereby,
validate its own transmissions and take remedial action in the event of a collision being detected.
4.4.10 Data Generator/Receiver
The Data Generator/Receiver is shown as part of the microprocessor control circuit in Figure 13, although
it appears on board P with the transmitter circuitry. A Motorola Advanced Data Link Controller, MC 6854
[26], device is used to provide the level 2 protocol for the International Standards Organisation (ISO),
Open System Interconnection (OSI), seven layer model for a Local Area Network. The initial data
preamble, required for synchronisation, is controlled by the microprocessor which sets the ADLC to
transmit a Mark on the idle condition. The destination address code is then selected and the the transmitter
line driver enabled. These conditions are maintained for 32 data bit periods. After this phase the ADLC will
be configured to generate and detect the appropriate protocol to ensure data transmission and reception.
The protocol includes flag detection and synchronisation, zero insertion and deletion, frame check
sequence generation and validation, etc. The transmitter and receiver sections are clocked at the 1200
Hz data clock rate.
Chapter 4 Page 81
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5 HARDWARE FUNCTIONAL TESTING
5.1 Summary
This chapter describes the system tests carried out on the hardware, as opposed to the tests of the
individual circuit elements described in chapter 4. The circuit configurations used for test purposes are
also outlined. Test results are also related back to the theoretical results predicted in sections 3.4 and
3.5.
5.2 Bit Error Rate (BER) Test
The first test to be carried out to determine some of the characteristics of the hardware was the
determination of the hardware address code demodulation in the presence of other signals and external
interference. This test was, therefore, designed to prove the concept illustrated mathematically in equation
(18) in section 1.9. Three transmitting nodes and two receivers were used for this test. This equipment
was configured in a similar manner to that shown in Figure 31.
The purpose of the test was to determine the Bit Error Rate (BER) produced under different levels of Signal
to Noise (S/N). The word noise is used here to represent total interfering signals and includes both
co-channel interference (from the two other transmitters) and external interference which took the form
of Added White Gaussian Noise (AWGN). The analogue White Gaussian noise signal was produced from
the Error Generator which is described in Appendix B by taking the 2^^-1 bit MLS at 36 MHz and passing
this through a simple low pass filter with a 3 MHz cut-off. The output of this MLS would produce a spectrum
of a (sine x)^ function illustrated in Figure 32 with its first null at the clock frequencey of 36 MHz. By band
limiting this to 3 MHz, only the central part of the spectrum is used, i.e. the section with a relatively constant
output level. The band limited output spectrum is shown in Figure 33a. True white noise contains all
Chapter 5 Page 83
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Figure 33b Photograph of Single Transmitter Spectrum
Chapter 5 Page 86
frequencies with equal energy but this signal actually contains discrete frequencies with a frequency
spacing of:-
f = fclock/(2"-1) = (3X10^) / ( 2 ^ - 1 ) = 0.0167Hz
With discrete spectral line spacing of 0.0167 Hz over the whole 3 MHz band this generator could be
considered to approximate to White Gaussian noise. The white noise was band limited to 3 MHz, as the
3dB bandwidth of the RS 1495 Analogue Multiplier (i.e. the receiver) is given as typically 3 MHz.
The three transmitter signals, si (t) to S3(t), were summed with the AWGN signal, J (t), before being injected
into the transmission medium, to arrive at the receivers as signal r(t). The HP 1645A Data Error Analyser
acted as a data source for transmitter #1 and the output of receiver #1 was routed to the same device
for analysis. Transmitter #2 and receiver #2 were used merely to demonstrate simultaneous data
communication, no measurements were made on channel #2. Transmitter #3 is included as an additional
source of co-channel interference. The transmission rate of the three transmitters is 1.2288 MHz and Figure
33b shows the spectrum of the received signal at r(t) with only one transmitter being input to the summing
amplifier and no additional noise signal, (ie. J(t) = 0). Figure 33c shows the spectrum at r(t) with three
transmitters and added noise at a signal to noise ratio of -11 dB.
The upper trace in Figure 33d shows the time domain of this same received signal. The lower trace shows
the data recovered, di(t), from this signal.
The output of the summing amplifier was tuned to increase the noise content in the output and the HP
3400A RMS voltmeter was used to measure the signal to noise values. The HP 1645A has a limited error
count before overflow occurs, therefore at higher error rates the number of bits selected to be included
in each test was much lower than for the low values of error rate where 10'' data bits were transmitted.
Chapter 5 Page 87
Figure 33c Photograph of Noise + Multi-Transmitters Spectrum
Figure 33d Photograph of Received Signal / Recovered Data
Chapter 5 Page 88
10 BER samples were taken at each selected S/N value and the average of these 10 tests plotted against
the S/N ratio to produce the graph shown in Figure 34.* It can be seen from this graph that with
approximately -13 dB signal to noise ratio the Bit Error Rate is as high as 2 x 10"^ but at -10 dB S/N the
BER drops so low that no errors were recorded in a 24 hour test period.
These results show that this type of Spread Spectrum system may be used to transmit data in the presence
of noise, even when the total interference is significantly greater than the signal.
53 Sliding Correlator Test
The sliding correlator was included in the receiver circuitry in order to be able to detect signals subject to
delay of up to 2 bits, caused by propagation delays and timing differences (see chapter 3). A peak of
correlation is found where the two signals are in phase, and the correlation value drops uniformly until,
with the signals more than ± 1 bit separated, zero correlation is apparant beween them, it is obvious,
therefore, that for maximum demodulation efficiency the receiver should ensure that the demodulation
process is carried out at the peak of the correlation function.
In order to carry out these tests a transmitter was modified slightly so that the code selected, to modulate
the transmitted data, could be delayed in 1/16th chip bit increments up to 2 complete bits. The coded
transmission was then injected at one end of the 100 metres of cable used for the development system
transmission line, and the receiver positioned at the opposite end of the line in order that both intentional
* NOTE The noise component in the S/N values is meant to include all interference, ie. both co-channel and AWGN.
Chapter 5 Page 89
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Chapter 5 Page 90
and the propagation delay effects caused by the line would be included in the results. Intentional delays
of 1, 9, 21 and 25 (x 1/16th) bits were introduced. Correlation values were taken in 1/16th bit intervals
across the 2 bit window for each of the 4 delayed signals noted above.
The analogue multiplier and integrate and dump filter circuits were adjusted to give a peak correlation of
±2.5 volts, and the Analogue to Digital converter set to reference voltages of ± 5 volts. This meant that
the peak periodic correlation value for a single received signal, over the full 1024 bits, should be ±64
(decimal). For the purpose of comparison in this test, only magnitudes are considered.
It can be seen from Figure 35 that the correlation output does, indeed, follow the trend indicated in section
3.4, with a peak value of about 64 occurring approximately 1/2 bit past the deliberately introduced delay.
This 1/2 bit is accounted for by propagation, clock recovery and processing delays etc. From this peak
the correlation falls to almost zero when the signals are separated by more than 1 full bit. By using the
sliding correlator, therefore, the receiver could determine the delay time which corresponds to the peak
correlation value and lock on to this peak for data demodulation purposes. It is also apparent that the
presence or absence of a valid signal anywhere in the 2 bit window is easily detected.
5.4 Collision Detection Tests
5.4.1 Test 1 Additive interference (overlap < 1 bit)
Having proved the ability of the hardware to detect signals anywhere in the 2 bit delay window specified
in the system design, thereby verifying the concepts outlined in chapter 3, the next step was to determine
the ability of the hardware to detect signal collisions.
For these tests the reference transmitter is co-located with the sync generator and is transmitting with
zero delay using channel address # 1 , Ci'(t). The colliding signal is provided by the modified transmitter,
Chapter 5 Page 91
Figure 35 Correlation With Delayed Signals
Chapter 5 Page 92
which generates the same address code with selectable simulated propagation delays. Figure 36 shows
the output of the correlator when the colliding transmission is subject to intentional delays of 1,5, 9 and
13 (x 1/16th) bits. The correlation value from the reference transmitter, ie. with no interference is included
for comparison purposes. It can be seen that the shape of the correlator output follows the trend described
above, see also Figure 35, with a peak correlation of between 60 and 64. The colliding signals shown in
Figure 36 all introduced additive interference, in that the same logical data value was modulated by both
reference and colliding transmitters. It can be seen that the correlation with the superimposed signals
reaches a peak well above that of the reference signal alone; the value of this peak being dependent on
the degree of overlap of the two signals. These curves follow, very closely, the shape of the curve predicted
for colliding signals in section 3.5. The detection of collisions is, therefore, relatively simple in this case as
both the peak correlation value and the width of the correlation curve can be seen to vary considerably
from that obtained for a signal with no interference.
5.4.2 Test 2 Additive interference (1 bit < overlap < 2 bits )
Figure 37 shows the correlation results obtained from superimposed signals, again causing additive
interference, when the colliding signal is more than 1 but less than 2 full bits separated from the reference
signal. Delays of 17, 21, 25 and 29 (x 1/16th) bits were used for the colliding signal and the results are
displayed, with the no interference signal included for comparison purposes. It can be seen that the peak
correlation values are only marginally above that of the reference but the shape of the correlation curve
is completely different. Again the detection of colliding signals under these conditions is a relatively straight
fonward process relying on the fact that the curve is very much wider than the reference curve across the
delay window.
5.4.3 Test 3 Destructive interference ( overlap <1 bit)
The next test was to repeat test # 1 , but this time the colliding and reference signals are modulating different
logical data bit values. The magnitude of the correlator's output is used in the graphs in order that
Chapter 5 Page 93
3 a
+> 3 0
0 Q <
c 0 I —
•p
0 H) L L 0 u
130
120-
110-
100
90
80
70
60
50
40
20
10^
I 0
0 4 8 12 16 20
No interference Displacement x 1/16 bit
5
24
9
28
13
Figure 36 Correlation of Additive Signals - Less Than 1 Bit Delay
Chapter 5 Page 94
70
r\ J
a J 0 0 Q <
c
v D
ID L L 0 0
6 0 -
50
4 0 -
3 0 -
2 0 -
1 0 -
0
0 4 8 12 16 20 24 28
No interference Displacennent x 1/16 bit
^ - 17 — 21 25 29
Figure 37 Correlation of Additive Signals - Greater Than 1 Bit Delay
Chapter 5 Page 95
comparisons with the results of the previous tests may be made. Figure 38 shows the correlation results
obtained when colliding signals of delays of 1, 5, 9 and 13 (x 1/16th) bits are used. It can be seen that
the peak correlation value is dependent on the degree of overlap with the reference signal and that the
width of the correlation curve is much narrower than that of the reference, and it has also a second peak
as was expected. As the correlation with the reference signal declines it is compensated for by the increase
in the correlation with the delayed signal. The comparison is not obvious since these are destructively
interfering signals. Figure 39 shows these results again, but this time the sign of the correlation is taken
into consideration, and the decline in the reference correlation value followed by the increase in the
delayed signal correlation value can more readily be seen. Again the detection of collisions is relatively
simple as the shape of the correlation curve and the peak magnitude of the correlation function both differ
quite considerably from those of the reference signal.
5.4.4 Test 4 Destructive interference (1 bit < overlap <2 bits )
Test #4 is a repeat of test #2 but using destructively interfering signals rather than additively interfering
signals. Figure 40 is a graph of the correlation values using colliding signals of 17,21,25 and 29 (x 1/16th)
bits. The correlation values are shown as magnitudes in this figure. It can be seen that the correlation
peaks are only marginally greater than that for the reference signal and also that the width of each of the
first correlation peaks is not substantially different either. The difference between the superimposed
correlations and the reference occurs in the second peak caused by the increase in the correlation with
the delayed signal. Figure 41 shows the same results but this time the sign as well as the magnitude of
the correlation results is included. It is quite apparent, therefore, that including the sign makes the task of
collision detection simple as + ve and -ve correlation peaks can only come from destructively interfering
signals.
These tests have demonstrated the ability to use the hardware to detect collisions with some reference
signal no matter what the delay and relative data bit sign of the colliding signals. The hardware circuits
perform exactly as predicted (see chapter 3).
Chapter 5 Page 96
70
r\ +J 3 a 3 0
0 Q <
4J
D
(D L L 0 0
6 0 -
50-
4 0 -
:!>o-
2 0 -
1 0 -
0-f
0 4 8 12 16 20 24 28
No interference Displacennent x 1/16 bit
— 1 — 5 9 13
Figure 38 Correlation of Destructive Signals - Less Than 1 Bit Delay
Chapter 5 Page 97
70 Destructive Signal interference
3 a +> 3 0
0 Q <
c 0
+5 0 0 L L 0 u
-60 —p-—P—^~—^—P~~~P
0 4 8 12
"l—T-T" 16 20
lo interference Displacement x 1/16 bit
— 1 — 5
24 28
9 13
Figure 39 Positive and Negative Correlation - Less Than 1 Bit Delay
Chapter 5 Page 98
80
r\ +• 3 a 3 0
0 Q <
0
0 L L 0 0
70
6 0 -
50-
40
3 0 -
2 0 -
1 0 -
0
— No interference Displacement x 1/16 bit
— 17 — 21
Figure 40 Correlation of Destructive Signals - Greater Than 1 Bit Delay
Chapter 5 Page 99
25 29
r
3 a 3 0
u Q <
C 0
I— •M
0
0 L L 0 0
Destructive Signal Interference
0 8 12 16 20 24 28
No interference Displacement x 1/16 bit
— 17 — 21
Figure 41 Positive and Negative Correlation - Greater Than 1 Bit Delay
Chapter 5 Page 100
25 29
6 THROUGHPUT MODEL
6.1 Summary
Chapter 6 describes the development of a theoretical throughput model for a Local Area Network with
the specifications described previously. A protocol suitable for the transmission of information in a network
of this type is also explained. Theoretical throughput figures are calculated and these are compared with
figures obtained from a simulation designed to model traffic throughput in this system. The differences
between the theoretical and simulated figures are discussed. The theoretical and simulation models form
a framework which may be used to evaluate the system under test conditions.
6.2 Theoretical Throughput
Since user address codes have been chosen for their orthogonality, it is assumed that each (CDMA)
channel's traffic may be regarded as independent in order to model individual channel throughput
characteristics.
The techniques used in the derivation of this throughput model are based upon those used by Kleinrock
and Tobagi [27]. In the development of this model the various assumptions are made. The assumptions
made by Kleinrock and Tobagi are included for convenience, to avoid constant reference back to their
paper, these are denoted by " >" and new or modified assumptions are denoted by "+"
Traffic sources, on a system and per channel basis, are regarded as Poisson sources with
a mean packet generation rate of X packets per second, i.e. independent and exponentially
distributed.
Chapter 6 Page 101
> Packets are of constant length of T seconds duration, such that the average number of
packets generated in this T second period is S = xT. Thus the input rate is normalised to the
transmission time T. S may then be called the Channel Throughput or Channel Utilisation.
The Offered Channel Traffic is denoted by G (where G > S). G is equal to the new traffic
plus the traffic requiring retransmission owing to some earlier collision.
X is the Mean Retransmission, or Back-off, time and is assumed large compared to T.
In this model non-persistent CSMA is used where, upon busy sensing and recognition the
transmitter will immediately back off an arbitrary time period X, and not continue to sense,
waiting for the channel to become free.
No positive acknowledgement scheme is incorporated, collisions being detected (in a finite
time T) by each station involved in the transmission of the colliding packets. After collision
detection, packet transmission will be continued for a further period T to jam the channel in
order to ensure that the other station(s) involved in the collision will actually detect it. The
time taken todetecttheactual collision plusthe jamming time is collectively called the collision
detection time. The ratio of the collision detection time T to the transmission time T is given
by a where a = T/T.
Busy Sensing is achieved in a period equal to the Collision Detection time a, where a is
normalised to T as shown above.
Propagation delays are negligible compared to T and are set to zero.
Chapter 6 Page 102
Let t be the arrival time, at a node, of a packet to be transmitted. The station will sense the channel for a
seconds and, sensing the channel free, will transmit immediately ie. at time (t -f- a), as shown in Figure 42.
* Another station obtaining a packet between t and (t + a) will sense the channel free and also transmit,
thus causing a collision. This period of a seconds is classified as the "Vulnerable Period", and if no other
station receives a packet for transmission in the period between t and (t -i- a), then the first's packet will
be successfully transmitted.
If (t + Y)isthetimeofarrivalofthelastpacket(whereO<Y< a), and (t+Y-i-a) is the time of transmission
of this packet, then at time (t+Y-i-2a) stations transmitting should have recognised the collision. Each
station will continue to transmit for a period of a seconds after collision detection, thus at time (t -i- Y + 3a)
all stations will have stopped transmitting. Since no transmissions are occurring during the first a seconds
of this period, while the first station is sensing the channel, the average duration of an unsuccessful
transmission is (Y-i-2a), and the duration of a successful transmission is equal to 1. The time when
transmissions are occurring is defined as that time when traffic is actually flowing and excludes the initial
sensing period. This transmission time, whether for a successful or an unsuccessful transmission, is called
the Transmission Period (TP) or Busy Period. Any period between two successive TPs is called an Idle
Period. A Busy Period followed by an Idle Period is called a Cycle. If B is the expected duration of a Busy
Period, and I the expected duration of an Idle period then the duration of a cycle would be B+I . Using
renewal theory, the average Channel Utilisation, S, may then be defined as
S = _U (24) B+i
* NOTE Upon commencement of transmission the busy sensing circuit is reset and re-activated as a collision detection circuit.
Chapter 6 Page 103
in 0) u u c
73 _o
Q_
75 CU O
u m g l/l cJ c c 1- 0)
3 h - CL
a •
Oi
o z d
*-- d -p > C3 L L-+
<Z d) X
l/l u 0) cJ
-P Q-d U c5
u +> in s_ Ot
-p u d i. d ^ U
c o
i5 o
t+Y+3a
t+Y+2a
t+Y+a
: :,: : " A' : . -t+Y A d •
^ T. . . .T . . . . t
E
c CJ L
I -
Oi c c
S
u OJ
(Li L 3 O)
Li_
Chapter 6 Page 104
U is the average time during a cycle that a channel is being used without conflict. U is given by the
probability that no other transmission occurs between t and (t-i-a) and therefore
U = e^® (25)
The average duration of an Idle Period, I, is simply 1/G , and the average duration of the Busy Period B
is given by
B = (Average unsuccessful time) * (Probability of an unsuccessful
transmission) -i- (Average successful time) * (Probability of a success
ful transmission)
The probability that the transmission will be successful (Ps) is equal to the probability that no other
transmissions occur between t and (t + a).
Ps = e-^°
B = (1-Ps)(Y + 2a) + (Ps)(1) (26)
The average value of Y, from Kleinrock and Tobagi [27], is given by
Chapter 6 Page 105
Y = a - (1 -e^Q) (27)
Substituting into equation (26) gives
,-aG , „-aG/^ „-aG B = 3a - (1 - e'^^) - 3ae-^^ + e"^^ + e-^^(1 - e'^^) (28)
Using the values for I, U and B and substituting into equation (26) gives
S = _U = Ge' Q (29) B +[ (3aG + (e-^°(2 -H G - 3aG - e^%)
Equation (29) above represents the throughput, S, in terms of the Offered Traffic, G, and the busy
sensing period, a. Figure 43 is a graph of S vs G, and the curves represent different values of a. These
cun/es show the expected characteristic shape with the throughput increasing as the offered traffic
increases until a breakpoint is reached. Above this point the probability of collisions occurring is such that
increasing the offered traffic actually causes a reduction in throughput as the channel capacity is
progressively taken up with more re-transmissions and less new traffic. It can be seen from Figure 43 that
the busy sensing time is a highly important parameter in the throughput model and that reducing the
sensing time causes the breakpoint in throughput to occur at higher levels of offered traffic. This point is
highlighted by the list of maximum throughput figures for each of these curves, which is included as Table
2. It shows that an increase in peak throughput corresponds to a decrease in the value of the vulnerable
period a. The table also includes the offered traffic at which the peak occurs.
Chapter 6 Page 106
Variation with Vulnerable Periotj "a"
(/)
a I a»
0 L I h
- - .001 Offere(i Traffic "G" (Log scale base 10)
.01 — .05 — .1 — .2 .5
Figure 43 Throughput vs Offered Traffic
Chapter 6 Page 107
Table 2 Peak Throughput as a Fu of Vulnerable Period
Vulnerable Period
a
0.500
0.200
0.100
0.050
0.010
0.001
Maximum Throughput
S
0.297
0.514
0.697
0.809
0.955
0.989
Offered Traffic
maxG
0.900
2.400
4.700
9.500
47.400
100.000
The throughput characteristics of this model are compared with those of some of the more familiar
multi-access protocols [27] in Figure 44. These curves are plotted using a value of a = 0.01, except for
the two Aloha protocols which are independent of a. In the Non-persistent and 1-persistent CSMA
models the value of a represents the propagation delay in the system, rather than a busy sensing period
as in this model, but in all three models a gives a representation of the vulnerable period for transmission
modelling purposes. These curves show the comparison between this system's model, which has been
developed for a LAN application, and other protocols (most noticably Aloha and Slotted Aloha) which
were not. Table 3 shows the peak throughput for each model represented in Figure 44. It shows that the
potential maximum throughput for this system is higher than that for the other systems which were
included for comparison purposes. The indication is that application specific protocols can offer
throughput advantage.
Chapter 6 Page 108
Vulnerable perio(j a = 0.01
\f]
+»
a I o» D 0 L I h
0,0 OA 0.8 1.2 1.6 2.0 2.4 2.8
Alo 0ffere(j Traffic "G" (Log base 10 scale)
SI Alo •—^ 1-P — Non-P This
Figure 44 Comparison of Throughput Characteristics
Chapter 6 Page 109
.T.?.'i?!.?.3...P?a.kTiiroughputa^ ^ Model
Vulnerable Period a = 0.010
System Model
Pure Aloha
Slotted Aloha
1-Persistent CSMA
Non-Persistent CSMA
This System Model
Maximum Throughput
S
0.184
0.368
0.529
0.815
0.955
Offered Traffic
maxG
0.500
1.000
1.000
9.400
47.400
63 Simulation of Throughput
A simple simulation of the CSMA protocol was developed in order to determine whether the theoretical
throughput characteristics illustrated in Figures 43 & 44 were realistic. The simulation model was based
on the work carried out by Rounds [28] for the National Aeronautics and Space Administration. The
simulation procedures Rounds adopted were designed to model the Non-Persistent CSMA protocol
described by Kleinrock and Tobagi [27]. The basic concepts are that the model generates traffic which
assumes a Poisson distribution in its arrival characteristics. The model then calculates the average
values:- U (channel Usage), B (channel Busy Time) and I (channel Idle Time). These values are then
used in the calculation of the simulated throughput using the formula shown in equation (24).
The mean packet generation rate \ results in a mean inter packet arrival time of 1/ X. The actual arrival
time is calculated to simulate Poisson distribution using a Pascal procedure written to emulate these
statistics. The implementation of this procedure is described in detail in Appendix F.
Chapter 6 Page 110
If the arrival time is less than the vulnerable period a then the packet is marked as a collision, and the Busy
Period set to the unsuccessful transmission period values (see Figure 42). If the arrival time is greater
than the Busy Period then the packet is successful and the Busy Period and Usage values set to the
successful transmission values (see Figure 42). The Idle period is then the difference between the busy
period and the arrival time of the latest packet. If a packet arrives after the vulnerable period but before
the Busy period has expired, then its busy sensing circuitry is assumed to detect that the channel is in
use and that packet is rejected, i.e. it causes neither a collision nor a successful transmission. This
simulates re-scheduling of the packet with a mean re-transmission delay, X, tending towards infinity. The
U, B and I values are then averaged before being used to calculate the Simulated Throughput, ST.
The specifications of Rounds' model had to be modified in orderto simulate the protocol described above
rather than the Non-Persistent protocol. Parameters relating to channel usage were modified and the
concepts relating to Propagation Delay altered to suit the Busy Sensing period implemented in the protocol
for this system. Rounds' program was completely redesigned to accomodate these changes and then
re-written in Pascal. This simple simulation program is included in Appendix D.
Table 4 shows the output of a typical simulation run. The figures produced represent the calculated values
of Theoretical Thoughput, TS, (calculated using the formula shown in Equation (18)), the Simulated
Throughput, ST, the Offered Traffic, G, in terms of traffic offered per packet transmission period (T), and
also the number of collisions detected, the number of packets arriving during channel busy periods and,
finally, the number of packets being successfully transmitted. The packets arriving during a channel busy
period are called "CLASHES", and are subject to the large re-scheduling delays discussed previously.
The busy period is set to a value of (1 + a) to represent the channel occupancy plus sensing time, thereby
ensuring the inter-packet gap necessary for this protocol. The program cycles through 50 iterations for
every offered traffic rate, so that the number of collisions represents collisions per 50 traffic packets offered.
Chapter 6 Page 111
I?.b!!B.4...Sirriulated^^
eoretical
0.091
0.166
0.284
0.441
0.495
0.658
0.818
0.888
0.910
0.919
0.902
0.886
0.865
0.841
0.841
0.781
Simulated
0.091
0.166
0.284
0.441
0.496
0.659
0.791
0.865
0.892
0.883
0.818
0.731
0.610
0.414
0.324
0.000
Offered
0.1
0.2
0.4
0.8
1
2
5
10
15
20
50
60
70
80
80
100
Collisions
0
0
0
0
0
0
0
0
0
0
16
33
36
47
46
50
Clashes
0
0
1
11
18
31
41
45
46
47
24
7
8
0
2
0
Successes
50
50
49
39
32
29
9
5
4
3
10
10
6
3
2
0
The Theoretical and Simulated throughput values are plotted against the Offered Traffic in Figure 45. It
can be seen that at low levels of offered traffic the Simulated and Theoretical values are very similar. The
simulated throughput tends to show signs of reaching a peak at much lower levels of offered traffic,
however, as the effects of collisions and packet rejection begin to accumulate. The reason for this
discrepency is that the theoretical model values are calculated using steady state conditions and mean
packet inter-arrival times whereas the simulated values attempt to take into consideration the potential for
"bursty" traffic, which is more realistic in practical local area networks.
Chapter 6 Page 112
Vulnerable Periocj = "a" = 0.0178
I/)
a I
0 L I h
0 . 9 -
0 .8 -
0 . 7 -
0 .6 -
0 .5 -
0.4
0 .3 -
0.2 H
0.1
• 0
0 1 — I — I — I — I — r
0 1 1 2 2 3
Offered Traffic "G" (Log scale base 10) 'heoretica! • ^ Simulated
Figure 45 Theoretical and Simulated Throughput
Chapter 6 Page 113
The number of collisions, C, is plotted against offered traffic, G, in Figure 46. It can be seen that there is
a direct linear relationship between traffic load and collisions. As the vulnerable period is relatively small
compared with the packet transmission period, collisions only become a problem at high offered traffic
rates. This Figure also includes a plot of the number of clashes, L, and the number of successfully delivered
packets, P.
The results of these theoretical calculations and simulations matched very well and provided some
extremely useful indicators about the level of performance which can be expected from this Local Area
Network. These models also gave a guide as to the type of tests to perform and the parameters to measure
when considering the throughput of this system, in order to gain confidence that the system hardware is
performing up to expectations.
Chapter 6 Page 114
50 Per 50 packets
n ID U C 0 L L 1 u u 0 0
L ID
E 3 Z
4 0 -
3 0 -
2 0 -
10
0
? f
M I
li
; I ^
i
\
\ \
\ \
\ k
\
1
\
1 i
Ki
\
\
/
/
/
/i /
/
/
\ /
\
\
\
i ^'A'
/
/
/ H
/i
J i
I /
/
/
/
J 1
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
I
0.1 0.4 1 5 15 50 70 80
1771 Collisions Of
A3 fered Traffic "G"
Clashes 2/2J Successes
Figure 46 Number of Collisions vs Offered Traffic
Chapter 6 Page 115
7 SOFTWARE AND SYSTEM TESTING
7.1 Summary
Since the operation of each node is determined by the program loaded into the control microprocessor,
and since it was necessary to modify and adapt the standard operational program to insert special test
functions, it was considered appropriate to describe the software and system testing in one integrated
chapter. This chapter, therfore, describes the node software, test layouts and procedures and the additions
made to the standard operational software to allow these tests to be carried out.
Appendix E is a listing of the control program, including throughput, performance, and testing
enhancements. The detail of the actual implementation may be seen in this commented listing. The
descriptions given in this chapter are intended to concentrate upon the logic behind the software and how
the software controls the hardware modules described in chapter 4.
7.2 Overview of Control Software
The primary functions of the control software are to:
control the node spread spectrum interface i.e. ISO level 1 (physical layer).
utilise the MC 6854 to fulfil the Data Link protocol ISO level 2.
Chapter 7 Page 116
73 Control of the Spread Spectrum Interface
The basic concept for the software is that everything is related to the time frame of a single 1200 Hz clock
pulse. During one such time period all functions relating to SS interface input/output, HDLC input/output
and Host or Test interface input/output must be serviced. With this as the prime directive no input can
be missed neither can any opportunity to transmit be missed. The whole system is, thus, designed on a
polling basis with every input or output being tested once and once only during each 1200 Hz clock pulse.
7J.1 Inputs
Tranmlssions intended for a particular node are modulated with the code for that particular receiver.
Because of propagation delays etc. the transmission may appear at the receiver anywhere within a 2 bit
window. The receiver must continuously scan across this window looking for such transmissions. The
first function of the software is to control the scanning of the receiver whilst it is looking for a valid signal.
This is done by issuing a 5 bit output signal, PBO to PB4 on VIA # 1 , to control the receiver sliding correlator.
The received signal is then modulated with the delayed locally generated signal and integrated over a
1024 chip bit period (ie. one 1200 Hz bit period). This value is sampled and held before being input to the
ADC 800. One ADC 800 is used and the input of Receiver Sample and Hold or Transmitter Sample and
Hold is selected using a single bit PB5 of VIA # 1 .
Since the Sample and Hold circuits track whilst the 1200 Hz clock is low and hold while it is logic 1 the
software waits until PA4 on VIA #2, ie. the 1200 Hz clock is a logic 1 (see also Figure 25, section 4.4.7).
The receiver signal is selected and a Start Conversion (SC) pulse sent to the ADC 800 using the CA2 output
of VIA #2. The End Of Conversion (EGG) signal from the ADC should occur in a maximum of 65.1 ms
(see section 4.4.7.). The software waits for this EOC response on the CA1 input of VIA #2 before reading
the converted value using PAO to PA7 of VIA # 1 .
Chapter 7 Page 117
It has been noted in the past that some 8 bit A/D converters occasionally fail to respond to a SC pulse.
For this reason an anti lock-out mechanism has been designed into the ADC read routine. When the SC
pulse is generated, timer 1 in VIA #2 is loaded with a value of 80 and instructed to decrement at a 1 MHz
rate. If the EOC pulse fails to arrive before the counter reaches 0 (i.e. 80 ms) a second SC pulse is
generated and the whole cycle repeated.
The input from the ADC is then checked to see if it is in the range allowed for valid signals. With magnitude
values ranging from 0 to 127 (the MSB being a sign bit) the range 0 to 15 is designated invalid as it could
be due to interference. The range 80 to 127 is designated as invalid as it can only have been generated
by colliding signals (see section 6.4). The range 16 to 79 is designated to represent valid signals. This
validation is achieved by means of a look-up table, so the various ranges can be modified to suit conditions
if necessary.
If the signal for this particular delay position is invalid no further action is taken and the delay counter
incremented for the next sample. If the bit is valid then the magnitude of the correlation peak is saved so
that the correlation characteristics can be examined. This is done so that the receiver may be automatically
tuned to lock onto the peak correlation delay position for reception of this transmission.
Once the correlation peak is found and the receiver locks-on, the scanning stops and each received data
bit is checked for validity as described above. Every single bit in a received message is validated in this
manner.
7.3.2 Outputs
When the transmitter section has a packet to transmit, the signal will be modulated with the code for the
intended recipient. This addess code is selected using a 3 bit address which selects one of 8 destination
addresses using PBS - PB7 of VIA #2.
Chapter 7 Page 118
Having selected the destination address, the first task is to scan the allowable 2 bit window for existing
signals with the same destination's address code. This is achieved in a similar manner to that described
for the receiver section but the transmitter sliding correlator delay is controlled using bits PBO - PB4 of
VIA #2. The ADC is then reset to look at the receiver sliding correlator. If no other transmissions are
detected after scanning across the 2 bit window, then the transmitter line driver is enabled using bit PB7
of VIA #1 and the transmitter sends a 64 data bit preamble prior to enabling the ADLC transmitter. This
ensures that any reciever will be guaranteed to be able to lock-on to the correlation peak of this
transmission before the ADLC sends its opening flag (see section 7.4.2.).
When the transmitter has detected a vacant channel and commenced its own transmission, the transmitter
sliding correlator is locked-on to the peak of the transmitters own signal and the transmitters output is
monitored to ensure that no other transmitter has commenced transmissions and has caused a signal
collision. Data validation is carried out as described in section 7,3.1. When a collision is detected the
transmitter sends a jamming signal so that every node can detect the collision. The actual protocols used,
in the event of a channel being identified as busy or a collision being detected, may require one of two
actions to be taken:
. Back off a random time which is long compared with the packet transmission period.
Back off a random time which is short compared with the packet transmission period.
Both have their relative merits and are discussed in the testing part of this chapter in sections 7.6 and 7.7.
In the absence of busy or collisions, at the end of the preamble transmission the ADLC transmitter is
re-programmed as a data transmitter and the ADLC transmitter control software activated.
Chapter 7 Page 119
7.4 ADLC Control
The "Data Link" protocol is essentially the High Level Data Link Control (HDLC). The message (or packet)
is defined in the following manner:-
i) Opening Flag (8 bits)
ii) Address Field (8 bits)
Hi) Control Field (8 bits)
iv) Data Field (up to 200 bytes of 8 bits/byte)
v) Cyclic Redundancy Check (CRC) (16 bits)
vi) Closing Flag (8 bits)
7.4.1 Receiver Control
Having established physical, logic level communications, with the receiver locked-on to the signal, the
ADLC (MC 6854) receiver section is reset and the recovered data signal routed to the ADLC for the next
level of protocol checking.
Chapter 7 Page 120
The receiver section of the ADLC checks the received data signal bit by bit looking for an opening flag.
The detection of an opening flag indicates the acquisition of data synchronisation. The 8 bits following
the flag is the address field. In conventional systems this is normally used to contain the destination
station's address, but since, in this system, the destination address is defined by the modulation code
used, this field is used to convey the identity of the originating node. The control field is normally used
to convey data link control information but, again, this is not necessary and is left vacant in this system.
The next field is the, variable length, data field which is set to a maximum of 200 bytes, for convenience,
in this system. Transfer of data into the "Last Data Address" of the ADLC causes a CRC of 16 bits to be
sent immediately after the last data byte. This CRC is then followed by a closing flag.
Detection of the closing flag at the receiver causes the previous 16 bits to be checked for CRC information
against the data accumulated for this packet. Verification of the CRC causes the ADLC to set its Frame
Valid status bit, othenA/ise the Error bit is set. All receiver status bits are tested and the results made
available for appropriate responses to be made by the next higher level of protocol.
Upon completion of a frame the software is in a position to cross check the Frame Valid status output
from the ADLC against the individual bit validation obtained from the bit level interface to the SS system.
This double level of checking may be used to convey added confidence in the integrity of the received
data.
Should the signal connection become broken, for some reason, or the transmitter detects a collision and
prematurely ceases transmissions then an abort signal will be received. This event is detected by the
system and the fact made available to the next level software for appropriate action to be taken.
Since this system is capable of simultaneous reception and transmission, communication between the
transmitter and receiver sections is essential. When the receiver has collected a new ADC value it looks
to see if there is a transmission in progress, and, if so, switches the ADC to accept a signal from the
Chapter 7 Page 121
Transmitter sliding correlator by setting bit A5 of VIA # 1 , in order to prepare the system to read from the
transmitter section.
7.4.2 Transmitter Control
On completion of the synchronisation preamble the ADLC transmitter is reset and the first byte of the
packet, ie. the originator's address, is loaded into the Frame Continue FIFO of the ADLC. This causes an
opening flag, followed by the address field information, to be sent. The status register is checked to
determine if the transmitter data register is empty. Each data bit transmitted is monitored, as previously
described, to ensure that colliding signals do not interfere with the transmission. Detection of a collision
results in the transmission of a jamming signal (which is the Abort signal), and resetting of the transmitter
section of the ADLC, followed by the re-start of transmitter scan procedures.
In the absence of collisions the final byte of the packet being sent is loaded into the Frame Terminate
address of the ADLC. Putting a data byte into this address, rather than the Frame Continue address,
causes the ADLC to automatically send a 16 bit CRC after the data, this is then followed by the transmission
of a closing flag.
When the whole packet has been successfully transmitted the ADLC transmitter is disabled and, if there
is another packet to be sent, the whole scan process re-started using the new destination's address code.
7.5 Connection Testing
The incorporation of the ADLC allows inter node communication testing to be conducted with relative
ease. With three stations (address codes $20, $40 and $60) node numbers # 1 , #2 and #3, the following
test was conducted. The node control software was modified slightly such that when a packet was
Chapter 7 Page 122
received, the originator's address was removed and replaced with the receiving node's address, the
packet was then transmitted to the third node such that a complete loop was formed. The instigator of
the loop counted the responses and stopped after 100 packets had passed round the loop. Passing the
same packet round the loop meant that the integrity of the data could be validated at each node.
The transmission time of a packet is made up of the following components:
i) A 32 bit channel occupancy scan
11) A 64 bit sync preamble
ii) An 8 bit opening flag
iv) 16 bits of address and control information
v) 200 bytes of 8 bits of data = 1600 bits
vi) 16 bits of CRC
vii) An 8 bit closing flag
The total number of bit periods required to send a packet is, therefore, 1744 bits, which at a data rate of
1200 Hz corresponds to a packet transmission time of 1.45 seconds. Since each packet needs three
Chapter 7 Page 123
transmissions to complete the loop and there are 100 packets, the total time for this test was 7 minutes
15 seconds. Repeating the test 10 times resulted in no errors being recorded at any of the three nodes.
7.6 Throughput Performance Testing
Whilst the results of the previous tests were excellent, these tests were not considered comprehensive
enough to qualify as system performance tests. It was decided to develop tests to attempt to measure
the individual channel throughput and compare the measured results with the theoretical and simulated
results described chapter 6.
7.6.1 Test Configuration and General Procedures
Three separate tests were carried out to verify the predicted performance characteristics. Figure 47 shows
the equipment configuration adopted during these tests, node #1 was designated the receiver, node #2
was the interference generator and node #3 was the traffic generator.
The value used for the packet transmission time was modified from that described in Section 7.5. The
reason for this is that the ADLC uses a bit oriented protocol to establish data transparency and this involves
the addition of logic zeros to ensure no data transmission replicates flag or abort signals etc. This "bit
stuffing" means that more bits will be sent than is absolutely warranted to represent the data. This is
obviously data dependent and so value of 1800 was used for the total number of bits per packet. This
represents only a 3.2% overhead on the absolute minimum value of 1744 quoted earlier, and was
considered quite reasonable. This value of 1800 then represents a packet time of 1.5 seconds.
The packet arrival times at the nodes is assumed to conform to Poisson distribution (see chapter 6). It
was, therefore, necessary to produce a random number generator which produces values with this
Chapter 7 Page 124
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particular distribution. The Poisson characteristic arrival times were then used for the traffic generator
(node #3). The interference generator, used only in tests #2 and #3, was included to represent the
accumulated potential traffic from other nodes which could be transmitting in the chosen channel. Since
an accumulation of Poisson events approximates to a Gaussian distribution of events, a Gaussian
distribution random number generator was also required to provide packet arrival data forthe interference
generator (node #2). A computer program which generates the required statistics was written, this
program is described and listed in Appendix F.
When a program such as this is run on a system like an IBM PC/AT there is a need to synchronise the
IBM to real world events. In the test configuration shown in Figure 47 this synchronisation is required to
achieve Poisson and/or Gaussian arrival characteristics and is obtained in the following manner :-
If each packet is regarded as 1800 bits long, then a packet arrival rate of G = 1 may be obtained by
counting 1800 at a rate of 1200 Hz.
Packet arrival times may then be normalised to a the packet transmision time by counting "n" clock pulses
at a rate of 1200 Hz ie. G = n/1800.
The value "n" is loaded into the T2 counter on VIA # 1 , this counter is then decremented by the 1200 Hz
data clock. When the count reaches zero, a stimulus is sent to the PC which then calculates
a) A Poisson distribution value
b) A Gaussian distribution value
Chapter 7 Page 126
both with a mean value of n/2.
These values are converted to Hexadecimal numbers and the Poisson number sent to node #3 and the
Gaussian number sent to node #2.
These numbers are loaded into the T2 counter of VIA #1 in the respective nodes, the counters being
decremented by the 1200 Hz data clock.
When the counter is decremented to zero it represents the "arrival" of a packet for transmission. These
"arrivals" are then subject to Poisson or Gaussian distribution characteristics at the rate of 'n' packets
per packet period, ie. these "arrivals" represent G, the "Offered Traffic".
In order to be able to determine the channel utilisation, it was then necessary to repeat the experiment
with different values of offered traffic and count the number of successful arrivals. To give repeatability
to the test procedure, a counter was used to interrupt node #1 after 256 seconds (this represents 170
packets). The number of successful arrivals, divided by 170, would then give the channel occupancy.
7.6.2 Test Results
Three separate tests were carried out in orderto develop a realistic idea of the system channel throughput.
7.6.2.1 Test#l Peak Channel Occupancy - no collisions
This test was designed to produce a figure which could be used as a target for peak channel
occupancy. No interference node was used in this test. Only the receiver, node # 1 , and the
traffic generator, node #3, were used. The transmitter was designed to operate using the
protocols described in section 6.2.
Chapter 7 Page 127
The pre-transmission channel scan period is 32 bits (ie. "a" = 32/1800 = 0.018)
Table 5 shows the results for this test. For each value of offered traffic the test was run 3 times
and the resultant number of arrivals is the average of these 3 runs. The channel occupancy is
calculated from the number of arrivals divided by the channel capacity (ie. 170 packets per test
run).
Table 5 Measured Peak Th^ ^
Theoretical
Traffic "G"
0.1
0.2
0.4
0.8
1.0
2.0
5.0
10.0
15.0
20.0
Delivered
Packets
17
34
59
75
89
113
141
146
150
152
LogioG
0.000
0.301
0.602
0.903
1.000
1.301
1.699
2.000
2.176
2.301
Throughput "S"
= Delivered/170
0.100
0.200
0.347
0.441
0.524
0.665
0.829
0.859
0.882
0.894
Figure 48 is a graph of the results of these tests. It can be seen, by comparing this graph with
Figure 45, that the peak channel occupancy is around 89%. This figure is actually dependent on
the mean inter-arrival period, since packets arriving while the channel is still occupied with exisiting
traffic are re-scheduled with a very long back off time, X (ie. tending to infinity for the purpose of
Chapter 7 Page 128
Test1 No Interference
(/)
a I a> D 0 L £ h
0.000 0.602 1.000 1.699 2.176
Offered Traffic "G" (Log scale base 10)
Figure 48 System Throughput - No Interference
Chapter 7 Page 129
these tests). Only packets which arrive when the channel is not actually occupied are accepted
for transmission, thus, if the mean inter-arrival time is large the channel could wait, unoccupied,
for a packet to transmit. With an offered traffic rate of 20, therefore, the channel could be
unoccupied for up to 5% of a packet period, waiting for a new packet to transmit. Under these
circumstances a peak channel occupancy in the order of 90% is not unreasonable. This figure
will then represent a guide to the channel occupancy in the presence of interfering traffic and will
also serve as a measure of the contention handling characteristics of the system.
7.6.2.2 Test #2 Throughput - vyith collisions
The parameters and protocols for this test are very similar to those used in test # 1 . This test
uses, however, both the Traffic and Interference generators shown in Figure 47. The presence
of the two packet generators means that collisions will occur, the packet arrival rate, representing
the offered traffic. The number of successful arrivals was counted at various offered traffic rates.
Table 6 shows the results of these measurements, and Figure 49 shows a graph of the results. It
can be seen that, the channel throughput increases uniformly with offered traffic until the effects
of collisions and re-scheduling begin to take effect. The peak channel throughput of approximately
78% occurs at an offered traffic rate of 5 packets per packet slot. Below this rate the inter-arrival
period is largely responsible for the non-utilised time between successive packets, and thus the
lower throughput. Above this rate the probability of the arrivals being in the vulnerable period,
thus causing collisions, begins to rise, and more of the channel time is occupied with
pre-transmission scanning and channel jamming caused by transmissions. At offered traffic rates
above 5 packets per slot, therefore, the throughput falls noticeably.
Chapter 7 Page 130
I.3b!e.6 Measured T^ ^
Theoretical
Traffic "G"
0.1
0.2
0.4
0.8
1.0
2.0
5.0
10.0
15.0
20.0
Delivered
Packets
17
33
49
80
90
125
131
123
100
69
LogioG
0.000
0.301
0.602
0.903
1.000
1.301
1.699
2.000
2.176
2.301
Throughput "S"
= Delivered/170
0.100
0.194
0.288
0.471
0.529
0.735
0.771
0.724
0.588
0.406
These characteristics follow the trends predicted in the Theoretical Model (see Figure 43) and in
the Simulation Model (see Figure 45), although the break point in both the simulation and
theoretical models occurs at higher rates of offered traffic. These results demonstrate the validity
of the models described in chapter 6.
7.6.2.3 Test #3 Short (Pseudo random) Re-scheduling Times
Because of the limitations highlighted by the preceding tests it was decided to investigate an
alternative protocol, with a view to increasing the peak throughput and maintaining this peak level.
The test procedures were the same as those described for test #2, above. The alternative takes
the form of drastically reducing the re-scheduling time to a random value in the range 1 to 255
bits. For this reason a pseudo random number generator, taking the form of an 8 bit MLS, was
included in the control software. Each transmitter loads the MLS generator with a different seed
value, to ensure variation between transmitters. The MLS is "clocked" once every polling cycle.
Chapter 7 Page 131
in
3 a I
0 L I h
0.8
0.7
0 . 6 -
0 .5 -
0 .4 -
0 . 3 -
0 . 2 -
0.1
Test 2 With Interference Generator
0.000 0.903 1.699 2.301
Offeree] Traffic "G" (Log scale base 10)
Figure 49 System Throughput - With Interference Generator
Chapter 7 Page 132
When a new packet arrives, if the channel is vacant the T2 counter is loaded with the Poisson or
Gaussian value, as previously described, and this packet is transmitted when the counter is
decremented to zero. If a collision then occurs, each station jams the channel and loads a backoff
counter from its MLS generator and waits this time before attempting to re-transmit the packet.
If a new arrival occurs while there is already a packet(s) either in the process of being transmitted
or awaiting transmission, then it is merely stacked in order that it can be transmitted as soon as
possible after the last packet has completed transmission.
If a node is in the process of transmitting a packet and already has another stacked then the node
will start the pre-transmission scan (ie. commence the transmission procedure) one bit after the
last packet has ended. If, however, node #2 is already transmitting and node #3 has a packet
awaiting transmission, then node #3 will be already subject to the small random backoff
procedures described above and will continue this process whilst attempting to send its packet.
This does not preclude collisions, as the backoff time may expire during node #2's vulnerable
period of its attempt to transmit the second packet. If a collision then results, both nodes will
revert to the small random backoff protocol.
This system is therefore a mixture of a "1-persistent" and an "n-persistent" protocol [27]. No
packets are lost, nor are any subjected to long re-schedule backoff counts and finally packets
are transmitted in order of their arrival.
Table 7 shows the results of the tests carried out to determine the efficiency of this protocol.
Figure 50 shows a graph of the values obtained from these tests. In this graph a linear scale is
used forthe "Offered Traffic", G, axis rather than the more usual LogioG axis used by Kleinrock
and Tobagi [27] and followed in the earlier part of this thesis. This allows a linear relationship
between S and G to be identified more readily. It can be seen, from Figure 50, that the throughput,
8, increases uniformly up to an offered traffic rate, G, of approximately 0.8 packets per packet
Chapter 7 Page 133
I/)
+» 3 a I a> 3 0 L I h
0.9
0.8
0.7 H
0 . 6 -
0.5 H
0.4
0.3 H
0 . 2 -
0.1
0.1
Test 3 Small Randonn Rescheduling
0.3 0.5 0.7 0.9 1.1
iipii Offered Traffic "G
Figure 50 System Throughput - Alternative Protocol (small random rescheduling)
Chapter 7 Page 134
I.?. !e 7 Altematiye Pr ^
Theoretical
Traffic "G"
0.1
0.2
0.4
0.8
0.818
0.837
0.857
0.878
0.9
0.923
0.947
0.973
1.028
1.059
1.091
Delivered
Packets
17
34
68
136
139
142
145
146
145
147
144
145
145
145
144
Throughput "S"
= Delivered/170
0.100
0.200
0.400
0.800
0.818
0.835
0.853
0.859
0.853
0.865
0.847
0.853
0.853
0.853
0.847
slot. Storing packets whilst awaiting channel availability, rather than subjecting them to large
re-scheduling delays, means that up to this rate every packet offered was actually transmitted
during the test period.
A peak value of approximately 0.86 was obtained at an offered traffic rate of the same order. This
throughput rate was then maintained, with further increases in offered traffic rate, rather than
Chapter 7 Page 135
suffering the decrease of the previous protocol, as illustrated in Figure 49 above. The cost of the
maintenance of the throughput rate was an increase in the number of packets being held at the
node awaiting transmission into the network. This means that the node requires significant storage
for these "delayed" packets.
7.7 Analysis of System Performance
Section 7.5 described the basic system connection testing. Node #1 transmitted to node #2 which
transmitted to node #3 which completed the loop by transmitting to node # 1 . 100 packets were
transmitted, each of which required 3 transmissions to complete the loop. Each packet was checked for
errors whenever it was received, and none were found. This procedure was carried out 10 times, resulting
in a total of 3000 separate transmissions taking place without error. This showed that the address code
selection, modulation, demodulation and data recovery circuits were performing as expected; and that
the HDLC synchronisation and clock recovery was being achieved satisfactorily.
After confirming the correct operation of the hardware the next step was to investigate the system's
performance characteristics. The three measures of system throughput or traffic handling performance
follow very closely the characteristics predicted in the theoretical and simulation studies carried out, and
described in chapter 6. This verifies the validity of the models developed. The excellent traffic handling
characteristics exhibited by the hardware (and software) confirm the suitability of the system to meet the
initial design aims. ie. to provide simultaneous multiple access facilities. The flexibility of the system is also
demonstrated in the fact that with the relatively simple modifications to the system software, outlined in
section 7.6.2.3., an alternative protocol could be investigated.
Overall these tests have verified and quantified the system's performance characteristics. The system has
performed as predicted by both the theoretical and simulation studies carried out for this purpose. These
tests verify that the system, as built, actually meets all of the original design criteria.
Chapter 7 Page 136
8 CONCLUSIONS
8.1 Discussion of the Project
In the preceding chapters it has been shown that it is a practical proposition to implement a Local Area
Network using Spread Spectrum techniques. The network produced has been designed with commonly
available components and proven, by exhaustive testing, to be both reliable and resistant to electrical
interference. This makes the network particularly useful in areas which, hitherto, have been considered
unsuitable for the installation of a LAN either because it wasn't cost effective or the environment in which
the l_AN would be expected to work was considered too hostile.
The channel address codes, used in a Code Division Multiple Access system such as this, are of paramount
importance, and 5 code allocation schemes were considered before a selection was made. The first 3 of
the schemes considered were suitable for asynchronous systems, and the latter 2 for synchronised
systems.
The suitability of the codes in the address allocation scheme selected was demonstrated practically. The
expectations about the shape and magnitude of the correlation values across the 2 bit window were also
confirmed by actual hardware measurements (Figures 35 to 41). This allowed significant modularity in
hardware design and testing, thus ensuring that validated modules could be assembled to form the final
system. The use of a Read Only Memory to store the synchronisation and address codes, meant that the
act of synchronising automatically created other codes in the correct phases to be used directly as address
codes. The creation of a discrete stepped sliding correlator meant that it was possible to use the
microprocessor control circuit to exercise direct control over the delay in this correlator, so that the
optimum decoding delay could be used.
Chapter 8 Page 137
The theoretical studies showed how the throughput could be expected to change with different values of
vulnerable period, a (Figure 43). The theoretical throughput model developed in Chapter 6 shows
significant throughput advantages over Aloha, Slotted Aloha and also the 1 -persistent and non-persistent
CSMA models. Figure 44 shows how, at a vulnerable period of a = 0.01, the throughput of this system
compares with that of the multiple access protocols noted above. The simulation results supported those
predicted by the theoretical work, and Figure 45 shows how the theoretical and simulated throughputs
compare at a vulnerable period value of a = 0.0178. The theoretical and simulation studies were extremely
valuable in that they provided a guideline against which the hardware could be compared; and these three
sets of results were, in fact, used to predict the expected performance of the hardware.
The vulnerable period in the system is determined by the time taken to perform the pre-transmission scan,
divided by the time taken to transmit a packet (ie. a = 32/1800). As explained in section 7.6.2.1, the peak
channel occupancy, 90%, is a function of the throughput test calculation methods. This peak value,
illustrated in Figure 48, is, therefore, the maximum against which the throughput with interference should
be measured. Having measured the performance under ideal conditions, the throughput characteristics
under "normal" conditions (ie. with more than one transmitter) were measured and compared with those
predicted. The measured and predicted results were again very close, as can be seen from Figure 49,
which shows how the throughput varies with an increase in the offered traffic rate, when the interference
increases in the same proportion. A very high level of confidence may be placed in the accuracy of the
measured throughput, as it compares very well with that predicted from both the theoretical and
simulation studies. This can be seen by comparing Figure 49 with Figure 45.
Having demonstrated the performance of the system, its flexibility was investigated, and Figure 50 shows
the throughput when the system was re-programmed to perform a slightly different protocol; one where
packets are stored for re-transmission rather than being subjected to a "very long" re-scheduling delay.
This protocol attempts to make more efficient use of the channel capacity by re-initiating the transmission
process, if there is a stored packet available, as soon as the previous transmission has been completed.
The peak throughput obtained with this protocol is 86%. This value compares well with the peak values
of 88%, predicted by the simulation studies, and 91%, predicted by the theoretical studies (Figure 45).
Chapter 8 Page 138
The number of packets retained at each node for transmission, however, grew with each increase in
offered traffic rate.
The points in favour of this protocol are:-
a high channel occupancy value is achieveable
the rate is maintainable
packets are transmitted in the order of arrival
The major disadvantage is that large amounts of primary memory (or secondary memory such as disk)
would be required to support the protocol with very high levels of offered traffic.
This implementation of an alternative protocol demonstrates the flexibility of the system. This is an
additional point in favour of this SS LAN, in that it may quite easily be tailored to meet the specific
conditions under which it may be expected to operate. The protocol developed and simulated in chapter
6, and tested in section 7.6.2.2, is probably more appropriate to systems where the anticipated traffic rate
is significantly below the breakpoint of 5 packets per traffic slot. Very little extra storage is required at each
node to implement this protocol. If, however, the system may be expected to be subjected to periods
where the offered traffic rate exceeds the breakpoint value of 5, then the alternative protocol, section
7.6.2.3, provides marginally higher throughput, because of the fewer collisions and re-schedulings. This
is achieved, however, at the cost of the extra storage which is required at each node.
Chapter 8 Page 139
During the course of this research project a Local Area Network using Spread Spectrum techniques has
been designed, built and tested. Individual module, and total system, perfonnance characteristics have
been theoretically estimated, simulated and then actually measured. Additional investigations which
demonstrate the system's flexibility have also been undertaken. This research project has, therefore, been
a complete success, and each of the design goals, identified in section 2.2, has been met.
8.2 Comparisons With Other Networks
The relative advantages or disadvantages of this system compared with other, more conventional,
CSMA/CD type LANs depends very much on the user's requirements and the conditions under which the
system will be used. The following discussion attempts to identify certain important operating conditions
and compare the two systems under these conditions, each assumes a user population of 100 :-
. If one node is dominant and the other 99 nodes all communicate with this one, eg. a file server, then
the conventional system is far superior. The SS LAN is designed for equi-probable multi-user
communications, ie. 50 pairs of nodes communicating concurrently.
A CSMA/CD bus shows its best performance for loads less than 0.2, the transfer delay increases rather
rapidly for loads greater than 0.4 and has a vertical asymptote at about 0.6 [29]. If the load is spread
evenly over 50 channels, then one would expect the overall SS load capacity to be 50 times that of a
conventional l_AN before delay becomes an important factor.
• The SS LAN can find and maintain synchronisation in an environment with 7% errors at the chip bit
rate (section 4.4.3.1). A 7% deviation from the correlation value of 64 expected from the A/D converter,
would result in a value between 56 and 70. These values are well within the range allowed (section
7.3.1), and would not cause incorrect data recovery and subsequent packet rejection. Errors in a
conventional l_AN could cause packet rejection.
Chapter 8 Page 140
A very reliable method of ensuring packet integrity is the use of error detecting codes and positive
acknowledgement of each packet received correctly [30]. The acknowledgement packets would,
however, be competing for channel space and could exacerbate loading problems in a conventional
LAN. The SS LAN already incorporates error detecting coding in the ADLC, and positive
acknowledgement does not cause a loading problem in the SS l_AN, since the pair of communicating
nodes each have a unique receive channel.
In a conventional LAN the vulnerable period is determined by the maximum propagation delay in the
system. The SS LAN has its vulnerable period, a, set to a value of 0.018 (section 7.6.2.1). Using a
propagation delay factor of 5 us / Km [29], a conventional LAN operating at 10 MHz would be able
to serve a network upto 650 metres in length. The SS LAN's vulnerable period is determined by the
channel scan time and, with a 2 bit separation between codes, this equates to a network of 488 metres
(section 3.3). So for the same value of vulnerable period the conventional LAN can service a longer
network.
• A cost comparison between the SS LAN and commercially available components is not absolute,
since profit and a component to cover development costs and company overheads are already
included in the price of bought items. Commercial l-AN cards vary considerably in cost, depending
on the facilities offered and the degree of inteligence in the card. The CMC ENP-66 costs $1380, and
is towards the top of the price range. The Ungermann Bass PC NIU AT costs $954, and is a mid-valued
item. The Micom Interlan NI5210-8 costs around $467, and is towards the economy end of the market.
A SS l_AN node could be made for under $200, so with profit and development cost components etc.
should be competitive with the Micom Interlan product.
Various manufacturers now offer LAN controller chips as microprocessor peripheral devices. Intel's
82586 Local Area Network Co-Processor costs $134 and AMD's AM77990 Local Area Network
Controller for Ethernet (LANCE) costs $68. The SS LAN card would cost more than these individual
chip controllers.
Chapter 8 Page 141
83 Suggestions for Future Work
During the development of this Spread Spectrum LAN, some areas have been identified which may be
suitable for enhancement in future:-
a reduction in the number of Integrated Circuits (ICs) in the control circuits could be achieved by
using a single chip microprocessor
• an improvement in processing potential is available by using a more modern 8 bit microprocessor,
such as the Motorola MC68008. An even more substantial improvement could, obviously, be achieved
with a MC68020 or MC68030 device
throughout this development, the decision to use standard commercial components has meant that
custom ICs have not been considered. The very recent introduction of re-programmable Application
Specific Integrated Circuits (ASICs) means that these devices may be cost effective and, therefore,
suitable for the replacement of a substantial amount of the digital logic in this system
the possible development of ASICs with analogue functions may mean that both the analogue and
digital chip count could be significantly reduced by using such devices, this would also reduce printed
circuit complexity and, hence, production costs
A/D converters with built in multiplexers, S/H circuits, etc., are now available. The use of such devices
would allow simultaneous monitoring of many channels to be performed
Chapter 8 Page 142
code generation using Random Access Memories (RAM) in conjunction with the ROM already used,
would allow dynamic channel address code allocation within the system. This may give wider appeal
to a system of this nature.
• one aspect of system design which could be further investigated is the incorporation of adaptive
transmission and reception sections. The system as it is now can be manually adapted to suit the
number of users in certain ranges eg. up to 10, or 20 to 40 etc. by tuning the "unit" voltage setting and
the analogue multiplier scale factor. This is static tuning and the system still has a limitation in its
dynamic range. The inclusion of adaptive control units in each node to sense the number of concurrent
users and dynamically adjust the "unit' and scale settings could overcome this limitation. This control
unit could also adjust the scale setting to cater for possible variations in the attenuation experienced
by transmissions from different nodes.
The incorporation of the above suggestions for future work into this, already working, system could only
enhance its market potential by making it cheaper to assemble and possibly more reliable, whilst at the
same time giving it performance improvements to increase its appeal to potential users.
Chapter 8 Page 143
Bibhography
1 SIMCOCK A.L., naRANONG C. and LEUNG P., "A Synchronised Spread Spectrum
Local Area Network", The Journal of The Institution of Electronic and Radio En
gineers, pp 17-21, Vol 57 No. 1 January/February 1987.
2 SCHOLTZ R.A., 'The Origins of Spread Spectrum Communications", I.E.E.E. Transac
tions on Communications, pp. 822-854, Vol. COM-30, No 5, May 1982.
MAHMOOD N., "Spread Spectrum Communication System For Civil Use", Wireless
World, pp. 76-80, March 1983.
SKAUG R. and HJELMSTAD J.F., "Spread Spectrum in Communication", Peter
Peringrinus (London), 1985.
PICKHOLTZ R.L, SCHILLING D.L, MILSTEIN LB., 'Theory of Spread Spectrum Com
munications - A Tutorial", I.E.E.E. Transactions on Communications, pp. 855-884,
Vol. COM-30, May 1982.
naRANONG C, SIMCOCK A.L. and LEUNG P. "A Spread Spectrum Manufacturing In
formation Network", The Third Annual Conference on Manufacturing Engineering -
Technology For Manufacturing Growth pp 118-122 Newcastle 1986
Bibliography Page 144
7 SIMCOCK A.L., naRANONG C. and LEUNG P., "A Spread Spectrum Manufacturing In
formation Network", College of Mechanical Engineering Technical Report, pp 1-5,
August 1987.
SIMCOCK A.L, naRANONG C. and LEUNG P., "Protection, Rejection and Throughput
Characteristics of a Spread Spectrum Local Area Network" Conference on Com
puting Systems and Information Technology 1987, pp 146-150, Brisbane,
Queensland June 1987.
9 SCHOLTZ R.A., "The Spread Spectrum Concept', I.E.E.E. Transactions on Communica
tions, pp 748-755, Vol. COM-25, August 1977.
10 PURSLEYM.B., "Spread-Spectrum Multiple Access Communications", - chapter in
"Multi-User Communications Systems", LongoG. (ED), 1981.
11 SIMCOCK A.L., naRANONG C. and LEUNG P., "A Localised Spread Spectrum Net
work" The Journal of Electrical and Electronic Engineers, Australia, pp 110-116,
Vol. 7, No. 2, June 1987.
12 DIXON R.C., "Spread Spectrum Systems", Wiley (New York), 1976.
13 SMYTHE C.S. and SPRACKLEN C.T., "A High Speed Local Area Network Using Spread-
spectrum Code-division-multiple-access Techniques", The Radio and Electronic
Engineer, pp 225-226, Vol. 54, May 1984.
Bibliography Page 145
14 ELHAKEEM A.K., HAFEZ H.M. and MAHMOUD S.A., "Spread-Spectrum Access to
Mixed Voice-Data Local Area Networks", I.E.E.E. Journal on Selected Areas in
Communication, pp 1054-1069, Vol. SAC-1, No. 6, December 1983..
15 PFIEFFER P. and MEYRUEIS P., "Fiber Optic Bus with Spread Spectrum Techniques",
Proceeding S.P.I.E. Int. Soc. Opt. Eng. (USA), pp 20-23, Vol. 434,1983.
16 HIROSAKI B., HASEGAWA S., SAWAI A., "Spread Spectrum Multiple Access Data
Loop", NEC Res DEV n71 pp 48-58, October 1983.
17 SPRACKLEN. C.T., SMYTHE C, SCOTT M.A. and ISMAIL N.A., "Spreadnet - A Spread
Spectrum Local Area Network", Journal of the Institution of Electronic and Radio
Engineers, pp 12-16, Vol 57, No 1. January/February 1987.
18 CARLSON BRUCE A., "Communication Systems -An Introduction to Signals and Noise
in Electrical Communication", McGraw-Hill, (Tokyo), 1981.
19 PETERSON W.W. and WELDON E.J., "Error Correcting Codes 2nd Edition", M.I.T.
Press (Cambridge, MA), 1972.
20 SARWATE D.V. and PURSLEY M.B., "Cross Correlation Properties of Pseudo- Random
and Related Sequences", Proc. I.E.E.E., pp 593-619, Vol. 69, May 1980.
21 CHORAFAS D.N., "Designing and Implementing Local Area Networks", McGraw-Hill
(New York), 1984.
Bibliography Page 146
22 HOPPER A., 'The Cambridge Ring - A Local Network", Advanced Techniques for
Microprocessor Systems, Hanna F.K. (ED), pp 67-71, Perigrinus (Stevenage,
Herts), 1980.
23 SIMCOCK A.L., naRANONG C. and LEUNG P., "Spread Spectrum Techniques for
LAN Interconnections" A.T.E.R.B. Workshop on LANs 1987, pp 34-38 Leura,
N.S.W. March 1987.
24 LINDHOLM J.H., "An Analysis of the Pseudo-Randomness Properties of Subsequen
ces of Long m-Sequences", I.E.E.E., Transactions on Information Theory, pp 569-
576, Vol. IT-14, July 1968.
25 GOLD R., "Optimal Binary Sequences For Spread Spectrum Multiplexing", I.E.E., Trans
actions on Information Theory, pp 619-621, Vol. IT-13,1967.
26 Motorola MC6854 Data Sheet.
27 KLEINROCK L and TOBAGI F.A., "Packet Switching in Radio Channels : Part 1 ", IEEE
Transactions on Communications, pp 1400-1416, Vol COM-23, December 1975.
28 ROUNDS F.N., "Use Modeling Techniques to Estimate Local-Net Success", E.D.N., pp
143-150, April 1983.
29 BUX W., "Local-Area Networks: A Performance Comparison", IEEE Transactions on
Communications, pp 1465-1473, Vol COM-29, No 10, October 1981.
Bibliography Page 147
30 TOBAGI F.A., "Multiaccess Protocols in Packet Communication Systems", IEEE Trans
actions on Communications, pp 468-488, Vol COM-28, No 4, April 1980.
31 GRAYBEAL W. and POOCH U.W., "Simulation Principles and Methods", Little, Brown
and Company, (Canada), 1980.
Bibliography Page 148
APPENDIX A
Appendix A Page 149
A CIRCUIT DIAGRAJMS
A.1 Summary
This appendix contains the full circuit diagrams (Figures Al to A5) for the Microprocessor and Peripheral
boards which together constitute a Node of this Spread Spectrum Local Area Network.
Appendix A Page 150
XTLl 4t«Z/.L7e00
D 3 , _
\Q M US 3
MAPPING CF
RAM -
ACIAl
ACIAH
VlAl
V1A2
ROM "
ADLC
US -
- Ull
- uia
U15
U14-
UB -
- COQO
BOARD -
QOOO-IFTF
- 4000
- eaaa - BOOQ
- AQUQ
EOaO-PFFF
ANALOG SECTION
THIS ADLC I.e. IS SHOWN HERE
FOR LQCIC CQM=l.ErENESS Ot-Y.
IT IS PHYSICALLY LOCATED
ON THE TRAN911TTEH BOARD.
.1: *CC , I TX(L___„
HT5 CT5'
RXO DCD
RXC CTDTRi
a»*IECTS TO flCCOCK CF T H A N a H T T E R BOARD lUlS PIN 91
SIGNAL COhMECTIONS FOR
ADLC ON TRANSMITTER
aOARO fVIA EUROCARD EDGE
CONNELTOH).
_^ Tcc sa
., TCC BI
,^ TCC sa
• TCC 19
t TCC 18
_ , TCC 17
-^ TCC 16
TCC 1S/«L12100 3B
, TCC 2+
, TCC 23
FIGURE A l MICROPROCESSOR BOARD (M) SHEET 1 OF E
VIPAQ V1PA2 V1PA+ VIPAE VIPBO VlPBa viPB*
FIGURE A2 MICROPROCESSOR BOARD IM) SHEET 2 OF 2
BYPASS CAPACITORS
AS- AST- lav o •SV 5 AS-
T T T UUUUT
' LCA 31
LCB 31
LCC 31
1
LCA 1
LCB 1
LCC 1
LCA a
LCB a
LCC S
i i
LCA 28
LCB 58
LCC as
LCA 3a
LCB sa
LCC 3a
1 1
LCA 3o/*Liaioo sa
LCB 30/*Liaioo se
LCC 3Q/*LiaiQ0 X
GND VCC V uaa /.fC68S4
VEE
CLR
U4a-A /.»«74LS74A
FIGURE A3 PERIPHERAL BOARD (P) SHEET 1 OP 3
i S P
U3 /.SN74LS1G4
mj'. rrr
&5L & n n
U4 /.SN74LS1B4
4 3 2 1 11514 13.13. — 1 1 ik ik 11 1 1 — m ik ik
M3i?
Ul /.SN74S133 US /.SN74LS30
5 P US /.SN74LS1B4
-« K »—• » -^ 1312 1110 6 rs
IS 116 5 4 3 aTl « 11—i—ik—li—ik—i
TT
U17 /.SN74LS374
U12-A /.SN74LS32
U9-F /.SN74LS04 r t
U12-C /.SN74LS32 U8 /.SN74LS1B1A
U3-E /.SN74LS04 3
UIB /.SN74LS251
10 BIT COUNTER
U13 /.SN74LS1G1A
14
13 Al
il2 A2
11 . A-q
.—t-CK
CLR
ENP
ENT
U14 /.SN74LSiBlA
3
*•' C
'i D
LD
CK
CLR
ENP
Al-e A4 A 3 _ B A 5
J,lg p AS 1 1 ^ A7
15
U15 /.SN74LS1B1A
3 l l f A 4-3
c t D
LD
<>CK
CLR
"1 ENP
ENT
°B Qc
°D
RCOJi
All
AlO
fA9
A8
A7
AG
PP y^'
UIB / .2732
C Qc
"^D Qp
LD
CK RCO
CLR
f ENP
ENT
C
f D
LD
>CK
CLR
ENP
ENT
TCA 15
t TCA 13
t
U9-D /.SN74LS04 U19-A /.SN74LS8B
U9-C /.SN74LS04 U19-B /.SN74LSBB
CLOCK JL
14 j3 Ull-B /.SN74LS08
12
11
UIO /.SN74LS1B1A
PR
0 Q
U7-A /.SN74LS74A
U12-B /.SN74LS32
Ull-A /.SN74LS08 U9-B /.SN74LS04
Ull-C /.SN74LS08 9
TDl
CLOCK
Ull-D /.SN74LS08 12 r—
'{>' U9-A /.SN74LS04
UB-A /.SN74LS74A UB-B /.SN74LS74A U19-C /.SN74LSBS
DCLQCK
TCA 9
DCLDCK
.. IN/OUT SYNC
FIGURE A4 PERIPHERAL BOARD (P) SHEET B OF 3 (SEE ALSO FIGURE 18)
+ 12V
TRia 2N3904
K
CD
cr R49
FIGURE A5 PERIPHERAL BOARD (P) SHEET 3 OF 3 (SEE ALSO FIGURE 24
APPENDIX B
Appendix B ' Page 156
B ERROR GENERATOR
B.l Summary
This appendix describes tine design and extensive testing of tlie programmable error generator designed
especially for this project. In common with the rest of this document the description is at block diagram
or functional level rather than at detailed chip implementation level. Complete circuit diagrams are,
however, included for reference.
B.2 The Requirements
The question of proving the eventual design of the Spread Spectrum LAN was considered from the very
early stages of development. The system had to be capable of maintaining communications even in an
electrically hostile environment. It was realised, therefore, that some means must be available to create
or simulate this type of environment in order to validate the system design. It would be necessary to inject
errors at the chip rate (of 1.2288 MHz) in order to test the synchronisation acquisition and maintenance
circuits, and also to investigate the correlation and integration processes in the receiver circuits. It would
also be necessary to inject errors in the 1200 Hz data signals, to test the data validation protocols and
any Automatic Request for Re-transmission or Acknowledgement features built into the network node
receivers.
Standard "white" or "pinit" noise generators were available as were some digital error generators but none
offered the facility to inject digital errors into data signals operating in the 1.5 IVIHz region, nor could they
be synchronised to several different data frequencies. Since no commercial equipment was available with
the required facilities, it was decided to construct one as a special piece of test equipment for the project.
Appendix B Page 157
The design parameters for the error generator are as follows:-
Programmable between 1 x 10"® and 9 x 10'
Synchronised to external data sources at up to 1.5 MHz.
Gaussian Distribution.
Error distribution constant over range of data input frequencies.
Seperate Error and Data + Error signals.
Transparent mode for data (ie. no errors injected).
B3 Circuit Description
Figure B1 shows the block diagram layout of this circuit. The basis of operation of the error generator is
that two 24 bit binary numbers "A" and "B" are compared with each other and an error generated if "B"
is greater than "A". The number "A" is generated by a pseudo random sequence generator, block 1 in
Figure B1. In this case a 31 stage Maximal Length Sequence generator producing a range of possible
values between 1 and 2^^-1, ie. 1 and 2,147,483,647. Of the 31 output stages,24 are actually used for
comparison purposes. This gives a range of values between 1 and 16,777,215. This MLS generator is
clocked by a high speed clock (block 2), the frequency of which must be at least 24 times the data rate
required. With the chip sequence data rate of 1.2288 MHz, therefore, the high speed clock rate f H, must
Appendix B Page 158
00
\ L 0;
-P c 3
L dj
75
ivI
o n u
U O £ 73 O C 375 dJ
L O •P
c
LD
OJ
T3 L
O pq
-p c
0 Q . X
U
L CU
-P
Ld
> , d
a in 00
n o3
L O
-P c3
Ol c (U
LD
L O L L
U
<4-
o
L CD c5
U O m
m Ol L 3 O)
l l
Appendix B Page 159
be at least 29.4912 MHz. 36 MHz was, in fact, chosen for convenience giving a maximum data rate of 1.5
MHz.
The reason why the clock must be at least 24 times the data rate is that the pseudo-random sequence
generator must be clocked 24 times to create a statistically independent value of "A" to be used in the
comparison. This ensures that error bits are generated independently. This complete change of
comparison number "A" is ensured by using a divide by 24 counter circuit (block 3) which causes a new
24 bit number to be loaded into a latch circuit (block 4) ready for comparison in the comparator circuit
(block 5). The other input to the comparator number "B", is produced from a look-up table comprising
of Read Only Memories, (block 6) which have been pre-loaded with values which correspond to equivalent
error rates of between 1 in 10'^ and 9 in 10' when compared to the 24 bit number "A". The output value
from the look-up table is produced by two select inputs, the number select and display (block 7) and the
exponent select and display (block 8). The outputs from these circuits act as address inputs to the look
up table. The range of values available from these select circuits must, therefore, be restricted as follows:-
Number Range 1 - 9
Exponent Range 1 - 6
The functional block which makes the error generator so versatile is the data synchronisation and error
insertion circuit (block 9). This circuit ensures that only one comparison is made per data bit and also
that a new 24 bit number for "A" has been used. This circuit also synchronises error insertion and re-times
the data after errors have been injected.
Appendix B Page 160
Table 81 shows the values pre-loaded into the look-up table. The table shows columns for:-
Error rate selected
Address used for look-up purposes
Decimal look-up value
Hexadecimal look-up value
Figure 82 shows the complete circuit diagram for board 1 of the error generator and Figure 83 shows
board 2, ie. the preset select and display circuits. Table 82 and 83 are the Integrated Circuit component
lists for these two boards and the IC numbers are cross referenced to Figures 82 and 83 respectively.
Appendix B Page 161
3 3 3
FIGURE B2 CIRCUIT DIAGRAM FOR ERROR GENERATOR BOARD 1
NOTE I ALL RESISTORS ARE IK 1/8 WATT 5%
•5
C&K 7109 SWITCH _
o
AO B-Al ^ AS B-
A3 B-
A4 B_
AS B_
AG B_
U7/DIS=LAY 1
i INA
1 INB
| INC
| IND y
Ji RBIN
Aif-
Cit
Elf-
G
TEST RBOUTf
f A
ii B
4! C
' D
1 E
1 F
' ^ CQMl COMH DP"
ii INA
INB §
INC 3 IND ^
RBIN
TEST
RBOUT
UNITS
US/DISPLAY H
A
f ^ f C
D
t i F
f '' coMi ccwe — f -
DPii
EXPONENT
FIGURE B3 CIRCUIT DIAGRAM FOR ERROR GENERATOR BOARD 2
Appendix B Page 163
Table BI - Error Generator PROM Details
Error
Rate
1x10"®
2
3
4
5
6
7
8
9
1x10'^
2
3
4
5
6
7
8
9
1x10"^
2
3
4
5
6
7
8
9
Hex
Address
61
62
63
64
65
66
67
68
69
51
52
53
54
55
56
57
58
59
41
42
43
44
45
46
47
48
49
Decimal
Value
17
34
50
67
84
101
117
134
151
168
336
503
671
839
1007
1174
1342
1510
1678
3355
5033
6711
8389
10066
11744
13422
15099
Hex
Value
11
22
32
43
54
65
75
86
97
A8
150
1F7
29F
347
3EF
496
53E
5E6
68E
DIB
13A9
1A37
20C5
2752
2DE0
346E
3AF8
Error
Rate
1x10"^
2
3
4
5
6
7
8
9
1x10'^
2
3
4
5
6
7
8
9
1x10'^
2
3
4
5
6
7
8
9
Hex
Address
31
32
33
34
35
36
37
38
39
21
22
23
24
25
26
27
28
29
11
12
13
14
15
16
17
18
19
Decimal
Value
16777
33554
50332
67109
83886
100663
117441
134218
150995
167772
335544
503317
671089
838861
1006633
1174405
1342177
1509949
1677722
3355443
5033165
6710886
8388608
10066329
11744051
13421772
15099493
Hex
Value
4189
8312
C49C
10625
147AE
18937
1CAC1
20C4A
24DD3
28F5C
51E68
7AE15
A3D71
CCCCD
F5C29
11E885
147AE1
170A3D
19999A
333333
4CCCCD
666666
800000
999999
833333
CCCCCC
E66665
Appendix B Page 164
I?ble 82-Error Gene
mber
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Type
04
164
164
164
164
86
92
74
2716
2716
2716
174
174
174
174
85
85
85
85
85
85
74
02
74
Vcc
14
14
14
14
14
14
10
14
24
24
24
16
16
16
16
16
16
16
16
16
16
14
14
14
GND.
7
7
7
7
7
7
5
7
12
12
12
8
8
8
8
8
8
8
8
8
8
7
7
7
No. Of Pins
14
14
14
14
14
14
14
14
24
24
24
16
16
16
16
16
16
16
16
16
16
14
14
14
NOTE All TTL devices are "LS"
Appendix B Page 165
Table 83-Error Ge ^
Number Type Vcc GND.
1 00 14 7
2 00 14 7
3 163 16 8
4 163 16 8
5 48 16 8
6 48 16 8
7 Disp ~ 4,12
8 Disp ~ 4,12
No. Of Pins
14
14
16
16
16
16
14
14
NOTE The displays are common cathode and use 74LS48 drivers. If common cathode displays are not
available it will be necessary to use common anode devices and 74LS47 drivers. All TTL devices are "LS".
B.4 Circuit Testing and Discussion of Results
In order to use this error generator, in the validation of the SS U\N circuits, its performance had to be
verified. The performance was tested thoroughly with respect to the following parameters:-
Accuracy of Preset Error Rate
Distribution of Errors within a preset rate
Consistency of Error rate with input data rate variation
Appendix B Page 166
Spread of single bit and multi-bit errors
Various tests were carried out to validate these parameters. Table 84 is a list of definitions used to describe
the conditions being tested. In this table zeros and ones are used to represent the presence or absence
of errors, ie. a single bit error is identified by the pattern 010, and a double bit error by the pattern 0110.
The reference letters A to J may then be used when describing the results obtained. Figures 84, 85 and
86 show the special test circuits built to create the conditions identified by the reference letters A to J
B.4.1 Test#l
Data rate set to 1 MHz.
Error rate pre-select set to 1 in 10.
Test circuit A in Figure 84 used.
The timer counter was set to record events over a 10 second period. 100 results were collected and a
histogram of the spread of the results was produced. Figure 87. This figure shows the distribution of all
errors produced.
Appendix B Page 167
CIRCUIT FOR TEST A '-\
RAW ERRORS = COUNT B
GENERATOR 0/P RAW ERRORS
CLOCK
+5
T
TO COUNTER
RAW ERRORS
CLOCK
L
H
CIRCUIT FOR TEST C +5
n n - * — 3 R -
m >
74LS1B4
x ( n " T i m a n r a > — * * X 3I« * * 3 ( « — * -
«—3K—X— i i— i n—M—3k—i l t
s > 03 > CD UJ ro FU H-
> ra > H- O C3
> > > V II A CD CD m
— 3 R — * — m -
E M
z
74L5B5 > > > V 11 A
CD d ) CD — f SK * -
n -
n
L H
L
SINGLE BIT ERRORS
Q 1 Q
TO COUNTER
FIGURE B4 TEST CIRCUITS A AND C
Appendix B Page 168
CIRCUIT FOR TEST D
RAW ERRORS
•S
CLOCK ii
vnn F air 0 1 1 a
Sg 741_S1S+
E J D D D D D D O x r ' n m a n t D >
fi • D m o b ^ ^ n s i A
C3 C3
ro mUMTEH
L H
CIRCUIT FOR TEST E
RAH ERRORS
OJOCK :p5;
T>«EE B I T ERRORS
0 1 1 1 a
Sg 74LSie4
• Q O D D D O Q
i i n i i n ISSI8 f t !S i :Sg
74L5SS
(D 03 CD '^ 03 P O
7+LS8S
o D) ffi H P ID m a
IT TO COKTER
L H
CIRCUIT FOR TEST F FOUR B I T EHHQR3
0 1 1 1 1 0
i3D QC OH OG
7+LS9S
a o o H sb D OS
r^NIIHI 741-SflS
O O CD H O (D O
T TO COJNTER
L H
FIGURE B5 TEST CIRCUITS D,E AND F
Appendix B Page 169
CIRCUIT FOR TEST G
FIVE BIT ERRORS
0 1 1 1 1 J D
74L.sas J > > >
Q] ID SI
U H
CIRCUIT FOR TEST H BIX a i T EFWKS
O l l l i l i O
QD QC OB QA QE
a ] > t D > I D > I ] 3 >
74L.sas
> > > > > > V I A m ID ID
l l I
L H
• • — « — « — » — * — • •
S > m > m u ro ro I-*
> > > 74CS8S
• * ? • > • • ' V »
M I ' "t TO carfTER
CIRCUIT FOR TEST I SEVENIOR MORE) BIT ERRORS
0 1 1 1 1 1 1 1
• D QC OB OA OH OG OF QE
•«—i—i—•—i—i—i—•-En S i« is S 5 g S
744jaS
aa OD 8D
74).SBS
? i i as 5 1 1 ID ID - f—•
TO COLKTER
CIRCUIT FOR TEST J Eiafl" lOR MORE) HIT ERRORS
oc ce
(—1
E
I '
I
— 1
— 1
1
^
K ft
1
1
tc
1 HI
;z
,
>
1
1 1
1
1 E c
• :
i
— 1
—
— i
> c
>
1
f—
— I H — 1
1—1
i a
u — 1
c
1
— 1
>
— J
— 1
a c
sa 1
1
—
> c
> > &
i
H
TO
~
FIGURE BG TEST CIRCUITS G . H . I AND J
Appendix B Page 170
(D u c L L D U U 0
i ) -
0
0 z
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0 LL
// / A
I ; .^ K /' ^
/ / /
T
99483 99713 99943 100172 100402 100632
Errors per 10 second period.
Figure 87 Distribution of All Errors (A). F = IMhz. R = 1 In 10
Appendix B Page 171
Table 8.4 - Error Generator Test Circuit Definitions
The following error conditions were tested:
A = All errors le. Total number of bit positions affected by errors
8 = Any error ie. Total number of different error occurences
ie. Total number of rising edges indicating errors of all (or any) length.
C = Separate single bit errors ie. 010
D = " double 0110
E = " triple 01110
F = " four " " " 011110
G = " five 0111110
H = " six 01111110
I = " seven or more 01111111
J = " eight " " " " " 11111111
Where 0 = No error in this bit position
And 1 = Error in this bit position
Appendix B Page 172
The main statistics from this set of results are:-
Thesumis 10000383
The mean is 100003.83
The variance of the samples is 78970.143
The standard deviation of the samples is 281.016
The mean value represents an error rate of 1.0000383 x 10 compared to the expected value of 1 x 10"
B.4.2 Test #2
These results show the raw errors or the total number of different error occurrences in the 10 second
period. The results histogram is included as Figure 88. The statistics are:-
Sum 8410954
l\/lean 84109.54
Variance 50361.827
Appendix B Page 173
10 (P u c ID L L D U U 0
> • -0
0 z
24
22
2 0 -
1 8 -
1 6 -
14
1 2 -
1 0 -
8 -
6 -
4 -
2 -
0
rjT 'T
/ / / / /
^77
Ul \///\ i / / / l l / / / i 1///I i / / / i^//j nr-7 u^ \L
83694 83954 84215 84475 84736
Errors per 10 second period.
Figure 88 Distribution of Any Error (8). F = IMHz. R = 1 in 10
Appendix B Page 174
Standard Deviation 224.414
B.4.3 Test #3
Similar to Test #1 but test circuit C is used (Figure 84)
These results show the distribution of single bit errors produced in a 10 second period, see Figure 89.
The statistics are:-
* Sum 7030714
Mean 70307.14
Variance 44376.99
Standard Deviation 210.658
B.4.4 Tests #4 to #8
These tests use similar parameters to those of previous test but are designed to investigate the distribution
of multi-bit errors. Test circuits D to H in Figures 84 to 86 were used. (The number of 7 and 8 bit errors
encountered was insignificant and not considered further).
Figures 810 to 814 show the results obtained from these tests.
Appendix B Page 175
22
9) ID U C t) L L 3 U U 0
< « -0
0 z
7T k'/
' ' A y
69974 70189 70404 70619 70834
Errors per 10 second period.
Figure 89 Distribution of 1 Bit Errors (0). F = IMHz. R = 1 in 10
Appendix B Page 176
Figure BIO Distribution of 2 Bit Errors (D). F = IMHz. R = 1 in 10
Appendix B Page 177
(f) ID U C 0 L L 1 u u 0 >l-
0
0 z
32
30
28
26
24
22
20
18
16
14
12
10
8
6
2
0 ^ UUJU-
1578 1643 1707 1771
rr—T-r 1^1 1836
Errors per 10 second period.
Figure 811 Distribution of 3 Bit Errors (E). F = IMHz. R = 1 in 10
Appendix B Page 178
ID u c 0 L L D 0 0 0
0
0 z
32
^0-
2 8 -
26
24
2 2 -
2 0 -
1 8 -
1 6 -
14
1 2 -
1 0 -
8 -
6
4 ^
2 -iv, 0
185
i / Y/A //A
VA'A
/ 7 / /
I l k / /
/ / ,
/
TT' "A if
y/A
Ah A /
/ / k
/
4 ! A A
'/\ K/y; A// '/A \ h I///
<'A\ \/1^ A I ' • ' ' ' V 7
K j /
^// /''! r // /
/ r// / / ui {AA
/ • V
/ y
k// M J ^
AO
' / / i A .
A A / / i r/ ///I rz l 204 223 242 261
Errors per 10 second period.
Figure 812 Distributionof 4 Bit Errors (F). F = IMHz. R = 1 in 10
Appendix B Page 179
(0 ID U C 0 L L
0 U 0
>h
0
0 z
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0 .V/ v/A V/A \//A \///
T
21 24
i/Z/i 1/7/ " • • ' 7
^ ^
26 29
Errors per 10 second period.
T 31
Figure 813 Distribution of 5 Bit Errors (G). F = IMHz. R = 1 in 10
Appendix B Page 180
FigureB14 Distributionof 6Bit Errors (H). F = IMHz. R = 1 in 10
Appendix B Page 181
Tests #1 to #8 were designed to map the distribution of all errors produced. These tests were carried
out at a single frequency. It can be seen from these results that the distribution of errors does approximate
to a Gaussian spread, as anticipated.
Figure 815 shows the distribution of separate error occurrences. It can be seen that on average for every
100 total errors produced there were 84 separate error occurrences made up of 70 single bit, 10 double
bit, 1.6 triple bit etc. Figure Bi 6 shows how these figures relate to the number of errors produced. Only
30 results were obtained for tests #7 and #8 since the numbers were very small.
B.4.5 Tests #9 and #10
These two tests are similar to test #1 except that the data rate used for these tests was 10 KHz and 100
KHz rather than 1 MHz.
As expected the number of errors occurring during a 10 second period is one hundreth and one tenth
respectively of that expected at 1 MHz. Figures 817 and 818 shows the distribution of All errors at these
data rates. When these figures are compared with Figure 87 it can be seen that the distribution envelopes
are almost identical, thus verifying the error rate consistency with varying data rates.
B.4.6 Tests #11 and #12
These two tests are similar to test #1 except that the error rates chosen were 1 in 100 and 1 in 1000 rather
than 1 in 10.
The number of errors was, as expected, reduced by factors of 10 and 100 respectively compared with the
figures obtained in Test # 1 . Figures 819 and 820 show the distribution of All errors at 1 MHz at the
Appendix B Page 182
110
100
+'«
00 I
Oh
7^ //A/ 90 - / / / /
80-Vi P 'V V
i n _ / / / f,' / / 70
60
50
4 0 -
30
20
1 0 -
7 / / /
AAA ^/A 7/V 7 7 ^ V/AA V/A \AA/\ ////
111 J II \//A V/f , / /
/ /
:/// K/// v-^
A/AA / / / /
r I / / ! / / /
/i / / / /
, , . i i I ' /A /// 'A/A \ \ V//,
''I l\ Y/A Y/A '//A K/"/'. 'AA' 11 \ 11 \ I / / /
' /
/ / / W'1 //f\ i^AA, Y/Ak Y//A Y/A^ '/A \AAf
' / I i / / / K//7 / ' / /
,/
0 / '/i y I I / / / / / I f / / / i r// A / / / ! ry-T-n
oil any 2 4 5 6
11-11 n" Bit Errors
Figure 815 Distribution of Separate Error Occurrences
Appendix B Page 183
110
100
90
8 0 -
/
c-o
i)„
00 I
oh
7 0 -
60
5 0 -
40
30
20
1 0 -
0
\ / \
/ /
]/' / I
/
/
\ \
r~7
V/
/
V / Y I
(A I
Y Y /
\
\ \
'/h 7. /
'\L 3L JLZX.
any 2 3 5 6
[771 Bits in Error
/cif n" Bit Errors Error Occurrences
Figure 816 Multi-Bit Error Characteristics
Appendix B Page 184
u c 1) L L 1 u u 0
4-0
0 7
18
17-^
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
- /
V /
V / A /
Y I
11
/ /I
/ /
A\ ' 11
YA.
A V ' / /
YAi ' A
/I
/ /
V/ / / / /
^ iZ/ /
955 977 999 1020 1042 1064
Errors per 10 second period.
Figure 817 Distribution of All Errors (A). F = lOKHz. R = 1 in 10
Appendix B Page 185
Figure 818 Distribution of All Errors (A). F = lOOKHz. R = 1 in 10
Appendix B Page 186
Figure 819 Distribution of All Errors (A). F = IMHz. R = 1 in 100
Appendix B Page 187
(D U C i) L L D U U 0
0
0 z
18
17^
16-
15'
14'
13
12
11
10
9
8
7
6
5
4
3
2
1
0 /
r7
1/ ^
993.8 996.6 999.4 1004.9 1007.7
Errors per 10 second period.
Figure 820 Distributionof All Errors (A). F = IMHz. R = 1 in 1000
Appendix B Page 188
selected error rates. When these figures are compared with Figure 87 it can be seen that the distribution
envelopes are very similar. This confirms the distribution properties and accuracy of rate selection across
the range of presetable error rates.
B.5 Appendix B Conclusions
The measurements made confirm that the error generator performs as expected, i.e. that it generates
errors with a Gaussian distribution, the program settings for error rate select are accurate, and that the
accuracy is maintained with changes in both rate and operating frequency. The confirmation that this
piece of test equipment performs exactly as expected means that it may, therefore, be used with
confidence in the testing of the circuits for the Spread Spectrum LAN, which is the main objective of this
project.
Appendix B Page 189
APPENDIX C
Appendix C Page 190
C THE ANALOGUE MULTIPLIER
C l Summary
This appendix includes details of the calculations made to choose the required peripheral circuit
component values associated with the RS 1495 Analogue Multiplier. The method of component calculation
follows very closely that illustrated in the component literature.
C.2 Theory of Operation
Figure 01 shows a circuit schematic of the analogue multiplier with calculated component values and the
level shifter already included. Figure 02, which shows the internal circuit schematic is taken from the
component data sheet. These circuits are referred to frequently in the following text.
The multiplier operates on the principle of variable transconductance. The differential output current
(seen at pins 2 and 14) is given by:
Ii4 -12 = (2 X Vx X Vy) / (Rx X Ry X I3)
where Vx and Vy are the input voltages and I3 is the scale factor current.
The scale factor is a value multiplied by the output to reduce the size. eg. For a scale factor 1 /10 then Vo
= Vx X Vy/10. This scale factor simply prevents overdriving of the amplifier causing non linear opeation.
Appendix C Page 191
AAArH>x AAAr^> >
CD
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CD
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Appendix C Page 192
OJ
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^ • ON (XJ
3
a c
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| \ Z
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Appendix C Page 193
The potential dividers on the inputs X and Y simply limit the maximum multiplier input to half the value of
the Vx and Vy input voltages. Once again, this is done simply to prevent the occurrence of non linear
operation if the inputs become too large.
The resistors Rx and Ry ensure the input transistors are always active, and 113 and I3 flow through Rx and
Ry respectively. To ensure the input transistors are always active then the voltages I13RX and IsRy should
be larger than the input voltages Vx and Vy, and the larger they are, with respect to Vx and Vy, the more
accurate the multiplier will be.
Pins 8 and 12 provide facilities for an X and Y offset adjustment. Even when transistor base emitter
junctions are matched within 1 mV and resistors within 2%, errors in the output can still occur. Correction
must, therefore, be allowed for. The arrangement shown in Figure CI allows for precise adjustment of
the X and Y inputs. These potentiometers combine with the output offset adjustment, connected to pin
2, give complete output control.
ie. Vo = K(Vx ± Viox ± Vxoff) (Vy ± Vloy ± Vyoff) ± Voo
K = scale factor (see section C.4)
Vx = X input voltage
Vy = Y input voltage
Viox = X input offset voltage
Appendix C Page 194
Vioy = Y input offset voltage
Vxoff = X input offset adjust voltage
Vyoff = Y input offset adjust voltage
Voo = output offset voltage
C3 Level Shifting
In order to convert the differential output between pins 2 and 14 on the multiplier to a single ended output
voltage, referenced to ground, a level shifter is required. The level shifter is designed separately to the
analogue multiplier. The level shifter simply takes the voltages on pins 2 and 14 and obtains the difference,
the result being used as the single ended output, ie.
Vo = (I2-I14) X Ri
Provided that in both cases Ri is equal, then no errors should occur in the output. Perfect fixed resistor
matching is, however, not possible and mismatches can be compensated for by using the offset adjust
potentiometers as described above.
Appendix C Page 195
c.4 Analogue Multiplier Design Procedure
In this description reference is made to Figure C2.
The resistors at the input are chosen to limit the X and Y inputs to ± 5 volts.
This is for a V'x = Vy = nominally ± 10 volt input
For a scale factor of 1/10 ie. Vo = (V'x x Vy) /10
(2Vx X2Vy)/10
4/10VxVy
scale factor K =4 /10
Step one is to select I3 ie. the current in pin 3. Device limitations indicate that this current cannot exceed
10mA.
Ii3 == I3 and in this case they are both set to equal 1 mA.
Appendix C Page 196
Setting I3 and I13 only needs the connection of a resistor between pin 13 and ground and between pin 3
and ground.
R13 + 500 = (V(- ) -0.7) / l i3
and R3 -I- 500 = (V(-) - 0.7) /13
V(-) = -12 volts &I3 = Ii3 = 1mA
.-. R3 -H 500 = 11.3 / 1 mA
.-. R3 = 10.8k n = 12k a (Nearest Preferred Value)
If R3 is made equal to 15kn by using a 12kn resistor and a lOkn potentiometer then adjustment of R3
and I3 would be allowed for, this also allows a convenient method of making a final trim of the scale factor.
The next step is the consideration of Rx and Ry. If reference is made to the schematic, then to ensure the
input transistors will always be active
(Vx/Rx) < Il3 & (Vy/Ry) < I3
Appendix C Page 197
IfVx = Vy = 5 volts
Then make Rx = Ry = lOkfl
Rx = Ry = lOkn is used ,as the larger the l3Ry and hsRx products in relation to Vy and Vx respectively
the more accurate the multiplier will be.
Next RL must be determined. Using the following known values Rx, Ry and I3, RL may be calculated using
the relationship
K = 2RL/ (Rx*Ry* l3) = 4 / 1 0
RL = 20kn « 22ka (Nearest Preferred Value)
Next Rl is chosen so that the voltage at pin one is several volts higher than the maximum input voltage,
hence it must be at least 6 volts as Vx = Vy = 5 volts, ( 7 volts was actually used). This is to ensure
transistors Ql ,Q2,Q3,Q4, are maintained in their active region.
The current in pin 1, li = 2 x I3 (see schematic)
.-. Ri = (V( + )-V1 ) /2 X I3
Appendix C Page 198
where Vi = 7 volts, V (-1-) = l2Vandl3 = 1mA
.-. Ri = 2.5k n .-. Use 3.3k n
C.5 Level Shifter Design
It can be shown that Vo = (I2 - Ii4) RL, and from the schematic
I2-I14 = 2 X Ix X I y / l 3
2 X Vx X Vy / (RX X Ry X I3)
.-. Vo = 2 X RL X Vx X Vy / (Rx X Ry X I3)
Referring to the Level Shifter diagram, C3, and using the values I2 = I14 = 13 = 1mA, Ro can easily be
found as V2 and V14 are half way between Vi and the supply rail ie. 9 volts.
From above diagram V14/RL + Ii4 = (V(4-) -V i4 ) /Ro
.-. Ro = 2.6k n
Appendix C Page 199
.-. use 3.3k a for Ro
Using a potentiometer in the R2 load resistor section allows flexibility. The following values have been
selected
R2 = 2.7k a
Ri4 = 3.3k n
RL = 22kn
R2L = 12kn -I- 10k a potentiometer
This completes Appendix C, the description of the selection of component values for the RS 1495
Analogue Multiplier
Appendix C Page 200
APPENDIX D
Appendix D Page 201
D PROGRAM - CSMA/CD SIMULATOR
D.l Summary
This appendix includes the code for the program written to simulate the throughput characteristics of the
CSMA/CD protocol developed theoretically in section 6.2. The use of the program and the results obtained
are described in section 6.3.
D.2 Brief Outline of the Program
The program simulates the arrival of packets into a node for transmission into the network. The average
arrival time is governed by the rate of traffic being offered, G. The actual arrival time is subject to Poisson
distribution characteristics around the average arrival time. (The POISSONRANDOM function used for
this purpose is described in Appendix F). 50 packets are offered to the node at each of 16 different offered
traffic rates. The first packet to arrive will find the network free and be assumed to be transmitted
successfully so the channel Use time is set to 1, the channel Busy time is set to 1 -i-a (ie. 1 plus the
channel occupancy sensing time) and the Idle time is set to the average arrival time (see also section
6.2). The arrival time for the next packet is then calculated and the procedure CSMA is used to determine:-
if the arrival time is less than the channel sensing time, ie. the vulnerable period, a, a collision is
assumed and both packets are "discarded". The COLLISION procedure is then used to reset the
Busy time to "3 x a" (the sensing time) and the Use time to zero.
If the arrival time is greater than the vulnerable period but less than the Busy time then the channel
is already occupied by another packet and the present packet is classified as a "CLASH" and is
discarded.
Appendix D Page 202
. If the arrival time is greater than the Busy time then the channel is assumed free again and the Use,
Busy and Idle times set for a successful packet arrival.
When 50 packets have arrived the CSMA statistics are calculated and the simulated throughput, ST, is
calculated from the average Use, average Busy and average Idle times as shown in equation (24).
For each offered traffic rate (G) the Theoretical Throughput (TS) is calculated from equation (31) and
saved on file with the Simulated Throughput (ST), the number of collisions, the number of successes
and the number of clashes, as shown in Table 5 in order that graphs may be plotted.
Appendix D Page 203
program Simcsma(input.output);
const packetbits = 1800; quit = 50;
type keeparr = array[1..50] of real; intarr = array[1..50] of integer;
var thrput : text; cyclecount, j,clash : integer; succtrans,col : integer; idle,busy,use,avebusy,aveidle,aveuse : real; mean,offered,aveariv.arivtime : real; totariv,totalbusy,totaluse,totalidle.a : real; theothr,simthr,garr : keeparr; cols,clashs : intarr;
procedure Collision; begin
col := col + 1; use := 0; busy := arivtime -I- (3 * a) ; {time channel occupied unsuccessfully]
end; {end of Collision}
procedure Csma; begin
if (arivtime > a) and (totariv < busy) then begin
clash := clash -I- 1; end else begin {start of outer else)
if arivtime <= a then Collision else begin
totariv := 0; use := 1; succtrans := succtrans + 1; busy := 1 -I- a; {channel occupancy plus sensing time)
end; begin
totalbusy := totalbusy + busy; idle := aveariv; totalidle := totalidle + idle; totaluse := totaluse + use;
end; end; {end of outer else)
end; {end of Csma)
Appendix D Page 204
procedure Csmastats; begin
if succtrans O 0 then begin
avebusy := totalbusy / succtrans; aveuse := totaluse / succtrans; aveidle := totalidle / succtrans; simthr[j] := aveuse / (avebusy + aveidle);
end; end; {end of Csmastats)
procedure Dispcond; begin
writeln('Bits Per Packet = ',packetbits); writelnCDetection time = ',a:6:4,' in units of packets'); writeln;
end; {end of Dispcond)
procedure Outmod; var
i : integer;
begin Dispcond; writeln('Theoretical Simulated Offered Collisions'); writeln; for i := 1 to j do begin
writeln(theothr[i]:8:4,simthr[i]:12:4, garr[i]:11:4,cols[i]:ll,clashs[i]:11);
writeln(thrput,theothr[i]:8:4,simthr[i]:12:4, garr[i]:11:4,cols[i]:11.clashs[i]:11);
end; end; {end of Outmod)
procedure Theocsma; var
x,y,g : real;
begin g := garr[j]; X := g * exp(-a*g); y := (3*a*g + (exp(-a*g)*(2 -t- g - 3*a*g - exp(-a*g)))) ; theothr[j] := x / y;
end; {end of Theocsma)
procedure Calcstats; begin
cols[j] := col; clashs[j] := clash; Csmastats; garr[j] := offered; Theocsma;
end; {end of Calcstats)
Appendix D Page 205
function PoissonRandom(mean: real): integer; var
product: real; n: integer;
begin { PoissonRandom } product := 1; n := 0; while product > exp(-mean) do begin
product := product * random; n := n -f- 1
end; PoissonRandom := n - 1
end; { PoissonRandom )
begin a := (32 / packetbits); for j := 1 to 16 do begin
randomize; case j of
1 : 2 : 3 : 4 5 6 7 8 9 10 11 12 13 14 15 16
end; (( arivtii clash totari-' col : = use : = idle : = totali totalu totalbi cyclec succtr busy : avearr
offered : offered . offered . offered offered offered offered offered offered offered offered offered
: offered : offered : offered : offered =nd of cas< ne := 0; := 0; ^ := 0; 0; 0; = 0; die := 0; se := 0; Lisy := 0; ount := 0; ans := 0; = 0; V := 1 / o
= =
= =
=
=
= = =
.=
: = : =
: = : = : =
: =
s)
0.1 0.2 0.4 0.8 1; 2; 5; 10; 15; 20; 50; 60; 70; 80; 80; 100;
fferec i;
Appendix D Page 206
for cyclecount := 1 to quit do begin
arivtime := (aveariv * PoissonRandom(20)/20); if arivtime <0 then writelnCnegative arrival'); totariv := totariv + arivtime; Csma;
end; Calcstats;
end; {end of for j) assign(thrput,'simres3.prn'); rewrite(thrput); Outmod; close(thrput);
end.
Appendix D Page 207
APPENDIX E
Appendix E Page 208
E JVQCROPROCESSOR PROGRAM
E.l Summary
This appendix contains the commented listing for the microprocessor control program.
Appendix E Page 209
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Appendix E Page 210
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Appendix E Page 211
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Appendix E Page 228
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Appendix E Page 229
APPENDIX F
Appendix F Page 230
F PROGRAM - TRAFFIC GENERATOR
F.l Summary
This appendix describes the random number generator which was written to produce the traffic arrival
characteristics required for System Test purposes (see chapter 7). The standard "random" function;
available in most high level programming languages, produces numbers with a uniform distribution. The
need to produce simulated packet arrivals subject to Poisson and/or Normal (Gaussian) distribution
characteristics, however, meant that the standard function could not be used directly, but had to be
modified to produce the required distribution.
F.2 Poisson & Normal Distribution Characteristics
F.2.1 Normal (Gaussian)
One of the most important examples of a continuous probability is the Normal, or Gaussian, distribution.
This distribution is represented, in standard form, by:-
Y = _ ! e" ^^^^^^^ ' (L1)
where z = (x - |x) / X and x is in standard units.
In such a case we can say the z is normally distributed with a mean of zero and a variance of one.
Appendix F Page 231
The major characteristics of the Gaussian distribution are:-
l\/lean = M-
Variance = n-
Standard Deviation = a
F.2.2 Poisson
The Poisson distribution has been widely used to model arrival distributions and other seemingly random
events. The distribution is named after Poisson, who discovered it in the early part of the 19th century.
The discrete probability distribution is given by:
p(x) =_xV^ (L2) x!
where e = 2.71828 and X is a given constant.
p (x) is then called the Poisson distribution.
The major characteristics of the Poisson distribution are:-
Appendix F Page 232
Mean = ^ = ^
Variance = Q- = x.
Standard Deviation = cr = V X
F 3 The "Random" Programs
IVIany texts have been written on the applications of stochastic processes in simulation and modelling.
One such text [31] describes standard procedures which will produce either Poisson or Gaussian
distribution characteristics from the uniformly distributed random numbers produced as a standard
language function.
F.3.1 Normal Distribution Numbers
The theorem for the production of numbers with a Gausssian distribution is called the "Central Limit
Theorem". It states that the sum, xn, of n identically distributed independent variables has an
approximately normal distribution with a mean = |j, n and a variance of na ^. Studies have shown that
with n = 12 this technique provides good results.
lfthevariablessummedfollowastandarduniformdistributionthen|x= 0.5ando-^= 1/12. Thus summing
n standard uniform random numbers gives an approximate Gaussian distribution with a mean of 0.5 n
andavarianceofn/12. By dividing the sum by 6 instead of 12 a mean value of 1 rather than 0.5 can
be obtained. A multiplying factor may then be applied to produce random numbers in a suitable range.
Appendix F Page 233
A procedure called NORMALRANDOM was written to produce random numbers with the characteristics
of Gaussian distribution. This routine was tested to determine the characteristics of the distribution
produced, see listing at the end of this appendix. The largest value of RANGE selectable in the program
is 2730 , this is in order to avoid Integer Overflow. This can be extended to 10000, however, if a Maths
co-processor is used. 10,000 samples were obtained from the procedure and the number of times each
value was produced was plotted against the value. Figure F1 is a plot of the distribution obtained, with a
mean value of 50. It can be seen that this distribution does, indeed, approximate to Gaussian
characteristics.
F.3.2 Poisson Number Program
Random numbers with a Poisson distribution with a mean of x may be accomplished by mulitplying, n,
successively generated numbers until the product is less than e" ' The value n -1 is then the value of the
Poisson random variable x.
A maximum value of 88 must be placed on the value of IVIEAN used with this procedure, in order to avoid
Floating Point Overflow. This value can be extended to 100 if a Maths co-processor is used. Figure F2 is
a plot of the distribution produced by the procedure POISSONRANDOiVI, which is part of the Traffic
program included in this appendix. 10,000 samples with a mean value of 50 were used to produce this
distribution curve. It can be seen that the error distribution obtained from this procedure approximates to
Poisson characteristics.
R4 The Traffic Program
The mean valued "TIME" is initialised at the start of the program (see section 7.6). This program accepts
an input from node #1 of the Spread Spectrum LAN, in order to synchronise to real world timing. Two
random numbers with the preset "TIME" value are then produced. One of the numbers is subjected to
Appendix F Page 234
Mean = 50
u c H) L L 3 U U
0 ii-
0
[ 3 z
Event Value
Figure F1 Probability Distribution Normal (Gaussian) Characteristics
Appendix F Page 235
Mean = 50
u c 0 L L 3 U U
0 M -0
1 (D D
[ 3 z
Event Value
Figure F2 Probability Distribution Poisson Characteristics
Appendix F Page 236
Gaussian distribution and the other to Poisson characteristics from the two procedures described above.
These numbers are converted to Hexadecimal ASCII characters. The Poisson number is transmitted to
node #3, the traffic generator, and the Gaussian number is transmitted to node #2, the interference
generator. These numbers are then used to represent packet arrival times. By altering the standard
inter-arrival delay produced by node #1, and adjusting the program's mean value accordingly, offered
traffic with Poisson and Gaussian distributions can be simulated.
Appendix F Page 237
program Traffic (input.output); {$C-}
type hexstr = array[1..4] of char;
var time,count,temp,j,i,c,d : integer; b,a : real; intval,trafval : hexstr; hold : byte;
integer) :char; function J begin
>elval(temp
case temp of 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
end; {«
Selval Selval Selval Selval Selval Selval Selval Selval Selval Selval Selval Selval Selval Selval Selval Selval
snd of caj
=
=
=
=
= =
=
= =
= =
=
= =
= =
36)
'0' '1' '2' '3' '4' '5' '6' '7' '8' '9' 'A' 'B' 'C 'D' 'E' 'F'
end; {end of Selval)
procedure Hexout(var hexval :hexstr ; nam : integer); begin
temp := hi(num) div 16 and $F; hexval[l] := Selval(temp); temp := hi(num) and $F; hexval[2] := Selval(temp); temp := lo(num) div 16 and $F; hexval[3] := Selval(temp); temp := lo(num) and $F; hexval[4] := Selval(temp);
end; {end of Hexout)
Appendix F Page 238
function NormalRandom(range: integer): real; { Generate normal distribution of random integers between 0 and range ) var
i: integer; sum: real;
begin { NormalRandom ) sum := 0; for i := 1 to 12 do sum := sum -f- random (range)/range; NormalRandom := (sum / 6)
end; { NormalRandom )
function PoissonRandom(mean: integer): integer; { Generate a Poisson distribution of random integers ) var
product: real; n: integer; res : real;
begin { PoissonRandom ) product := 1; n := 0; res := exp(-mean); while product > res do begin
product := product * random; n := n + 1
end; PoissonRandom := n - 1
end; { PoissonRandom }
procedure Send; begin
repeat until ((port[$3fd] and $01) > 0); {wait for prompt from rx board) hold := port[$3f8]; {clear flag from rx board) for j := 1 to 4 do {send hex arrival times to both transmitters) begin
repeat until ((port[$3fd] and $20) > 0); hold := ord(trafval[j]); {send to traffic gen) port[$3f8] := hold; repeat until ((port[$2fd] and $20) > 0); port[$2f8] := ord(intval[j]); {send to interference gen)
end; end; {end of Send)
Appendix F Page 239
{set up serial port 1) {to go to traffic generator)
{set up serial port 2) {to go to interference generator'
begin { Traffic Generator ) count := 0; port[$3fb] := $9A port[$3f8] := $0C port[$3f9] := $00 port[$3fb] := $1A port[$2fb] := $9A port[$2f8] := $00 port[$2f9] := $00 port[$2fb] := $1A repeat begin
write('Enter mean value for this run readln(time); randomize; a := (PoissonRandom(100))/100; b := NormalRandom(10000); c := trunc(a*time); d := trunc(b*time); Hexout(trafval,c); Hexout(intval,d); Send; count := count + 1; write(count,' ' ) ; for j := 1 to 4 do write(trafval[j]); write(' ' ) ; for j := 1 to 4 do write(intval[j]); writeln;
end; until (keypressed or (count = 10000));
end. { Traffic Generator }
' ) ;
Appendix F Page 240
APPENDIX G
Appendix G Page 241
G PUBLICATIONS
G.l Summary
This appendix contains copies of all of the conference and journal papers which were written as a direct
result of the work carried out on this research project.
Appendix G Page 242
UDC 621.394.4 Indexing Terms: Data transmission. Local area networks. Spread spectrum
A synchronized spread-spectrum local area network
A. L. S IMCOCK, BSc-
C. na RANONG, BE, PhD*
and
P. LEUNG, BE, MEngSc*
• Department of Electrical and Electronic Engineering, Footscray Institute of Technology, Footscray, Australia 3011
SUMMARY
As the number of nodes connected to a local area network increases, the network throughput decreases owing to channel contention. This is conventionally overcome by either upgrading the network channel bandwidth, and hence increasing the data rate, or introducing a hierarchical network structure. This paper describes an adaptation of spread-spectrum communication techniques, used by the military, to a localized network. The resulting system enables multiple simultaneous communications within a channel rather than the conventional single communication. Such a system is capable of retaining communications facilities in a heavily loaded multi-user environment.
transmission are: . 3 - 5
(2)
1 Introduction The expanding need for data communication channels has increased the pressure on the available transmission bandwidth. This has led to developments in two broad areas: the extension of the usable spectrum through the use of even higher frequency carriers and the development of complex frequency allocation algorithms. An extension to the latter has led to the adaptation of spread-spectrum techniques which were originally developed in the mid 1950s' for military use as a means of providing a jam resistant communication link.
Spread-spectrum communication involves a transmission system which uses an overall frequency bandwidth far in excess of the minimum required. The receiver restores the signal to its norma! bandwidth and, in so doing, it enhances the desired signal while suppressing the effects of all other prevailing signals and noise. Overall, the communication channel bandwidth is not 'wasted' because, with a suitable selection of transmission scheme, several nodes may simultaneously transmit messages over the same channel with almost zero interference between transmissions.
A local area network (LAN) such as Ethernet, where multiple nodes use a single communication channel—one pair at a time, is a prime candidate for the application of spread-spectrum techniques. Being inherently jam-proof, spread-spectrum techniques have the potential of reducing the contention and allowing multi-pair communications, thus increasing the network's throughput under these conditions.
This paper deals with an implementation of a synchronized spread-spectrum LAN by the Department of Electrical and Electronic Engineering, Footscray Institute of Technology. A code division multiple access (CDMA) scheme sense is used.^ Within the CDMA channel a carrier sense multiple access scheme with collision detection (CSMA/CD) is used to reconcile the remaining contention problems.
Journal of ih« Institution of Bectronic and Radio Ctigineers. Vot 57, No.y:pp: f7^2frJa''a9ri^^ruar^T9fff^
2 Spread Spectrum Techniques The three primary methods of spreading the data
which the data is directly fast pseudo-random code
(1) Direct sequence—in modulated with a sequence. Frequency hopping—in which the carrier which is modulating the data is caused to change frequency in a pseudo-random manner.
(3) Time hopping—which can be likened to the pseudorandom allocation of channels in a time division multiplexed system.
The proposed network uses the direct sequence method, as shown in Fig. 1. The data signal d{t) is multiplied by a fast pseudo-random binary sequence (the direct or chipping sequence) pit) to produce a received waveform r{t) which, in the presence of an interfering waveform J(f), would be
r{t) = d{t)p{t) + J{t) (1)
Da-ta Sour-ce
Pd)
sequence generator
ranaon sequence generator
Transnitter Receiver
Fig. 1. Single channet direct sequence sy^em.
1.1987IERE.-
At the receiver this signal is multiplied by the same pseudo-random signal in order to recover the original data as in equation (2)
r(t)p(t) = d(t)-i-J(t)p(t) (2)
In equation (2) the jamming signal Jit) may be external interference or it may be interference from other transmitting nodes. The rejection of the other nodes' transmissions as noise depends upon the orthogonality of the codes "® used for spreading each node's data.
3 Network Considerations Current bus and ring local area network topologies typified by Ethernet and the Cambridge Ring respectively employ some form of (asynchronous) time division multiplexing. This may be in the more or less fixed compartment format of the Cambridge Ring or the packet message type format of Ethernet. Whichever system is used, any node wishing to access the system must wait until a time when no other users are transmitting. The node will then transmit at a relatively high bit rate into the system. The overall effect is that each node emits bursts of data at high bit rates for relatively short periods and then remains dormant for a much longer period. Occasionally, two or more nodes attempt to transmit at the same time and the messages collide; back-off and retransmission algorithms would then be used to arbitrate. Thus, network throughput is dependent on the number of nodes in the network and the network bandwidth. Special chip sets capable of high speed burst transmission (e.g. Motorola 68590) have been developed for this purpose.
The application of spread-spectrum techniques to a local area network provides it with the ability to have many nodes transmitdng simultaneously, thus increasing network throughput and possibly eliminating the need for very high speed transmissions. The system under development utilizes a code division multiple access scheme where each node has its own 'address' and associated code (or spreading sequence). The bus structure is shown in Fig. 2.
In the point-to-point communication system adopted in the network, if node X wishes to transmit to node Y then node X will modulate its data with the code of node Y. Hence, the transmitter of each node must be able to modulate its data with any recipient's address code. Since only one node at any instant in time may be transmitting to a particular address, a collision check for the intended receiver is still necessary, i.e. a CSMA/CD scheme is adopted within the channel. Thus, each transmitter has a built in demodulator to pre-check for collisions and continuously check while transmitting.
As a receiver, each node monitors the line, looking for data modulated with its own 'address code'. It treats data for any other intended recipient as noise and rejects it (as shown in equation (2)) but demodulates the data encoded with its own address code in order to recover the original data.
Each node has two demodulators—one for monitoring the channel for its own message and another one for collision avoidance and detection. The first demodulator works exclusively with its own address code whereas the _codtused in the second is switchable.
The"fask of choosing codes for their orthogonality can be simplified if the environment in which the system is to work, such as connection distance and hence propagation delay; attenuation, etc., can be controlled. This degree of control allows a synchronous network to be produced. Synchronization may be considered from both chip and dat» bil v^wpoint^ In a synchronous, cable-connected network such as this, with predictable delay- and
Host conputer
etc.
node
Sync line
node 3
node
Data line
node 4
node 5
Fig. 2. Bus structured node interconnections.
attenuation characteristics, the effect of the so called odd-even cross correlation properties are also predictable and codes with multi-level cross correlation values, e.g. Gold or Kasami codes,^"' are not necessary. The code allocation scheme selected is based on providing each address with a code which is a phase shifted version of the master code; this master code is also the synchronization code transmitted on the sync, line indicated in Fig. 2. Thus the cross correlation between codes is the auto-correlation function of the one code. This simplifies both the code generation and decision making circuitry. The allocation of phase shifted versions of the one code to act as the individual node address codes is similar to that used by B. Hirosaki et alA° in their performance analysis of a fibre optics system. They showed that the variance lq'{t)y in mutual interference from node i is given by
iq'(jNT,)y = \/N' (3)
where j represents the individual bit position, N is the chipping sequence length and T^ is the chip sequence bit period.
Equation (3) above shows that the per-channel interference is inversely proportional to the square of the chip sequence length, or processing gain; and since one of the design aims was to produce a reliable and resilient system, a fairly large 'processing gain' of 1024 (approx. 30 dB) was selected. This choice of value for the processing gain produces a system capable of working in an electrically hostile environment and also allows a large number of simultaneous code transmissions.
Gp = processing gain = Br
SS (4)
where Bss = bandwidth of the spread-spectrum signal, and BD = bandwidth of the data signal.
The concept of processing gain noted above is simply a power improvement factor which a receiver, possessing a replica of the spreading sequence, can achieve by a correlation process. For an ideal system the theoretical maximum number of users that a system could support would be equal to the processing gain Gp. This is not realistic under practical conditions and a figure of Gp/10 (Ref. 5) is usually accepted as being the maximum number of users which a system can accommodate.
Using maximal length sequences (MLS) of 2 ' ° - l bits (i.e. 1023) to encode each data bit results in a residual offset effect at the output of the analogue multiplier which is dependent on the number of simultaneous transmitting stations. This results from the two level (1023, - 1 ) autocorrelation function of an MLS. In drder to eliminate
"Xie/fE. Vot S7, No 1. Januerr/Febrvary1987
I Cyclic shift of 1023 bit MUS Additional Binary Z»ro
Fig. 3. Address code generation.
this residual effect the MLS sequences were modified to produce codes with (1024, 0) autocorrelation properties by the addition of an extra binary zero. The code for each station, therefore, becomes an MLS, cyclically bit shifted within its 1023 bit length, plus an additional binary zero which is transmitted as bit number 1024, as illustrated in Fig. 3. Each data bit is then encoded by the 1024 bit modified MLS.
The proposed network is based oti twisted or parallel pair cable; this is to maintain simplicity and allow new nodes to be connected to, or disconnected from, the network without unduly affecting other users. Figure 4 shows a simple system layout with a number of transmitting nodes and a single receiving node. The output from each node is added onto the line to produce a received waveform rit) (Fig. 5), which is a summadon of the outputs from each transmitter;
rit) = s,(t) + S2(r) + S3(t) + . . .s„it) n
rit) = X s„it) n = l
(5)
(6)
At the receiver the multi-level line signal r(() is multiplied by the receiver's own +1 level chip sequence Px(r) and from equation (2)
r(0p,(0 = 4(0+ E s„it)p,it) + n = l
+ t s„it)p^it) + Jit)pM (7)
where 1 < x < «. The first term 4 ( 0 's the recovered one-dimensional data signal and the last three terms are the multi-dimensional interference or jamming signals. The output from the analogue multiplier is subjected to low-pass filtering in the integrate and dump circuit in order to remove the unwanted high frequency components before being passed on to the decision circuit to determine whether this particular data bit represents a logic one or a logic zero.
In a completely asynchronous system, acquisition has two=stages, with both the code and the code phase being Vji^lepndata recovery. In the completely synchronous system adopted in our network the code phase search stage is eliminated since channel address codes are in a fixed phase relationship with the synchronization channel. The phase search stage is replaced, however, by a requirement to scan the locally generated address code over a time
.w'oicw.in.order to identify possible delayed versions of the" same code; this process is called traclcing using the 'sfidtag, cMFBlator^ method.^ The maximum propagation
delay in the system, therefore, determines the size of the window for tracking purposes and also the code allocation spacing since no two stations should be allocated codes which could be mistaken for delayed versions of each other within this tracking window.
Consider an example system with a tracking window of 2 bits. It would be necessary to allocate station addresses separated by more than 3 bits. Incremental tracking steps could vary from 1/4 to say 1/64 of a chip bit. The first would give rapid aquisition but only coarse tuning and a smaller 'noise margin'; the second would give much finer tuning but at the expense of aquisition time and the need to include a longer data packet synchronization preamble. A compromise figure of 1/16 bit would seem appropriate, representing the need for a preamble of 32 bits to each data packet. The practice of including a data packet preamble is common in most LAN systems. This figure of 32 tracking steps compares favourably with that which would be necessary if different codes were used for each address and all code phases had to be tested. The system in this example would work in a network up to 450 metres long at the present chip rate of 1-2288 MHz. The practicality of increasing the chip rate beyond this figure is being investigated.
In order to test phase synchronization aspects, a novel error generator which produces random errors at rates between 1 x 10"^ and 9x 10"' is used. This generator is capable of maintaining the error rates irrespective of the input data rate, which may vary from 1 Hz to 1-5 MHz. Tests with the prototype system have shown that the system reliably achieves phase synchronization within 40 ms, even with an error rate as high as 1 x 10''^, and that synchronization drop-out does not become a problem until the error rate reaches 2 x lO"'^.
4 Code Investigations Computer programs have been written to investigate the system coding aspects. These programs are designed to emulate (in non-real time) the ideal line drive characteristics of a 60 user system and have been written to investigate two areas of coding and code allocation:
(1) To ensure that transmission number x (where 1 ^ X ^ 60, see Fig. 4) will be successfully decoded when a number of simultaneous transmissions are taking place. A program emulating 60 nodes has been developed and the correlation properties investigated. This has verified the (1024, 0) correlation properties of the codes selected.
(2) To investigate the orthogonality properties of the codes used. This part takes the form of emulating a number of simultaneous transmissions (numbers i to n excluding x) and attempting to extract data using code p^it) (i.e. the code omitted). Up to 59
rf_(0
Fig. 4. Sfrnple system fayout'
A.-L SIMCOCK. C. NA RANONG & P. LEUNG: A-SYNCHRONIZED SPREAD SPECTRUM L.A.N: 19,
»1
-1
»i
- I
• 2 -
•1 "
-1 .
- 2 •
"1
1 .
-1
1
-
L
t
t
^
Fig. 5. Typical transmitter waveforms.
simultaneous transmissions have been demonstrated to create no mimicry problems, i.e. no combination of code transmissions from up to 59 stations looks like the code of the non-transmitting station x. These tests have been carried out with channel allocations based on code separations of 1, 5 and 10 bits, with the same results.
5 Prototype System Tests The system was configured as shown in Fig. 4 for the purpose of the preliminary bit error rate (BER) measurements. Three transmitters and two receivers were used. The first transmitter/receiver pair was used for the BER measurements and the second pair used to verify the simultaneous transmission capability, the third transmitter acting merely as an additional source of interference. Each transmitter, s^it) to Sjit), outputs a signal which represents the summation of +1 volt on to the transmission line, as illustrated in Fig. 5, In the absence of other signals, therefore, Si(f) would cause a ± 1 volt signal to appear at r(f). The upper trace in Fig. 6 shows the total composite signal rit) (see Fig. 4) when s^it), S2(t), Sjit) and J(£) (added white Gaussian noise (AWGN)) are all present. J(t) is band limited to 3 MHz. The signal-to-noise figures are actually signal-to-total-interference figures, S/I, and are the ratio of the signal r(£) due to s,(f) alone compared to that due to all signals other than Si(0-
mn
Fig';- frfhPBewwd signat' and recovered data.
Signals were measured with a true r.m.s. voltmeter the input to which was band limited to 3 MHz. The upper trace in Fig. 6 shows the composite signal r(f) at a Sfl ratio of — lOdB, and the lower trace shows the data recovered on channel 1. Figure 7 shows the preliminary results of the BER vs S/I Ratio measurements taken on channel I with channels 2 and 3 both transmitting and AWGN also present. This illustrates the system's ability to recover data in the presence of simultaneous multiple transmissions and external interference.
150 - \
140 -
130 -\
IZO -
no -100 -
»0 -
80 -
70 -
50 -
50 -
<0 -
30 -
ZO -
10 -
0 -
\
a
\ \
^ B - .
"^^^~ » ^
, , . — ^ II
S/l Ral io ( d S )
Fig. 7. BER vs S//ratio.
20
6 Conclusions By applying a CDMA spread-spectrum technique to the design of a local area network, a simple and error resistant network is being developed. Its main application will be either as a network in an electrically noisy environment or in a high throughput multiple access network. Computer studies carried out indicate that the system will be capable of supporting over 60 users transmitting simultaneously. Tests carried out on a prototype network consisting of 5 nodes (3 transmitting nodes and 2 receiver nodes) have verified the results predicted by the computer studies and demonstrated the feasibility of simultaneous multi-pair communications.
The next stages of the project will be to investigate alternative phase synchronization schemes and to determine the protocols necessary to control this type of system.
Whilst it is too early at this stage of development to make accurate predictions regarding the cost and reliability of the final network, the reliability of the low cost development modules has been encouraging.
7 Acknowledgments This research project is being supported by a grant from the Australian Telecommunications and Electronics Research Board.
8 References 1 Schoitz. R. A., 'The origins of spread-spectrum communications',
IEEE Trans on Communications, COM-30, no. 5, pp. 822-54, May 1982.
2 Smythe, C. S. and Spracken, C. T., 'A high speed local area network using spread-spectrum code-division-multiple-access techniques'. The Radio and Electronic Engineer. 54, no. 5, pp. 225-6, May 1984.
3 Dixon, R. C, 'Spread-spectrum Systems' (Wiley, New York, ! 976). 4 Holmo, J. K., 'Coherent Spread-spectrum Systems' (Wiley. New
York, 1982). 5 Pickfcoitz, R. L.. SchflKngt. D: L. and Milsttin. L. B.. 'Theory of _
spi«Ki'4pectrum communications—a tutorial'. /EEE Trans.. COW-30, no: 5,'lpp. 85y-8CWar I9«2. - • ~ " ~ - - -
J. lERE, Vol. 57. No. 1. January/February 1987
Sarwate, D. V. and Pursley, M. B., 'Cross-correlation properties of pseudo-random and related sequences', Proc. IEEE, 68. no. 5, pp, 593-619, May 1980. Gold, R., 'Optimal binary sequences for spread-spectrum multiplexing', !EEE Trans on Information Theory, IT-13, no. '4, pp. 619-21, October 1967. Bruce-Carlson, A., 'Communication Systems—An Introduction to Signals and Noise in Electrical Communication' (McGraw-Hill. Tokyo, 1981).
9 Pursley. M. B. and Sarawatc. D. P.. "Perrormance evaluation for phase-coded spread-spectrum multiple-access communications— part i r , IEEE Trans, COlVl-25, no. S. pp. 800-3. August 1977.
10 Hirosaki, B.. Hasegawa, S. and Sawai, A.. Spread-spectrum multiple-access data loop'. .V£C Res. & Dcv.. no. 71. pp. 48-58. October 1983.
Manuscript first received by the Inslitulion on 2Slh October I9S5 and in revi.vd form on 13th Mav I9M. Paper No. 2257JCOMM423
The Authors
A. L. Simcock
Alec Simcock graduated from the University of Kent at Canterbury with a BSc(Hons) degree in Electronics in 1972. He worked for 12 years with the Procurement Executive of the Ministry of Defence in the UK, researching in digital circuit design, digital data switching, computer controlled communication systems, and microprocessor replacement of digital circuits. The work also involved the implementation of software project management techniques. He was appointed to a Lectureship with the.Department of Electrical and Electronic Engineering, Footscray Institute of Technology in 1983.
C. na Ranong
Chula na Ranong received the BE(Hons) degree in Electrical Engineering and PhD from the University of New South Wales in 1970 and 1973 respectively. Since 1972 he has been with the Department of Electrical and Electronic Engineering, Footscray Institute of Technology, as a Lecturer and, later, Senior Lecturer in Digital Electronics and Systems. During 1977-78, he spent a year as a Visiting Professor at Cornell University, USA. Then, for the first six months of 1982, he worked as a Specialist Engineer with Compagnie Euro-peenne de Teletransmission (Thomson-CSF) in France developing a mass storage system for a real-time digital data network supervisory control system. More recently, as a result of his interest in Automation Technology, Dr Ranong spent two months in Japan in 1984 visiting government, industrial and educational research institutions.
Patrick Leung received the degrees of BE(Elect)and MEngSci in Electrical Engineering from Ihc University of Melbourne in 1 72 and 1974 respectively. Between 1975 and 1477 he was a Lecturer in the Department of Electrical and Electronic Engineering. Footscray Institute of Technology. In 1977 he joined Telecom Australia as an Engineer in the Datel design and provisioning section, but rejoined F.I.T. as a Lecturer in Communications Engineering in 1979. In the first half of 1985 he visited the Department of Electrical Engineering, Ottawa University, as a Research Fellow, to carry out work in data communications over satellite channels. On his return to F.I.T. he was appointed Senior Lecturer in Communications. His main interests are data transmission techniques, data networks and data protocols.
*. L SIMCOCK, C. NA RANONG & P. LEUNG; A SyNCHRONIZED SPREAD SPECTRUM C.A.N.
Conference on Computing Systems and Information Technologv 1987 Brisbane, 17-19 June, 1987
Protection, Rejection and Throughput Characteristics Of A Spread Spectrum Local Area Network
A.L. SIMCOCK Lecturer, Department of Electrical & Electronic Engineering, Footscray Institute of Technology
C. NA RANONG Centre for Automation Technology, Department of Electrical and Electronic Engineering Footscray
Institute of Technology
P. LEUNG Senior Lecturer, Department of Electrical & Electronic Engineering, Footscray Institute of Technology
SOV1MARY More and more infonratlon Is being stored on magnetic media, with Local Networks of computers sharing th i s data. Since some of th i s mater ia l wl 1 1 be v a l u a b l e to the owner It is necessary to protect the data, f i r s t l y against corrupt ion during transmission and secondly against prying or Intercept ion.
TTils paper descr ibes SOTT^ of the more per t inent features of a Local Area Nenvork being developed, by the Department of E l e c t r i c a l and Elec t ronic Engineering of the Footscray I n s t i t u t e of Techno 1 ogy, to address these j o i n t s . The th roughput c h a r a c t e r i s t i c s of t h i s LAN, based on Spread Spectrum t e c h n i q u e s , a r e a l s o
1 INTRCDUCriCN
The advent of the microprocessor has had a dramatic Impact on socie ty . The s ign i f i can t reduction in the c o s t of c o m p u t i n g power h a s r e s u l t e d In t he w idesca l e use of computers for a l 1 k inds of da ta nianlpulatlon and s torage . Magnetic storage devices such as floppy d isks have, to some extent , replaced paper as a means of i n t r a and i n t e r company da ta transfer. Local Area Networks (LAN) were pr imar i ly developed to a l l o w the s h a r i n g of expens ive resources, but t h e i r development has a l s o allowed the s h a r i n g of d a t a between i n t e r e s t e d p a r t i e s without the need to p h y s i c a l l y t ransfer the storage medlui).
The ever Increasing use of LANs has b r o u ^ t with i t one problem with two manifes ta t ions . The problem Is to p r o t e c t the d a t a . F i r s t l y , I t i s n e c e s s a r y to p r o t e c t the d a t a a g a i n s t i n t e r f e r e n c e , be i t d e l i b e r a t e or o t h e r w i s e , in o r d e r t o e n s u r e d e l i v e r y of c o r r e c t in fo rmat ion to the c o r r e c t user . If t h i s i s a c h i e v e d the LAN may be used wi th confidence in an e l e c t r i c a l l y h o s t i l e environment. Secondly, as more p r o p r i e t o r y in format ion i s a p p e a r i n g on d a t a b a s e s , i t i s b e c o m i n g i n c r e a s i n g l y n e c e s s a r y to protect the Information aga ins t p ry ing or I n t e r c e p t i o n . S o c i e t y h a s , indeed, become Information conscious to the extent tha t In format ion , t he a c q u i s i t i o n of i t and the protect ion of i t has become an industry in I t s own r igh t .
Various techniques are a l ready being used, or are under development, to address these problems. One communication t e c h n i q u e which looks to have the p o t e n t i a l to be of a s s i s t a n c e in both a r e a s i s c a l l e d Spread Spectrum (SS). The Department of E l e c t r i c a l and E lec t ron i c Engineering at Footscray
_ I n s t i t u t e of Technology Is developing a Local Area -^twotrk_based on these Spread Spectrim techniques.
2- CHARACTER I STI(^ OF SPREAD SPBCTRtM
Oie de f in i t ion of Spread Spectrun v^ich adequately r e f l e c t s t he ma jo r c h a r a c t e r i s t i c s of t h i s technique Is as f o l l o w s : -
"Spread Spectrun Is a means of transmission in which th© s i g n a l occupies a bandwidth i n
excess of the minimum n e c e s s a r y to send the i n f o r m a t i o n . The band s p r e a d i n g i s accompl ished by modula t ing the d a t a wi th a code, which i s Independent of the d a t a . A synchronised vers ion of the same code is then used at the rece iver in order to despread the s ignal and f a c i l i t a t e data recovery."
There are three primary methods of achieving th i s bandwidth spreadIng:-
a) D i r e c t Sequence - In which t h e d a t a i s d i r e c t l y modulated with a fast pseudo random code sequence.
b) Frequency Hopping - in which the c a r r i e r which i s modu la t ing the da ta i s caused to hop from one frequency to another in a pseudo random manner.
c) Time Hopping - which may be l i k e n e d to the pseudo random a l l o c a t i o n of channels In a Time Divis ion Mult iplexed (TDM) system.
Data Source
ol(t) r ( t ) X
p<t)
pseudo randoh
sequence generator
i. U
I n t e g r a t e %, dunp
pseudo randon
sequence generotor
Transmitter Receiver
Figure 1 Ctotnponents of a SS Comiunlcat Ions System
F i g u r e 1 i l l u s t r a t e s a t y p i c a l s i n g l e channel d i r e c t sequence system. The data d(t) i s m u l t i p l i e d by the ch ip sequence p( t ) c r e a t i n g a r e c e i v e d s i g n a l , r ( t ) of the following form:
r ( t ) = d ( t ) p ( t ) (1)
i4e
T h i s s i g n a l i s r e - m u l t i p l l e d by a synch ron i sed version of the chip sequence in order to c o l l a p s e ^ the s i g n a l back into the data s i g n a l ' s bandwidth |
1 " — 4
and a l low data recovery
r ( t ) p ( t ) = d ( t ) p 2 ( t ) (2)
And, s i n c e p ( t ) = +^1, p2 ( t ) » 1 t h e r e f o r e
r ( t ) p ( t ) = d ( t ) (3)
It may seem s t r a n g e to d e v i s e a t r a n s m i s s i o n system which in ten t iona l ly uses more bandwidth than necessa ry , but the v e r y n a t u r e of the Spread Spectrum s i g n a l c h a r a c t e r i s t i c s imparts at l e a s t five Inportant perfonnance a t t r i b u t e s : -
1) Low Probabl 1 1 ty of I n t e r c e p t (LPI). This can be achieved with the use of a high processing gain and unpredictable c a r r i e r s i g n a l s , which r e s u l t in power be ing sp read t h i n l y and un i fo rmly over the s p e c t r a l bandwidth. Th i s makes d e t e c t i o n a g a i n s t background noise , by a s u r v e i l l a n c e r ece ive r , very d i f f i cu l t . A Low P r o b a b i l i t y of Posi t ion Fix (LPPF) a t t r ibu te goes one s t ep fur ther in inclixiing both In te rcep t and D i r e c t i o n F ind ing (DFing) in i t s evaluation. Low P r o b a b i l i t y of Signal Explo i ta t ion (LPSE) or g i v i n g a l l s t a t i o n s a U n i v e r s a l Transmi t te r F i n g e r p r i n t (UTF) o f f e r a d d i t i o n a l b e n e f i t s in t h a t s i g n a l I d e n t i f i c a t i o n and e x p l o i t a t i o n p o s s i b i l i t i e s a re den ied to the interceptor,
1 i) Ant i jam capabi 1 i t i e s can be ga ined wl th the use of an unpredic tab le c a r r i e r s igna l . Ihe jammer cannot use s i g n a l o b s e r v a t i o n s to improve i t s performance, and must r e l y on janming t echn iques which are independent of the signal being jarnned.
i l i ) High time r e s o l u t i o n i s a t t a i n e d by the c o r r e l a t i o n d e t e c t i o n of wide band s i g n a l s . Di f ferences in the Time Of A r r i v a l (TOA), of the wide band s i g n a l , in the order of the reciprocal of the signal bandwidth, are de tec tab le . This property can be used to suppress mul t ipath and, at the same time, render r e p e a t e r jammers i n e f f e c t i v e or minimise the e f f e c t s of r e f l e c t i o n s , caused by impedance mismatches in cable systems.
iv) T r a n s m i t t e r R e c e i v e r pa i r s using independent pseudo raiKlom c a r r i e r s can operate concurrent ly in the same bandwidth w i t h minimal i n t e r - c h a n n e l i n t e r f e r e n c e . These a r e c a l l e d Spread Spectrum Mult iple Access (SSMA) or Code Divis ion Mul t i p l e Access) sys tems .
v) Cryp tograph ic c a p a b i l i t i e s r e s u l t when the data modula t ion cannot be d i s t i n g u i s h e d from the car r ie r modulation, and the c a r r i e r modulation is e f fec t ive ly random to an unwanted observer. In th i s case the SS c a r r i e r modulation takes on the r o t e of a key in a C i p h e r s y s t e m . A s y s t e m u s i n g indis t inguishable data and SS c a r r i e r modulation is a form of pr ivacy system.
These a t t r i b u t e s may be s e e n to c o v e r many appl ica t ions and have been ex tens ive ly explo i ted in the m i l i t a r y env i ronment , where f a c t o r s such as Antijam and a Iftiiversal Transmitter Fingerprint (i and 11 above) have p a r t i c u l a r s igni f icance . These are not, neces sa r i l y , the factors of i n t e r e s t when the q u e s t i o n of d a t a p r o t e c t i o n in a LAN i s t o be addressed, features such as interference r e j ec t ion ,
.a mu l t i u s e r c a p a b i l i t y and p r i v a c y ( a t t r i b u t e s [M^ii . - iv and v above) a r e of g r e a t e r i n t e r e s t and
wi l l he considered fur ther .
3 PBOTECriCti PROPERTIES
1) Be easy to generate 2) Be random in nature 3) Have a long period 4) Be d i f f i c u l t to reconstruct from a short
segment.
Both cryptographic and SS codes require p roper t ies 1, 2 and 3 but they have d i f f e r e n t r e q u i r e m e n t s w i th r e s p e c t to p r o p e r t y 4. A good c r y p t o g r a p h i c code s h o u l d be d i f f i c u l t (a lmost imposs ib l e ) to r e c o n s t r u c t from a s h o r t segment, in o rde r tha t d a t a r e c o v e r y by anyone o t h e r than the Intended r e c i p i e n t shou ld be as d i f f i c u l t as p o s s i b l e . SS sys tems , on the o t h e r hand, r e q u i r e tha t the t ransmi t te r and rece iver have synchronised codes to f a c i l i t a t e the bandwidth co l l aps ing necessary for data recovery. This means that the rece ive r should be able to synchronise the l o c a l l y generated code to that of the t ransmi t te r , and in order to do th i s in a p rac t i ca l amount of time i t should be poss ib le to r e g e n e r a t e the code from a r e l a t i v e l y s h o r t segment. From th i s point of view, therefore, SS and cryptographic codes have con f l i c t i ng requirements. C r y p t o g r a p h i c and SS p r o t e c t i o n a r e n o t , f o r t u n a t e l y , m u t u a l l y e x c l u s i v e as SS codes do provide protect ion against the casual eavesdropper.
The act of spreading the data causes the frequency spec t rum of the t r a n s m i t t e d Informat ion to be changed from t h a t shown In F igure 2 (which i s the spectrun of the data , d(t)) to that shown in Figure 3 (which i s the spectrum of the spread d a t a , d ( t ) p ( t ) , wi th the ch ip sequence, p ( t ) , h a v i n g a f requency of f^). This ac t has b e n e f i t from two p o i n t s of view, f i r s t 1y the r e c e i v e r must remove the s p r e a d i n g e f f e c t of the ch ip sequence , i e . dec ryp t the t r a n s m i s s i o n , In o rder to o b t a i n the o r ig ina l data , and secondly the actual magnitude of the s ignal is very much reduced; poss ib ly into the n o i s e t h r e s h o l d r e g i o n . T h i s means t h a t t h e r e c e i v e r must h a v e b o t h t h e code and t h e SS demodulation equipment to recover the data.
- f c - f d f d f c
Figure 2 Spectral Occupancy of Data Signal
Spread doto signol pC-t)dCt)
The protection and rejection properties inherent in SS systems come from the codes used to spread the data. For cryptography the ideal code should:-
Figure 3 Spectral Occupancy of Spread Data Signal
Maximal Length Sequences (MLSs) and Gold codes are p r o b a b l y the most common codes for use in SS sys tems . MLSs c e r t a i n l y have the a p p r o p r i a t e p rope r t i e s with respect to synchronisation e tc . in SS systems. Ihe two level au tocor re la t ion function of the MLS makes s y n c h r o n i s a t i o n a r e l a t i v e l y s t ra ightforward mat ter and the code is r e l a t i v e l y
raafcuj-- 147
long i e . t h e code l e n g t h , N, i s g i v e n by 2" - 1, where n Is the number of s h i f t r e g i s t e r s in the generator function. Even if the code is r e l a t i v e l y long, however , s y n c h r o n i s a t i o n can be ob t a ined r e l a t i v e l y q u i c k l y , If n = 100 such t h a t the code l eng th N = 2^"" - 1 » lO'^", i t would s t l 1 1 be p o s s i b l e to r e c o n s t r u c t the e n t i r e sequence from only 198 b i t s by s o l v i n g 198 l inea r equations, not a d i f f i c u l t task for a computer.
For mul t i -use r a p p l i c a t i o n s , however, MLSs are not ideal s ince the cross c o r r e l a t i o n between MLSs of the same l e n g t h (but g e n e r a t e d from d i f f e r e n t polynomial expressions) can vary widely. (Sold codes a r e g e n e r a t e d in " f a m i l i e s " and t h e c r o s s co r r e l a t i on between d i f f e ren t codes within the same family is p r ed i c t ab l e and subject to i den t i f i ab l e bounds. Gold code g e n e r a t i o n Is i l l u s t r a t e d in Figure 4. F igu re 4a shows how a sequence may be formed from a Linear Feedback Shift Register (LFSR) of degree 10 which g e n e r a t e s a sequence of pe r iod 2^ - 1 = 31, from the generator polynomial
x 10 + x ' + X + 1
,10 since there are V" - 1 s t a t e s , the number of different sequences, ie.
poss ib le non-zero I n i t i a l s t a t e s which r e s u l t in
the nunber of codes in the 1) = 2^ + 1 = 33. F igure
4b I l l u s t r a t e s the same Gold code f ami ly being generated from two independent 5 b i t LFSRs,
fami ly , i s <2^'^ - l ) / ( 2 ^
' l = X + x*" + X + 1
and F2 = X = x^ + x" + 1
the outputs of which are modulo 2 added to form the output code. The actual code generated, out of the family of codes, i s dependent on the r e l a t i v e phase of the two 5 bi t LFSRs.
should. I d e a l l y , tie completely orthogonal Init, even if the codes themselves are orthogonal , in r e a l i t y a m p l i t u d e and phase d i s t o r t i o n w i l l cause some i n t e r f e r e n c e in the demodula t ion p r o c e s s be ing ca r r i ed out by the receiver .
E x t e r n a l i n t e r f e r e n c e , J ( t ) , may a l s o be p r e s e n t , as I l l u s t r a t e d In f i gu re 5. Equat ion 3 does not i n d i c a t e the f u l l p i c t u r e which, w i th s e v e r a l s t a t i o n s t r a n s m i t t i n g and In the p re sence of e x t e r n a l i n t e r f e r e n c e . Is more r e a l i s t i c a l l y represented by
r ( t )p j j ( t ) IC-I
^x^t) •K2px ( t )sn ( t )
+ y p ^ ( t ) s n ( t ) + j ( t ) p ^ ( t ) (4)
Where Sr,(t) = d „ ( t ) p „ ( t ) 'n n ' ^Pn' and 1 < X .< n
The first term, djj(t), occupies the bandwidth of the data signal, i^, see Figure 2. The remaining three terms occupy a much greater bandwidth appropriate to the chip sequence frequency, f,,, see Figure 3. By filtering out the high frequency components it is possible to leave only the data signal d^(t).
dK-t)
d8<t)
*i<-i)
dxa)
Neither Gold codes nor MLSs are p a r t i c u l a r l y good cryptographic codes, but i t is poss ib le to design a SS s y s t e m w h i c h u s e s s h o r t e r c o d e s f o r s y n c h r o n i s a t i o n a n d , h a v i n g a c h i e v e d synchronisation, then r e v e r t s to the use of a code with b e t t e r c r y p t o g r a p h i c p r o p e r t i e s for a c t u a l da ta s p r e a d i n g . Cross c o r r e l a t i o n proper t ies in a mul t i -user environment would, however, s t i l l have to t)e considered.
^3MHH>O-{HHH^ (a)
^
4^ <^ ^
(b)
; ^ j \ ; . ; : ." -Figure 4 Gold Code CJeneratlon
4 REJECriCN PROPERTIES
The c i r c u i t shown in Figure 1 represen t s the ideal case. Figure 5 I l l u s t r a t e s a more r e a l i s t i c system. Bach of thfr 'n ' t r a n s m i t t e r s has been a l 1ocated a code for data spreading purposes. TTiese codes
Figure 5 Rea l i s t i c System Model
I t can be seen , t h e r e f o r e , t ha t u s i n g more ch ip b i t s t o r e p r e s e n t each d a t a b i t s p r e a d s t h e unwanted s i g n a l s over a much wider bandwidth, with an acconpanying reduction in magnitude, thus making the f 1 1 t e r i n g more e f f e c t i v e . The number of ch ip b i t s per data b i t is c a l l e d the Processing Gain of the system. The Processing Gain g ives an indicat ion of the interference re ject ion c a p a b i l i t i e s of the sys tem, but the t rue f igu re of me r i t a l s o depends on the SNR of the f i l t e r and on the codes used. For a given Processing (jaln i t is poss ib le to have one long sequence modula t ing the d a t a , or to have severa l r e p e t i t i o n s of a s h o r t e r sequence . S ince , however, the spacing of the spec t ra l l i ne s , Af, is given by f^/N, a long sequence wl 1 1 have many 1 ines c l o s e l y spaced , and a s h o r t e r sequence wl 1l have fewer l i n e s f u r t h e r a p a r t . This i n d i c a t e s t h a t a long sequence should g ive b e t t e r r e s u l t s than a short sequence.
5 THE FIT SYSTEM
The sys tem be ing deve 1 oped a t FIT u se s the Di rec t S e q u e n c e method of d a t a s p r e a d i n g , and Is connected using a Bus Topology, as shown in Figure 6. A Code Divis ion Mul t ip le Access (C3DMA) mechanism is used to al 1 ow mul t l -use r access. In t h i s type of sys tem each node I s a l l o c a t e d a unique ch ip sequence as i t s "address code". Data interxled for a node must be modulated with the "address code" for t h a t p a r t i c u l a r node, thus If Node »1 wishes to communicate wi th Node #3 then i t s d a t a must be m o d u l a t e d w i t h t h e code f o r Node # 3 . Codes a l l o c a t e d to each node are b i t sh i f ted vers ions of the one modif ied MLS, and the whole system i s
14»
synchronised by means of a separate sync channel. THOXUPUT CHARACTER ICT ICS
The sys tem be ing d e v e l o p e d at FIT a l s o o f f e r s a s e c u r i t y , f a c i l i t y by the v e r y n a t u r e of i t s construct ion. In t h i s synchronised system the delay time between one Node and ano the r i s f i x e d , and cou ld be v a l i d a t e d , thus any p a r t y w i sh ing to Inject mis-information into the system by posing as a va 1 id u s e r would have to be c o - s i ted wl th t h a t u se r , or emu la t e the i n t e r -node d e l a y p r o p e r t i e s exact ly .
Data line
Figure 6 Bus-Connected System Topology
A prototype system s imi l a r to that i l l u s t r a t e d In F i g u r e 5 h a s been b u i l t f o r t h e p u r p o s e of preliminary Bit Error Rate (BER) against Signal to Noise (S/N) measurements; where Noise is used to r e p r e s e n t t o t a l i n t e r f e r e n c e , le e x t e r n a l interference J ( t ) p lus interference caused by other nodes t r a n s m i t t i n g s i m u l t a n e o u s l y . T h r e e t ransmit ters and two rece ive r s were used. The f i r s t t r ansmi t t e r / r ece ive r pa i r were used for the BER vs S/N measurements. The second t r ansmi t t e r / r ece ive r p a i r was u sed t o v e r i f y t h e s i m u l t a n e o u s t r a n s m i s s i o n c a p a b i l i t y , the t h i r d t r a n s m i t t e r a c t i n g m e r e l y as an a d d i t i o n a l s o u r c e of interference.
Figure 7 shows pre 1 iminary r e s u l t s of the BER vs S/N R a t i o measurements . The p r e l i m i n a r y r e s u l t s obta ined from the p r o t o t y p e system have v e r i f i e d the concept of a synchronous LAN using b i t shif ted modified Maximal Length Sequences as the address codes. Data r e c o v e r y has been demons t ra t ed , wi th the e r r o r r a t e s i n d i c a t e d in F i g u r e 7, t h u s 11 lus t ra t ing the po ten t i a l of such a system for use in an e l e c t r i c a l l y noisy environment.
DIT ElUCn BATE vs S/N RATIO
- U -10
The modi f i ed MLS codes were chosen to g e n e r a t e as l i t t l e co-channel interference as pos s ib l e , i t is assumed t h a t each (CDMA) c h a n n e l ' s t r a f f i c may be r e g a r d e d a s i n d e p e n d e n t in o r d e r to model i n d i v i d u a l channel throughput c h a r a c t e r i s t i c s . Whl1 St each channe1 's t r a f f i c may be rega rded as Independent i t is p o s s i b l e to have c o n t e n t i o n w i t h i n an I n d i v i d u a l channe l . Th i s c o n t e n t i o n i s h a n d l e d by a mechanism s i m i l a r to C a r r i e r Sense Mul t i p l e Access with Col I ision Detection (CSMA/CD). The spec i f i c channel address code is the "car r ie r" tieing sensed in th is case.
The t e c h n i q u e s used in the d e r i v a t i o n of t h i s th roughput model a re based upon those used by Kleinrock and Tobagi. The fu l l development of the model i s o u t s i d e the scope of t h i s paper but the f i n a l t r a f f i c throughput , S, in terms of the offered t r a f f i c , G, and the busy sensing period, a, is given by
_Ge -aG (3aG + (e~^°(2 + G 3aG - e~^°)))
(5)
Figure 8 i s a graph of S vs G, and s e v e r a l c u r v e s are included in order to represent d i f fe ren t va lues of a. These curves show the expected c h a r a c t e r i s t i c shape with the throughput increasing as the offered t r a f f i c i n c r e a s e s u n t i l a b r eakpo in t i s reached. Above t h i s po in t the p r o b a b i l i t y of c o l l i s i o n s o c c u r r i n g i s such tha t i n c r e a s i n g the o f f e r ed t r a f f i c a c t u a l l y causes a reduction in throughput as the channel capacity is p rogres s ive ly taken up with more retransmissions and less new t r a f f i c . It can be seen from Figure 9 t ha t the busy s e n s i n g t ime i s a h i g h l y i m p o r t a n t p a r a m e t e r in t h e th roughput model and that r educ ing t h i s s e n s i n g t ime c a u s e s the breakpoint in throughput to occur at higher l e v e l s of offered t r a f f i c .
The throughput c h a r a c t e r i s t i c s of t h i s model a r e compared wi th those of some of the more fami 1 i a r m u l t i - a c c e s s p r o t o c o l s in F igure 9. These c u r v e s a r e p l o t t e d us ing a v a l u e of a = 0.01, except for the two Aloha protocols which are independent of a. In the Non-persistent and 1-persls tent CSMA models the v a l u e of a represents the propagation delay in the system, ra ther than a busy sensing period as in t h i s model , but in a l l t h r ee models a g i v e s a r e p r e s e n t a t i o n of the ' v u l n e r a b l e p e r i o d ' for transmission modelling purposes. These curves show the comparison t)etween the FIT system model, which has been developed for a LAN app l i ca t ion , and other p ro toco l s (most noticably Aloha and S lo t t ed Aloha) v^^ich were not. The indication is that app l i ca t i on spec i f i c protocols can offer throughput advantages.
S/N Italio (cU>)
Figure 7. BER vs S/N Ratio Figure 8. Throuf^put vs Offered Traff ic
149
i ....
Figure 9. Comparison of Throughput Cha rac t e r i s t i c s
7 (XNCLUSIO^S
The app l ica t ion of CDMA, spread spectrum techniques to the design of a Local Area Network can r e s u l t In a s y s t e m w i t h i n h e r e n t d a t a p r i v a c y c h a r a c t e r i s t i c s , which i s r e l a t i v e l y s imple and a l s o h a s s i g n i f i c a n t e r r o r r e j e c t i o n c h a r a c t e r i s t i c s .
A system of t h i s n a t u r e c o u l d , t h e r e f o r e , be used where no i se r e j e c t i o n in an e l e c t r i c a l l y n o i s y environment i s of prime concern , or to p r o v i d e va l ida t ion and p r ivacy fo r v a l u a b l e Informat ion .
Whatever the a p p l i c a t i o n the throughput model Indicates that th i s type of system provides a 'high a v a i l a b i l i t y " system for mul t i -user environments.
8 ACKN3WLEDGEMENTS
This research project ts being supported by a grant from t h e A u s t r a l i a n T e l e c o m m u n i c a t i o n s and E lec t ron ics Research Board.
9 REFERENCES
DlX(a^, R.C. (1976). "Spread Spectrun Systems. New York, Wiley.
HOLMES, J.K. (1982). Coherent Spread Spectrum Systems. New York, Wiley.
KLEINROCK, L. and TOBAGI, F.A. (1975). Packet Switching in Radio Channels : Part 1. I.E.E.E. Transactions on Conmunicat Ions. Vol-23, pp 1400-1416.
PICKHOLTZ, R.L., SCHILLING, D.L. and MILSTEIN, L.B. (1982) Theory of Spread Spectrum Coninunlcat ions - A Tutorial. I.E.E.E. Transactions on Conrnunlcations. Vol. OCM-30, pp. 855-884.
SCHOLTZ, R.A. (1982). The Origins of Spread Spectrun Ctonmunl cat Ions. I.E.E.E. Transactions on Coarnunlcations. Vol. CCM-30, No 5, pp. 822-854.
SKAUG, R. and HJELMSTAD, J.F. (1985). Spread Spectrum in Communications. Peter Peregrinus.
Tsa
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•ri,c l' ^"'" t^f A spread-spectrum manufacturing information network by A.L. Simcock, C. na Ranong and P. Leung This paper concerns the development and implementation of a totally integrated, computerised manufacturing environment. This concept has been called by a number of buzz-words or phrases: computer integrated manufacturing (CIM), flexible manufacturing system (FMS), integrated manufacturing system (IMS). Whatever it is called most Australian manufacturers will come across it in the next few years, and the rapidity of the absorption of the CIM concept may well decide the future of Australia as a manufacturing country.
Introduction Footscray Instrtirte of Technology is developing a computer interconnection system, or local area network, the architecture of which makes it particularly suitable for use in the type of environment often found in a manufacturing environment. A description of the background and development of the concepts of CIM would, however, be useful in order to pi/t into proper perspective the system being developed.
History of MAP Several years ago General Motors realised the need for a multivendor local area network (l-AN) for factory automation. The scale and complexity of machinery and computers needed on the factory floor was so vast that no single manufacturer could provide all the required equipment. This state of affairs led to the fonnation of islands of automation, as shown in figure 1, unable to communicate on any type of global scale. To remedy this
PLC_ / PLc/s»nsof\cNC; yobot
factofy floor
Figure 1 : Islands of automation
situation GM set about defining a true multivendor LAN, basing it on existing standards and protocols where appropriate. Where gaps existed GM worked with Ihe standards committees and other interested parties (o fiil these gaps. The outcome of this was GM's manufacturing automation protocol (MAP). The public first became aware of the benefits at the Las Vegas National Computer Conference in July 1984, where the first demonstration of inter-vendor interoperation took place using GM's MAP. Only seven companies took part; Allen Bradley. Concord Data Systems, DEC, Gould, HP, IBM and Motorola. By the time the second public demonstration occurred, in November 1985 at the Autofact 85 exhibition in Detroit, 21 companies were demonstrating equipment operating with GM's MAP. This sparked off enormous interest- in MAP and now user groups are springing up all over the US, Europe and Japan. Two "interest groups" have also been formed in Melbourne and Sydney.
The requirement To achieve an integrated manufacturing system it is necessary to be able lo take tliese Islands of automation and connect them together in an orderly fashion, so that they are no longer isolated but form part of a coherent network, as shown in figure 2, resulting in factory-wide automation. This is not the end of it, however, as other sections within the company could benefit from
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being incorporated Into the network. With this in mind the Society of Manufacturing Engineers produced the computer integrated manufacturing or CIM wheel, figure 3. This represents a company-wide networking requirement. Many of the interactions are obvious eg machine scheduling, manpower, production rates etc. Some of the other interactions, though not as obvious, may be equally crucial to company profitability. The goods inward, stores receipts and purchasing department interaction may well mean that less capital could be tied up in raw materials and cash flow/liquidity improved by exercising better control over
stock and re-order levels etc. ff this sounds familiar, it should do, because this is precisely the type of control needed to implement zero Inventory or just-ln-llme procedures.
How It Is achieved Computers around fhctory may be combined encompassing both the manufacturing automation protocol (courtesy of GM), coupled in with the technical office protocol (TOP), which was pioneered by Boeing. The combination of the two makes factory and administratton internetworking
Figure 2: An integrated network
Figure 3: The Society of Manufacturing Engineers' CIM wheel -
Capyrighi 1985 CASA/SME. 2nd edilicm. mvised Nov 5 1985
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possiW© this wealing company-wide Integration. In order to establish data transfer, control and communteation the computers are connected together into a network- This can be accomplished in several ways. If there were only two computers A and B (commonly called stations or nodes) they could be connected in what is called the point-to-point configuration (or topotogy), as in figure 4a. This is impractical with more than two nodes and other topologies must be considered. Each topology has its problems, both the ring and the star, f»gures 4b and 4c, are subject to significant disruptton in the event of even a single point failure. The bus, figure 4d, is not affected in the same way but informatksn could he lost if two or more nodes attempt to transmit simultaneously; there are, however, protocols to minimise this problem. MAP and TOP use two different protocols to handle the contentton problem.
MAP and TOP specifications MAP and TOP have both l>een recognised by the IEEE as worthy of support in the form of standards publication and classification. This means that any supplier can obtain a copy of the standard and produce equipment satisfying the requirements. Table 1 lists some of the more imporlant features of both MAP and TOP. Both MAP and TOP are designed to implement the International Standards Organisation open systems interconnection seven-layer model for a communications network.
shown in figure 5. The lower 3 layers have been fully defined to the point where most, if not all, features have been agreed. Layer 4 is almost at the same general acceptance level. These tower layers are designed to provide reliable end-to-end system communicatkins. The upper 3 levels, however, have not been defined to anywhere near the same degree, but are intended to provide for the encoding rules, data formats etc necessary to ensure usable information transfer between application processes. GM has been concentrating on level 7, in order that user program interfaces may be agreed, thus altowing independent software producers a fixed point of reference when writing packages designed for MAP implementation.
The FIT LAN system Having illustrated a little of the background, and introduced MAP and TOP, It is possible to put Ihe LAN being developed at Footscray Institute of Technology in true perspective. The FIT LAN system should not be seen as a universal replacement for MAP, rather it should be considered more in the light of augmenting MAP by altowing networks to be implemented in areas which might otherwise be considered too hostile. By hostile I refer to electrtoal hostility such as noise or interference. A great deal of work has gone info the analysis of electrical noise and many factories could be classified as very noisy. Prime culprits are heavy rotating machinery, arc welders etc, the effects of which could
contention handling
topology
bandwidth
transmission medium
IEEE Standard
MAP
token passing
bus
broadband
co-axial cable
802.4
TOP
CSMA/CD
bus
baseband
co-axial cable
802.3
Figure 4: Network topologies Table 1: IWajor MAP and TOP features
Alex SiTKOck graduatad from <ha Un/irersity of Kant at Cantartxjry iWtf) iho BSc(Hons} (eharonks) m 1972. He woiiied hr 12 years tw'tfi Pmcuramenf Exoculrya ol Ifm Ministry ol Delence in Britain, researching in me Mowing areas: digital drcuil design, digital data swItcHng. computer-controlled communication systems and microprocessor replacement ol digital drculs. The work also involved the Implementalion ol software project management techniques. He was appointed to a lectureship with the depanment ol elearical and electronic engineering. Footscray Institute of Technology, in 1983.
Chula na Ftenong received the BEfHons) degree in electrical engineering and PhD from the University of New South Wales in WTO and 1973 respec^ety. Since 1972 he has t>een with the department ol electrical and electronic engineermg, Footscray Institute ol Tachnology as a lecturer and later, senior lecturer in digital electronics and systems. During 1977-78, he spent a year as a visiting professor school ol electrical engineering. Cornell University, Ithaca, New York. US. Then, lor the first six months ol 1982, he worked as a sp^allst engineer with Compagnie Europaene de Teletransmission (Thomson-CSF). Chaiou. France, devetopmg a mass storage system lor a real-time digital data network supervisory control system. More recently, as a result ol Ns interest in automation technology, Chula undertook a two-month study visit to Japanese government, in(*jslrial and educaional research institutions in 1984.
Patrkk Leung received # » BEfElecp and MEngSc in elearical engineering from the University of Meltxjume in 1972 and 1974 resoectlvefy Between 1975 and 1977 he was a lecturer in the department of electrical and eleclronlc engineering, Footscray Institute Of Technotooy In 1977 he joined Telecom Australia as an engineer in the Datel design and provisioning section, m 1979 he rejoined FIT MS a lecturer h communications englnoering. In the first hall of 1985 he visited the department ol electrical engineer^ Ottawa UnlvenltY, as a research fellow, to carry out wori^ In data communications over satellile channels. On hs return to FIT he was appointed senior lecturer In communications. Hs mam mierests are data transmission techniques, data networi^s and data protocds
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Meelunieal Celhg* Tttmical (Report Engineers Australia August 7 1987 3
User program Application programs (not part of the OSI model)
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nn
ac
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ter
Manages lower-layer Application O services, including
application programs
Restructures data to and from Preserrtation ' * standardised format used
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Figure 5: Open systems in terconnect ion (OSI) seven-layer model
create havoc with computer communcations. A whole subculture has grown up around the design of equipment and transmission systems whtoh are resistant to electromagnetic interference (EMI), and/or producing equipment which transmKs a minimum of interfering signals, in other words designing equipment for electromagnetic compatibility (EMC). Most of the detailed EMC research has been earned out in the military field and it is this same environment which spawned the techniques upon whtoh our system is based. These techniques, called spread spectrum have been defined as "a communkatton system whtoh transmits data using a much greater bandwidth than the minimum necessary". This might seem a little strange at first but it works like this. Each data bit, see figure 6a, (at a frequency fd) is spread across a much wider spectral bandwtoth by multiplying it with a fast pseudo-random (commonly called the chipping sequence) running at a frequency of fc, figure 6b. At the receiver the resultant signal is re-multiplied by the same chipping sequence thus recovering the original data by collapsing the signal back into the bandwidth of fd, ie that of the data signal. This act of multiplication at the receiver has the effect of spreading any interference signal over the chip sequence bandwWth, thus altowing the data to be recovered by a filtering process. Rgure 7 illustrates the concept of noise rejectton in a spread-spectrum system. If the data was transmitted in its original form them a noise spike could completely swamp the data signal, as shown in figure 7a, thus causing an error. If this same noise spike were to interfere with the spread-data signal, however, then only a small portfon of the informatfon content wouW be tost, as shown in figure 7b, and it wouW be possible to recover the original data signal without error, tn this manner the act of spreading the data for transmission imparts inherent interference rejectton capabilities to the
...,J [ c 6 6
(a)
'c
spread data signal rtt)d(t)
__,..-—'—
•
•fc - 'd f .
(b)
'c
Figure 6: Data and "spread data" frequency characteristics
data d(t|
(a)
spread data signal p(l)d(t| i
S
(b)
Figure 7: No ise re ject ion i l lustrat ion
transmission. This type of system is, therefore, parttoularly suitable when error-free communication in a hostile environment is the primary objective.
Multi-user system The FIT system is connected using a bus topology, as illustrated in figure 8. Each node in the network is allocated a unique code for its chipping sequence, which acts as an address for that node. Thus if node 2 wishes to transmit to node 5 then it should encode Its data for transmission with the chipping sequence for node 5. By carefully selecting the codes which are used for the chipping sequences it is possible to have many messages being transmitted simultaneously, with each transmisston causing little or no interference to the others. This system is called code division multiple access (CDMA), The more traditional methods of multi-access ie time division multiple access (TDMA) and frequency division multiple access (FDMA) are, ft is true, more efficient in their use of bandwidth. These mechanisms operate with fixed time or frequency slots, however, and do not offer the same random access addressing capabilities that are offered by CDMA neither do they have CDMA's inherent interference rejection capabilities.
Prototype system tests A simple prototype system has already been built, with three transmitters and two receivers. With this prototype system we have t)een able to demonstrate the viability of simultaneous multiple transmisstons. Tests have also been carried out to prove the error rejection capabilities, and preliminary results indicate that it is possible to recover data from the transmission medium even when the signal transmitted is subjected to interference by sources of 20 times the power. These preliminary results clearly demonstrate the potential which the FIT system has to carry computerised manufacturing information in a hostile environment.
Conclusions The MAP concept is not fully mature, and the present positton may well define only a subset of future systems. This is precisely where MAP illustrates one of its major .features; even if MAP is expanded, present systems will not be obsolete as they will be fully compatible subsets of the expanded system. Thus users need not have a daunting inrtial capital outlay in order to use a MAP system. They can buy for their present needs and rest assured that they will be able to update as their needs devetop, and that they will be able to select MAP components from many manufacturers, thereby excluding obsolescence and altowing the selection of the most suitable item for the job..AH of
Mechanical Co/leg» Technical fleport Engineers Australia August 7 1987
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ie 1
host cc
1 sync line
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node 4
mp
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I
Figure 8: Bus-connected system
these points guarantee that MAP will stay and develop in importance. More and more will be written about computer integrated manufacturing and MAP in the near future, in fact it could be said that this Is the future for Australian industry. This includes both components of industry, the system users such as car manufacturers etc, since it won't be too tong before almost all manufacturing equipment purchased wilt have a MAP interface, and also the machine tool manufacturers, since it will be impossible to sell such tools unless they are supplied with a MAP interface. In fact Boeing has already issued a policy statement indicating that preference will be given t a suppliers who have TOP systems. The future is not all that far away as a target window of 1987 has been identified. Before this date producing MAP-compatible equipment may prove too costly, but leaving it too tong after this date could mean that
Australian manufacturers may well miss the boat. We believe the system which we are designing could complement the MAP system, thus ensuring hostile environment operation, and in doing so may prove a valuable tool in generating a manufacturing-led recovery to extract Australia from the current depresston.
Acknowledgements This research project is being supported by a grant from the Australian Telecommunicattons and Elecfrontos Research Board.
References Gold R. (1967), "Optimal binary sequences for spread spectrum multiplexing". lEE Transactions on Information Theory, Vol IT-13, pp619-621. Hirosaki B., Hasegawa S.. Sawai A. (1983), "Spread spectrum multiple access data loop", NEC Res Dev n71, October pp48-58. Holmes J.K. (1982), -Coherent spread spectrum systems". Wiley (New York). Ptokholtz R.L. Schilling D.L. Milstein LB. (1982), "Theory of spread spectrum communtoations - a tutorial", IEEE Transactions on Communtoattons, Vol Com-30, May, Schoitz R.A. (1982), "The origins of spread spectrum communications'. IEEE Transactions on Communtoations. Vol Com-30 May. Watt D.G. (1985). "Networking software support for FMS", Manufacturing Engineering. September, pp103-106. Weber D.M. (1985), "Technology update: manufacturing -more versatile tools speed factory automation", Elecfrontos. October. pp52-55.
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-34-
Spread Spectrim Techniques For LAH Interconnections
A. L. SlmcocJc, C na Ranong 5t P. Leung
1. I n t r o d u c t i o n
This i s an age of a u s t e r i t y , a t l e a s t as f a r as t he a l l o c a t i o n of t ransmiss ion baridwldth Is concerned. Ever Increas ing demands on an a l r eady overc rowded e l e c t r o m a g n e t i c spect rum have l e d t o de ve lopme n t s In two a reas :
a) Extending the u sab l e spectrum through the use of even higher frequency c a r r i e r s -
b) The design of complex frequency a l l o c a t i o n a lgor i thms .
Spread spectrum (SS) techniques were o r i g i n a l l y developed In the mid 1950s for m i l i t a r y a p p l i c a t i o n s , but i t i s o n l y r e l a t i v e l y r e c e n t l y t h a t the techniques have begun to be explo i ted in a commercial environment. Areas of commercial i n t e r e s t Include mobile rad io , rad io telephony, amateur radio and s a t e l l i t e communications-
SS sys tems may be d e f i n e d as those which t r a n s m i t us ing a f requency a l l o c a t i o n In e x c e s s of t he minimum r e q u i r e d , and as such do not r e l y on developments in e i t h e r of the above f i e l d s , r a t h e r on the use and re-use of the same bandwid th . One of t h e p r o p e r t i e s of a SS system is t h a t s e v e r a l nodes may s imul taneous ly transmit messages, occupying the same bandwidth, with minimal i n t e r f e r ence between t r a n s m i s s i o n s -
The Department of E l e c t r i c a l and E l e c t r o n i c E n g i n e e r i n g a t F o o t s c r a y T n s t l t u t e of Technology i s c u r r e n t l y i n v e s t i g a t i n g SS techniques and t h e i r a p p l i c a t i o n in Local Area Networks-
2. Basic Spread Spectrum Fundamentals
The th ree primary methods of Spreading the data t ransmiss ion are :
a) Direct sequence - in which the data i s d i r e c t l y modulated with a fas t pseudo random code sequence.
b) Frequency hopping - in which the c a r r i e r which i s modulating the data I s caused t o hop from one f requency to a n o t h e r in a pseudo random manner.
c) Time hopping - which can be l ikened to the pseudo random a l l o c a t i o n of channels In a time d i v i s i o n mul t ip lexed system.
The D i r e c t Sequence method a p p e a r s t o be t h e most a p p l i c a b l e In the LAN env^tronment, and has been the one s e l e c t e d for f u r t he r i n v e s t i g a t i o n . The d i r e c t spreading sequence i s sometimes a l s o c a l l e d the "CHIP SEQUENCE" .
Figure 1 I l l u s t r a t e s a simple s i n g l e channel d i r e c t sequence system-
- 3 6 -
A• System Under Investigation
Hos-t conputer
e-tc.
Da-ta
Figure 2 Bus Structured Node Interconnections
(NOTE The seperate Sync line is included to allow synchronisation and clock recovery.)
Figure 2 Illustrates the bus structured LAN topology currently being Investigated. Being a bus structured system each node can transmit and receive Independently of the others. This is achieved by using a Code Division Multiple Access (CDMA) system where each node has Its own 'address' and associated code (or chip sequence). Thus, with the point to point communications adopted In our system, if node #A wishes to transmit to node #2 then node #4 will modulate Its data with the code of node #2. The code Allocated to each node Is a delayed version of the synchronosatlon code. The delay between allocated codes being such that no code plus propagation delay (upto the maximum propagation delay In the system) can Immltate any other allocated code-It Is obvious, however, that only one node at any Instant In time may be trans-mlt t Ing to a particular address- This necessitates a collision check, as In Ethernet, but only for transmissions to the same receiver-Each node has two demodulators - one to monitor the system for Its own data and one to pre-check for collisions and continuously check whilst transmitting. The first demodulator works exclusively with l.ts own address code whereas the code used In the second Is switchable. Each node is also equipped with one transmitter, which must be able to modulate the data with any recipient's address code-
The pre-t ransmlsslon monitoring'requires each node to check over a time window, equal to the maximum propagation delay, to ensure that no transmission Is curcently In progress to the desired recipient. Figure 3 illustrates this scanning* across a delay window equa l to two chip bit
- 3 7 -
perlods, to find a transmission- Continuous monitoring for c o l l i s i o n s Is a l s o carried out throughout the transmission, and Figure A I l l u s t r a t e s the e f f e c t s of simultaneous transmissions by two nodes to the same recipient with various propagation delays between the Interferelng s ignals .
t a o
Figure 3 Pre-Transmlsslon Scan
Reference
Figure I* Correlation Output With Coll iding Signals
Conclusions
The SS LAN being Investigated at FIT has been developed to the point where the code type, code a l l o c a t i o n , s y n c h r o n i s a t i o n and c o l l i s i o n d e t e c t i o n a s p e c t s have a l l been cons idered . The future workplan . I n v o l v e s the i n v e s t i g a t i o n p r o t o c o l s s u i t a b l e for the c o n t r o l of a system of t h i s
nature
s' Acknowledgements
This research project Is being supported by a grant from the Australian Talacommunlcations and Elactronlcs Research Board-
- 3 8 -
References
1. ROBERT A. SCHOLTZ, "The O r i g i n s of S p r e a d S p e c t r u m C o m m u n i c a t i o n s " , I.E.E.E. T r a n s a c t i o n s on Communicat ions, V o l . Com-30, May 1982, pp 8 2 2 - 8 5 0 .
2. C S. SMYTHE and CT. SPRACKLEN, "A High Speed Loca l Area Network Using S p r e a d - s p e c t r u m C o d e - d l v l s l o n - m u l t i p l e - a c c e s s T e c h n i q u e s " , The R a d i o and E l e c t r o n i c Eng inee r , Vol . 5A, May 198*!), pp.225-226-
3 . R. C. DIXON, "Spread Spectrum Systems", Wiley (New York), 1976.
A. J . K. HOLMES, " C o h e r e n t S p r e a d S p e c t r u m S y s t e m s " , W i l e y (New York) 1982.
5. R. L. PICKHOLTZ, D. L. SCHILLING, L. B. MILSTEIN, " T h e o r y of S p r e a d S p e c t r u m C o m m u n i c a t i o n s - A T u t o r i a l " , I .E .E .E . T r a n s a c t i o n s on Communica t ions , Vol- COM-30, May 1982, pp 855-88A-
6. D.V.SARWATE and M. B- PURSLEY, "Cross C o r r e l a t i o n P r o p e r t i e s of Pseudo-Random and R e l a t e d - S e q u e n c e s " , P r o c I-E-E-E- V o l - 69 , May 1980 , p p . 5 9 3 - 6 1 9 .
7. R. GOLD, "Opt imal Binary Sequences For Spread Spectrum M u l t i p l e x i n g " , . I . E . E . , T r a n s a c t i o n s on I n f o r m a t i o n Theory , V o l - I T - 1 3 , 1967 , p p - 6 1 9 - 6 2 1 -
8- A. BRUCE CARLSON, " C o m m u n i c a t i o n S y s t e m s -An I n t r o d u c t i o n t o S i g n a l s and Noise In E l e c t r i c a l Communication", McGraw-Hi l l , (Tokyo), 1981-
9. M. B. PURSLEY and D. P. SARAWATE, " P e r f o r m a n c e E v a l u a t i o n f o r P h a s e Coded S p r e a d S p e c t r u m M u l t i p l e A c c e s s C o m m u n i c a t i o n s - P a r t I I " , I .E .E .E . T r a n s a c t i o n s on C o m m u n i c a t i o n s V o l . COM-25, Augus t 1977 , p p . 8 0 0 - 8 0 3 .
10. B. HIROSAKI, S. HASEGAWA, A- SAWAI, " S p r e a d S p e c t r u m M u l t i p l e A c c e s s Data Loop", NEC Res DEV n71 , October 1983, pp-A8-58-
on Manufacturing Engineering 1986 Newcastle 4-6 August. 1986
A Spread Spectrum Manufacturing Information Network C. NA RANONG
Centre for Automation Technology, Department of Electrical and Electronic Engineering, Footscray Institute of
Technology
A.L. SIMCOCK Lecturer, Department of Electrical & Electronic Engineering, Footscray institute of Technology
P. LEUNG Senior Lecturer, Department of Electrical & Electronic Engineering, Footscray Institute of Technologv
SUMMARY An e r r o r f r e e a n d r e l i a b l e d a t a n e t w o r k i s v i t a l f o r r e a l t i m e control of an automated manufacturing process. Special s h i e l d i n g or optical f ibre can be used to protect the network against a p l a n t ' s h o s t i l e e l e c t r i c a l environment.
This paper p roposes the a d a p t a t i o n of Spread Spectrum t e c h n i q u e s , which were o r i g i n a l ly deve loped for mi 1 i t a r y use as a means of p r o v i d i n g a jam r e s i s t a n t communication 1 ink, to a manufactur ing process network, to p r o v i d e an e r r o r r e s i s t a n t , low cos t network. An increased network throughput i s a l s o achieveable , through the maintenance of network a v a i l a b i l i t y in a muil t i p l e access high noise environment. 1. IJSTIRCOUCTICN
In a F l e x i b l e Manufac tur ing System, FMS,par t s product ion and m a t e r i a 1 hand 1 ing a re ach ieved by automated workce l l s . The c e l J s receive their work orders e i t he r from a supervisory console or from a c e n t r a l computer. P a r t s programs may a l s o be r e c e i v e d from remote Computer Aided Design, CAD, s y s t e m s . The r e s u l t s of each work o r d e r a r e r e t u r n e d t o t h e r e q u e s t e r when t h e work i s completed.
Ultimately the goal of f a c t o r y automation is to t i e a number of d i f f e r e n t sys tems, or i s l a n d s of automation, into a s i ng l e manufacturing process. To manufacture a random p a r t s mix ture in a ee l 1, the pa r t s programs t h a t a r e to be used by each d e v i c e c o n t r o l l e r must be downloaded to each of them for the p a r t i c u l a r p a r t or p a r t s to be made. This implies conmuni cat ion between the c o n t r o l system and the d e v i c e c o n t r o l l e r s . Such communication i n t e r f a c e s must dea l wi th a v a r i e t y of machine t o o l s , r o b o t s , v i s i o n and measu r ing systems e t c . c o n t r o l l e d by a v a r i e t y of CNCs, PLCs and robot c o n t r o l l e r s . Th i s leads to the need to spec i fy s t a n d a r d s t h a t d e v i c e c o n t r o l l e r s can use to communicate wi th each o the r and with the supervisory computers. The leading proponent being the General Motors C o r p o r a t i o n ' s Manufactur ing Automation Protocol , MAP.
Compliance with GM's MAP spec i f ica t ions , means that machine t o o l s , robots, prograrmab1e c o n t r o l l e r s and computers must be a b l e to communicate through an IEEE-802.4 token p a s s i n g p ro toco l l i nked wi th an E the rne t broadband Local Area Network (LAN). Data transmission occurs at 10 M b i t s per second vstiich is adequate both for r e a l time c o n t r o l at the machine tool leve l and for de t a i l ed data c o l l e c t i o n at the supervisory l e v e l .
This paper proposes the a d a p t a t i o n of Spread -Spectrum t echn iques as a means of implementing a "low cos t , noise r e s i s t a n t comnunication network for a f a c t o r y automat ion communication l i n k such as MAP.
Spread spectrum (SS) techniques were o r i g i n a l ly d e v e l o p e d in the mid 1950s fo r m i l i t a r y a p p l i c a t i o n s as a means of p r o v i d i n g a jam resistant conmuni cat Ion link. The ma] or attrltnites of- s fwe«*spectrum-signal 11 ng are- i t s hlg)v na l se
le to
irrmunity cha rac t e r i s t i c s and the a b i l i t y to sustain m u l t i p l e o r s i m u l t a n e o u s a c c e s s w i t h i n i t s l ink . These p r o p e r t i e s have only r e l a t i v e l y r e c e n t l y begun to be exploi ted in a commercial environment such as mobi le r a d i o , r ad io te lephony, amateur radio and s a t e l l i t e conrnunlcations.
The Centre of Automation Technology, Department of E l e c t r i c a l and E l e c t r o n i c Engineer ing of the Footscray I n s t i t u t e of Technology is in the process of developing a Local Area Network based on spread spec t rum techniques to implement point to point communicat ions. The primary o b j e c t i v e of the research is to develop a system which is simpl implement, r e l i a b l e , r e s i l i e n t and f l e x i b l e .
2. MANUFACTURING PROCESS (XMVIUNICATICN LINK
The d e f i n i t i o n of what comprises a manufactur ing c e l l v a r i e s wide ly ac ross the indus t ry . Here, a c e l l i s assumed to be a c o l l e c t i o n of 2 to 20 machine t o o l s , a t ransportat ion system and possibly i n s p e c t i o n s y s t e m s ( i n c l u d i n g v i s i o n ) . The o p e r a t i o n of the ce 1 1 is con t ro l led by the eel 1 management software and the machine dependent d e v i c e c o n t r o l l e r . Ce l l management software performs the task such as part program management, production con t ro l , resource management, equipment m o n i t o r i n g e t c . , whi le the dev ice c o n t r o l l e r i n c l u d e s the hardware and software r equ i red to c o n t r o l and monitor the i nd iv idua l dev ice in the c e l l .
The a rch i t ec tu re of the coomunication link d ic ta tes the f l e x i b i l i t y that the manufacturing systems may a c h i e v e (Watt, 1985; Weber, 1985). There are three major approaches: a cen t ra l i sed system, a network and a t o t a l l y d i s t r i b u t e d sys t em; w i t h the i n t e l 1 igence being progressively driven down to the lowest l e v e l . In the case of a cen t ra l i sed system, the hardware comnunication connections required may be complex and d i v e r s e . In the f ac to ry , the re is Often e l e c t r i c a l noise which makes the use of long RS232C or d i g i t a l i n p u t / o u t p u t ( 1 /0 ) l i n e s undes i r ab le and spec ia l c a b l i n g or o p t i c a l f i b r e a r e used . With s u i t a b l e sof tware , the re i s a high deeree of f l e x i b i l i t y in the c e n t r a l i s e d system; h o w e v e r , changes or a d d i t i o n s of hardware c o n f i g u r a t i o n may Involve c o s t l y r e t r o r i t of connartcatton ports, "me last two approaches, which
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provide higher overal 1 system f l ex lb i11 ty , u t i l i s e the development of LANs which provide high speed, e r r o r f r e e t r a n s m i s s i o n and m i c r o p r o c e s s o r s to d i s t r i b u t e the control system. The protocol sect ion of the machine dependent sof tware is con ta ined in Network I n t e r f a c e Modules , which connect to the network. Ihe point of connection is known as a Node and a network in terface module is required for each n o d e . Owing t o t h e b e w i l d e r i n g a r r a y of communication i n t e r f a c e s from t h e d i f f e r e n t v e n d o r s t h e r e i s a g r o w i n g p r e s s u r e f o r s tandard isa t ion in t h i s area as the present factory automation system requi res customised software and hardware to cope wi th the problem of non s t a n d a r d in te r faces .
G e n e r a l M o t o r s C o r p o r a t i o n i s promoting i t s Manufacturing Automat ion P ro toco l as a s t a n d a r d . (A p r o t o t y p e system was e x h i b i t e d in D e t r o i t 1 a s t November.) In the proposed MAP local area network system, machine t o o l s , r o b o t s and programmable c o n t r o l l e r s wi 1 1 t)e ab le to commmicate with each other and with the supervisory computers through an IEEE 802.4 token passing protocol linked with a 10 M b i t s per second E t h e r n e t broadband l oca l a rea network. The protocol i s based on the Internat ional Organisation for Standardisat ion (ISO) seven layer Open Systems In te rconnec t ion (OSI) model shown in Figure 1.
1 7 6 5 4 3 2 1
Applicat ion Presentation Session Transport Network Data Link Phys i ca1
(Highest
(Lowest)
1. Direct sequence - in which the data is d i r e c t l y m o d u l a t e d w i t h a f a s t pseudo random code sequence.
2. Frequency hopping - in which the c a r r i e r which i s modu la t ing the data i s caused to s h i f t frequency in a pseudo random manner.
3. Time hopping - which can be l ikened to the pseudo random a l l o c a t i o n of channels in a time d i v i s i o n mult iplexed system.
The proposed system uses the Direct Sequence method (Holmes, 1982; Pickholtz et a l , 1982) and therefore d i s c u s s i o n wi1 1 be r e s t r i c t e d to t h i s t echn ique . C o n c e p t u a l l y , each da ta b i t i s t r a n s m i t t e d as a s e r i e s of ( n a r r o w e r ) d a t a b i t s and a s a consequence , the r equ i r ed t ransmiss ion bandwidth increases. An appropriate se lec t ion of the data bi t coding sequences g i v e s r i s e to the i n t e r f e r e n c e proof p r o p e r t i e s of spread spectrum systems. The d i r ec t spreading sequence is sometimes a l so c a l l e d the CHIP SEQUENCE.
Figures 2 and 3 i l l u s t r a t e a simple s ing le channel d i r e c t sequence system and typical waveforms.
Da-ta Source
d<t)
p<t)
i ranaon srqu«nct
g«n»rotor -A
In-l»gra-t« d dunp
sequence generator
Figure 1 : ISO OSI Reference Model Transnl-tter Receiver
In b r i e f , a d e v i c e c o n t r o l l e r i n t e r f a c e s to the communication network v i a the Phys ica l and Data Link l a y e r s . (The network cotimunication medium i s a l so part of the Physical layer.) Ihe Network layer is required for interconnections between more than one LAN. The next two l e v e l s , Transport and Session l a y e r s , m a i n t a i n and i d e n t i f y a l l the nodes (or processes) connected to the network and f a c i l i t a t e the da ta communication n e c e s s a r y for the c o n t r o l and monitoring function of a manufacturing system. Ihe upper two l e v e l s , Presentat ion and Applicat ion (or User ) , r e p r e s e n t the methods by which the c o n t r o l and mon i to r ing func t ions are ach ieved . These include message formats and the i r contents , graphic d i sp l ays , encryption e tc .
Ihe proposed spread spectrun implementa t ion d e a l s wi th the two lowest l e v e l : the Phys ica l and Data Link layers .
Figure 2 : Single channel d i rec t sequence system.
•tine
p<-t)
Ine
3. SPREAD SPBCIRLM OOVMUNICATICNS
Spread spectrum (SS) t e chn iques were o r i g i n a l l y d e v e l o p e d In t he mid 1950s f o r m i l i t a r y a p p l i c a t i o n s ( S c h o i t z , 1982), but i t i s o n l y r e l a t i v e l y r ecen t ly that the techniques have begun to be exploi ted in a comnerclal environment. Spread Spectrum systems may be def ined as those which transmit using a frequency a l l o c a t i o n in excess of the minimum r e q u i r e d and as s u c h , h a v e t h e c a p a b i l i t i e s of u s i n g and r e - u s l n g the same bandwidth. The three primary methods of Spreading the data transmission are :
Figure 3 : Data and chip waveforms
Each data bit d(t), of energy E^ and duration T may be represented by
d(t)
This one dimensional signal is multiplied by a binary +1 chipping sequence p(t) running at a frequency of fg chips/sec, le. a total of f^T chip bits per data bit. Ihe resultant sequence d(t)p<t) is then a n = f<,T dimensional signal. If this
119
signal is transmitted in the presence of a jamming signal J(t), the received signal would be
r(t) = d(t)p(t) + J(t) 0 , t < T (1)
At the receiver this signa1 is mul t ip1 led by the same chipping sequence p(t) that was used to encode the transmitted data. Tlie output of the multiplier is integrated over a period T to produce a decision variable U, where
I • T T
u T
r(t)p(t) dt (2)
from which the deci s i on can be made as to whether •yjE^/T ov -JE^/T was sent depending on whether Uis greater than or less than zero.
The in t eg rand in e q u a t i o n (2) can be expanded as follows
r ( t ) p ( t ) = d( t )p '^( t ) + J ( t ) p( t ) (3)
is a binary ±1 signal the square of this signal p (t) = 1 and Since the chipping sequence p(t) signal the square of this signa therefore equation (3) may then tie rewritten
r(t)p(t) = d(t) + J(t) p(t) (4)
It can be seen from th i s that the rece iver recovers the one d imensional da t a s i g n a l and tha t t h i s recovery p roces s a c t u a l l y sp reads the jamming s igna l energy over a much wider bandwidth, thus reducing the energy per Hz of the jamming s igna l .
The s igna l J ( t ) in e q u a t i o n (4) may be del i b e r a t e jamining or i t may be i n t e r f e r e n c e from o the r t r a n s m i t t i n g nodes or e l e c t r i c a l n o i s e . The r e j e c t i o n of the o t h e r nodes ' t r a n s m i s s i o n s as noise depends upon the or thogonal i ty of the codes used for sp r ead ing each node 's d a t a . That i s , an appropriate s e l e c t i o n of a set of chipping sequence enables severa l nodes to s i m u l t a n e o u s l y t r ansmi t messages in a spread spect rum system, wi th a lmost zero interference between transmissions.
The primary aims of the project were to produce a system which is s i m p l e , r e l i a b l e and r e s i l i e n t . The task of choosing codes for the i r or thogonal i ty was s implif ied a f te r r e a l i s i n g that i t was poss ib le to c o n t r o l the environment in which the system i s to work, wi th r e s p e c t to connec t ion d i s t a n c e and hence propagation delay, a t tenuat ion e tc . , that i t should be p o s s i b l e t o p r o d u c e a s y n c h r o n o u s network. The choice of a synchronous network would then mean tha t the so c a l l e d odd-even c r o s s cor re la t ion proper t ies could be avoided, and that i t should not be necessary to resor t to codes with m u l t i - l e v e l cross c o r r e l a t i o n proper t ies , e.g. (jold or Kasami codes (Gold, 19 67).
This being the case i t was decided to a l l o c a t e codes to each node such tha t each add res s code would be a phase shif ted version of the same code, phase s y n c h r o n i s a t i o n and c lock r ecove ry being f a c i l i t a t e d by t h e p r o v i s i o n of a s e p a r a t e s^^ohEonisation l ine (Hirosaki et a l , 1983), thus the Across co r r e l a t i on between codes is in fact the au tocorre la t ion function of the one code.
3.1 (flannel Re-use Capabi l i ty
Figure 4 i l l u s t r a t e s a p o s s i b l e bus s t r u c t u r e d topo logy employed to i n t e r connec t system nodes. Being a bus s t r u c t u r e d system each node can transmtt and receive independently of the others.
Host conputtr
etc. t
node HI
node »2
Sync line
node 113
node
Data line
node »4
node «5
Figure 4 : Bus Structured Node Interconnections
The p r o p o s e d communica t ion l i n k u s e s a Code Divis ion Mul t ip le Access system where each node has i t s own 'address ' and associated code (or spreading s e q u e n c e ) . Thus w i t h t he p o i n t to p o i n t communications adopted in our system if node #4 wishes t r ansmi t to to node tf2 then node #4 wi 1 1 modula te i t s da ta wi th the code of node #2. Each node monitors the l ine looking for data modulated wi th i t s own ' address code' , and should recognise data for any other intended recipient as noise and r e j e c t i t , as shown in Equation (4), but should be abl e to demodul a t e the data encoded wi th i t s own address code in order to recover the or iginal data.
I t i s o b v i o u s , however, tha t on ly one node at any ins tant in time may be transmitt ing to a pa r t i cu l a r address. This necess i ta tes a c o l l i s i o n check, as in Ethernet , but only for transmissions to the same r e c e i v e r . Each node has two demodula tors - one to monitor the system for i t s own data and one to pre-check for col 1 islons and continuously check whi 1st t r a n s m i t t i n g . The f i r s t demodulator works e x c l u s i v e l y wi th i t s own address code whereas the code used In the second i s s w i t c h a b l e . Each node Is a l s o equipped wi th one t r a n s m i t t e r , which must be a b l e t o modula te the data wi th any r e c i p i e n t ' s a d d r e s s code.
Se l ec t ion of the nuiiber of 'chip' b i t s to represent a da ta waveform determines the Processing Gain of the sys tem, and hence i t s performance in presence of no ise ; and th i s in turns determines the maximun number of s imul taneous communications which the sys tem can s u s t a i n before i t s performance (eg. e r ro r ra te ) de te r io ra tes rapidly. However, because of t he channel r e - u s e c a p a b i l i t y of the spread spec t rum system, the ac tua l number of channe ls a v a i l a b l e to the ove ra l l system is greater than the nunber of simultaneous channels that the system can s u s t a i n . For example, in the presence of s eve re janming or e l e c t r i c a l n o i s e , a 32 channel spread spec t rum system may be ab l e to c a r r y 10 channe l s ' simultaneous transmissions. Having more s i gna l l i ng channels than could be s i m u l t a n e o u s l y c a r r i e d by the spread spectrun system has neg l ig ib l e effect on the system throughput performance s ince each data t r a n s m i s s i o n tends to be shor t and very r a r e l y would a l l the 32 channels be used at the same time.
3.2 Noise Resistance
Figure 5 I l l u s t r a t e s a simple system layout, with a nunber of t ransmit t ing nodes and a s ing le receiving node shown. The output from each node is added onto the 1 ine to produce a rece ived waveform r(t ) which i s a summation of the outputs from e»oh transmitter, as shown in Figure 6. ^
120
<12<t) K ^ s2<t) pa<t)
I I
P"<«f
Figure 5. Sinple System Layout
t l
sl(t)
- I
• I
sa(t>
-1
• 2
•1
r t t )
- I _
-e
I in ni I I l i—11—
I I U LJU I I t
^
I I U |_J I t
"Tl II I I—^-H • t
Figure 6. Typical t ransmi t te r waveforms
Figure 5 shows a number (n) of t r a n s m i t t i n g nodes and a s i n g l e r e c e i v e r (node #x), where 1 v< x N< n Ihe output of each t ransmi t te r s^(t) is given by
The upper t r a c e in Figure 7 shows of a p o r t i o n of received waveform with three t ransmi t te rs and Added White Gauss ian Noise, the lower t r a c e shows the d a t a r e c o v e r e d from t h i s s i g n a l . A p l o t of Bi t E r ro r Ra te a g a i n s t Signal to Noise r a t i o i s g i v e n in F i g u r e 8.
Figure 7 : Rx waveform and recovered data .
S/*l notlo <<lb)
Figure 8 : BER vs. S/N Ratio
sn(t) Pn<t> dn(t)
And, in the absence of e x t e r n a l i n t e r f e r e n c e ie . J(t) = 0, the received signal is given by
r ( t ) = s i ( t ) + S2(t) + S3(t) + Sn(t) (6)
(7) z S j , ( t )
Ihe demodulation is carried out and from equation (4)
r(t) p^tt) = dx(t) + Sj,(t)pjj(t) +Sjj(t)px(t) (8)
where 1 < x < n
In the presence of an external noise input J(t) the "received signa 1 becomes
r(t) = Sj,(t) + J(t)
Hhich Is demodulated to <' i r-y"^
r(t)pjj(t) •dx<t) *) Sj,(t)px(t) + \ Sn(t)px(t)
••• Jl(t)p^<t) (10)
(5) 4. APPLIC:ATICN IN A MANUFACTURING NE7W3RK
The Manufacturing Automation Protocol revis ion 2.1 which i s an emerging f ac to ry networking scheme promoted by General Motors Corporation, proposes a broadband factory wide comnunication network which a l lows modulated s igna ls to be send using nunerous c h a n n e l s or c a r r i e r f requenc ies i .e . the t o t a l f requency spectrum of the network i s subdiv ided into channel by frequency a I location scheme.
By u s i n g d i r e c t sequence code a l l o c a t i o n scheme ou t l i ned alx)ve, a spread spectrun system could be s u b s t i t u t e d for the broadband network, wi th the a d v a n t a g e s of channel r e - u s e capabi 1 i t y and high r e s i s t a n c e to e l e c t r i c a l no i se i n t e r f e r e n c e . The appl i c a t i o n of spread spectrum s i g n a l 1 ing is not r e s t r i c t e d to a network system such as MAP, but i t can be used in any communication l i nk where the a v a i 1 ab l e 1 ink bandwidth i s 1 a rge r than the data
(9) communication bandwidth.
5. CCNCLUSICNS
By a p p l y i n g Spread Spectrum techniques to the d e s i g n of a manufactur ing informat ion network, a s imple e r ro r r e s i s t an t network is being develope*!.
121 -V
when the in te r fe rence l e v e l s are many times g rea te r than the signal levels. This feature together with the ease of connection (via twisted pair cable) makes t h i s type of system eminen t ly s u i t a b l e for c a r r y i n g c o m p u t e r c o m m u n i c a t i o n s w i t h i n manufacturing p l a n t s .
6 . ACKNOWLEDGHViEl>n:S
This research project Is being supported by a grant from t h e A u s t r a l i a n T e l e c o m m u n i c a t i o n s and Electronics Research Board.
7. REFERENCES
GOLD R.( 1967), "Optimal Binary Sequences For Spread Spectrum Mul t lp lex lng" , I.E.E., Transactions on Informat ion Theory, Vol . IT-13, pp.619-621
HIROSAKI B., HASEGAWA S., SAWAI A.dSSS) , "Spread Spectrum Mu 111 p 1 e Access Data Loop", NEC Res DEV n71, October, pp.48-58
HOLMES J.K. (1982), "Coherent Spread Spec t run Systems", Wl 1 ey (New York)
PICKHOLTZ R.L., SCHILLING D.L., MILSTEIN L.B. (1982), "Theory of Spread Spectrun Conrnunlcations -A Tu_t^o_rJ_a,J_;;^, I . E . E . E . T r a n s a c t i o n s on Cormiunl cat Ions, Vol. CCM-30, May
SCHOLTZ R.A. (1982) , "The O r i g i n s o£ Spread Spectrun Conrnunlcations", I.E.E.E. T r a n s a c t i o n s on Conrnunlcations, Vol. Com-30 May
WAIT D.G. (1985), "Networking Software Support for FMS" , Manufac tur ing Engineer ing, September, pp. 103-106
WEBER D.M. ( 1 9 8 5 ) , " T e c h n o l o g y Update j . Manufacturing 2. More Versa t i l e Tools Speed Factory Automation" , Elec t ronics , October, pp. 52-55
122
A Localised Spread Spectrum Network A.L. Simock*, C. na Ranong* and P. Leung*
SUMMARY The need, for many users to be able to communicate wi th in a l o c a l i s e d environment gave r i s e to the Local Area Network (LAN). T h i s paper p r o p o s e s the a d a p t a t i o n of Spread Spectrum t e c h n i q u e s , which were o r i g i n a l l y deve loped for m i l i t a r y use as a means of prov id ing a jam r e s i s t a n t communication l i n k , to a LAN, the o b j e c t i v e being to d e v e l o p a system capable of maintaining communications In a m u l l t l p l e access high n o i s e environment.
1 IfrrRODUCTIOH
The expanding need for data communication channels in Loca l Area Networks (LANs) has Increased the p r e s s u r e on the a v a i l a b l e transmission bandwidth. Th i s has l e d t o d e v e l o p m e n t s in two broad a r e a s : the e x t e n s i o n of the u s a b l e spectrum through the use of e v e n h i g h e r f r e q u e n c y c a r r i e r s and the d e v e l o p m e n t of complex n e t w o r k i n g and m u l t i p l e a c c e s s a l g o r i t h m s . An e x t e n s i o n to the l a t t e r has l e d to the a d a p t a t i o n of Spread Spectrum CDMA techniques , which were o r i g i n a l l y developed In the mid 1950s Cl) for m i l i t a r y use as a means of providing a jam r e s i s t a n t communication l ink .
S p r e a d S p e c t r u m c o m m u n i c a t i o n i n v o l v e s a transmiss ion system which uses an o v e r a l l frequency bandwidth far In e x c e s s of the minimum r e q u i r e d . Through a c o r r e l a t i o n process the r e c e i v e r re s tores the s i g n a l to i t s normal bandwidth and in doing so ,
" i r enhances the des i red s i g n a l whi l e s u b s t a n t i a l l y r e d u c i n g the e f f e c t s of I n t e r f e r e n c e and n o i s e . O v e r a l l , the communication channel capacity Is not 'was ted ' b e c a u s e w i t h a s u i t a b l e s e l e c t i o n of s p r e a d i n g codes ( h a v i n g low c r o s s c o r r e l a t i o n p r o p e r t i e s ) s e v e r a l nodes may s i m u l t a n e o u s l y transmit messages over the same channel, with low, p r e d i c t a b l e , i n t e r f e r e n c e between nodes-
A Loca l Area Network such as E t h e r n e t , where m u l t i p l e nodes use a s i n g l e communication channel -one p a i r at a t i m e , i s a prime c a n d i d a t e for the a p p l i c a t i o n of Spread Spectrum t e c h n i q u e s . Being I n h e r e n t l y j a m - r e n 1 s t a n t , Spread S p e c t r u m t e c h n i q u e s have the p o t e n t i a l of reduc ing the content ion and a l l o w i n g m u l t i - p a i r communications, t h u s i n c r e a s i n g t h e ne twork ' s throughput under t h e s e c o n d i t i o n s . CDMA l a not as e f f i c i e n t as Frequency D i v i s i o n M u l t i p l e Access (FDMA) or Time D i v i s i o n M u l t i p l e A c c e s s (TDMA) In t e r m s o f throughput per unit bandwidth, but i t does have the advantage that random a c c e s s may be achieved.
a l l o w ' m u l t i c h a n n e l ' a c c e s s , and C a r r i e r Sense M u l t i p l e Access with C o l l i s i o n Detect ion (CSMA/CD) i s used t o r e s o l v e any r e m a i n i n g c o n t e n t i o n problems within channels-
2 SPREAD SPECTR0M ASPECTS
The t h r e e primary methods of Spreading the data t r a n s m i s s i o n are C3), C4], [53 : a- Direct sequence - In which the data Is d i r e c t l y
m o d u l a t e d w i t h a f a s t p s e u d o random c o d e sequence.
b. Frequency hopping - in which the m o d u l a t i n g c a r r i e r i s caused to hop from one frequency to another in a pseudo random manner.
c. Time hopping - which can be l i k e n e d to the pseudo random a l l o c a t i o n of channels In a time d i v i s i o n mul t ip lexed system-
AL3SNET u s e s t h e D i r e c t S e q u e n c e m e t h o d , a s I l l u s t r a t e d In Figure 1. The pseudo random binary s e q u e n c e I s a l s o known as the d i r e c t or c h i p sequence .
Data Source
cl<t) r<t) X
p(t)
pseudo randon
s*qu«nc( generotor
o k ij
Integrate tl dunp
pseudo randon
s*qu«nc* generotor
Transnitter Receiver
T h i s p a p e r d e a l s w i t h t h e d e v e l o p m e n t o f A - L o o a l i s e d Spread Spectrun Hetvorki ALS5NET, by the " D l i p t t r t a e n t o f E l e c t r i c a l and E l e c t r o n i c
E n g i n e e r i n g ! F o o t s c r a y I n s t i t u t e of Techno logy-Cod* D i v i s i o n M u l t i p l e Access (CDMA) C2J i s used to
A.L, S i a c o c k i C< na Ranong & F. Leung are a l l • e a b a r a ot t h e O e p a r t a e n t of E l e c t r i c a l & K l e e t r o n l e E n g l n e e r i n g t at Footscray I n s t i t u t e of T c e b n o l o g f t and h o l d t h e p o s i t i o n s o f l e c t u r e r . ar«irior l « e t t t r * r and s e n i o r Icet i trar r e s p « e t i v e l y . CFftper EI279 submitted i n May 198&)
Figure 1 S ingle channel d i rec t sequence system
Th« r e l a t i o n s h i p between the data and chip s i g n a l s i s shown in Figure 3
Each d a t a b i t d ( t ) , of energy E,, and d u r a t i o n T, may b« represented by
d ( t ) 1] h^^ (1)
T h i s o n s d l a s n s l o n a l d»t» b i t I s • n l t l p l l a d by b i n a r y • I cHIjr m^ifvmncm, p f t ) . runivlng a t
r~.—«< «/• ritetrieal and Eltcironlcs Engineering. Auslnlta — lEAustA IREEAusL. YcL 7, No. 2 June. 19!
f r e q u e n c y o f f^ c h l p a / s e c , l e . a t o t a l of f T c h i p s p e r d a t a b i t . The r e s u l t a n t s e q u e n c e d ( t ) p ( t ) I s t h e n a f„T d i m e n s i o n a l s i g n a l .
c
T h e r a t i o o f t h e d i m e n s i o n a l i t y o f t h e c h i p
s e q u e n c e t o t h e d a t a i s c a l l e d t h e " P r o c e s s i n g
Cain ' i and i s d e f i n e d a s
P r o c e s s i n g C a i n ^ ' ; < ; ( 2 )
Br
Where B and Br
SS B a n d w i d t h o f t h e Spread Spectrum S i g n a l
B a n d w i d t h o f t h e Data S i g n a l
The n u m e r i c a l v a l u e o f t h e p r o c e s s i n g g a i n i s an i n d i c a t i o n o f a ' p o w e r i m p r o v e m e n t f a c t o r , w h i c h a r e c e i v e r , p o s e s s i n g a c o p y o f t h e t r a n s m i t t e r ' s c h i p s e q u e n c e , c a n a c h i e v e by a p r o c e s s o f c o r r e l a t i o n . T h i s f i g u r e g i v e s an I n d i c a t i o n of t h e I n t e r f e r e n c e r e j e c t i o n c a p a b i l i t y .
I f t h e ' c h i p p e d d a t a ' s l g n a l i d ( t ) p ( t ) , i s t r a n s m i t t e d i n t h e p r e s e n c e o f an I n t e r f e r i n g s i g n a l J ( t ) , t h e r e c e i v e d s i g n a l would be
r ( t ) d ( t ) p ( t ) > J ( t ) 0 s< t ,< T ( 3 )
At the r e c e i v e r t h e c o r r e l a t i o n p r o c e s s I s c a r r i e d o u t by m u l t i p l y i n g t h e r e c e i v e d s i g n a l w i t h t h e same c h i p s e q u e n c e u s e d t o e n c o d e t h e t r a n s m i t t e d d a t a , and t h e n i n t e g r a t i n g the r e s u l t o v e r a p e r i o d T t o p r o d u c e a d e c i s i o n v a r i a b l e U, where
U - J E J J / T r ( t ) p ( t ) dt C )
•tjne
p<t)
t l '
-
tine
F i g u r e 2 T y p i c a l Chip and Data Waveforms
From e q u a t i o n Ct) i t c a n be d e t e r m i n e d w h e t h e r ^ . /T o r - j E t / T " w a s was s e n t , d e p e n d i n g o n
w h e t h e r U i s p o s i t i v e o r n e g a t i v e - ' T h e i n t e g r a n d i n • a y t h e n be e x p a n d e d a s f o l l o w s
r ( t ) p ( t ) d ( t ) p ' = ( t ) • J ( t ) p ( t )
And. since p (t) - 1, this may be rewritten as
r(t)p(t) - d(t) • J(t)p(t)
( 5 )
( 6 )
t h u s t h e r e c e i v e r r e c o v e r s t h e o r i g i n a l o n e d i m e n s i o n a l d a t a s i g n a l d ( t ) .
. _ l n . _ e q u a t i o n ( 6 ) t h e J s a n l n g s i g n a l J(t) n a y be a n e x t e r n a l i n t e r f e r e n c e s i g n a l , e g . n e a r b y h i g h v o l t a g e e q u i p n e n t . o r i t nay be i n t e r f e r e n c e from o t h e r t r a n s n l t t i n g n o d e s - The r e j e c t i o n o f t h e o t h e r n o d e s t r s n s a l s s i o n s a s n o i s e depends upon t h e o r t h o g o n a l i t y o f t h e c o d e s C 6 } . C 7 ] , t S l u s e d f o r s p r e a d i n g e a c h n o d e ' s d a t a .
Th* t a s k o f e h o o s i n g c o d e s f o r t h e i r o r t h o g o n a l i t y « a n b * s l a t r t l f l a d ^ i f t h * e n v l r o n a e n t I n w h i c h t h *
s y s t e m I s t o work, s u c h as c o n n e c t i o n d i s t a n c e and h e n c e p r o p a g a t i o n d e l a y , a t t e n u a t i o n e t c - c a n be c o n t r o l l e d . T h i s d e g r e e o f c o n t r o l a l l o w s a s y n c h r o n o u s ne twork t o be produced. S y n c h r o n i s a t i o n may be c o n s i d e r e d f r o n b o t h c h i p and d a t a b i t v i e w p o i n t s - I n a s y n c h r o n o u s , c a b l e c o n n e c t e d , n e t w o r k s u c h a s t h i s , w i t h p r e d i c t a b l e d e l a y and a t t e n u a t i o n c h a r a c t e r i s t i c s , t h e e f f e c t o f t h e s o c a l l e d o d d - e v e n c r o s s c o r r e l a t i o n p r o p e r t i e s a r e m i n i m a l a n d c o d e s w i t h m u l t i - l e v e l c r o s s c o r r e l a t i o n v a l u e s , e . g . C o l d o r Kasami c o d e s C 6 ) , C 7 ) , t8J< C9) a r e not n e c e s s a r y - The c o d e a l l o c a t i o n s c h e m e s e l e c t e d I s based on p r o v i d i n g e a c h a d d r e s s a code which I s a b i t s h i f t e d v e r s i o n o f t h e m a s t e r c o d e , t h i s master code a l s o b e i n g t h e s y n c h r o n i s a t i o n c o d e I n d i c a t e d In F i g u r e 3- Thus t h e c r o s s c o r r e l a t i o n b e t w e e n c o d e s I s t h e a u t o c o r r e l a t i o n f u n c t i o n o f t h e o n e c o d e - T h i s s i m p l i f i e s b o t h t h e c o d e g e n e r a t i o n and d e c i s i o n making c i r c u i t r y . The a l l o c a t i o n of phase s h i f t e d v e r s i o n s o f t h e o n e c o d e t o a c t a s t h e I n d i v i d u a l n o d e a d d r e s s c o d e s i s s i m i l a r t o t h a t u s e d by 8-H i r o s a k i e t a l CIO] in t h e i r performance a n a l y s i s o f a f i b r e o p t i c s s y s t e m . They s h o w e d t h a t t h e v a r i a n c e Cq ( t ) l in mutual I n t e r f e r e n c e from node #1 i s g i v e n by
Cq^"- ( j N T j , ) ] ^ - 1/N^ ( 7 )
where J r e p r e s e n t s t h e i n d i v i d u a l b i t p o s i t i o n , N t h e c h i p s e q u e n c e l e n g t h , T t h e c h i p s e q u e n c e b i t p e r i o d
The e q u a t i o n (7 ) a b o v e , shows that the p e r - c h a n n e l i n t e r f e r e n c e I s i n v e r s e l y p r o p o r t i o n a l t o t h e s q u a r e o f t h e c h i p s e q u e n c e r e p e t i t i o n l e n g t h , o r P r o c e s s i n g C a l n t and s i n c e o n e o f t h e d e s i g n a l m s was t o p r o d u c e a r e l i a b l e and r o b u s t s y s t e m • a f a i r l y l a r g e p r o c e s s i n g g a i n of 1024 (approx . 30dB) was s e l e c t e d . E v i d e n c e I n d i c a t e s 151 t h a t t h e m a x i m u m n u m b e r o f s i m u l t a n e o u s u s e r s I s a p p r o x i m a t e l y o n e t e n t h o f t h e p r o c e s s i n g g a i n . T h i s c h o i c e o f a h i g h v a l u e f o r the p r o c e s s i n g g a i n p r o d u c e s a s y s t e m c a p a b l e o f w o r k i n g i n an e l e c t r i c a l l y h o s t i l e env ironment and a l l o w s a l a r g e number o f s i m u l t a n e o u s code t r a n s m i s s i o n s .
U s i n g M a x i m a l L e n g t h S e q u e n c e s (MLS) o f 2 - 1 b i t s ( l e . 1 0 2 3 ) t o e n c o d e e a c h d a t a b i t r e s u l t s In a r e s i d u a l o f f s e t e f f e c t a t t h e o u t p u t o f t h e a n a l o g u e m u l t i p l i e r w h i c h I s d e p e n d e n t on t h e number o f s t a t i o n s t r a n s m i t t i n g s i m u l t a n e o u s l y . T h i s r e s u l t s f r o m t h e t w o l e v e l ( 1 0 2 3 , - 1 ) a u t o c o r r e l a t i o n f u n c t i o n o f a MLS- In o r d e r t o e l i m i n a t e t h i s r e s i d u a l e f f e c t t h e ML s e q u e n c e s w e r e m o d i f i e d t o p r o d u c e c o d e s w i t h ( 1 0 2 ' i , 0 ) a u t o c o r r e l a t i o n p r o p e r t i e s , by the a d d i t i o n o f cn e x t r a b i n a r y z e r o - Each s t a t i o n c o d e I s t h e n made up from a c y c l i c a l l y b i t s h i f t e d MLS p l u s an e x t r a b i n a r y z e r o wh ich I s t r a n s m i t t e d as c h i p b i t number 102<t. Each d a t a b i t i s then encoded by t h e 1024 b i t m o d i f i e d MLS. The s t a t i o n code a l l o c a t i o n scheme I s not a f f e c t e d , e a c h s t a t i o n be ing a l l o c a t e d a p h a s e s h i f t e d v e r s i o n o f t h e same m o d i f i e d MLS.
3 LAJI ASPICTS
C u r r e n t bus and r i n g Loca l Area Network t o p o l o g i e s , t y p i f i e d b y E t h e r n e t a n d C a m b r i d g e R i n g r e s p e c t i v e l y , e m p l o y aoue form o f ( a s y n c h r o n o u s ) t i m e d i v i s i o n a u l t i p l e x l n g . T h i s may be In t h e more o r l e s s f i x e d coapartment format o f C a a b r l d g e Ring o r t h e P a c k e t Message type format o f E t h e r n e t . W h i c h e v e r s y s t e m I s u s e d , any node w i s h i n g t o a c c e s s t h e s y s t e a a u s t w a i t u n t i l a t l a e when no o t h e r u s e r s a r e t r a n s a i t t i n g . The n o d e w i l l t h e n t r a n s a i t a t a r e l a t i v e l y h i g h b i t r a t e i n t o t h * s y s t e a . Th* o v e r a l l e f f e c t i s t h a t e s e h nod* e a l t s b t t c s t * o f d a t a : » t h . l » h b t t r a t e a f o r r e i a t t v e l y
Mumat t^Eleelrieat and Ettctnnla Enginetrtng. Australia — IE Atat. A IREE Aust. VoL 7, No. 2 June, 1987
short p e r i o d s , and than remains dormant for a much l o n g e r p e r i o d . O c c a s i o n a l l y , two or more nodes a t t e m p t t o t r a n s m i t at the same time and the a e s s a g e s c o l l i d e ; back o f f and r e t r a n s m i s s i o n a l g o r i t h m s would then be used to 'arbi trate ' - Thus network throughput Is dependent on the number nodes In the ne twork and the network bandwidth- S p e c i a l chip s e t s capab le of high speed burst transmiss ion (eg. Motorola 68590) have been deve loped for t h i s purpose.
Simultaneous m u l t i p l e a c c e s s , o f fered by TDMA, FDMA and CDMAi In a Loca l Area Network can I n c r e a s e o v e r a l l network throughput and p o s s i b l y e l i m i n a t e the need for very high speed transmiss ions . ALSSNET c a p i t a l i s e s on t h e random a c c e s s , d i s c r e t e address ing c a p a b i l i t i e s of CDMA and uses a scheme where e a c h n o d e has I t s own ' a d d r e s s ' and a s s o c i a t e d code (or s p r e a d i n g s e q u e n c e ) - The bus s t ruc ture i s shown in Figure 2.
In the point to point communication system adopted in the n e t w o r k , i f node 1 w i s h e s to t ransmi t to node 2 then node 1 w i l l modulate i t s data with the code of node 2. Hence, the transmit ter of each node must be a b l e t o m o d u l a t e I t s d a t a w i t h any r e c i p i e n t ' s a d d r e s s code . S ince o n l y one node at any I n s t a n t In t ime may be t r a n s m i t t i n g to a p a r t i c u l a r a d d r e s s , a c o l l i s i o n check for the intended r e c e i v e r i s s t i l l necessary, and a CSMA/CD p r o t o c o l i s used t o r e s o l v e c o n t e n t i o n s w i t h i n c h a n n e l s . Each t r a n s m i t t e r h a s a b u i l t In demodulator to pre-check for t r a f f i c in the desired channel and c o n t i n u o u s l y check for c o l l i s i o n s whi le transmit t ing . Thus each node has two demodulators -one for monitoring the channel for I t s own message and a n o t h e r o n e f o r c o l l i s i o n a v o i d a n c e and d e t e c t i o n . The f i r s t demodulator works e x c l u s i v e l y with I t s own address code whereas the code used in Che second i s s w i t c h a b l e .
The r e c e i v e r s e c t i o n of each node monitors the l i n e l o o k i n g f o r d a t a modula ted w i t h I t s own 'address code' i I t d e m o d u l a t e s the data encoded with t h i s code , i n o r d e r t o r e c o v e r the o r i g i n a l d a t a , but t r e a t s d a t a f o r any o t h e r In tended r e c i p i e n t as n o i s e and r e j e c t s i t , as shown in e q u a t i o n (6 ) . As each node has a unique a d d r e s s o n l y s i g n a l s modulated with t h i s address code w i l l c o r r e l a t e In i t s r e c e i v e r , and be despread. a l l other codes w i l l not c o r r e l a t e and w i l l be spread further across the band * ,
mismatches and fe f - l ecc ions . and each node outputs onto the transmiss ion medium via a high impedence c u r r e n t d r i v e r . F igure •- shows a s i m p l e s y s t e a l a y o u t , i l l u s t r a t i n g the a l l t l p l e acces s concept, w i t h a number of t r a n s a i t t i n g nodes and a s i n g l e r e c e i v i n g node. The output from each node i s added onto the l i n e to produce a received waveform r ( t ) , Figure 5. which i s a summation of the outputs from each t r a n s m i t t e r ,
r ( t ) - s ^ ( t ) » s jCt) . s „ ( t )
I
«n(^)
( 8 )
( 9 )
tntegro Iff and dunp d x ( t )
-U'-A (.\-\ p2<t)j I
d3(t) " v Y y s3(«> > T y
dn(t) V y sn ( t ) \ _ V pn(t)1
Figure 4 Multiple Access Concept
At the r e c e i v e r the m u l t i - l e v e l l i n e s i g n a l r ( t ) Is m u l t i p l i e d by the r e c e i v e r ' s own • 1 l e v e l c h i p sequence Px(t) and from equation (6)"
r ( t ) p j ^ ( t ) - dj^Ct) . \ s ^ ( t ) p j j ( t )
r-( t ) p ^ ( t ) • j ( t ) p j ^ ( t ) ( 1 0 )
Where 1 . x . n
• I
sl(t)
s2<t>
^ t
-I
• t
_ -
Host conputer
etc.
• I
s3(t)
r(t)
t
Figure 3 Systea Bus Structure
o • 2 '
• I
-1 -
- 2 "
- 3
^ W \
ALSSNET ia baaed on twis ted or p a r a l l e l pair cablet t h i s i s t o n s i n t s i n s i a p l i c i t y and a l l o w new nodes t o b* c o n n e c t e d t o . or d i s c o n n e c t e d f r o a . the R»tver ) t w i t h o u t undu ly s f f t e t l n g o t h e r u s e r s . Th« c.abl* l i tsralnattd with an ippropritta r a a l a t a n e * s t both mnAm In o r d e r t o - a l n l a t s »
Figure 5 Typical transmitter waveforms
Th* f i r s t t e r a d^Ct). in e q u a t i o n ( l O ) . I s t h * rtcoTtrad on« diMflfioul dttt signal and ths laat t h r o v t*rHr « r * t h * a u l t l d l a « n s i o n s l lnt«rf*r«ne*:
JtjmuiteifEltcinealand^Eharoma Engineerings Auuraiia — lEAusu A IREEAusL, ^ol 7, No. 2 June. 1987
s i g n a l s - The output froa the analogue m u l t i p l i e r Is s u b j e c t e d t o low p a s s f i l t e r i n g In the I n t e g r a t e and dump c i r c u i t , in o r d e r to remove the unwanted high frequency components, b e f o r e be ing passed on t o the d e c i s i o n c i r c u i t to d e t e r m i n e whether t h i s p a r t i c u l a r d a t a b i t r e p r e s e n t s a l o g i c one or a l o g i c zero-In o r d e r t o t e s t c o d e r e c o g n i t i o n and p h a s e s y n c h r o n i s a t i o n , a n o v e l e r r o r g e n e r a t o r which p r o d u c e s r a n d o m - e r r o r s at r a t e s between 1 x 10" and 9 X 10" la used- T h i s g e n e r a t o r i s c a p a b l e of m a i n t a i n i n g the e r r o r r a t e s i r r e s p e c t i v e of the
Input d a t a r a t e which may v a r y from 1 to 1-5 x 10 b i t s per s e c o n d . T e s t s w i t h the p r o t o t y p e s y s t e m have showed that the system r e l i a b l y ach ieves phase s y n c h r o n i s a t i o n w i t h i n t 0 ms , e v e n with an e r r o r
— 2 rata as high as 1 x 10" , and that synchronisat ion dropout does not become a problem u n t i l the e r r o r rata reaches 2 x 10~ .
4 COHPUTK* STUnr
A computer s t u d y of the s y s t e m c o d i n g a s p e c t s I s being deve loped • I d e a l l i n e d r i v e c h a r a c t e r i s t i c s of a 60 user system have been i n v e s t i g a t e d and the performance e v a l u a t e d from two aspec t s :
t h e e r r o r r a t e s I n d i c a t e d In F i g u r e 7, t h u s i l l u s t r a t i n g the p o t e n t i a l of such a system for use In an e l e c t r i c a l l y noisy environment-
Figure 6 Received Signal and Recovered Datj
I) To ensure that transmiss ion *x (see Figure 4; where 1 < x < n ) w i l l be s u c c e s s f u l l y decoded when a number of s i m u l t a n e o u s t r a n s m i s s i o n s are t a k i n g p l a c e - A s i m u l a t i o n c o n t a i n i n g 60 nodes has been deve loped and the c o r r e l a t i o n proper t i e s i n v e s t i g a t e d - This s i m u l a t i o n has v e r i f i e d the 102^1, 0 c o r r e l a t i o n propert ies of the codes s e l e c t e d -
II ) To I n v e s t i g a t e the o r t h o g o n a l i t y propert ies of the c o d e s used- T h i s part t a k e s the form of s i m u l a t i n g a n u m b e r o f s i m u l t a n e o u s t r a n s m i s s i o n s (#1 to an e x c l u d i n g icx) and a t t e m p t i n g to e x t r a c t data u s i n g code P. *^) ( l a - the code o m i t t e d ) - Upto 59 s i m u l t a n e o u s transmiss ions have been demonstrated to create no mimicry p r o b l e m s , l e - no combinat ion of code transmiss ions from upto 59 s t a t i o n s looks l i k e the code of the non-transmitt ing s t a t i o n #x.
5 PROTOTTPK SYSTEM TESTS
The m u l t i p l e a c c e s s c o n c e p t I s I l l u s t r a t e d In Figure It. Three t ransmi t t er s and two r e c e i v e r s were used for the purpose of prel iminary Bit Error Rate (BER) measurements- The f i r s t t r a n s m i t t e r / r e c e i v e r p a i r were used f o r the BER v s S/N measurements-The second t r a n s m i t t e r / r e c e i v e r p a i r was used t o v e r i f y the s i m u l t a n e o u s t r a n s m i s s i o n c a p a b i l i t y , t h e t h i r d t r a n s m i t t e r a c t i n g m e r e l y as an a d d i t i o n a l source of in ter ference- The upper trace In F i g u r e 6 shows the r e c e i v e d s i g n a l r ( t ) w i t h t h r e e t r e n s a i t t e r s . s ^ ( t ] t o S 3 ( t ) i and Added White Gaussian Noise a l l present . In t h i s trace the S/N r a t i o i s -10 db. The lower trace shows the data recovered froa t h i s s i g n a l -F i g u r e 7 shows p r e l i a i n a r y r e s u l t s of the BER v s S/H R a t i o a e a » u r e a e n t s . The p r e l i m i n a r y r e s u l t s o b t a i n e d f r o a the p r o t o t y p e s y s t e a have v e r i f i e d the concept of a synchronous LAH using bit s h i f t e d a o d i f l e d Maximal Length Sequences as the a d d r e s s c o d e s . Data r e c o v e r y has been d e a o n s t r a t e d , w i t h
BIT DWDK BATE v i S/N KATIO
- I J -12 - H -10
S/M Ratio (db)
Figure 7 BER vs S/N Ratio
6 THROUGHPUT MODEL
Since user address codes have been chosen for the ir o r t h o g o n a l i t y , a point demonstrated by the s imple computer study o u t l i n e d In s e c t i o n 4, i t Is assumed that each (CDMA) channel's t r a f f i c may be regarded as Independent In order to model ind iv idua l channel throughput c h a r a c t e r i s t i c s .
The t e c h n i q u e s used In the d e r i v a t i o n of t h i s t h r o u g h p u t model are based upon those used by K l e i n r o c k and Tobagi C l l ] . In the deve lopment of t h i s model the f o l l o w i n g assumptions are made:
a) T r a f f i c s o u r c e s , on a sys t em and per channe l b a s i s , are regarded as Poisson sources with a mean packet g e n e r a t i o n r a t e of A p a c k e t s per second.
b) P a c k e t s are of c o n s t a n t l e n g t h of T s e c o n d s d u r a t i o n , such that the a v e r a g e n"mber of packets generated In t h i s T second period i s S a AT. Thus the input rate i s normalised to the t r a n s a i s s i o n t l ae T. S may then be c a l l e d the Channel Throughput or Channel U t i l i s a t i o n .
* NOT! the word Nois* Is used to represent t o t a l tiitarf*r«ne«> la extarnal Inttrftrane* J(t) plus liic»rf*r«ne« eaustd by othar nodes transBittlng •lmtXtsD*oasly>
Aumal ^Electrical and Electronics Engineering. Auaraila — IE Anst. A IREE AUSL, VOL 7. No. 2
c) The offered channel traffic is denoted by C (whtra 6 ) 8). C is equal to the new traffic -plus th* traffic requiring^ retransaission ^ owing to soa* earlier collision. t
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d) X i s the mean r e t r a n s a i s s i o n . or back-off , time and Is assumed large compared to T-
e) In t h i s model n o n - p e r s i s t e n t CSMA i s used w h e r e , upon busy s e n s i n g and r e c o g n i t i o n the t r a n s m i t t e r w i l l lmffle_dlataly back o f f an a r b i t r a r y t i m e p e r i o d X. and not c o n t i n u e t o s e n s e , wa i t ing for the channel to become free-
f) No p o s i t i v e a c k n o w l e d g e m e n t scheme I s Incorporated, c o l l i s i o n s being detected (In a f i n i t e time T) by each s t a t i o n Invo lved In the t r a n s m i s s i o n of the c o l l i d i n g packets. After c o l l i s i o n d e t e c t i o n packet transmission w i l l be continued for a further period T to jam the c h a n n e l In o r d e r t o t o e n s u r e t h a t the o t h e r s t a t l o n ( s ) I n v o l v e d in the c o l l i s i o n w i l l d e t e c t t h e c o l l i s i o n . The r a t i o of t h e c o l l i s i o n d e t e c t i o n time T to the transmiss ion t ime T i s g i v e n by • where a - T/T.
g) Busy s e n s i n g Is ach ieved in a period equal t o ' the c o l l i s i o n d e t e c t i o n time a.
h) Propagation d e l a y s are negl lgabl 'e compared t o T and are s e t t o z e r o -
1) The Interpacket a r r i v a l times are Independent and e x p o n e n t i a l l y d i s t r i b u t e d -
Unsuccessful Tronsmssfon Period
Successful Tronsnisslon
P«nod
t* "1, ""^^ ,h
rr . V . .
1
1. The t ime when t r a n s m i s s i o n s are o c c u r r i n g Is d e f i n e d as t h a t t ime when t r a f f i c Is a c t u a l l y f l o w i n g and e x c l u d e s the i n i t i a l s e n s i n g per iod-This t r a n s a i s s i o n time, whether for a s u c c e s s f u l or an u n s u c c e s s f u l t r a n s m i s s i o n , Is c a l l e d the TransmlsBlon Period (TP) or Busy Period. Any period between two s u c c e s s i v e TPs Is c a l l e d an I d l e P e r i o d , and a Busy Period f o l l o w e d by an I d l e P e r i o d I s c a l l e d a C y c l e - If B i s the e x p e c t e d d u r a t i o n of a Busy Per iod and I the e x p e c t e d d u r a t i o n of an I d l e _ p e r l o d then the d u r a t i o n of a c y c l e would be B*I. Using renewal theory the average Channel U t i l i s a t i o n S may then be defined as
S - _IL-B*I
(11)
where D i s the a v e r a g e time during a c y c l e that a channel i s being used without c o n f l i c t . B Is g iven by the p r o b a b i l i t y that no o ther t r a n s m i s s i o n occurs between t and ( t . a ) and therefore
U -aC (12)
The a v e r a g e d u r a t i o n of an I d l e P e r i o d . I , I s s i m p l y 1/C I and the a v e r a g e d u r a t i o n of the Busy Period B i s g i v e n by
B - (Average unsuccessful t ime)(Probabi lIty of an unsuccess fu l t r a n s m i s s i o n ) * (Average s u c c e s s f u l t 1 me ) ( P r o b a b 1 1 1 1 y of a s u c c e s s f u l transmission)
The p r o b a b i l i t y that the t r a n s m i s s i o n w i l l be s u c c e s s f u l (Ps) Is equal to the probab i l i t y that no other transmiss ions occur between t and ( t«a) .
Ps - e -aC
Thus - (1 - Ps)(Y • 2a) » ( P a ) ( l ) (13)
The average v a l u e of T , from C l l ] , i s g iven by
(1 ,-aG) ( U )
I IniOco-tes Arrivol Df A Pocke-t A-t A Nod«
Figure 8 Channel Transmission C h a r a c t e r i s t i c s
Let t be the a r r i v a l t i m e , at a node , of a packet to be t r a n s m i t t e d . The s t a t i o n w i l l s e n s e the c h a n n e l f o r a s e c o n d s and. s e n s i n g the c h a n n e l f r e e , w i l l t r a n s m i t at t ime ( t « a ) . as shown In Figure 8. * Another s t a t i o n obta in ing a packet between t and ( t * « ) w i l l sense the channel free and a l s o t r a n s m i t , t h u s c a u s i n g a c o l l i s i o n . T h i s p e r i o d o f • s e c o n d s i s c l a s s i f i e d a s t h e ' v u l n e r a b l e per iod" , and If no o t h e r s t a t i o n r e c e i v e s a packet for transmiss ion in t h i s period then t h * f i r s t ' s p a c k e t w i l l be s u c c e s s f u l l y t ransmi t t ed .
* NOTE Upon coaaencement of t r a n s m i s s i o n the busy sens ing c i r c u i t i s r e s e t and r e - a c t l v a t e d as a c o l l i s i o n d e t e c t i o n c i r c u i t .
. - I l _ ( t * I * a ) i s the t l a e of transmiss ion of the l a s t packet then at t i a * (t*T»2a) s t a t i o n s t r a n s a i t t i n g should have recognised the c o l l i s i o n . Each s t a t i o n w i l l cont inue to t r a n s a i t for a period of a seconds a f t e r c o l l i s i o n d e t e c t i o n , thus at t l a e (t4^T*3a) a l l s t a t i o n s w i l l have stopped t r a n s a i t t i n g - Since no t r a n s a i s s i o n s a r e o c c u r r i n g d u r i n g the f i r s t a saeonds of t h i s pcr lodi w h l l * th* f i r s t s t a t i o n i s • • n * l n f th« channali th* a v t r s g * duration of an
'ttnr*ttee»»»fttl tr»nsal»»toi t 1* (T*2fth and the-duccfetoat of s sueessaful transaisaloo i s equal t o
Subs t i tu t ing into equation (13) gives
B - 3o - ( 1 e ) - J a e • e
C
. -aG (1 e"»°) (15)
Us ing t h e v a l u e s f o r I . U and B and s u b s t i t u t i n g i n t o equat ion (11) g i v e s
S - U 1*T (3aG • (( r i f f ^
JlA -aC
3aC - e"*'^))) (16)
E q u a t i o n (16 ) above r e p r e s e n t s the throughput . S. In tarme of t h e o f f e r e d t r a f f i c . C. and the busy s e n s i n g p e r i o d , a. F igure 9 la a graph of S v s C. and s e v e r a l c u r v e s are i n c l u d e d in order t o represent d i f f e r e n t v a l u e s of a. These curves show t h * e x p e c t e d c h a r a c t e r i s t i c s h a p e w i t h t h e t h r o u g h p u t i n c r e a s i n g as the o f f e r e d t r a f f i c i n c r e a s e s u n t i l a breakpoint i s reached. Above t h i s p o i n t t h e p r o b a b i l i t y of c o l l i s i o n s o c c u r r i n g ia such that increas ing the offered t r a f f i c a c t u a l l y c a u s e s a r e d u c t i o n in throughput as the channel c a p a c i t y i s p r o g r e s s i v e l y taken up w i t h more r e t r a n s a i s s i o n s and l e s s new t r a f f i c I t can be s e e n f r o a F i g u r e 9 t h a t the busy s e n s i n g t l a e i s a hlf i i ly laportant paraa«t*r In th* throughput aodel aii4^tli«t^r»4uclJ»fe_thl» sensing t l a a eansaa th«^ ; breakpoint tn thcoagbput to occur at htgh«r l e v e l »
MMnHd e/EUctrkai and Ehetnmies Engineering. Australia — IE AUSL A IREE Aust. VoL 7. No^ 2 June, 19ST
of o f f ered t r a f f i c -
The t h r o u g h p u t c h a r a c t e r i s t i c s of t h i s model are compared w i t h t h o s e of some of the more f a m i l i a r m u l t i - a c c e s s p r o t o c o l s In Figure 10- These curves are p l o t t e d u s i n g a v a l u e of a • 0 -01 . e x c e p t for the two Aloha p r o t o c o l s which are Independent of a. In the N o n - p e r s i s t e n t and l - p e r s l s t e n t CSMA models the v a l u e of a represent s the propagation delay In the system, rather than a busy sensing period as In t h i s m o d e l , but In a l l t h r e e mode l s a g i v e s a r e p r e s e n t a t i o n of the ' v u l n e r a b l e p e r i o d ' for transmiss ion m o d e l l i n g purposes- These curves show the comparison between the ALSSNET model, which has been d e v e l o p e d f o r a LAN a p p l i c a t i o n , and o t h e r p r o t o c o l s (most n o t i c a b l y Aloha and S l o t t e d Aloha) which were not- The Ind ica t ion Is that a p p l i c a t i o n s p e c i f i c p r o t o c o l s can o f f e r throughput advantages-
lOO
Figure 9 Throughput vs Offered Traff ic
Figure 10 Comparison of Throughput C h a r a c t e r i s t i c s
7 CONCLUSIONS
By a p p l y i n g a CDMA spread spectrum t e c h n i q u e s t o the d e s i g n of a L o c a l Area Network, a s i m p l e and e r r o r r e s i s t a n t network I s be ing d e v e l o p e d . I t s main a p p l i c a t i o n w i l l be e i t h e r as network in an e l e c t r i c a l l y n o i s y env ironment or In a h i g h throughput m u l t i p l e a c c e s s n e t w o r k . Computer s l B u l a t l o n s c a r r i e d out i n d i c a t e t h a t the s y s t e m w i l l be c a p a b l e of s u p p o r t i n g o v e r 60 u s e r s t r a n s a i t t i n g s i m u l t a n e o u s l y . Tests carried out on a p r o t o t y p e n e t w o r k c o n s i s t i n g o f 5 n o d e s : 3 t r a n s a i t t i n g nodes end 2 r e c e i v e r n o d e s , have v e r i f i e d the r e s u l t s p r e d i c t e d by the computer s i a u l a t i o n and d e m o n s t r a t e d the f e a s i b i l i t y of s i a u l t a n e o u s m u l t i - p a i r coaaunicatIons .
Th* n*xt s tagas of tha project w i l l b* to
I n v e s t i g a t e a l t e r n a t i v e phase s y n c h r o n i s a t i o n schemes and determine the whether the model of the p r o t o c o l , o u t l i n e d above, i s optimal for control of a s y s t e m of t h i s n a t u r e . The computer s t u d i e s are a l s o t o be enhanced in order to I n v e s t i g a t e the l i n e monitoring and c o l l i s i o n d e t e c t i o n funct ions assumed in the model d e v e l o p e d . I n v e s t i g a t i o n of code p r o p e r t i e s under more r e a l i s t i c condl : lons Is a l s o proposed.
Whilst It Is too ear ly at t h i s s tage of development to make accurate predic t ions regarding the cost and r e l i a b i l i t y of the f i n a l network, the r e l i a b i l i t y of the low c o s t deve lopment modules has been encouraging •
8 ACXNOWLEDGEMENTS
This research project Is being supported by a grant from t h e A u s t r a l i a n T e l e c o m m u n i c a t i o n s and E l e c t r o n i c s Research Board.
9 REFERENCES
1- SCHOLTZ R.A., "The Origins of Spread Spectrum Communicat ions". I .E .E.E. T r a n s a c t i o n s on Communicat ions , Vol- COM-30, No 5, Hay 1982, pp. 8 2 2 - 8 5 ^ .
2. SMYTHE C.S. and SPRACKLEN CT- , "A High Speed Local Area Network Using Spread-spectrum Code-d 1 V 1 s l o n - m u 1 t 1 p 1 e - a c c e s s Techn lques ' i The Radio and E l e c t r o n i c Eng ineer , Vol- 5^, May 198^. pp.225-226.
11.
DIXON R.C, "Spread Spectrum Systems'
(New York), 1976. W i l e y
i< • HOLMES J-K-, "Coherent Spread S p e c t r u m Systems", Wiley (New York) 1982.
5- PICKHOLTZ R-L-, SCHILLING D-L-. MILSTEIN L.B-, ""Theory of Spread Spectrum Communications - A T u t o r i a l " , I . E . E . E . T r a n s a c t i o n s on Communicat ions , Vo l . COM-30, May 1982, pp. 855-88A.
6- SARWATE D-Y- and PURSLEY M-B.. ""Cross C o r r e l a t i o n P r o p e r t i e s of Pseudo-Random and R e l a t e d Sequences" . P r o c I.E.E-E. Vol . 69 , May 1980, pp-593-619.
7. GOLD R.. '"Optimal Binary Sequences For Spread Spectrum Mult ip lex ing"", I.E.E., T r a n s a c t i o n s on I n f o r m a t i o n Theory. V o l . I T - 1 3 , 1967 , pp .619-621 .
8. CARLSON BRUCE A., "Communication Systems -An I n t r o d u c t i o n t o S i g n a l s and N o i s e In E l e c t r i c a l C o m m u n i c a t i o n " , McGraw-Hi l l , (Tokyo) , 1981 .
9. PURSLEY M. B. and SARWATE D. V., "Performance E v a l u a t i o n for Phase Coded Spread Spectrum M u l t i p l e A c c e s s Communications - Part I I " , I.E.E.E. T r a n s a c t i o n s on Communications Vol-COM-25. August 1977. pp.800-803-
10- HIROSAKI B.. HASEGAWA S-. SAWAI A., "Spread Spectrum M u l t i p l e Access Dato Loop". NEC Res DEV n71. October 1983, pp.«8-58.
KLEINROCK L. and TOBAGI F.A-. " P a c k e t S w i t c h i n g In Radio Channe l s : Part 1 ", IEEE T r a n s a c t i o n s on C o m m u n i c a t i o n s V o l - 2 3 , December 1975, pp I'.OO-l'.lS
Ittiir^i of Elearical and Elearonia Engineering. Australia — IE Aust. i IREE AusL. Vol. 7. No. 2 June, mr'
A L SIMCOCK
Alec Simcock graduated from the University of Kent at Canterbury with the B.Sc. (Hons) (Electronics) in 1972. He worked for 12 years with Procurement Executive of the Ministry of Defence in UK, researching in the following areas: Digital Circuit design, Digital Data switching, computer controlled Communication systems and Microprocessor replacement of Digital Circuits, The work also involved the implementation of Software Project Management techniques. He was appointed to a Lectureship with the Department of Electrical and Electronic Engineering, Footscray Institute of Technology in 1983.
C na RANONG
Chula na Ranong received the B.E.(Hons) degree in Electrical Engineering and Ph.D. from the University of New South Wales in 1970 and 1973 respectively. Since 1972 he has been with the Department of Electrical and Electronic Engineering, Footscray Institute of Technology as a Lecturer and hater. Senior Lecturer in Digital Electronics and Systems. During 1977-78, he spent a year as a Visiting Professor, School of Electrical Engineering, Cornell University, Ithaca, New York, USA. Then, for the first six months of 1982, he worked as a Specialist Engineer with Compagnie Europeene de Teletransmission (Thomson-CSF), Chatou. France developing a mass storage system for a real time digital data.network supervisory control system. More recently, as a result of his interest in Automation Technology, Chula undertook a two months study visits to Japanese government, industrial and educational research institutions in 1984.
P S K LEUNG
Patrick Leung received the B.E. (Elect) and M.Eng.Sc. in Electrical Engineering from the University of Melbourne in 1972 and 1974 respectively. Between 1975 and 1977 he was a lecturer in the Department of Electrical and Electronic Engineering, Footscray Institute of Technology. In 1977 he joined Telecom Australia as an engineer in the Datel design and provisioning section. In 1979 he rejoined F.I.T. as a lecturer in communications engineering. In the first half of 1985 he visited the Department of Electrical Engineering, Ottawa Univeristy, as a research fellow, to carry out work in data communications over satellite channels. On his return to F.I.T. he was appointed senior lecturer in communications. His main interests are data transmission techniques, data networks and data protocols.
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