Lithography-free fabrication of carbon nanotube network transistors

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IOP PUBLISHING NANOTECHNOLOGY

Nanotechnology 22 (2011) 065303 (6pp) doi:10.1088/0957-4484/22/6/065303

Lithography-free fabrication of carbonnanotube network transistorsMarina Y Timmermans1,4, Kestutis Grigoras2,Albert G Nasibulin1, Ville Hurskainen3, Sami Franssila2,Vladimir Ermolov3 and Esko I Kauppinen1

1 NanoMaterials Group, Department of Applied Physics and Center for New Materials, AaltoUniversity School of Science and Technology, PO Box 15100, 00076 Aalto, Finland2 Microfabrication Group, Department of Materials Science and Engineering, Aalto UniversitySchool of Science and Technology, PL 13000, 00076 Aalto, Finland3 Nokia Research Center, Itamerenkatu 9, 00180 Helsinki, Finland

E-mail: marina.timmermans@hut.fi and kestas.grigoras@tkk.fi

Received 20 October 2010, in final form 25 November 2010Published 7 January 2011Online at stacks.iop.org/Nano/22/065303

AbstractA novel non-lithographic technique for the fabrication of carbon nanotube thin film transistorsis presented. The whole transistor fabrication process requires only one mask which is usedboth to pattern transistor channels based on aerosol synthesized carbon nanotubes and todeposit electrodes by metal evaporation at different angles. An important effect ofelectrodynamic focusing was utilized for the directed assembly of transistor channels withfeature sizes smaller than the mask openings. This dry non-lithographic method opens up newavenues for device fabrication especially for low cost flexible and transparent electronics.

S Online supplementary data available from stacks.iop.org/Nano/22/065303/mmedia

(Some figures in this article are in colour only in the electronic version)

1. Introduction

Carbon nanotube networks (CNTNs) have been widely studieddue to their potential for low cost applications in electronics,enabling large area coverage with high transparency andstructural flexibility. Significant progress has been madein the deposition of carbon nanotubes (CNTs) on differentsubstrates. Depending on the processing technique, thereare two commonly used approaches for the preparation ofCNTNs at low temperatures. CNTs can be grown directlyon a substrate using a chemical vapor deposition (CVD)process and dry-transferred from their growth substrates to thereceiver surfaces by the stamp method [1, 2]. The drawbacksare a need for a suitable CNT transfer medium onto heat-intolerant substrates (since high temperatures are required forthe CVD process) and complications with the CNT transferefficiency and uniformity. Another commonly used way isthe deposition of CNTs from their liquid suspensions byvarious methods, e.g. inkjet printing, spin-coating, vacuumfiltration, airbrushing, electrophoretic deposition etc [3, 4].

4 Previously published as Marina Y Zavodchikova.

Using this approach, CNTs synthesized by one of the severalbulk methods can be purified, sorted by length or chirality anddeposited at room temperature. The main disadvantages ofthis approach are high time consumption and possible CNTlength reduction, contamination and degradation of electricalproperties caused by the high power ultrasonication and acidtreatments needed to prepare homogeneous dispersions ofCNTs. Recently, we have demonstrated the third approach—an alternative and very efficient technique to deposit single-walled CNTs (SWCNTs) at room temperature directly fromthe aerosol (floating catalyst) synthesis reactor. This single-step technique, instantaneously following the CNT growth,offers a dry simple and quick method to deposit pristineSWCNT networks with controllable density, avoiding timeand resource consuming and potentially detrimental liquidpurification and dispersion steps, and allowing the use of lowcost, transparent, flexible and heat-sensitive substrate materialsas well as conventional silicon substrates [5, 6].

However, successful implementation of CNTNs in devicesrequires the ability to pattern the networks into various featuresat desired locations on the substrate. Low material qualityand high processing temperatures are the main challenges of

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pre-growth patterning techniques, i.e. CNT growth selectivelyon a pre-patterned catalyst film by the CVD process [7, 8].To overcome these problems, a number of post-growthpatterning techniques have been demonstrated, includinginkjet [9, 10] or screen printing processes [11], electrophoresisdeposition [12, 13] and chemically anchored deposition [14],where CNTs are patterned onto the substrates after the growthand purification processes from their liquid suspensions.Standard photolithography and subsequent etching methodsare currently the most widely used for patterning CNTnetworks to electrically separate individual devices from eachother and eliminate parasitic leakage paths. Typically, afterdevice fabrication, the channel area is protected by a patternedphotoresist and the rest of the substrate is cleaned from theCNTs with oxygen plasma dry etching [15] or CO2 snowjet [16], followed by photoresist removal in acetone. However,most of the methods mentioned above typically require tediouspreparation and implementation steps, precise control of thepatterning conditions and possess such limitations as substraterestrictions or requirements of substrate modification. Whilephotolithography can be successfully exploited for patterningthe network of CNTs and metal electrodes, there is a possibilityof CNT material contamination associated with photoresisthandling [17], as well as the reduction of the networkdensity during the final lift-off step. Moreover, since contactelectrodes are typically deposited by means of lithographyand lift-off, there are multiple alignment steps involved inthe device fabrication process that require accuracy and timeconsumption.

Here, we propose a novel method for the fabrication ofCNT thin film transistors (TFTs), which does not requirephotolithographic or etching processes and is performed atroom temperature, allowing the use of heat-sensitive flexibleand transparent substrate materials. This method enables us toeliminate the tedious processing steps of the CNT dispersionpreparation, during which the alteration of the electricalperformance of CNTs is unavoidable. Requiring minimumfabrication steps, our new method is time-saving, efficient andattractive for scalable fabrication of CNTN devices. The keyfeature of the technique is the utilization of a single shadowmask used both to create a patterned network of CNTs andsubsequently define the metal electrodes on top, fabricatingboth the back-gate and top-gate transistor geometries. Here, forthe first time we demonstrate the process of CNTN patternedself-assembly at ambient conditions simultaneously with theirdeposition from the gas phase and precise alignment of all thetransistor layers just by changing the deposition angle, keepingthe shadow mask in place. Utilizing this single mask approach,we successfully fabricated CNTN transistors on both rigid andflexible substrates. The proposed technique can be used forthe fabrication of various devices based on other nanomaterialssynthesized in the gas phase.

2. Results and discussion

SWCNTs were synthesized in the gas phase by thermaldecomposition of ferrocene vapor (FeCp2, 99%, StremChemicals) in a carbon monoxide (CO) atmosphere, using

an aerosol (floating catalyst) CVD reactor at a temperatureof 880 ◦C (with an addition of 0.75% of CO2) [18], anddeposited directly downstream from the synthesis reactor atroom temperature. The product consisted mainly of smallbundles of high quality SWCNTs with a mean diameter ofaround 1.5 nm and average bundle length 3 μm (supplementarydata, figure S1 available at stacks.iop.org/Nano/22/065303/mmedia). The deposition was performed by means ofan electrostatic precipitator (supplementary data, figure S2available at stacks.iop.org/Nano/22/065303/mmedia), wherethe density of the collected network was defined by thedeposition time and the applied electric field, as described indetails elsewhere [5, 6]. Controllable positioning of the CNTsat the desired areas during the deposition was achieved byusing a shadow mask located at a certain distance from thesubstrate surface.

2.1. Bottom-gate CNT TFTs

CNT TFTs with a bottom-gate structure were fabricated ona highly boron doped Si substrate, coated with a thermallygrown SiO2 (100 nm), acting as a gate dielectric. To providea better contact for the back-gate electrode, a 200 nm thickAl layer was sputtered on the back-side. The schematicsof the step-by-step device fabrication process is shown infigure 1. A polymer mask (ultem or kapton material),fabricated separately, was attached to the substrate surfacevia clips and/or tape, leaving a gap of ∼70 μm betweenthe substrate and the mask (figure 1(a)). This ‘sandwich’structure was placed inside an electrostatic precipitator, usedfor the efficient deposition of CNTs by means of an electricfield straight from the aerosol (floating catalyst) synthesisreactor, as mentioned earlier. The openings in the mask(50 × 100 μm2 in the kapton mask or 100 × 200 μm2

in the ultem mask) defined the regions where the CNTNwas to be deposited (figure 1(b)). The CNTN density wascontrolled by varying the deposition time (typically 30–120 s)and applied electric field (300 kV m−1). The deposition of theCNTN was followed by metal evaporation. 50 nm thick Auelectrodes were evaporated using an electron beam evaporator(IM9912) through the shadow mask by adjusting the metaldeposition angle (or by tilting the sample stage during themetal deposition), as shown in figures 1(c) and (d). Thetilting angle determined the distance between the electrodes(channel length), and was adjusted depending on the openingin the mask, taking into account the focused deposition of theCNTs (as described further), and the gap between the maskand substrate using a simple geometry formula (supplementarydata, figure S3 available at stacks.iop.org/Nano/22/065303/mmedia). In our case, the typical tilting angle was around20◦, resulting in channel lengths of 20–60 μm. The layer-to-layer alignment accuracy was verified using both opticaland scanning electron microscopy imaging. The schematics ofthe ready-made bottom-gate transistor and a scanning electronmicrograph of the CNTN, patterned with a polymer shadowmask, are shown in figure 1(e).

The devices were measured at ambient conditions usingan HP 4155A semiconductor parameter analyzer (SPA), and

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Figure 1. Schematics of a step-by-step fabrication process of a CNT TFT based on the application of a single shadow mask both for ((a), (b))the deposition of SWCNTs directly after their aerosol phase synthesis and ((c), (d)) defining source and drain electrodes by adjusting themetal deposition angle. (e) Schematics of the as-fabricated bottom-gate CNT TFT without a mask and scanning electron micrograph of theCNTN channel between the source and drain electrodes. Fabrication of a top-gate TFT by (f) depositing a dielectric layer of Al2O3 using anALD technique, (g) straight metal evaporation and (h) mask removal.

Figure 2. (a) Transfer ID–VGS characteristics of a typical bottom-gate CNT TFT, fabricated using a polymer shadow mask with the openingsize 50 × 100 μm2. The TFT channel length is 55 μm and width ∼10 μm (the substrate tilted on the axis perpendicular to the CNT channelduring metal evaporation). (b) Ids–Vg characteristics of a typical top-gate CNT TFT with a 145 nm thick ALD Al2O3 layer as a gate dielectric,fabricated using a polymer shadow mask with the opening size 100 × 200 μm2. The TFT channel length is 40 μm and width ∼130 μm.

exhibited an on/off ratio of up to 105 with the effective devicemobility of ∼5 cm2 V−1 s−1 (figure 2(a)). The mobility wascalculated by a commonly used formula [19], where the CNTNis treated as a uniform film and a parallel plate model is usedfor the gate capacitance calculation (known to underestimatethe mobility by about a factor of 2 [20]). We observedhysteresis in the transfer characteristics of CNT TFTs, typicalfor CNT-based transistors, which can be reduced by protectingthe nanotube channel from ambient humidity with surfacepassivation [5, 21], modifying the chemical structure of thesubstrate surface where CNTs are deposited [22, 23] or using ashort-pulsed measurement technique [24, 25].

2.2. Top-gate CNT TFTs

The lithography-free CNT TFT fabrication method wasfurther applied for the manufacturing of a top-gate transistorstructure where all transistor layers were patterned by meansof a single shadow mask. In the case of the top-gatetransistor fabrication, after patterning of a CNTN and definingsource/drain electrodes, a 145 nm thick Al2O3 dielectric layerwas deposited through the openings in the shadow maskby atomic layer deposition (ALD) technique, still keepingthe shadow mask intact on the substrate (figure 1(f)). Theprocess was carried out in a TFS-500 reactor (Beneq) usingtrimethyl aluminum (TMA) as a precursor for aluminum and

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Figure 3. (a)–(c) Scanning electron micrograph showing electrodynamic focusing of charged SWCNTs on a Si/SiO2 surface (the actualshadow mask opening is shown by a dashed line). Polymer mask openings 50 μm, 100 μm and 200 μm wide result in CNTN patternsfocused to a width of around 10 μm, 40 μm and 100–150 μm, respectively. Electric field and potential simulations for a −6 kV voltageapplied to the substrate surface and a charge of (d) 10−5 C m−2 and (e) 10−4 C m−2, accumulated on the mask surface, reveal focusing ofCNTs into the 100 μm mask opening. The accumulated charge on the mask surface was simulated by adding a uniform 2D surface charge tothe upper 10 nm layer of the mask. The thickness of the arrows illustrates the strength of the electric field. The dashed lines schematicallydemonstrate the trajectory of CNTs during the gas phase deposition. The mask material is kapton (ε = 3), the mask opening is100 × 100 μm2. The gap between the mask and the substrate is 70 μm.

water or ozone as a precursor for oxidation. The standardtemperature of the ALD growth process was 200 ◦C, but lowertemperatures (80 ◦C) were used in the case of heat-sensitivepolymer substrates. The final step was the formation of a topgate by gold evaporation (electron beam evaporator IM9912),straight through the mask opening without tilting the substrate.The metal contact appeared exactly over the CNTN channel(figure 1(g)). Finally, the shadow mask was removed fromthe substrate surface (figure 1(h)). Electrical measurementsof the devices were performed at ambient atmosphere withHP 4155A SPA. Figure 2(b) shows an example of the transfercharacteristics of as-fabricated top-gate CNTN transistors.Opposed to the bottom-gate structures, the top-gate transistorsexhibited ambipolar conductivity due to the absence of chargetransfer and doping effects [23, 26]. The performance of thesedevices can be improved by optimizing the device structure andCNTN density.

2.3. CNTN patterned assembly

Typically, when using a shadow (stencil) mask, patterns with aline spacing of 100 μm or less are difficult to achieve due tothe limitations in shadow mask fabrication. Here, in order topattern CNTNs, we were able to overcome the mask resolutionlimits by means of the electrodynamic focusing effect ofCNTs during their deposition in the gas phase. An analogousfocusing effect, but for nanoparticles assembled within thephotolithographically prepared patterns, was shown earlier byKim et al [27], who additionally introduced ions of the samepolarity as charged aerosol nanoparticles to achieve focusing.

However, such focused self-assembly of CNTs was observedhere for the first time. This effect can be described andexplained as follows. The SWCNTs form small bundles duringthe synthesis process by the aerosol (floating catalyst) methodand are spontaneously charged with up to five elementarycharges, as shown recently [28]. The charging was explainedin the framework of aggregation processes leading to theenergy release due to the minimization of the surface energyand emission of electrons and positive adsorbent molecules,as described in detail elsewhere [28]. We utilized thisphenomenon to increase the deposition efficiency of SWCNTbundles onto the substrate by applying an electric field [5, 6],and here the use of a shadow mask allowed us to control thelateral positioning of CNTs during the gas phase deposition.At the initial stages of the deposition process, charged SWCNTbundles are uniformly distributed through the mask openingwith the density still below the percolation limit. Chargeis accumulated on the shadow mask surface simultaneouslywith the CNT deposition process, modifying the appliedelectric field and producing electrostatic lenses around themask opening. Further, charged CNTs approaching the maskare repelled by the charge of the same polarity, accumulated onthe mask surface, and are efficiently focused through the maskopening onto the collecting substrate, producing feature sizesof the obtained patterns smaller than the openings in the mask.Scanning electron micrographs of the typical CNTN patterns,deposited through the shadow mask for the same time period,can be seen in figures 3(a)–(c). The polymer mask openings of50 μm, 100 μm and 200 μm were producing CNTN patternswith a width of around 10 μm, 40 μm and 100–150 μm,

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Figure 4. (a) Scanning electron micrograph showing selective deposition of SWCNT bundles via electrodynamic focusing through a polymermask (opening size 100 μm), attached to the Si/SiO2 substrate with a gap of 70 μm between the mask and the substrate. A voltage of−5.5 kV, corresponding to 10−4 C m−2 surface charge accumulation, was applied to the mask surface, covered with a 100 nm layer of Au,while −6 kV was applied to the substrate. (b) Corresponding electric field and potential simulations (kapton mask, ε = 3, 100 × 100 μm2

opening).

respectively. The obtained results show that the focusingeffect is strongly related to the size of the opening: for over200 μm the focusing is negligible, and for a 50 μm openingthe focusing ratio is about 5:1. This can be explained by thedifference in electric field strength in the formed electrostaticlenses.

By varying the amount of charge accumulated on themask surface, it is possible to control the CNT depositionprocess through the mask, as can be seen from the electric fieldand potential simulations performed with CST E-static solver(version 2010) to verify the experimental results (figures 3(d)and (e)). According to the electric field simulations, thefocused deposition of CNTs was achieved during 60–120 sCNT collection times. This corresponds to the accumulatedsurface charge on the order of 10−5–10−4 C m−2, as estimatedtheoretically taking into account nonequilibrium charging ofthe SWCNT bundles with 1–5 elementary charges, substratesize and the average SWCNT bundle density. Over time theamount of charge accumulated on the mask surface increases,leading to a higher density of CNTs collected in the area of thesubstrate corresponding to the center of the mask opening. Thefocused patterning of CNTs was tested using various shapes ofthe mask openings (supplementary data, figure S5 available atstacks.iop.org/Nano/22/065303/mmedia). The controllabilityof the focused deposition of CNTs can be further studiedby introducing charged aerosols prior to the deposition ofthe CNTs, as shown in [20] for nanoparticles or applying avoltage directly to the mask in order to repel the CNTs fromthe mask surface during the deposition while simultaneouslyforcing them into the mask openings. The latter techniquewas demonstrated in [29] for nanofibers and was successfullyused here to achieve focused assembly of CNTs, as shownin figure 4. By applying a voltage directly to the mask itis possible to achieve a better control over the size of theCNTN, depositing narrower CNT patterns, since no priorcharge accumulation onto the mask during the CNT depositionis required for focusing to occur. Therefore, by controllingthe electric field induced motion of CNTs, we are able toselectively deposit CNTs and scale down the features of CNTNpatterns, overcoming the mask resolution limits, which isadvantageous for various electronic applications.

Both polymer and silicon masks have been used in ourexperiments. Rigid silicon masks exhibit an advantage fromthe mechanical stability of the material, excluding possibledistortion in the created device patterns that might be causedby the flexibility of thin polymer masks. The use of a siliconmask with our fabrication method was successfully tested,giving similar results as with a plastic mask, as shown inthe supplementary data, figure S6 (available at stacks.iop.org/Nano/22/065303/mmedia).

The demonstrated behavior of as-fabricated CNT TFTsis superior to typical low cost organic transistors, butleaves room for further improvements in order to realizethe performance levels potentially achievable with the CNTmaterial. The performance of CNT TFTs can be furtherimproved by tuning the chiral distribution of SWCNTsduring the synthesis [30–32], increasing the tube length aswell as aligning the tubes perpendicular with respect tothe electrodes [33–36]. The competitive advantage of themethod, demonstrated here, is that it allows us to minimizethe intermediate steps between the SWCNT synthesisand application by eliminating the potentially detrimentalliquid-based purification and dispersion procedures in thepreparation of a CNTN, and importantly, simplifies the devicemanufacturing by avoiding tedious processing required for thefabrication of TFTs by lithographic means. Thus, due to thereduction of time and resource consumption, lower fabricationcosts are achievable. Moreover, the method is conducive to thefabrication of CNT TFTs on flexible and transparent substrates.To demonstrate that, we have successfully fabricated CNTTFTs on a polyethylene naphthalate (PEN) polyester substrateusing the shadow mask approach (figure 5).

3. Conclusions

In summary, a novel dry lithography-free fabrication methodof CNTN transistors is demonstrated. This technique isexpected to provide a low cost manufacturing method, enablinga simple process of CNTN direct deposition and patterningusing a shadow mask, and the subsequent formation of all theelectrodes and insulating layers in a self-aligned manner bykeeping the mask fixed on the substrate. Both bottom- and

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Figure 5. Flexible CNT TFT fabricated using a lithography-free technique: (a) photograph of an array of TFTs on a flexible PEN substrate.(b) Transfer (ID–VGS) characteristics of a top-gate CNT TFT on a PEN substrate, fabricated using a polymer shadow mask with the openingsize 100 × 200 μm2, where a thin layer of Al2O3, grown by ALD technique, was used as a gate oxide.

top-gated transistors were successfully fabricated on siliconand transparent flexible polymer substrates, exploiting plasticand silicon masks. The effect of electrodynamic focusing ofthe CNTs was utilized for the directed assembly of transistorchannels with feature sizes smaller than the mask openings.This method is scalable and easy to implement for thefabrication of various integrated circuit components especiallyfor low cost flexible and transparent electronics.

Acknowledgments

The authors thank Mr Colin Timmermans for graphics design,Dr Ilya Anoshkin for assistance with absorption measurementsand insightful advice, Dr Anton Anisimov for the contributionwith the SWCNT synthesis and Dr Aravind Vijayraghavan forfruitful discussions. This project was partially funded by theAcademy of Finland (project No. 128445).

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