IMTC ?OM Instmmrntation and Measurement Technology Conference Coma. tdy. May 18-?0.2004

Measurement of the Silicon Resistivity at Very High Temperature with Junction Isolated Van der Pauw Structures

C. Corvasce, M. Ciappa, D. Barlini, F. Illien, and W. Fichtner

Swiss Federal Institute of Technology (ETH) Integratud Systems Labontory

ETH-Zentmm ~ CH-8092 Zurich, Switzerland Phone: +41 I 632 1597, Fax: +41 I 632 1194. E-mail: cchim@iis.er.rthi.ch

The performance o f modern Integrated Circuits (IC) oper- ated in harsh environments (e.g. automotive, mobile applica- tions) strongly depends on the robustness o f the on-chip pro- tection structures that prevent damage produced either hy elec- tromagnetic interference or by switching of inductive loads. In almost all these cases the related failure mechanisms are driven by the filamentation of the current with a consequent localized self-heating o f the semiconductor at temperatures exceeding IOO0"C. The most recent approaches to design robust protec- lion devices make use o f physical device analysis combined with device simulation [ I ] . Nowadays, device simulators are not very accurate in predicting the transient behavior o f protec- tion devices because the models used for the physical semicon- ductor parameters as conductivity. mobility, impact ionization coefficients, are experimentally validated for temperatures be- low the 250-300°C. The lack o f experimental data over 300°C i s due to the use o f test structures and procedures which prop- erly operate in the low temperature range hut fail at highertem- peratures.

The van der Pauw (VdP) four probes technique allows to measure the specific resistivity o f flat samples with arhitrary shape. The method works under the assumption that the con- tacts are small enough and placed at the periphery of the sam- ple. which has to he unifiirmly thick and a simply connected surface. The main advantages o f the VdP technique are that no dimensional information is required to extract the sheet re- sistance and that the measurement just consists o f forcing a current between two ad.iacent nodes sensing the voltage drop across the remaining two ones. For perfectly symmetrical sam- ples shaped as squares, circles and greek crosses (GC), the

0-7803-8248-X/04/$17.00 02004 IEEE

sheet resistance i s extracted by the general equation [21:

where I,, is the current forced hetween two contacts and 1/34 i s the voltage drop across the other ones. Measurements are normally carried out over an extended doping range on inte- grated standard test structures which make use ofjunction iso- lation. As the temperature increases structural factors such as the geometry and the doping profile start to become critical becausc o f the junction sensitivity to the thermal carrier gener- ation which strongly affects the local potentials. Thus, at high temperatures, the sample resistivity cannot be longer predicted

As an example, Fig. I shows the sheet resistance o f a sam- ple as measured on a junction isolated greek cross (dots) in comparison with the values expected from the theory (solid lines) [3][4][5]. Starting from a critical temperature (TC), the experimental resistivity curve drops largely before the sample becomes intrinsic. This effect does not allow any correct resis- tivity evaluation in a temperature range beyond TC.

by Eq. (1).

0 f W 2M MO 4 0 0 MO so0 no Tmpr. lum<cl

Fig. I. Sheet resistance YS temperature as measured on il GC junclion isolated VdP (dots) and according tu rhr theoretical models (lines). TC=33O"C

In this paper thc parasitic effects related to the thcrmal gen- eration in VdP structures are investigated in order to extend the

131

measurement range up to temperatures higher than TC. With this purpose. we propose suitable design rules combined with a proper biasing scheme for the test structures. In this framc- work, full three-dimensional physical device simulations have been extensively used hoth to investigate thermal generation at critical junctions and to identify the parasitic current leakage paths through the substrate as the temperature increases. The simulation data have been validated by experiments.

11. EXPERIMENTAL

A. Samples

The measurements have been performed with greek cross and circular silicon resistors (p- and n-type) fabricated by using the different layers available in a commercial smart power technology for automotive applications. The arms of the greek crosses are 125pm long and 10pm wide. The boron-doped resistor (GC) is diffused in a n-epitaxial layer doped 1 x 10'6m-3 and has a peak concentration of 1.3 x 10'8m-3. The diameter of the p-doped circular resistors is 100pm. They are supplied with three different doping profiles: a lightly p-doped resistor (PI) having a peak concentration of 5.7 x 1016c77-3, a resistor (PZ) having a doping density of 1.2 x l O ' * ~ m - ~ , and finally a heavy doped p+ resistor (P3) reaching an impurity concentration of 2.6 x 1020m-3. All devices are diffused in a n-type epitaxial layer having a doping density of 7.4 x~ 10'5cm-3. A common feature of the circular p-doped samples is a buried, high-low junction formed by dif- fusing a heavy n+ implant into the n-epi. The junction is con- tacted by the n-sink diffusion having approximately the same doping of the buried layer and surrounding the resistor area. The n-doped resistors are supplied with the following doping profiles: a lightly n-doped resistor (NI) having a peak conccn- tration of 4.8 x 10'7cm-3, a shallow junction higher doped resistor (N2) having a doping density of 1.2 x l O ' @ ~ m - ~ and a heavy doped n+ resistor (N3) with an impurity concentra- tion of 6.4 x lO*"~m-~. They are all diffused in a p-well area having a doping density of 5 x 10'6cm-3 contacted by a ded- icated implant. The contact area of all devices is 1pm2, while the circular resistors are provided by two additional auxiliary contacts that allow the polarization of the resistor junction and the buried junction as well.

B. Measuremerits set-up The extraction of physical parameters in silicon at tempera-

ture beyond 400°C imposes very strict requirements in terms of the experimental setup. The main issues arc related to tempera- ture control, tu thc low current sensitivity of the equipment, and to leakage current paths. Two experimental systems have been realized to perform very high temperalure measurcments. The first system is hased on a standard thermal chamber equipped by a dedicated Proportional Integral Derivative control (PID), which enahles 10 scl the chamber temperature with an accu- racy of 0.3"C up to 500°C. The second system makes use of a radiation heated chamber with a working range up to I00O"C

in an argon atmosphere. A new adaptive PC-driven process controller has been designed to reach the targeted temperature in the shortest time, without temperature overshoots, and with an accuracy of 0.5"C. Once stabilized, the control starts auto- matically the measurement sequences. In hoth cases a novel cable isolation technique has bcen used to reduce the level of the leakage current down to the lOpA range.

C. Simulation tool

Full three-dimensional (3D) numerical simulations of the resistors have been performed using the device simulator DESSISISE 161. The simulation models have the same size of the real samples resulting in a maximum number of 150,000 grid points. For sake of simplicity, circular VdP resistors have been approximated with square shaped simulation models. For illustrating structure design criteria hy simulation results the P2 doping profile has been used as a reference.

111. SIMULATION RESULTS

A. Thermal leakage

The simulation has heen carried out at different tempera- tures forcing a constant current of 10pA in a square p-doped VdP with the P2 profile and by keeping the substrate Roat- ing. Because of the capacitive coupling between the layers, the junction is hiased and a small current flows through it. At room temperature, almost the total flow of majority carriers is con- fined within the resistor, while the diffusion current towards the substrate is negligible and does not impact the measurement of the sheet resistance.

As the temperature is increased the following parameters are strongly affected.

~~

ni: as soon the intrinsic carrier concentration approaches the doping concentration, an abrupt decrease of the resis- tivity is expected. This effect occurs firstly in the epitaxial layers or in general in the regions with the lowest doping concentration. Vb;: the built-in potential of the junction decreases as the intrinsic carrier concentration increases. This is due to thermally generated electron-hole pairs in the junction. The impact of this effect on the space charge region of the considered sample is shown in Fig. 2. As soon the n-epi layer and the low-doped tail of the p+ diffusion approach the intrinsic regime. the electric junction shifts inside the p+ doped region. When hoth become intrinsic, the har- rier disappenrs and and the current is no longer confined within the p-region, since the sample behaves as a dif- fused resistor with a very large conducting crosssection. p: due to the mobility degradation with temperature, the voltage applied to the injection terminals (working at con- stant current) has to he increased when increasing the tem- perature. This leads to an increase of the voltage drop across the junction, especially in the close vicinity of the high voltage terminal.

I34

Fig. 2. Space charge distribution at thermal equilibrium as B function of the tcrnperatuturr in rhc 25-425"C nnge (atep=SO"C)

Figure 3 shows the current density contours in the VdP resistor at the critical temperature TC and the related equivalent cir- cuit, consisting of two vertical PNP transistors (p+ emitter, n- epi base, p-substrate collector), of resistors (layer resistance), and of a current source (constant current injection hetween the terminals).

The onset of the current concentration immediately helow the injecting contacts is due to the turn on of the bipolar tran- sistors, whose base current is provided by the electrons that are thermally generated in the n-epi layer. Although their gain is quite poor. due to the large base thickness combined with thc high resistance of the layers, the PNP transistors star1 to represent an efficient alternative conduction path as soon the resistance of the p+ layer increases due to the mobility degra- dation with temperature. This explains why the apparent sheet resistance of 3 VdP sample dccreases heforc one of the layers gets intrinsic.

At higher temperatures. the low-doped regions get intrinsic (n-epi and p-sub in the present case) such that both junctions no longer provide an isolation between the layers. As a con- sequence, the forced current is not longcr confined within the p+ resistor and llows within the intrinsic layers producing the observcd sudden drop of the apparent sheet resistance.

E. Geometry impact

Different geometries have been proposed to measure the sheet resistance by the four probe technique. In parlicular, the Greek cross and the square resistor conligurations have been compared using full 3D simulations to investigate the impact of the geometry on the accuracy of the resistivity extraction at high tempcrature.

Figure 4 shows the latcral conduction path, which sets on at 300°C i n a Greek cross resistor. As can he seen, the currenl is no longer confined within the cross since a large amount of the current Rows in the n-epi layer. Thc incasured rL. 'Clstance '

is therefor equivalent to the parallel connection of the p+ layer and the n-epi. This behavior suggesls the onset of a parasilic lateral bipolar action. Figure Sa shows the comparison between

Fig. 4. Lalrnl conduction path in B floating substrate G m k cross VdP resistor due to the pmsilic lateral bipolar 1rmsis10r

the temperature dependence of the apparent sheet resistance as extracted from a Greek cross and from an equivalent square VdP test structure. The turning point of the curve to the Greek cross occurs at about 210°C , i.e. about S O T lower than for the square resistor. This hehavior can be attributed to the turn on of the lateral parasitic bipolar transistor in the Greek cross resistor.

Figure Sb shows the dependence of the location of the turn- ing point on the aspect ratio of the arms of the Greek cross. Greek crosses with a lower aspect ratio are less sensitive tn the effect of parasitic lateral transistors, since they result into a lower value of the VdP resistor and thus, at a constant injected current, into a lower collector-to-emitter voltage.

In summary, this analysis indicates that square or circular VdP shctures are more suitahlc as test structures for high tem- perature measurements because they are intrinsically immune to parasitic lateral bipolar transistors.

C. Doping impact

The results exposed in the previous sections clearly indicate that proper ,junction engineering is fundamental to extend the operating temperature range o l the VdP structures. The struc- tures considered to investigate the impact ofthe suhstrate dop- ing and of the layer thickness are represented in Fig. 6. They

0 , m . w r o u a a t w 2 m x o . m '-,cl T W W * , G ,

Fig. 5 . Shea resistance YS lernpenture: a) cornpaison ktween a square~shaptd resistor and m equivalent Greek cross h) deprndrncu on the

arms spec1 d o in a Greek cross

are square-shaped VdP stmctures with the same doping level for the resistor (p+) hut different doping profiles for the un- derlying layers. Three relevant isolation cases have been com- pared: (a) n-epi/n+/p-sub, (b) n+/p-sub, and (c) n-epilp-sub. The effect of the thickness of the n-epi-layer on the leakage

(a) (b) i ~ (C)

- P r a m *

U& L*

CQ-

Fig. 6 . Simulated doping configurations

currents has been investigated in the case of structure (c) and it is shown in Fig. 7a. As expected, the thicker epi-layer re- sults into the hest performance since i t decreases the gain of the parasitic vertical transistor by increasing its base width.

The effect of the doping level of the n-epi layer has been in- vestigated by comparing the structure (b) and (c) (n-epi thick- ness 10prn). Figure 7b shows that by increasing the doping level hy one decade, the operating range of the VdP suucture can he extended by about I0o"C up to a maximum tempera- ture of 350°C. This effect is no longer related to the inhibition of the bipolar parasitics but is mainly due to the increased in- trinsic temperature of the highly doped layer, which makes the p+/n-epi junction isolation slay effective up to higher tempera- tures.

The effect of the different device architectures is investi- gated hy coinparing the behavior of the structure (a) and (c), by assuming the same thickness of the n epi-layer. Figure 7c shows that the operating temperature limit of structure (a) ex- ceeds the temperature limit of structure (c) by about I O O T thanks to the additional n+ layer, which blocks the holes in- jection into the n epi-layer and reduces the parasitic vertical current flow.

In summary, it can he concluded that the most efficient way to extend the operating temperature range of a VdP structure (with floating substrate and no bias) is to modulate the junc- tion doping as it has been demonstrated above in the case of

the highly doped huried layer. In (c), the buried layer mainly acts as a source of majority carriers for the n-layer. enabling it to sustain a sufficient electron concentration gradient and a built-in potential up to higher temperatures. On the contrary, the strategy aimed to reduce the gain of parasitic bipolars has been shown to he less effective. In any case, the maximum op- erating temperature reacheable by this countermeasures does not exceed 350°C.

I I D Irn am 3M *w

i.*G,m?+,iC,

Fig. 1. Sheet resistance YS temperalure: a) dependence on the n-rpi lhicknrss h) drprndrncr on Ihe n-rpi doping c) effect of the huried layer

IV. EXPERIMENTAL RESULTS

A. Juncriori reverse bios

The use of a reverse bias applied both to the resistor and to the huried junction in order to confine the current Row in the resistor area has been proposed in [5] . It is shown below that the working principle of this technique is to limit the leakage current by turning off the bipolar parasitics and by draining the thermally generated majority carriers away from the depletion region. The effectiveness of this approach is demonstrated by comparing the experimental data acquired on six different re- sistor profiles with the corresponding full 3D simulations.

Figures 8a and h show the hole and the electron distribution along a depth cross section (symmetry axis) of a VdP stmc- ture under different temperature and bias conditions. When a reverse hias higher than 0.5V is applied to the sample the col- lection of the thermal generated carriers stms to become ef- fective. The depletion region and the related harrier (circle in Figs. 8a and b) are restored so that the injected current remains confined within the resistor area. B. New e.rrractinn inethod

In the following an extraction technique is proposed which enables to obtain the measured sheet resistance without contri- butions introduced by the additional external bias.

I36

io0 1 mum) lo

* I

Fig. 8. Electrons and holes distribution along the symmetry axis of the VdP stmcture under different conditions. The reverse bins results into a bettcr

current confincrnent within the resistor

It is assumed here that the measurement is performed with the traditional four brobe VdP structure without additional con- tacts for the reverse bias. The polarization scheme is summa- rized in Fig. 9, i.e. a positive constant bias V,,, is applied to the n-epi layer, while the p-substrate and the potential ref- erence contact of the resistor are tied to ground. The current is forced through the constant current source from the node IJ. while the resulting voltage drop 1/34 across the sample is sensed differentially. Under previous assumptions, the current

Fig, 9. Bias conliguration

at the node I , includes two contributions: thc injected current ( I f E d ) and the junction leakage current ( I t ,&, reverse thermal current) collected by the resistor along its length. As the tem- prature increases. Ilk is no longer negligible. If the extraction is performed by considering the nominal value of the current fbrced by the current source ( I f o r c e d ) . i.e. by neglecting the

voltage drop due to It,,. the traditional extraction technique based on the computation of the ratio V 3 4 / I f o r o e d delivers a temperature-dependent overestimate of the sheet resistance of the sample. On the contrary, if the extractinn is carried out by considering the current collected at the node I, ( I c o l l r , : ~ e d ) . i.e. by assuming that I t h flows across the resistor from IJ to I,. the traditional procedure based on the ratio V34/Icol~retp,, leads to a temperature-dependent underestimate of the sheet resistance. Both situations are represented in Fig. 10.

Under the realistic assumption that the reversc thermal cur- rent does not depend on the level of the forced current I f m d , a differential extraction technique can he proposed, which is based on the following equation:

The results obtained with the differential extraction tech- nique are compared with those ofthe standard method in Fig. 10. where the symbols represent the measured data and the solid line is the resistivity a extracted by simulation. In this case, the spurious effect of the leakage current becomes non- negligible starting from 300°C.

1 o * ' m m , . m ' m w m

iompsraluie ('cl

Fig. IO. Extraction of the sample resistivity with different techniques (dots: mpefimental, solid linus: simulation)

The range of validity of the assumption that I th does not depend on the level of I f m d is shown in Fig. 1 I , where ex- periment and simulations are compared in the case of the P2 resistor for I f m d = 10pA and 50pA. The exponential be- haviour of the current'in the 100°C up to 430°C temperature range shows that the main component of I th is a diffusion cur- rent. This is also confirmed hy the measured activation energy of 0.93 eV, which is in good agreement with the theoretical value of I .07 eV (the deviation of the simulation from the mea- sured curve in the low temperature range is due to the limited resolution of the experimental set up).

Figure IO clearly shows that the operating range of VdP structures can k extended by the reverse bias method. pro- vided that thc extraction of the sheet resistance is performed by the proposed differential technique.

137

ow1 owls ow om5 om om I/? (X ‘1

Rg. I 1 Arrhrnws plot of Ith

C. Results

The accuracy of the biased VdP structures in conjunction with the differenlial extraction procedure has been assessed by using different samples with six different doping profiles. A selection of representative results i s reported in Figs. 12a and b, where the measurements and the simulations related to the samples P2 and P3 are comparcd in the floating substrate con- figuration, as well with a substrate reverse bias V,,, = 2V. All results show good agreement of the measurements with simu- lations and indicate that the method can he successfully applied up to 500°C (for highly doped samples).

More caution has to he taken with low-doped samples (N < 1 x l O ” ~ r n - ~ ) as shown in Fig. 12c. As can be argued from Fig. 8a and b, reverse bias applied to the junction increases the width of the depletion region by resulting into a reduction of the resistor cross section. In the case of thin low-doped resis- tors this effect may produce a systematic overestimate of the resistivity up to 20% 01 the real value. Therelore, measure- ments on low-doped samples have to he carried out possibly on thick resistors and at the lowest possible V,,,. This does not represent a limiting condition, since the intrinsic tempera- ture of low-doped resistors is already reached at relatively low temperatures.

On the contrary, this technique highly extends the maxi- mum operating lemperatunt in the case of highly-doped sam- ples. The example reported in Fig. 12d demonstrates that the sheet resistance can he reliably characterized up to 500”C, i.e. exceeding by more than 200°C the limit reacheable by the tra- ditional technique.

V. CONCLUSIONS

It has been shown that the operating temperature range of VdP t a t structures can he extended both by proper design and by the use of reverse bias. The proposed design rules have heen finalized to optimize the geometry of the samples in order to reduce the impact of parasitic bipolar transistors and to im- prove the potential harriers by accurate junction engineering. The use of a reverse bias has been demonstrated to he effective especially for highly-doped resistors with high intrinsic tem- peratures. In this case, thc extraction of the sheet resistance

Fig. I?. Validation of the proposed approach: P? mistor b) P3 resistor c) modulation of the resistor thickness in low doped PI resistor d) extension of

the useful tempemlure range far highly-dopcd N2 resistor

has to he carried out by the proposed differential technique in order to avoid systematic errors due to the additional leakage currents.

A balanced combination of both strategies enables to extend the maximum operating temperature of junction isolated VdP dcvices up to the limit imposed by the intrinsic temperature of the lowest doped layer, that is up to 500°C for highly doped samples.

VI. ACKNOWLEDGEMENTS

This investigation has been carricd out in the framework of the European Research Project DEMAND (EU-IST-2000- 30033).

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