HARDWARE DESIGN AND PETRI NETS
-
Upload
khangminh22 -
Category
Documents
-
view
3 -
download
0
Transcript of HARDWARE DESIGN AND PETRI NETS
Hardware Design and Petri Nets
Edited by
Alex Yakovlev University of Newcastle upon Tyne
Luis Gomes Universidade Nova de Lisboa
and
Luciano Lavagno Universitd di Udine
SPRINGER-SCIENCE+BUSINESS MEDIA, B.V.
A C.I.P. Catalogue record for this book is available from the Library of Congress.
ISBN 978-1-4419-4969-1 ISBN 978-1-4757-3143-9 (eBook) DOI 10.1007/978-1-4757-3143-9
Printed on acid-free paper
All Rights Reserved © 2000 Springer Science+Business Media Dordrecht
Originally published by Kluwer Academic Publishers in 2000 Softcover reprint ofthe hardcover 1st edition 2000
No part of the material protected by this copyright notice may be reproduced or utilized in any form or by any means, electronic or mechanical, including photocopying, recording or by any information storage and retrieval system, without written permission from the copyright owner.
Contents
Preface vii
Part I Hardware Modelling using Petri Nets
1 Comprehensive Causal Specification of Asynchronous Controller
and Arbiter Behaviour Ralf Wollowski and Jochen Beister
2 Complementing Role Models with Petri Nets in Studying Asyn
chronous Data Communications Fei Xia and Ian Clark
3
3
33
Petri Net Representations of Computational and Communication 51 Operators
David H. Schaefer and James H. Sosa
Part II Model Analysis and Verification for Asynchronous Design
4 Properties of Change Diagrams 77 Uwe Schwiegelshohn and Lothar Thiele
5 LTrL-based Model Checking for a Restricted Class of Signal Tran- 93
sition Graphs R. Meyer and P.S. Thiagarajan
6 A Polynomial Algorithm to Compute the Concurrency Relation of
a Regular STG Andrei Kovalyov
v
107
v1 HARDWARE DESIGN AND PETRI NETS
Part III Theory and Practice of Petri Net Based Synthesis
7 Synthesis of Synchronous Digital Systems Specified by Petri Nets 129 Norian Marranghello, Jaroslaw Mirkowski and Krzysztof Bilinski
8 Deriving Signal Transition Graphs from Behavioral Verilog HDL 151 Ivan Blunno and Luciano Lavagno
9 The Design of the Control Circuits for an A§_ynchronous Instruction
Prefetch Unit Using Signal Transition Graphs Suck-Heui Chung and Steve Furber
Part IV Hardware Design Methods and Tools
10
171
Electronic System Design Automation Using High Level Petri Nets 193 Patrik Rokyta, Wolfgang Fengler and Thorsten Hummel
11 An Evolutionary Approach to the Use of Petri Net based Models 205 Ricardo J. Machado, Joiio ·M. Fernandes, Antonio J. Esteves and Henrique D. Santos
12 Modelling and Implementation of Petri Nets Using VHDL Dave Prothero
Part V Architecture Modelling and Performance Analysis
13 Performance Analysis of Asynchronous Circuits and Systems using
Stochastic Timed Petri Nets Aiguo Xie and Peter A. Beerel
14 Performance Analysis of Dataflow Architectures Using Timed
Coloured Petri Nets
223
239
269
B.R. T.M. Witlox, P. van der Wolf, E.H.L. Aarts and W.M.P. van der Aalst
15 Modeling a Memory Subsystem with Petri Nets: a Case Study Matthias Gries
16
291
Performance Modeling of Multithreaded Distributed Memory 311 Architectures
Wlodek M. Zuberek
Preface
With the advent of sub-micron VLSI technology, which will soon enable a billion of transistors to be placed on a single chip, hardware design becomes a big challenge. Future VLSI circuits will often be systems-on-chip, whose subsystems include processors, memory banks and input/output controllers. Problems with distributing the global clock between these subsystems, treated as Intellectual Property (IP) cores, are unavoidable. Systems-on-chip will effectively lose the global notion of physical time and permit actions in different parts of the systems to be executed in parallel or independently of one another. Such hardware systems will inevitably become more asynchronous and concurrent, thus causing a sharp increase in complexity in their dynamic behaviour. To cope with the growing complexity and with the need to meet time-to-market demands, designers will require adequate development techniques and tools to enable the analysis, synthesis and verification of concurrent hardware.
The cornerstone of a viable hardware design technology is a good language for adequate modelling and specification of system behaviour. In the past, when systems were predominantly synchronous and sequential, such a language was provided by the model of a Finite State Machine (FSM). As systems become more asynchronous and concurrent, an FSM is inadequate because it is based on states and transitions, inherently sequential and global concepts. Even if the FSM representation allows modelling of non-sequential effects in hardware such as races, the model still uses the notion of a global state, and any concurrent transitions are modelled as a set of possible interleavings of state transitions. Use of an FSM composition may only offer a partial (though often successful!) solution to the modelling and verifying of concurrent systems because it requires constructing a product FSM, which, apart from combinatorial
VII
vm HARDWARE DESIGN AND PETRI NETS
state explosion, faces the problem of adequate interpretation of concurrency and synchronisation between transitions in different FSMs.
Petri nets can act as FSMs if the modelled system is totally sequential. However, if there is an explicit need to model concurrency without showing it in its interleaving form, even for the purposes of a more compact representation, Petri nets have proved most adequate for doing so.
The area of hardware design has traditionally been a fertile field for research in concurrency and Petri nets. Many new ideas about modelling and analysis of concurrent systems, and Petri nets in particular, originated in theory of (asynchronous) digital circuits. For example, the theory of speed-independent circuits by D.E. Muller and W.C. Bartky laid a foundation to the important concepts of feasible sequences, cumulative states, finite equivalence classes, confluence, semi-modularity and so on. Similarly, the theory and practice of digital circuit design have always recognised Petri nets as a powerful and easy-to-understand modelling tool.
The history of the "marriage" between digital hardware and Petri nets has witnessed many bright moments. One such example is the seminal work on parallel computers, asynchronous structures and Petri nets carried out at MIT in the seventies, which involved J.B. Dennis, F. Furtek, M. Hack, J.R. Jump, D. Misunas, S. Patil, P.S. Thiagarajan and others. Another example is the increase of interest to Petri nets and their interpretations in the nineties, driven by the Design Automation community. Signal Transition Graphs (STGs) and software packages built around this model (SIS, ASSASSIN, Petrify) have made Petri nets a practical tool in the hands of VLSI designers. In the last few years, parts of industrial strength microprocessors and interfaces have been designed using STGs, and this process is on its rise. The ever-growing demand for design automation in the IT sector, to build various types of computer-based systems, creates many opportunities for Petri nets to establish their role of a formal backbone in future tools for constructing systems that are distributed, concurrent and asynchronous. Petri nets have already proved very effective in supporting algorithms for solving key problems in synthesis of hardware control circuits. However, since the front end to any realistic design flow in the future is likely to rely on more pragmatic Hardware Description Languages (HDLs), such as VHDL and Verilog, it is crucial that Petri nets are well interfaced to such languages.
The papers collected in this book cover the scope of applications of Petri nets in hardware design, as it is seen at present, sufficiently well. The material is split into five parts, which cover aspects of behavioural modelling, analysis and verification, synthesis from Petri nets and STGs,
PREFACE IX
design environments based on high level Petri nets and HDLs and finally performance analysis using Petri nets.
The three chapters in Part I (Hardware Modelling using Petri Nets) illustrate how Petri nets can be used to model the behaviour of hardware at different levels of functional abstraction. The first chapter, written by R. Wollowski and J. Beister, extends the current status of circuit modelling at a very fundamental level, with a number of new notions of causality, exhibited by circuits (possibly with analogue components) captured in a true concurrency framework. Then, F. Xia and I. Clark use Petri nets to formalise the modelling and to facilitate the mechanical analysis of a non-trivial asynchronous communication mechanism, previously dealt with in a much less automatable way. D.H. Schaefer and J.A. Sosa present, in the third chapter, a large set of modelling constructs or operators, based on high-level Coloured Petri nets, that covers many types of components found in computer-based systems, starting from elementary gates and leading to massively parallel processors. This also offers a unified and intuitive way of explaining the behaviour of modern computing and communication systems.
Part II (Model Analysis and Verification for Asynchronous Design) discovers new solutions in the area of analysis of the two popular specification models of circuits, STGs and Change Diagrams. Change Diagrams, although relatively restrictive (they don't capture choice), can model systems with the AND and OR forms of causality. In chapter 4, U. Schwiegelshohn and L. Thiele, for the first time, study this model as a class of dynamic min-max graphs. They provide efficient algorithms for analysis of both untimed and timed Change Diagrams, with respect to liveness and boundedness. The fifth chapter, written by R. Meyer and P.S. Thiagarajan, addresses the problem of model checking for a subclass of choice-free STGs based on the linear time temporal logic LTrL. Chapter 6, written by A. Kovalyov, improves on the structural approach to the computation of concurrency relation, one of the key problems in STG analysis and STG-based circuit synthesis. The new polynomial algorithm lifts the previous restriction on the class of Petri nets, Free-Choice, to that of Regularity, thus moving closer to the class of STGs that are synthesable by exponential, state-based, algorithms.
Part III (Theory and Practice of Petri net based Synthesis) looks at various issues involved in synthesis of digital hardware using Petri nets and STGs. Chapter 7, written by N. Marranghello, J. Mirkowski and K. Bilinski, provides an overview of methods used to synthesise synchronous digital systems specified by Petri nets. I. Blunno and L. Lavagno, in chapter 8, describe an automated method for deriving STGs from behavioral Verilog HDL for subsequent implementation into an asynchronous
x HARDWARE DESIGN AND PETRI NETS
control circuit by an automatic synthesis tool (Petrify). This approach shows how Petri nets and asynchronous synthesis tools can be placed into the overall asynchronous design flow that is maximally oriented to a designer who is non-expert in Petri nets or STGs, and has limited experience in asynchronous design. Although the paper shows only the first idea of this approach it is believed to be the most natural way of adapting Petri nets in an industrial CAD environment. Finally, in the last chapter of this part, S.-H.Chung and S.B. Furber, present the design of control circuits for an industrial strength microprocessor Amulet 3; namely, they illustrate how an asynchronous Instruction Prefetch Unit is constructed using STGs and tool Petrify.
Part IV (Hardware Design Methods and Tools) covers aspects of designing systems, that are either hardware or hardware-software controllers, from (high-level) Petri nets specifications maximally using the standard design and simulation environments. Chapter 10, written by P. Rokyta, W. Fengler, and Th. Hummel, describes a concept of the automated design flow, starting from a specification in coloured Petri nets, unfolded to Hardware Petri net description, which is subsequently converted to fully synthesisable (into synchronous logic) VHDL. In chapter 11, R.J. Machado, J. M. Fernandes, A. J. Esteves, and H.D. Santos, present an evolutionary approach to the use of Petri net based models in designing (again, synchronous) systems of increasing complexity from parallel controllers to hardware-software codesign. Finally, D. Protheroe describes in a very systematic way, how self-timed systems, specified by Petri nets at different levels of abstraction, can be expressed in VHDL and simulated. This approach, if combined with that of I. Blunno and L. Lavagno, would provide an idea of a future HDL-based design environment for asynchronous controllers. The front end of this environment, at both specification and feedback sides, is supported by HDL interface, while the back end and appropriate logic synthesis routines are applied to an "object-code" of Petri nets and STGs, suitably hidden from the (possibly inexperienced) designer.
Part V (Architecture Modelling and Performance Analysis) focuses on a generally important application area of Petri nets, the area of performance analysis, with interesting industrial case studies. First, in chapter 13, A. Xie and P. A. Beerel, discuss the performance analysis of asynchronous circuits and systems using Stochastic Timed Petri nets (STPN), where both an overview of the state-of-the-art and original results of the authors in applying STPN to self-timed circuits are presented. They illustrate their method by applying it to Intel's recent asynchronous design experiment, an instruction length decoder for the X86 architecture, called RAPPID. In chapter 14, B.R.T.M. Witlox,
PREFACE x1
P. van der Wolf, E.H.L. Aarts, and W.M.P. van der Aalst, present a systematic approach to model dataflow architectures at a high level of abstraction using Timed Coloured Petri Nets, with the purpose of performance analysis. They apply the method to the Prophid dataflow architecture, recently studied at Philips. Chapter 15, written by M. Gries, describes a method in which a complex Petri net model of a memory subsystem can be constructed and analysed for performance. The paper illustrates how using Timed Coloured Petri Nets and associated modelling environment (CodeSign) eventually helps to improve a particular memory organisation. Finally, W.M. Zuberek presents a method for the performance modelling of multi-threaded processor architectures with distributed memory. Timed Petri nets are used to model a number of such architectures at the instruction and thread levels.
This book is based on the proceedings of two International Workshops on Hardware Design and Petri Nets, held in 1998 in Lisbon and in 1999 in Williamsburg, VA, as part of the 19th and 20th International Conferences on Applications and Theory of Petri nets (ICATPN).
Acknowledgements. We are very much indebted to all the authors contributing to this book, to Jordi Cortadella and Ganesh Gopalakrishnan, the invited speakers of the Workshops, to our colleagues who helped us with reviewing this material at the pre- and post-Workshop stages, namely Albert Koelmans, Maciej Koutny, Ken McMillan, Marta Pietkiewicz-Koutny, and of course to all the participants of both HWPN workshops for their constructive criticism. We also address our special thanks to the Steering Committee of the ICATPN for offering us the opportunity to organise the Workshops, to Gianfranco Ciardo, the ICATPN'99 Organising Committee Chair, and all other colleagues from Universidade Nova de Lis boa and from the College of William and Mary for the local organisation of the workshops. Many thanks to Kluwer Academic Publishers, and in particular to James Finlay for efficient handling of this book.
ALEX Y AKOVLEV
LUIS GOMES
LUCIANO LAVAGNO