ELEC3720 Chapter 8 MIPS Instructions Part 1

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ELEC3720-2009-B6-PSB ACADEMY-LKH-Chapter 08 1

ELEC3720 Programmable Logic DesignELEC3720 Programmable Logic DesignChapter 08 MIPS Instruction SetChapter 08 MIPS Instruction Set


Instructions The words of a machine’s language Vocabulary is the instruction set More primitive than higher level languages, e.g., no

sophisticated control flow Very restrictive, e.g., MIPS Arithmetic Instructions Will be looking at the MIPS instruction set architecture

- similar to other architectures developed since the 1980's- almost 100 million MIPS processors manufactured in 2002- used by NEC, Nintendo, Silicon Graphics, Sony, and many

others Design goals: simplicity (easy to build the hardware and the

compiler ) while maximising performance and minimising cost


Design Goals Design Principle 1: simplicity favors regularity. Why?

Regularity motivates many features of the MIPS instruction set

- keeping all instructions in a single size

- always requiring 3 operands in the arithmetic instructions

- keeping the register fields in same place

Design Principle 3: smaller is faster. Why?

Operands must be register and there are only 32 registers

Large register set may increase the clock cycle time as it will take long electronic signals when they travel farther

32 keeps the no. of bits to 5, increasing no. of register requires more bits to address the register


Design Goals Design Principle 2: make the common case fast. Why?

Design Principle 4: good design demands good compromises. Why?


MIPS Arithmetic• All arithmetic instructions have 3 operands• Operand order is fixed (destination first)

– Simplicity favours regularity• Example:

C code: A = B + CMIPS code: add $s0,$s1,$s2 #$s0=$s1+$s2

#compiler adds contents of#register $s1 and $s2 and put#the result in register $s3

(compiler associates variables with registers)

• Example:C code: A = B - CMIPS code: sub $s0,$s1,$s2 #$s0=$s1-$s2


MIPS Arithmetic• Simplicity complicates some things...

C code: A = B + C + D;E = F - A;

MIPS code: add $t0,$s1,$s2 #$t0=$s1(B)+$s2(C)add $s0,$t0,$s3 #$s0(A)=$t0+$s3(D)sub $s4,$s5,$s0 #$s4(E)=$s5(F)-$s0

• Make the common case fast– MIPS includes only commonly used instructions– Reduced Instruction Set Computer (RISC)– Complex Instruction Set Computer (CISC)


Operands The natural number of operands for an operation like

addition is three…requiring every instruction to have exactly three operands, no more and no less, conforms to the philosophy of keeping the hardware simple

• Operands retrieved from– Registers– Memory– Constants (or immediate)

• Memory is slow• Limited number of fast registers (on-chip)

– MIPS has thirty-two 32-bit registers– What about programs with lots of variables?


Register vs Memory Arithmetic instruction operands must be registers – only 32

32-bit registers are provided Compiler associates variables with registers What if a program contains many variables?

Processor I/O

Control

Datapath

Memory

Input

Output

Computer Components


Memory Organisation A very large, one dimensional array A memory address is an index into the array “Byte Addressing” means that the index points to a byte of

memory affects array indexing

0

1

2

3

4

5

6

...

8 bits of data

8 bits of data

8 bits of data

8 bits of data

8 bits of data

8 bits of data

8 bits of dataaddress


Memory Organisation Bytes are nice, but most data items use larger "words“ For MIPS, a word is 32 bits or 4 bytes

232 bytes with byte addresses from 0 to 232-1

230 words with byte addresses 0, 4, 8, ... 232-4

Words are aligned, i.e., the least 2 significant bits of a word address are 0s,

xx............xx00

048

12...

32 bits of data32 bits of data32 bits of data32 bits of data

Registers hold 32 bits of data


Word-Addressable Memory • For explanation purposes, we begin by describing a word-

addressable memory, where each 32-bit data word has a unique address.


Reading Word-Addressable Memory • Load a word of data from memory address 1 into $s3.

– Assembly code: lw $s3, 1($0)

• Memory address calculation:– add the base address ($0) to the offset (1)– In this case, the memory address is ($0 + 1) = 1

• Any register may be used to store the base address• $s3 holds the value 0xF2F1AC07 after the instruction is

completed


Writing Word-Addressable Memory • Write (store) the word held in $t4 into memory address 7

– Assembly code: sw $t4, 0x7($0)

• The offset can be written in decimal (default) or hexadecimal

• Memory address calculation:– Add the base address ($0) to the offset (0x7) – In this case, the memory address is ($0 + 0x7) = 7

• Any register may be used to store the base address


Byte-Addressable Memory • Each data byte has a unique address• Load and store single bytes: load byte (lb) and store byte

(sb) • Each 32-bit words has 4 bytes, so the word address

increments by 4– Words are aligned; i.e., the least 2 significant bits of a

word address are 0s (xx............xx00)


Reading Byte-Addressable Memory • The address of a memory word must now be multiplied by

4. For example,– the address of memory word 2 is 2 × 4 = 8– the address of memory word 10 is 10 × 4 = 40 (0x28)

• Load a word of data at memory address 4 into $s3– Assembly code: lw $s3, 4($0)

• $s3 holds the value 0xF2F1AC07 after the instruction is completed


Writing Byte-Addressable Memory • The assembly code below stores the value held in $t7 into

memory address 0x2C (44).

MIPS assembly codesw $t7, 44($0)# write $t7 into memory word 11


Big-Endian and Little-Endian Memory • How to number bytes within a word• Word address is the same for big- or little-endian• Little-endian: numbers bytes starting at the little (least

significant) end• Big-endian: numbers bytes starting at the big (most

significant) end

0 1 2 3MSB LSB

4 5 6 78 9 A BC D E F

ByteAddress

3 2 1 007 6 5 44B A 9 88F E D CC

ByteAddress

WordAddress

Big-Endian Little-Endian

MSB LSB


Big-Endian and Little-Endian Memory • From Jonathan Swift’s Gulliver’s Travels where the Little-

Endians broke their eggs on the little end of the egg and the Big-Endians broke their eggs on the big end.

• As indicated by the farcical name, it doesn’t really matter which addressing type is used – except when the two systems need to share data!

0 1 2 3MSB LSB

4 5 6 78 9 A BC D E F

ByteAddress

3 2 1 007 6 5 44B A 9 88F E D CC

ByteAddress

WordAddress


MSB LSB


Big- and Little-Endian Example • Suppose $t0 initially contains 0x23456789. After the

following program is run on a big-endian system, what value does $s0 contain? In a little-endian system?

sw $s0, 0($0)

lb $s0, 1($0)


Big- and Little-Endian Example • Suppose $t0 initially contains 0x23456789. After the

following program is run on a big-endian system, what value does $s0 contain? In a little-endian system?

sw $t0, 0($0)

lb $s0, 1($0)

• Big-endian: 0x00000045• Little-endian: 0x00000067

23 45 67 890 1 2 3

23 45 67 8903 2 1 0

WordAddress


Byte AddressData Value

Byte AddressData Value

MSB LSB MSB LSB


Data Transfer Instructions Load instructions copy data from memory to register Store instructions copy data from register to memory Example (assume $s3 contains base address of array A):

C code: A[12] = h + A[8];MIPS code: lw $t0, 32($s3) # load word, $t0 = A[8]

# $t0=Mem[$s3+32],# base or displacement# addressing mode

add $t0, $s2, $t0sw $t0, 48($s3) # store word

# Mem[$s3+48]=$t0 Store word has destination last Remember arithmetic operands are registers, not memory Can’t write: add 48($s3), $s2, 32($s3)


Data Transfer InstructionsIllustration:

lw $t0, 32($s3)

add $t0, $s2, $t0

sw $t0, 48($s3)A[0]($s3)A[1]4($s3)A[2]8($s3)A[3]12($s3)A[4]16($s3)A[5]20($s3)A[6]24($s3)A[7]28($s3)A[8]32($s3)A[9]36($s3)

A[10]40($s3)A[11]44($s3)A[12]48($s3)

$t0

Content of A[8]1 byte

$t0$s2$t0

$t0


Checkpoint 1: so far we’ve learned:• MIPS

— loading words but addressing bytes— arithmetic on registers only

• Instruction Meaning

add $s1, $s2, $s3 $s1 = $s2 + $s3sub $s1, $s2, $s3 $s1 = $s2 – $s3lw $s1, 100($s2) $s1 = Memory[$s2+100] sw $s1, 100($s2) Memory[$s2+100] = $s1


Machine Language Instructions, like registers and words of data, are also 32 bits

long (simplicity favors regularity)- example: add $t0, $s1, $s2- registers have numbers, $t0=8, $s1=17, $s2=18 Instruction Format contains 6 fields for R type instructions:

op: opcode (basic operation of the instruction)rs: 1st register operand, rt: 2nd register operandrd: register destination operandshamt: shift amount (bit shifting)funct: select variant in op field, known as function code

functshamtrd ($t0)rt ($s2)rs ($s1) op (add)6 bits5 bits5 bits5 bits5 bits6 bits

10000000000010001001010001000000


Machine Language Consider the load-word and store-word instructions,

- What would the regularity principle have us do?- Design Principle 4: good design demands a compromise

The address length and constant size have been compromised to keep all instruction the same length

Introduce a new type of instruction format- I-type for data transfer instructions- other format was R-type for register

Example: lw $t0, 32($s2)


• Assembly provides convenient symbolic representation– much easier than writing down numbers– e.g., destination first

• Machine language is the underlying reality– e.g., destination is no longer first

• Assembly can provide 'pseudoinstructions'– e.g., “move $t0, $t1” exists only in Assembly – would be implemented using “add $t0,$t1,$zero”

• When considering performance you should count real instructions

Assembly Language vs. Machine Language


MIPS Machine Language

Data transfer formataddressrtrsopII-format

Arithmetic instruction format

funct

shamtrdrtrsopRR-format

All MIPS instructions 32 bits

6 bits5 bits5 bits5

bits5

bits6

bitsField size

sw $s1, 100($s2)100171843Isw

lw $s1, 100($s2)100171835Ilw

sub $s1, $s2, $s33401719180Rsub

add $s1, $s2, $s33201719180Radd

CommentsExampleFormatName


Logical Operations• Use to operate on fields of bits within a word or even on

individual bits• MIPS logical instructions

– and, or, nor, xor

• MIPS shift instructions– sll (shift left logical)– srl (shift right logical)– sra (shift right arith.)

msb lsb "0"

msb lsb"0"

msb lsb

Example: sll $t2, $s0, 8 # $t2 = $s0<<8 bits


• Decision making instructions– alter the control flow,– i.e., change the "next" instruction to be executed

• MIPS conditional branch instructions:

bne $t0, $t1, Label # branch if not equalbeq $t0, $t1, Label # branch if equal

• Example: if (i==j) h = i + j;

bne $s0, $s1, Labeladd $s3, $s0, $s1

Label:....

Control


• MIPS jump (unconditional branch) instructions:

j label

• Example:

if (i!=j) beq $s4, $s5, Elseh=i+j; add $s3, $s4, $s5

else j Exith=i-j;Else: sub $s3, $s4, $s5

Exit: ...

• Can we implement loops using these instructions?

Control


Control: For Loop• Example

int sum = 0;

for (I=0; I!=10; I=I+1){sum = sum+1;

}

add $s1,$0,$0 # sum=0addi $s0,$0,0 # i=0addi $t0,$0,10 # $t0=10

for:beq $s0,$t0,done # if i=10,

# branch to doneadd $s1,$s1,$s0 # sum=sum+1addi $s0,$s0,1 # increment ij for

done:

C code MIPS code


Control: While Loop Assume i = $s3, k = $s5 and the base of array save = $s6,

considerC Codewhile (save[i]==k)

i+=1; The implementation using MIPS instructions

MIPS CodeLoop:sll $t1, $s3, 2 # $t1 = 4*i

add $t1, $t1, $s6 # $t1 = address of save[i] lw $t0, 0($t1) # $t0 = save[i]bne $t0, $s5, Exit # go to EXIT if save[i] kaddi $s3, $s3, 1 # i = i + 1j Loop # go to Loop

Exit: …


• We have beq, bne, what about Branch-if-less-than?• There isn’t, but it can be implemented using various

instructions• New instruction (set on less than):

slt $t0, $s1, $s2 # if $s1 < $s2 then # $t0=1 else $t0=0

• Can use this instruction to build "blt $s1, $s2, Label” slt $t0, $s1, $s2bne $t0, $zero, Label

• Can similarly build other conditional branch pseudoinstructions like ble, bgt, bge, beqz, bnez

• A register $at is reserved for use by the assembler to do this

Control Flow


Checkpoint #2: So far… Instruction Meaning

add $s1,$s2,$s3 $s1 = $s2 + $s3 (arithmetic)and $s1,$s2,$s3 $s1 = $s2 & $s3 (logical)sll $s1,$s2,8 $s1 = $s2 << 8 (shift) lw $s1,100($s2) $s1 = Memory[$s2+100] sw $s1,100($s2) Memory[$s2+100] = $s1bne $s4,$s5,L Next instr. is at Label if $s4!=$s5beq $s4,$s5,L Next instr. is at Label if $s4=$s5j Label Next instr. is at Labelslt $t0,$s1,$s2 If $s1<$s2 then $t0=1 else $t0=0

Formats:


Constants Small constants are used quite frequently (50% of operands),

e.g., A = A + 5; B = B + 1;C = C - 18;

Solution? Why not?- put 'typical constants' in memory and load them - create hard-wired registers (like $zero, with constant value

0) for constants like one or zero A better and faster solution would be to specify the constant

inside the instruction itself using “immediate addressing” Design Principle 3 : make the common case fast In MIP making common case fast includes using immediate

addressing for constant operands


Immediate Addressing

• I-Format:

• MIPS Immediate Instructions:addi $s0, $s0, 4 # add immediateandi $s0, $s0, 15 # and immediateori $s0, $s0, 15 # or immediatexori $s0, $s0, 15 # xor immediateslti $t0, $s2, 10 # set on less than imm

• Constants are specified using a 16-bit immediate field• Can represent a negative constant using 2’s complement

addi $s0, $s0, -4• This makes subi unnecessary


How about Larger Constants? It is possible to load a 32-bit constant into a register Must use two instructions, new "load upper immediate"

instructionlui $t0, 1010101010101010

1010101010101010 0000000000000000 Then must get the lower order bits right, i.e.,

ori $t0, $t0, 1010101010101010

1010101010101010 0000000000000000ori 0000000000000000 1010101010101010

1010101010101010 1010101010101010

Filled with zeros


• Instructions:bne $t4,$t5,Label #Next instruction is at Label if $t4!=$t5beq $t4,$t5,Label #Next instruction is at Label if $t4=$t5

• Format:

• 16-bit field is far too small to specify the absolute address• Could specify a register (like lw and sw) and add it to address

– use the program counter (PC)– most branches are local (principle of locality)– PC-relative addressing (position independent code)– 16-bit field specifies the # of instructions/words (not bytes) to

branch relative to the following instruction (PC+4)

Addressing in Branches


• Instruction:j Label # Next instruction is at Label

• Formats:

• 26-bit field is also a word address • The upper 4 bits of the PC are concatenated with the 26-bit

field to give the jump word address• Pseudodirect addressing• Must be careful to avoid placing a program across an

address boundary of 256 MB

Addressing in Jumps


MIPS Addressing Modes


Procedures Use to structure programs, both to make them easier to

understand and to allow code to be reused Registers used for procedure calling

- $a0 - $a3: 4 argument registers to pass parameters- $v0 - $v1: 2 value registers to return values- $ra: 1 return address register to return to point of origin Jump-and-link instruction

- jump to an address and simultaneously save the address of the following instruction (PC+4) in register $ra

jal ProcedureAddress Jump register instruction - to do the return jump

jr $ra


MIPS Register Convention

Name Register number Usage$zero 0 the constant value 0$v0-$v1 2-3 values for results and expression evaluation$a0-$a3 4-7 arguments$t0-$t7 8-15 temporaries$s0-$s7 16-23 saved$t8-$t9 24-25 more temporaries$gp 28 global pointer$sp 29 stack pointer$fp 30 frame pointer$ra 31 return address

Saved registers must be preserved on a procedure call if used, the called procedure (callee) saves and restore them

Temporary registers are not preserved by the callee on a procedure call Reg 1 ($at) is reserved for the assembler Reg 26 ($k0) and Reg 27 ($k1) are reserved for the operating system


Stack Use to save registers used by procedures “grow” from higher addresses to lower address Stack pointer ($sp) points to the “top” of the stack PUSH stack (to save 3 registers)

addi $sp, $sp, -12sw $s0, 8($sp)sw $s1, 4($sp)sw $s2, 0($sp)

POP stack (to restore the 3 register values)lw $s2, 0($sp)lw $s1, 4($sp)lw $s0, 8($sp)addi $sp, $sp, 12


• Simple instructions all 32 bits wide• very structured• only three instruction formats

Overview of MIPS


picoProcessor ISA The picoProcessor (pP) is an 8-bit processor intended for

education purposes It is similar to typical 8-bit microprocessors for small

embedded applications, but has an instruction set architecture more similar to RISC processors Summarised specification:

- 8-bit processor- Instruction memory is 4K instructions- Data memory is 256 bytes- 256 input and output ports- Eight 8-bit general purpose registers- 19-bit instructions


picoProcessor ISA


Project Design and implement an embedded microcontroller using

ALTERA FLEX10K device with the following specifications:- MIPS-type architecture- 16-bit instructions- 3 explicit operands arithmetic and logic instructions- 8-bit data path- 256 16 ROM for instructions- 256 8 RAM for data- 4 8 input ports- 4 8 output ports

ELEC3720 Chapter 8 MIPS Instructions Part 1

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