Efficient Logic Controller DesignGrzegorz Borowik

and Mariusz RawskiWarsaw University of TechnologyInstitute of Telecommunications

Nowowiejska 15/19, 00-665 WarsawEmail: G.Borowik@tele.pw.edu.pl

M.Rawski@tele.pw.edu.pl

Grzegorz Łabiakand Arkadiusz BukowiecUniversity of Zielona Gora

Institute of Computer Engineeringand Electronics

Podgorna 50, 65-246 Zielona GoraEmail: G.Labiak@iie.uz.zgora.pl

A.Bukowiec@iie.uz.zgora.pl

Henry SelvarajUniversity of Nevada, Las Vegas

Department of Electricaland Computer Engineering4505 S. Maryland Parkway

Las Vegas, Nevada 89154-4026AEmail: selvaraj@unlv.nevada.edu

Abstract—Logic controller is a digital device used for automa-tion of electromechanical processes, such as control of machineryon factory assembly line or lighting fixtures. This paper presentsthe method for designing a logic controller. We implement it usingreprogrammable structure equipped with Embedded MemoryBlocks, e.g. CPLD or FPGA. We find that specification ofthe controller with appropriate statechart diagram and furthersynthesis as equivalent Finite State Machine yields encouragingresults: the number of programmable resources has been reducedapproximately by 85%. Result of the research is illustrated withsynthesis of practical controllers, where hardware resource con-sumption is presented. It shows the usefulness of the approach.1

Index Terms—logic controller, statechart diagram, finite statemachine, decomposition, embedded memory block

I. INTRODUCTION

Logic controller is an electronic digital device implementedas digital circuit. It is used for automation of electrome-chanical processes, such as control of machinery on factoryassembly line, lighting fixtures, traffic control system, or evenautomation of system whose role is to maintain an ongoinginteraction with their environment, i.e. controlling mechanicaldevices such as a train, a plane, or ongoing processes such asa biochemical reactor.

Logic controllers can find their application in different areasof biotechnology either. In [19] a technology of smart handprosthesis control based on myoelectric signals is presented.The key elements of this design are arithmetic and controlunits. Bioreactor controller is the focus of the paper [11].This article provides an overview of current and emergingbioreactor control strategies based on unstructured dynamicmodels of cell growth and product formation. Nevertheless,process control plays a limited role in the biotechnologyindustry as compared to the petroleum and chemical industries.This demand for process modeling and control is increasing,however, due to the expiration of pharmaceutical patentsand the continuing development of global competition inbiochemical manufacturing. The lack of online sensors thatallow real-time monitoring of the process state has been anobstruction to biochemical process control. Recent advances in

1This work was partly supported by the Ministry of Science and HigherEducation of Poland – research grant no. N516 418538 for years 2010–2012.

Synthesis

Behaviour description

Statechart

(mathematical model)

ROM-based

decomposition

Architectural

decomposition

FSM

(KISS format)

Fig. 1. General idea of FSM-based logic controller design.

biochemical measurement technology, however, have enabledthe development of advanced process control systems [11].

In this paper, we propose the method for designing a logiccontroller in reprogrammable structure. Such a structure offersability to update the functionality, partial reconfiguration andthe low non-recurring engineering costs relative to an ASICdesign.

The method starts with formal specification of the logiccontroller behavior. To specify a complex nature of a controllerwe have chosen a statechart diagram [10]. An importantadvantage of this specification is the possibility of detecting allreachable deadlocks [13], since any failure in a safety-criticalsystem may cause injury or death to human beings.

Having graphically specified behavior, it is subsequentlyconverted into mathematical model [15]. The mathematicalmodel of statechart can be transformed formally into equiv-alent finite state machine (FSM) [14]. Finally, such a logiccontroller in FSM form can be implemented in various archi-tectures [1], [3], [6] (Fig. 1). Summarizing, formal descriptionis transformed into Boolean equations in a suitable form forthe given technology.

II. STATECHART DIAGRAM SPECIFIES CHEMICALREACTOR

A statechart diagram is a state-based graphical scheme.It is enhanced with concurrency, hierarchy and broadcastingmechanism. The statechart diagram usually describes a com-plex system. However, it requires that the system described iscomposed of a finite number of states [10].

978-1-4244-6952-9/10/$26.00 ©2010 IEEE

y3 y4

y5

y2y1

x1x2

x0

A

R

SV1 SV2

x9

x3x4

x5

x6y7

y9 y8

x7 x8

y6

SV3

WC

W

MV1 MV2

Fig. 2. Schematic diagram of chemical reactor.

The statechart diagram can certainly specify reactive systembehavior. As an example of practical application, the schematicdiagram of a chemical reactor and appropriate statechartdiagram of its logic controller are presented in Fig. 2 and 3,respectively.

The working of the reactor is as follows. Initially, the react-ing substances are kept in containers SV1 and SV2 (Fig. 2), andthe emptied wagon waits in its initial position on the far rightposition (Fig. 3, state WaitingForStart). Then, the operatorstarts the proces with the signal x0. The pump y1 and thepump y2 make that liquid substrates from containers SV1, SV2are being measured out in scales MV1 and MV2, respectively(state Preparations). During this, the wagon is coming backto its far left position. After the substrates are measuredout, the main reaction starts (state Reaction). Next, scalesfill main container R with agents (state AgentDispensing) andagitator A starts rotating (state StirringControl). After fillingup the main container, the product of the reactor is poured tothe wagon (state EmptyingReactor). Then, the wagon goes toempty (states WagonRight and EmptyingWagon).

Rounded rectangles in the statechart diagram, called states,correspond to activities in the controlled object (in this casechemical reactor). In general, states can be in sequential rela-tionship (OR state), or in concurrent relationship (AND states).Then, these states make sequential or parallel automaton.States can be simple or compound. The latter state can benested with other compound or simple. In the diagram (Fig.3), the AND states are separated with a dashed line. Statesare connected with transitions with predicates imposed on it.Predicates must be met to transform activity between statesconnected with an arc.

III. LOGIC INTERPRETATION AND TRANSFORMATION

The issue of hardware synthesis of statecharts is not solvedultimately. There are many implementation schemes dependedon target technology. First, published in [8], consists transfor-mation of the statechart into the set of hierarchically linkedFSMs traditionally implemented. In [9], a special encoding ofthe statechart configurations targeted at PLA structures is pre-sented. The drawback of this method is that diagram expresses

a)t1: i / {t1}

ACTION

entry / entr

do / d

exit / ext

START STOPt2: t1 / {t2}

b)

c)i

STARTACTION

entr, d, t1

STOP,

ext, t2STOP

Fig. 4. Simple diagram (a), its waveform (b) and equivalent FSM (c).

transitions between simple states only. In [17], Drusinskyenhanced the coding scheme by introducing a prefix-encoding.However, the common drawbacks of the presented methodsis the lack of support for history attributes and broadcastmechanism. Other implementation methods using HDL andbased on ASIP are presented in [12] and [4], respectively.

To synthesis statechart-base logic controller it is necessaryto precisely define its behavior in terms of logic values. InFig. 4 a simply diagram and its waveform illustrate the maindynamic features. Logic value 1 means activity of a state orpresence of an event, and value 0 means their absence. Whentransition t1 is fired (T = 350) event t1 is broadcast andbecomes available to the system at next instant of discretetime (T = 450). The activity moves from state START tostate ACTION, where entry action (keyword entry) and do-activity (ongoing activity, keyword do) are performed (eventsentr and d are broadcast). Now, transition t2 becomes enabled.Its source state is active and predicate imposed on it (event t1)is met. So, at the instant of time T = 450, the system transformsactivity to the state STOP, performs exit action (keyword exit,event ext) and triggers event t2, which do not affect any othertransition. The step is finished.

Summarizing, dynamic characteristics of hardware imple-mentation are as follows:

• system is synchronous,• system reacts to the set of available events through

transition executions,• generated events are accessible to the system during next

tick of the clock.Noticeably, statechart-based controller can be perceived as

a finite state machine of a Moore type. Transformation ofstatechart diagram into FSM model involves building equiv-alent Moore-type automaton using statechart elements which

FillingMV1

do / y1

t2: x1

Preparations

FillingMV2

do / y2

t3: x3

WagonLeft

do / y9

EmptyingMV1

do / y3

t7: !x2

EmptyingScales

EptyingMV2

do / y4

t8: !x4

EmptyingReactor

do / y5

t10: z1

Stirring

do / y7

Waiting

t5: x5*x6 t6: !x5*x6

Reactiont4

t11

t12: x8

t13: !x9

WagonRight

do / y8

EmptyingWagon

do / y6

WagonWaiting

do / z1

t9: x7

Process

WagonReturn

StirringControl

t15: !x6

WaitingForStart

t1: x0

Substrates

AgentsDispensing

t14: !x6

Fig. 3. Statechart diagram of chemical reactor.

for external observer behaves just the way statechart does;members of the sets are explicitly enumerated and functionsare given symbolically in tabular form, i.e. KISS formattransition table [20].

Classic Moore automatom is defined as a quintuple〈X,S, Y, δ, λ〉, where X is a set of input signals, S is a set ofstates, Y is a set of output signals, δ is a transition functionand λ is an output function dependent only on states. The setof equivalent FSM input signals X is the set of statechart inputevents, the set of FSM output signals Y is the set of statechartevents visible to the environment. The set S of equivalent FSMstates is a set of statechart global states which are constructedfrom local activities: states, actions (entry, do, exit) and eventsbroadcast when transition is fired (e.g. t1 and t2 in diagramfrom Fig. 4). Transition function δ is a function which mapscurrent global state into next global state depending on the setof currently accessible events, hence transition function δ is avector of Boolean functions. Each component of the vector isbound up with either a state or action or transition event [15].The exact algorithm of generating an equivalent FSM in KISSformat is presented in [14].

IV. ROM-BASED SYNTHESIS

One of the main goals of the synthesis is not only technolog-ical implementation of logic controller but also optimization of

hardware resources consumption. It is particularly importantwhen the design is intended for novel programmable structurecontaining LUT-based cells and embedded memory blocks.The other factor of vital importance is Boolean minimizationstrategy. Authors’ proposition is to apply the idea of functionaldecomposition, i.e. a structure with address modifier (Fig.5b), which is best suited for the FSMs in KISS format fromprevious section [3], [18].

A limited size of embedded memory blocks available inFPGAs is the main reason behind the application of thisstructure. The implementation of an FSM shown in Fig. 5bcan be seen as a serial decomposition of the memory blockincluded in the structure of Fig. 5a into two blocks: an addressmodifier and a memory block of smaller capacity than requiredfor the realization of the structure in Fig. 5a. As a result,sequential circuits requiring large-capacity ROM memories(and thus not implementable in the architecture of Fig. 5a)can be implemented using a memory block with a smallernumber of inputs and an additional combinational logic block– the address modifier. Then, the size of the required memory[3] is equal

M = 2w · (r + p). (1)

The address modifier can be synthesized with advancedalgorithms of functional decomposition, applied until recently

a)

ad resd s

m

r

p

REGISTER

ROM

inputs

outputs

b)m

r

p

u

v

w - u

w w < m + p

REGISTER

ADDRESSMODIFIER

ROM

inputs

outputs

Fig. 5. FSM implementation: a) using ROM memory, b) with the additionof an address modifier.

exclusively to synthesis of combinational circuits.For example, Altera FLEX family devices have 2048-bit

EAB memory blocks. In [18] it is demonstrated that theROM-based implementation of an example sequential circuit– the tbk benchmark – requires 16,384 bits of memory; thisconsiderably exceeds the resources available in the FLEX10K device. An alternative implementation of this circuit withLUTs requires 895 logic cells (a result from the Altera QuartusII ver. 8.1 system); this also exceeds the resources availablein the FLEX 10K device, as it has only 576 cells. Thus, thetbk implementation with this device must rely on the a newFSM architecture. Clearly, a considerably larger number andsize of embedded memory blocks in the newer programmableStratix and Cyclone devices do not eliminate this problem,as there will always be FSMs whose implementation wouldrequire more memory than is available in the state-of-the-artprogrammable devices.

Assuming an FSM implementation with an FPGA device,the advantage of the proposed architecture lies in that theaddress modifier can be mapped into a network of LUTcells or into a PAL matrix, while the memory block can bemapped into the built-in EAB matrices. The application of thisconcept to the synthesis of the earlier discussed benchmark tbkresults in a design composed of 333 logic cells and a 4096-bit embedded memory block, which fits entirely within thelimited resources of the FLEX structure.

V. SYNTHESIS BASED ON ARCHITECTURALDECOMPOSITION

Another method of hardware reduction of an FSM circuit isthe application of architectural decomposition [1]. Generally,in this case, the FSM circuit is represented as a double- ormulti-level structure after architectural decomposition. The

P

RG

Y

Q

Τ

X

Y

CCΦ

Ψ

Fig. 6. The structural diagram of PAY0 Mealy FSM.

first-level circuit is a combinational circuit that implementsBoolean functions of the decomposed FSM. In comparisonwith the single-level circuit the gain on this circuit is that itimplements less Boolean functions and typically requires lesshardware resources (LUTs). The second-level circuit typicallyworks as a decoder and functions describing its behaviorhave a regular structure. It means that it can be implementedin new FPGA devices with the use of embedded memoryblocks. Overall, such a circuit requires less logic elements butadditional memory resources, although memories in FPGAsare very often not used for any other purpose.

Special methods of encoding [2] and modification of a logiccircuit structure are applied. Proposed methods are based onmultiple encoding [5] of internal states and microinstructions,where the current state is used as partitioning set, of a finitestate machine. In this case the code of a microinstructionK(Yt) is represented by concatenation of the multiple codeof the microinstruction Km(Yt) and the code of the currentstate K(am):

K(Yt) = Km(Yt) ∗K(am), (2)

and the code of the internal state K(as) is represented byconcatenation of the multiple code of the internal state Km(as)and the code of the current state K(am):

K(as) = Km(as) ∗K(am). (3)

A digital circuit of a FSM with such encodings can beimplemented as a double-level structure, called PAY0 (Fig. 6).In this structure, the combinational circuit P implementsBoolean functions. The circuit Y implements a decoder ofmicroinstruction system and circuit CC decodes internal statesand generates excitation function; RG is a register file.

The starting point for architectural decomposition is theKISS file obtained from transformation of the statechart.

Part of KISS description of the chemical reactor from Fig. 2:

.i 10

.o 9

.p 263

.s 33

.r sdfg(...)---1---0-- s7 s6 000001000-------0-1 s8 s6 000001000---1---0-1 s9 s6 000001000-------1-- s6 s10 000000000---1---1-- s7 s10 000000000-------1-1 s8 s10 000000000---------1 s11 s10 000000000(...)

Architectural decomposition consists of the following steps.The multiple encoding of microinstructions and internal

states is based on binary encoding of microinstructions andinternal states in each subset.

In the case of chemical reactor example, there are 33states. It means that there are 33 subsets of microinstructionsand 33 subsets of internal states. There are maximum 16microinstructions in one subset. It means that for encodingonly 4 bits are required. E.g. for the subset based on the states8, the following encoding is obtained:Ks8(000001000) = 0000,Ks8(000000000) = 0001,Ks8(000001100) = 0010,Ks8(000000100) = 0011.

Similar situation is obtained for internal states.The formation of the transformed table is the base for

forming system of Boolean functions. It is created from theoriginal table (described in the KISS file) by replacing thestate, the microinstruction and the internal state with theircodes.

Part of KISS transformed table:

.i 10

.o 9

.p 263

.s 33

.r sdfg(...)---1---0-- 000110 0000 0000-------0-1 000111 0001 0000---1---0-1 001000 0000 0000-------1-- 000101 0001 0001---1---1-- 001001 0001 0001-------1-1 000111 0001 0001---------1 001010 0000 0001(...)

The formation of the system of Boolean functions isthe base for obtaining Boolean functions. These systems areobtained from a transformed table in a classical way [1]. E.g.ψ1 = x1x2x3x4x9Q1Q2Q3Q4Q5Q6 + x1x2x3x4x9Q1Q2Q3Q4Q5Q6

+ x1x2x3x4x9Q1Q2Q3Q4Q5Q6 + x1x2x3x4x9Q1Q2Q3Q4Q5Q6

+ x1x2x3x4x9Q1Q2Q3Q4Q5Q6 + x1x2x3x4x9Q1Q2Q3Q4Q5Q6

+. . .

The formation of the decoder table . This step forms thetable that describes the behavior of circuit Y. This table hasfour columns:

• binary code of the current state;• binary code of the microinstruction (from adequate sub-

set);• binary representation of the microinstruction (from ade-

quate subset);• number of the line.

Table I shows part of such table for our example.The formation of the internal state code converter table .

This step forms the table that describe behavior of the circuitCC. This table has four columns:

• binary code of the current state;• binary code of the internal state (from adequate subset);

TABLE ITHE PART OF THE DECODER TABLE

K(am) Km(Yt) Yt h

000000 0000 000000000 1000001 0000 010000000 2000001 0001 000000000 3000010 0000 010000000 4000010 0001 000100000 5

TABLE IITHE PART OF THE CODE CONVERTER TABLE

K(am) Km(as) D h

000000 0000 000011 1000001 0000 000001 2000001 0001 000011 3000010 0000 000001 4000010 0001 000010 5

• binary representation of excitation functions that switchesthe memory of the FSM;

• number of the line.Table II shows part of such table for the presented example.

The implementation of the logic circuit of the FSM . Thecombinational circuit P and the register are implemented byCLBs – LUTs and D-type flip-flops. The decoder Y is imple-mented using embedded memory blocks with 2(R+N2) wordsof N bits and the content of the memory is described by thedecoder table where the concatenation of the binary code of thecurrent state and the binary code of a microinstruction (2) isan address and the binary representation of a microinstructionis the value of word. The internal state converter CC is alsoimplemented in an embedded memory block with 2(R+R1)

words of R bits and the content of the memory is described bythe internal state code converter table where the concatenationof the binary code of the current state and the binary code ofthe internal state (3) is an address and the binary representationof excitation functions is a value of the word. Any (don’t care)value can be assigned for addresses missing in both tablesbecause such concatenations of codes for both memories arenever used.

This is only one possible architecture that could be obtainedafter architectural decomposition with the application of multi-ple encoding. The architecture depends on which parameter(s)is(are) encoded and which parameter is used as partitionset [7]. The presented architecture gives very good synthesisresults [6] but the gain is strongly dependent on the character-istics of the control algorithm. It means that architecture andmethod of encoding should be chosen individually for eachalgorithm.

VI. SUMMARY

FSM-based logic control synthesis is one of many ap-proaches in logic controller design. The idea presented inthe paper is targeted at complex concurrent behavior speci-fied with statechart, which is finally implemented in modernprogrammable device equipped with memory blocks and con-figurable logics. Both synthesis strategies (ROM-based scheme

TABLE IIIFSM SYNTHESIS RESULTS BEFORE AND AFTER INTRODUCTION OF ADDRESS MODIFIER

before after gain dec.name #in #out #q #cube #bit #bit % ratio

Garage 6 3 4 49 7168 1664 77 4.3TVRemoteControl 8 5 4 55 36864 6912 81 5.3

SimpleReactor 10 15 8 986 6029312 294912 95 20.4ReactorWithWagon (Fig. 2) 10 9 6 263 983040 26112 97 37.6

gain =#bitbefore−#bitafter

#bitbefore· 100% decreasing ratio =

#bitbefore

#bitafter

TABLE IVFSM SYNTHESIS RESULTS WITH STANDARD METHOD AND AS PAY0 MEALY FSM

Standard method PAY0 LUT gain dec.name #LUT #FF #LUT #FF #BRAM % ratio

Garage 82 14 10 4 2 88 8.2TVRemoteControl 102 12 28 4 2 73 3.6

SimpleReactor 1965 163 472 13 23 77 4.2ReactorWithWagon 423 33 46 6 5 89 9.2

gain =#LUTstd method−#LUTPAY0

#LUTstd method· 100% decreasing ratio =

#LUTstd method#LUTPAY0

with address modifier and architectural decomposition) con-sume hardware resources to different extent.

ROM-based method uses only memory blocks. Table IIIpresents the gain in memory bits obtained after functionaldecomposition scheme application in the architecture withaddress modifier and memory (Fig. 5b) with comparison tothe implementation without address modifier. Decreasing ratiois of the order of tens and the method is especially efficientfor more complex behavior.

Architectural decomposition uses both, memory and con-figurable logics. According to Fig. 6 blocks CC and Y aremapped into memory and blocks P and RG are implementedin LUTs. Table IV presents the gain in LUTs obtained afterapplication of architectural decomposition in comparison tostandard FSM synthesis method [21]. Method [21] is wellknown VHDL template which uses the instruction case inprocess and is fully mapped into LUTs blocks. The resultswere obtained from Xilinx tool with standard settings.

The idea of functional decomposition which is the base foraddress modifier concept can be applied to any function [16].Its application to functions implemented in blocks P, Y andCC can bring further reductions in hardware resources, notonly memory bits, but also in configurable logic.

It seems that combining architectural synthesis with func-tional ROM-based decomposition is very promising for logiccontroller design, especially for modern programmable devicesequipped with memory blocks.

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