IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 59, NO. 10, OCTOBER 2012 3797

Design of a Discrete-Time Linear Control Strategyfor a Multicell UPQC

Javier A. Muñoz, Student Member, IEEE, José R. Espinoza, Member, IEEE, Carlos R. Baier, Member, IEEE,Luis A. Morán, Fellow, IEEE, Eduardo E. Espinosa, Pedro E. Melín, Student Member, IEEE, and

Daniel G. Sbárbaro, Senior Member, IEEE

Abstract—A discrete-time linear control strategy for a multi-level three-phase unified power quality conditioner (UPQC) basedon single-phase power cells is presented. The multi-variable, non-linear, and coupled features of these topologies make the controlstrategy design a difficult task. Controlling this kind of sys-tem with single-variable linear controllers—as proposed in thiswork—presents significant advantages compared with other ap-proaches as simplicity in the design steps due to the large amountof tools developed for this kind of schemes. Particularly, a classicdesign method based on the root locus approach is used to choosethe controllers parameters in order to achieve a given dynamicalbehavior. Compensation of reactive power and fundamental fre-quency disturbances is presented in this paper as part of a generalcontrol strategy for multilevel active power filters. The proposedcontrol strategy is implemented on the TMS320C6713 DSP-basedsystem for a low-power laboratory prototype, and thus the con-trollers design is carried out on the discrete-time and -frequencydomain. Also, due to the inherent asymmetries among the powercells in a modular topology, a dedicated local control strategy isproposed to ensure a symmetrical distribution of the power amongthe power cells. This feature allows the semiconductor devicesof each module to operate under the same voltage and currentratings. Simulated and experimental results showing stationaryand transient conditions demonstrate the feasibility of the controlscheme.

Index Terms—Linear control, multilevel power converters,power quality (PQ), unified power quality conditioner (UPQC).

I. INTRODUCTION

POWER quality problem has become a significant issue inrecent years due to the high number of power electronic

devices that behave like nonlinear loads and generate severalperturbations in the electric grid [1]–[4]. One of the interestingproposals to mitigate the power quality problems [5]–[8] is theunified power quality conditioner (UPQC) topology [9]–[14]that integrates the capabilities of the series and shunt filter,thanks to the back-to-back connection of the power converters.

Manuscript received December 10, 2010; revised April 27, 2011; acceptedJune 2, 2011. Date of publication June 23, 2011; date of current versionApril 27, 2012. This work was supported by the Chilean Government underProject FONDECYT 108-0247 and 111-0794.

J. A. Muñoz and C. R. Baier are with the Department of Industrial Tech-nologies, University of Talca, Talca 747-C, Chile (e-mail: jamunoz@utalca.cl;cbaier@utalca.cl).

J. R. Espinoza, L. A. Morán, E. E. Espinosa, P. E. Melín and D. G. Sbárbaroare with the Department of Electrical Engineering, University of Concepción,Concepción 160-C, Chile (e-mail: jose.espinoza@udec.cl; luis.moran@udec.cl; eespinosa@udec.cl; pemelin@udec.cl; dsbarbar@udec.cl).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TIE.2011.2160511

Thus, this equipment can compensate sags and swells in thepoint of common coupling (PCC), the overall power factor, andthe supply current harmonic distortion.

As a result of technological restrictions on the power semi-conductors ratings, the use of multilevel configurations hasincreased in order to reach higher power levels and to complywith the power quality standards. Up to now, several topologieshave been proposed to overcome the semiconductors ratinglimitation, like the neutral point-clamped (NPC) converters orstructures based on power cells [15]–[22]. These approachesallow the distribution of the load power among each componentof the topology; however, due to the natural asymmetries ofthe elements, the control scheme must be in charge of thesymmetric power distribution among them.

Elimination of both harmonics and reactive power can bedone isolating each task in separated power modules utilizingdifferent topological characteristics and control principles. Thisis a choice in order to analyze and develop modular topologiesto solve power quality challenges. Thus, the scope of this workis to compensate just fundamental frequency disturbances aspart of a global strategy. Harmonic compensation using thiskind of approach can be found in [23].

A modular UPQC multilevel configuration [24] is studied inthis work. The topology is built up upon single-phase powercells and presents interesting challenges at the control level,due to the nonlinear, multi-variable, and coupled nature ofthe resulting system. In this paper, the results of a low-powerlaboratory prototype are shown to probe the feasibility of theproposed control scheme previously published in [25]. Thiscontrol scheme includes single-variable linear controllers, dueto the simplicity and available design tools for this approach.The design is made up using classic control methods, all ofthem in the discrete-time and -frequency domain, and severaltests in the laboratory prototype illustrate the overall dynamicand static performance of the system.

II. MULTICELL UPQC

The UPQC classical topology [9] can be redefined so as toinclude a multiple power cell arranged in order to reach higherpower levels, while overcoming the limits of the semiconduc-tors rating. The electric variable that limits the operation of theseries compensator in the UPQC is the total current according tothe transformer turns ratio and for the shunt compensator is thetotal voltage, because it has to deal with the total load voltage[24]. The proposed configuration overcomes these limitations

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3798 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 59, NO. 10, OCTOBER 2012

Fig. 1. Proposed UPQC topology based on power cells.

by interconnecting multiple power cells as shown in Fig. 1,where we can see nc cells per phase and thus 3nc cells forthe total system. This connection provides a way for the PCCcurrent and load voltage to be shared among all the modulesof the configuration. This justifies the parallel connection at theseries side of the cells and the series connection at the shuntside.

As shown in Fig. 1, the series side compensator is con-nected through a series transformer, in order to compensatethe PCC voltage disturbances, because the load voltage vabc

L

is the result of the addition of the PCC voltage vabcpcc and

the injected series voltage vabcs . On the other hand, the shunt

side of the compensator is connected at the same load volt-age, to sink or inject current harmonics, and compensatethe reactive power, because the PCC current iabc

pcc is com-posed of the load current iabc

L and the shunt current iabcp of

the UPQC.Fig. 2 shows the basic power cell that is based on single-

phase converters in both the series and shunt sides of the con-figuration. The superscript n is for the phase, with n = {a, b, c}and i is for the power cell number, with i = 1, 2, . . . , nc. Eachcell is composed of a series converter, shunt converter, anda DC link. The DC capacitor links both the series and shuntconverters, provides a path for the power flow between thecompensators, and acts as a voltage source to ensure the properoperation of the topology.

III. SYSTEM MODELING

As described in the technical literature [9]–[14], the compen-sation tasks are clearly defined for each compensation stage:the series compensator controls the load voltage and the shuntcompensator regulates the overall power factor and the DC

Fig. 2. Simplified power cell circuit.

Fig. 3. Series compensator equivalent circuit.

link capacitor voltage. The model at fundamental frequency ofeach stage is obtained in order to propose a suitable controlscheme.

A. Series Compensator Model

To obtain the series compensator model, a constant DCvoltage is assumed for each power cell. Taking into account thatthe nc power cells per each phase are connected in a parallelway at the series side, the equivalent circuit is shown in Fig. 3.

Inspecting Fig. 3, the equations that model the series stageare

msVdc =Ls

nc

disdt

+Rs

ncis + vc

ncCsdvc

dt= is − nsipcc (1)

where ms is the modulating signal of the converter.

MUÑOZ et al.: DESIGN OF A DISCRETE-TIME LINEAR CONTROL STRATEGY FOR A MULTICELL UPQC 3799

Applying the single-phase time-variant dq transformationproposed in [12], the model becomes:

ids = − Rs

Lsids − ωiqs −

nc

Lsvd

c +nc

Lsmd

sVdc

iqs =ωids − Rs

Lsiqs −

nc

Lsvq

c +nc

Lsmq

sVdc

vdc = − ωvq

c +ids − nsi

dpcc

ncCs

vqc =ωvd

c +iqs − nsi

qpcc

ncCs. (2)

As a state-space model, the series compensator stage can beexpressed as:

xs(t) =Asxs(t) + Bsus(t) + Esps(t)

ys(t) =Csxs(t) + Dsus(t) + Fsps(t) (3)

where:

As =

⎡⎢⎢⎣−Rs

Ls−ω − nc

Ls0

ω −Rs

Ls0 − nc

Ls1

ncCs0 0 −ω

0 1ncCs

ω 0

⎤⎥⎥⎦

Bs =

⎡⎢⎢⎣

ncVdc

Ls0

0 ncVdc

Ls

0 00 0

⎤⎥⎥⎦Es =

⎡⎢⎢⎣

0 00 0

−ns

ncCs0

0 −ns

ncCs

⎤⎥⎥⎦

Cs =[

0 0 ns 00 0 0 ns

]Ds =

[0 00 0

]Fs =

[0 00 0

]. (4)

Thus, the state-space variables of the series subsystem are:

xs = [x1s x2s x3s x4s]T =[ids iqs vd

c vqc

]T. (5)

The subsystem inputs are the modulating signals:

us = [u1s u2s]T =[md

s mqs

]T. (6)

The subsystem disturbances are:

ps = [p1s p2s]T =[idpcc iqpcc

]T. (7)

The control objective of this stage is to maintain the loadvoltage in the desired value, so the system outputs must be thedirect and quadrature voltages in the primary winding of theseries transformer. Thus,

ys = [y1s y2s]T =[nsv

dc nsv

qc

]T. (8)

As the control strategy is intended to be implemented on adigital way, it is desirable to obtain an equivalent discrete-timemodel. There is a standard procedure described in literature [26]to carry out the discretization of linear systems. This method isbased on the transition matrix Φs(t), calculated as the inverseLaplace transform:

Φs(t) = L−1{(sI − As)−1

}. (9)

Using this definition—for a constant sampling time Tm—theequivalent discrete system is:

xs(k + 1) =Asdxs(k) + Bsdus(k) + Esdps(k)

ys(k) =Csdxs(k) + Dsdus(k) + Fsdps(k) (10)

where:

Asd =Φs(Tm) Bsd =

Tm∫0

Φs(Tm − σ)Bsdσ Csd = Cs

Esd =

Tm∫0

Φs(Tm − σ)Esdσ Dsd = Ds Fsd = Fs. (11)

In order to design proper control parameters, it is convenientto find the system transfer matrix Hsd(z), given by,

Hsd(z) =Csd(zI − Asd)−1Bsd + Dsd

=[

hsd11(z) hsd12(z)hsd21(z) hsd22(z)

](12)

as illustrated later.

B. Shunt Compensator Model

As explained in [24], the shunt compensator model is

d

dtip = − Rp

Lpip − npGacmpvdc

Lp+

n2p

ncLpvL

d

dtvdc =

Gac

Cdc

[mpipnp

− nsms(iL + ip)nc

](13)

and thus the equivalent synchronous frame model becomes

idp = − Rp

Lpidp+ωiqp−

npGacmdpvdc

Lp+

n2p

ncLpvd

L

iqp = − ωidp−Rp

Lpiqp−

npGacmqpvdc

Lp+

n2p

ncLpvq

L

vdc =Gac

2Cdc

{md

pidp+mq

piqp

np

−ns

[md

s

(idL+idp

)+mq

s

(iqL+iqp

)]nc

}. (14)

From the control point of view, for this compensator, theoutputs are the power factor at the PCC and the DC link voltage.This can be written as

yp = [y1p y2p]T =

[vdc tan−1

(iqL + iqpidL + idp

)]T

. (15)

As it can be seen in (14) and (15), the shunt compensatormodel is nonlinear. Thus, for a proper linear control scheme

3800 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 59, NO. 10, OCTOBER 2012

design, it is necessary to obtain a linearized model of thesystem. This model is given in

Δxp(t) =ApΔxp(t) + BpΔup(t) + EpΔpp(t)

Δyp(t) =CpΔxp(t) + DpΔup(t) + FpΔpp(t) (16)

where the matrices are as shown in (17) at the bottom ofthe page.

In the same way as the series stage, a discrete-time linearmodel is obtained. Thus, the model becomes:

Δxp(k + 1) =ApdΔxp(k) + BpdΔup(k) + EpdΔpp(k)

Δyp(k) =CpdΔxp(k) + DpdΔup(k)

+ FpdΔpp(k) (18)

where:

Apd =Φp(Tm) Bpd =

Tm∫0

Φp(Tm − σ)Bpdσ Cpd = Cp

Epd =

Tm∫0

Φp(Tm − σ)Epdσ Dpd = Dp Fpd = Fp. (19)

In order to design the controllers parameters, the transfermatrix of the shunt stage is also obtained as:

Hpd(z) =Cpd(zI − Apd)−1Bpd + Dpd

=[

hpd11(z) hpd12(z)hpd21(z) hpd22(z)

]. (20)

IV. OPERATING POINT

As shown in the previous section, when a nonlinear system islinearized and controlled with a linear scheme, the value of allthe state variables, inputs, and outputs in the desired operatingpoint are needed to validate the model and then to synthesizethe controllers.

To obtain these operating point values, the original nonlinearsystem equations must be solved in steady state, i.e., the statemodel equations must be equaled to zero for the continuousdomain model.

TABLE INOMINAL CONDITIONS AND PARAMETERS

The resulting general model is used to design a controlscheme for a low-power laboratory prototype to test the the-oretical considerations developed so far in this work. The mainparameters and conditions of the system are listed in Table I.

Using the parameters in Table I and solving the equations(2) and (14) for steady state conditions, the system inputs arecalculated and applied to the converters. The main results areshown in Fig. 4.

The waveforms in Fig. 4(a) show that the PCC current phaseis near to the PCC voltage phase, despite that the load currenthas a poor inductive power factor. This is achieved thanks tothe current injection of the shunt compensator. Thus, the 0.98power factor requested in Table I is achieved in steady state.This fact corroborates that the mathematical model is correct.

It can be also seen from Fig. 4(a) that the PCC current isnear sinusoidal, considering that the switching frequency is just10 p.u., thanks to the triangular phase shifting SPWM techniqueapplied to the modular use of power cells [27]. This techniqueallows obtaining an equivalent switching frequency equals tothe number of power cells times the actual switching frequency.

Fig. 4(b) shows the DC voltages of two cells of the samephase, considering the same operating point described inTable I. As stated earlier, the differences among the elements ofthe configuration produce an asymmetrical power distributionamong the cells, which results in asymmetrical DC voltagesamong the power cells. This difference is increased by themodulating technique because the instantaneous power of eachcell is different.

Ap =

⎡⎢⎢⎣

−Rp

Lpω −npGacMd

po

Lp

−ω −Rp

Lp−npGacMq

po

Lp

Gac

2Cdc

{Md

po

np− nsMd

so

nc

}Gac

2Cdc

{Mq

po

np− nsMq

so

nc

}0

⎤⎥⎥⎦Bp =

⎡⎢⎢⎣−npGacVdc

Lp0

0 −npGacVdc

Lp

GacIdpo

2npCdc

GacIqpo

2npCdc

⎤⎥⎥⎦

Cp =

[0 0 1

− 1

(Idpo+Id

Lo)2+(Iq

po+IqLo)

2Id

po+IdLo

(Idpo+Id

Lo)2+(Iq

po+IqLo)

2 0

]Dp =

[0 00 0

]

Ep =

⎡⎣ 0 0

0 0−nsGacMd

so

2Cdcnc−nsGacMq

so

2Cdcnc

⎤⎦Fp =

⎡⎣ 0 − 1

(Idpo+Id

Lo)2+(Iq

po+IqLo)

2

0 Idpo+Id

Lo

(Idpo+Id

Lo)2+(Iq

po+IqLo)

2

⎤⎦

T

(17)

MUÑOZ et al.: DESIGN OF A DISCRETE-TIME LINEAR CONTROL STRATEGY FOR A MULTICELL UPQC 3801

Fig. 4. Steady state waveforms; (a) System currents and PCC voltage. (b) DC voltages.

Fig. 5. Global UPQC control scheme. (a) Global series compensator control scheme. (b) Global shunt compensator control scheme.

As seen in the Fig. 4(b), the DC voltage in the cells can bevery different from the desired steady state value, even thoughthe AC variables are equal to its operating values. Taking thisfact into account, the control scheme should be designed inorder to overcome these asymmetries in the topology.

V. CONTROL SCHEME

As mentioned earlier, the series compensator control schememust regulate the load voltage, and the shunt compensator con-trol scheme must regulate the overall power factor. In addition,the power balancing in the modules is achieved by distributingsymmetrically the series current and shunt voltage among thepower modules. Thus, two types of controllers are proposed,the global controllers that take care of the load voltage andthe PCC power factor and the local controllers that ensure thesymmetrical power distribution.

The global series compensator control scheme must considera strategy to manipulate the direct and quadrature components

of the injected series voltage, in order to obtain the desirableload voltage condition. Thus, the rms and phase angle of theload voltage values are the controllers references.The globalseries compensator control scheme, Fig. 5(a), includes twofeedback loops featuring a linear controller for both the directand quadrature components of the load voltage, and a feedfor-ward loop is included in the direct voltage loop to improve thedynamic behavior of the scheme. The quadrature feedforwardloop is not necessary due to the synchronization with the PCCvoltage. Feedback and feedforward loops are highlighted inFig. 5(a) for better understanding of the proposed scheme. Theoutputs of these controllers are sent to the local series currentdistribution control scheme, which is in charge of the symmetricdistribution of the power in the series stage.

The global shunt compensator control scheme has to main-tain the fundamental PCC power factor in its reference value.To achieve this task the controller modifies the φ angle thatrepresents the phase shift between the PCC voltage and current.

3802 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 59, NO. 10, OCTOBER 2012

Fig. 6. Local power distribution control scheme. (a) Local series current distribution control. (b) Local shunt voltage distribution control.

The proposed configuration controls the PCC power factor byinjecting a shunt current, so this global controller must generatepart of the modulating signals so that the shunt current achievesthe desired PCC power factor. The global shunt compensatorcontrol scheme, shown in Fig. 5(b), consists in sampling thePCC current, calculating its instantaneous angle and comparingthat angle with the desired reference. A single-variable linearcontroller generates an output that is used by the local shuntvoltage distribution control scheme to calculate the shunt con-verters modulating signals.

The local series current distribution control scheme takescare of the internal variables in the series side of the modularUPQC. Particularly, due to the parallel connection of this part ofthe topology, this controller must ensure that the series currentwill be the same in each cell. Thus, the power distributionis equal among all the cells of the series side. The localseries current distribution control scheme, shown in Fig. 6(a),modifies the amplitude of the modulating signal generated inthe global control scheme. Each cell increases its modulatingsignal amplitude in ΔM , obtained as the output of a controllerthat maintains the series current equals to its reference valuecalculated from the total PCC current.

In the same way of the series stage, there is a local shuntvoltage distribution control scheme to ensure that all cells oper-ate under the same conditions. Each loop consists in samplingthe Vdc voltage of the cell and compares it with its reference;then a linear controller generates the corresponding modulatingsignal. The shunt stage outputs are given by (15).

For the shunt controller, it is not evident which inputs controlwhich outputs, so a static decoupler is included in the schemein order to design single-variable controllers for each controlloop, as two separated systems. The decoupler achieves perfectdecoupled behavior in steady state for the chosen operatingpoint, as shown in Fig. 6(b). The value of the static decoupleris obtained by using the inverse of the transfer matrix in steadystate Hpd(1)−1.

VI. CONTROLLERS DESIGN

The design of all controllers considers the use of the rootlocus approach and the discrete equivalent linearized systemmodel. Each control loop is designed in the z-domain con-

TABLE IISYSTEM TRANSFER FUNCTIONS

sidering a sampling frequency of 4 kHz. Closed loop stabilityand robustness analysis is carried out to check the performanceof the proposed scheme. In addition, guidelines about scalingup the procedure to high-power rated applications are alsoincluded.

A. Controllers Parameters Selection

System transfer matrices (12) and (20) are calculated basedon parameters of Table I. As the control scheme is based onsingle-variable controllers, only the diagonal elements are con-sidered to design the controllers parameters, which are shownin Table II. Closed loop pole placement is done to achieve agiven dynamical behavior in the variables.

In the case of the series control scheme, a first-order compen-sator is proposed. A discrete integrator (z = 1) is also includedin the controller to ensure zero steady state error. Classicallead compensator design rules [28] can be followed to choosethe controllers parameters in order to achieve a given dynamicresponse. Particularly, a step response without overshoot and atime constant of about 1 ms is desired. Taking these specifica-tions into account, the controllers transfer function results

CVL(z) = k

z − β

(z − γ)(z − 1)= 2.8 · 10−4 (z + 0.02435)

(z − 0.21)(z − 1).

(21)

Fig. 7(a) shows the root locus of the load voltage discretetransfer function (hsd11(z) = hsd22(z)) with poles and zerosadded by the controller shown in (21). The step responseof the load voltage closed loop transfer function is shownin Fig. 7(b).

MUÑOZ et al.: DESIGN OF A DISCRETE-TIME LINEAR CONTROL STRATEGY FOR A MULTICELL UPQC 3803

Fig. 7. Control scheme discrete-time design. (a) Load voltage roots locus.(b) Load voltage step response. (c) Power factor roots locus. (d) Power factorstep response. (e) DC voltage roots locus. (f) DC voltage step response.

On the other hand, in the shunt control scheme, a discrete PIcontroller was chosen to ensure the desired dynamic behavior.The controller was tuned by the design rules given by [28], adamping coefficient of 0.95 (to obtain an overshoot less than1%) and a settling time—for a 5% band—of about 5 ms areused as design specifications. The root locus of the equivalentdiscrete system (hpd22(z)) is shown in Fig. 7(c), and a powerfactor step response is shown in Fig. 7(d). In this case, the powerfactor PI controller transfer function results

Cfp(z) = kz − β

z − 1= 0.3

z − 0.67z − 1

. (22)

For the local shunt control scheme, a PI controller (hpd11(z))was chosen to control the DC voltage of each cell, the root locusand the step response are shown in Fig. 7(e) and (f), respec-tively. The proposed PI variables were designed to achieve afirst-order closed loop step response with a time constant ofabout 150 ms, is shown in

CVdc(z) = k

z − β

z − 1= 0.027

z − 0.9355z − 1

. (23)

Fig. 8. Series control stability analysis. (a) Global series compensator con-troller stability. (b) Local series current distribution controller stability.

TABLE IIISERIES CONTROLLERS STABILITY ANALYSIS

B. Stability Analysis

As shown earlier, the series compensator model can beexpressed with linear equations. This fact is achieved becausethe DC link voltage control is performed by the shunt controlscheme. Thus, the stability analysis in the series subsystem canbe performed with the classical tools such as the gain and phasemargins. On the other hand, the shunt compensator system ismodeled with nonlinear equations (14), so the stability analysiscan be performed calculating the gain and phase margins overan operating region.

1) Series Compensator: To study the stability of the se-ries compensator, the gain and phase margins of each controlscheme is calculated. These results are summarized in Fig. 8and Table III.

It can be seen that the system will remain stable even ifthe linearized transfer function has some variations from theoperating point.

2) Shunt Compensator: To study the robust stability of theshunt compensator, a linearization over a given operating regionis performed. The controller equations will remain constant andthe system model will vary depending on the operating point.Particularly, a variation in the α angle (phase angle betweenthe load and PCC voltages) and the k factor (Per Unit PCCvoltage) is introduced in the nonlinear equations. Then, thegain and phase margins are calculated for each operating pointof the entire region. As can be seen in Fig. 9, the gain andphase margin remain positive for both global and local controlschemes. This fact ensures stability for the entire operatingregion of the shunt compensator.

It is necessary to point out that the system will remain stablefor the chosen operating region, but the dynamic performancewill be modified since all controllers are linear.

3804 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 59, NO. 10, OCTOBER 2012

Fig. 9. Shunt control stability analysis. (a) Global shunt compensator con-troller gain margin. (b) Global shunt compensator controller phase margin.(c) Local shunt compensator controller gain margin. (d) Local shunt compen-sator controller phase margin.

C. Robustness Analysis

In order to test how robust is the scheme when the systemparameters change, a ±20% variation of the main passiveelements is introduced, while the controller equations are keptconstant. The root locus diagrams of Fig. 7 are redrawn for aset of systems, resulting from each possible combination withinthe ±20% range. Results are shown in Fig. 10. The gray areacorresponds to all the positions where the closed loop polescould be located, and the black region corresponds to the actuallocation of the closed loop poles with the designed controller.

It can be seen from these diagrams that the dynamic perfor-mance will be seriously modified because the closed loop polesare located in different places depending on the variation intro-duced. However—and consequently with the previous stabilityanalysis—the system will remain stable even in the presence ofparameter variations up to ±20%.

D. Scaling-Up Guidelines

Analytical considerations developed so far are made over alow-power rated system, as shown in Table I. However, thesystematic procedure presented in this work can be extendedto any power level just by redefining the generalized systemtransfer matrixes (12) and (20). This generates different polesand zeros in Table II; however, the controllers transfer functionsshould be also modified in order to maintain the same closedloop dynamical behavior imposed by design.

On the other hand, higher power in the system will leadto smaller damping coefficients, due to higher X/R ratios. Ifthe same closed loop response is needed, the converters couldlie in the overmodulation region, so the dynamical behaviorrequirements should be relaxed. A practical way to scale up this

Fig. 10. Control scheme robustness analysis. (a) Load voltage roots locus.(b) Power factor roots locus. (c) DC voltage roots locus.

procedure is to work with per unit quantities, so the extensioncan be achieved naturally.

VII. RESULTS

A. Simulated Results

The proposed control scheme performance is analyzedthroughout the closed loop nonlinear system simulation withthe PSim 7.0 software. Specifically, PCC voltage disturbance,DC link voltages equalization, and power factor referencechanges are tested. The results show that the proposed con-trol scheme has a satisfactory dynamical behavior. Indeed,Fig. 11(a) shows the controller performance during a 20% sagin the PCC voltage. As it can be seen, the control schememaintains the load voltage in the desired value thanks to theproper series injected voltage.

Fig. 11(b) shows the DC link voltages equalization at 45 V,for the two cells of the phase a. The dynamic behavior of thisloop is similar to the designed approximate linear step responseof Fig. 7(f).

Fig. 12 shows a power factor step-up from 0.8 (no com-pensation) to unitary PCC power factor. These waveformswill be corroborated with the experimental results discussedhereafter.

B. Experimental Results

A 1-kVA power prototype was implemented to confirmthe controllers’ performance. The synchronization, modulation,control scheme, and frame transformations algorithms wereimplemented into a TMS 320C6713 DSP based board.

Fig. 13(a) illustrates the behavior of the local shunt voltagedistribution control scheme. The figure shows the DC linkvoltages transient behavior of four different cells when the con-troller is activated. First, the voltages are highly asymmetric;

MUÑOZ et al.: DESIGN OF A DISCRETE-TIME LINEAR CONTROL STRATEGY FOR A MULTICELL UPQC 3805

Fig. 11. Key simulated waveforms. (a) Voltage sag. (b) DC voltage equalization.

Fig. 12. Power factor correction simulated waveforms. (a) Load and PCC current and voltage. (b) Shunt current.

Fig. 13. Reference tracking dynamic performance; (a) DC voltage equalization. (b) Power factor correction.

however, once the controller is turned on, this voltage changesto the desired steady state value with a dynamic dictatedfor the designed controller. This transient response is slightlydifferent from the simulated results due to the differencesbetween the idealized components used in the simulation andthe real components used in the prototype. Experimental workhas demonstrated that parameters like parasitic resistance insome components (such as the DC link capacitor) and switcheslosses do influence mainly the dynamic performance of thecontrol scheme compared with the simulated results. Also,it can be seen in Fig. 13(a) that one of the voltages has anegative overshoot giving the wrong idea of a non-minimalphase system; however, this is due to the transition from an openloop to a closed loop system. In this case, the controllers outputis not cleared before activating the controller, and consequentlyat the beginning of the transient response, the system output canpresent a negative overshoot.

Fig. 13(b) shows the waveforms for the step change in thePCC power factor reference from 0.8—corresponding at the

same load phase delay—up to 1.0. Similar to what happenedin the simulated results, it can be seen that the PCC current lagsthe voltage in the first cycle; however, thanks to the controllersaction, after a couple of cycles, the phase angle of thesevariables becomes equal to zero. The figure also shows thatthe shunt current (ip) changes its steady state value, becausethe compensator in combination with the closed loop schemeinjects the suitable reactive current in order to maintain the PCCpower factor in the desired value.

Fig. 14(a) shows the extreme operating point when a 40%voltage sag is present in the system. During the sag, the DCvoltages decrease because the capacitors need to inject therequired energy to maintain the other loops working properly.As it was predicted in the stability analysis, the proposed con-troller can overcome a disturbance even though it is differentfrom the considered operating point, which is one of the mainconcerns of linear controllers. It can be also seen that the controlregulates the DC voltage of the cells equalized even during thetransient.

3806 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 59, NO. 10, OCTOBER 2012

Fig. 14. Disturbance rejection dynamic performance; (a) PCC voltage sag. (b) Load impact.

Fig. 15. Parameter variation dynamic performance.

A 50% load impact was also tested to analyze the controlperformance. Results in Fig. 14(b) show that the controller caneffectively regulate the overall power factor in the presence ofthis kind of disturbances. It’s important to point out that theproposed scheme can compensate the load impact even duringthe transient.

Additionally, a 20% variation in the shunt filter parame-ters was introduced to confirm the robustness analysis results.Fig. 15 shows the same power factor step-up of Fig. 13(b), andit can be seen that the dynamical behavior is slightly different.In this case, the shunt current ip presents a small overshoot thatthe original response does not show. It was expected from thetheoretical analysis that the step response would be different;however, the system is still stable when this variation wasintroduced.

VIII. CONCLUSION

Classic design methods, like root locus, present a simpleand effective alternative as a way to design and choose thecontrollers parameters. This paper shows that a UPQC based

on single-phase power cells can be controlled based on thisapproach. It is also shown a systematic procedure to findthe parameters that can be scaled up to high power systems.Considering the nonlinear nature of the topology, the dynamicand steady state error performance of linear controllers issatisfactory. Simulated and experimental results confirm thedesign procedure.

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Javier A. Muñoz (S’08) was born in Concepción,Chile, in 1983. He received the Engineer degreein electronic engineering (with first-class honors)and the M.Sc. degree in electrical engineering fromthe University of Concepción, Concepción, Chile, in2007 and 2009, respectively, where he is currentlyworking toward the D.Sc. degree in electrical en-gineering in the area of digital control of multicellpower converters.

Recently, since April 2011, he is a Professor at theDepartment of Industrial Technologies, University of

Talca, Talca, Chile, where he is currently teaching in the areas of dynamic sys-tems and robotics. His research interests include modular multilevel convertersto improve power quality.

José R. Espinoza (S’92–M’97) received the Eng.degree in electronic engineering and the M.Sc. de-gree in electrical engineering from the University ofConcepcion, Concepcion, Chile, in 1989 and 1992,respectively, and the Ph.D. degree in electrical en-gineering from Concordia University, Montreal, QC,Canada, in 1997.

Since January 2006, he is Professor in the De-partment of Electrical Engineering, University ofConcepcion, where he is engaged in teaching andresearch in the areas of automatic control and power

electronics. He has authored and coauthored more than 100 refereed journaland conference papers and contributed to one chapter in the Power ElectronicsHandbook published in 2011 by Academic Press.

Dr. Espinoza is currently an Associate Editor of the IEEE TRANSACTIONS

ON INDUSTRIAL ELECTRONICS and Power Electronics.

Carlos R. Baier (S’08–M’11) was born in Temuco,Chile, in 1979. He received the B.S., M.Sc., andD.Sc. degrees in electrical engineering from the Uni-versity of Concepcion, Concepcion, Chile, in 2004,2006, and 2010, respectively.

Since 2009, he has been a Professor in the Depart-ment of Industrial Technologies, University of Talca,Talca, Chile, where he is teaching in the areas of au-tomatic control and power electronics. His researchinterests include improved control techniques formulticell converters, new multilevel topologies, and

high energy efficient improvements for medium-voltage converter topologies.

Luis A. Morán (S’79–M’81–SM’94–F’05) wasborn in Concepción, Chile. He received the elec-trical engineering degree from the University ofConcepción, Concepción Chile, in 1982 and thePh.D. degree from Concordia University, Montreal,QC, Canada, in 1990.

Since 1990, he has been with the Electrical En-gineering Department, University of Concepción,where he is a Professor. He has extensive consultingexperience in the mining industry, particularly inthe application of medium-voltage ac drives, large-

power cycloconverter drives for SAG mills, and power-quality issues. His mainareas of interest are in ac drives, power quality, active power filters, FACTS,and power protection systems.

Dr. Morán was the Associate Editor of the IEEE TRANSACTIONS ON

POWER ELECTRONICS from 1997 to 2001. In 1995, he received theIEEE Outstanding Paper Award from the Industrial Electronics Society forthe best paper published in the IEEE TRANSACTIONS ON INDUSTRIAL

ELECTRONICS, and he was recently appointed Distinguished Lecture of theIEEE for the period 1 January 2008 to 31 December 2009. In 1998, he receivedthe City of Concepción Medal of Honour for achievement in applied research.He has written and published more than 25 papers on active power filters andstatic VAR compensators in IEEE TRANSACTIONS.

Eduardo E. Espinosa was born in Concepción,Chile in 1983. He received the Eng. degreein electronic engineering from the University ofConcepción, Concepción, Chile, in 2009. He is cur-rently working toward the D.Sc. degree in electricalengineering in the area of multicell voltage convert-ers topologies.

His topics of interest are asymmetric multicellinverters and minimization of THD.

Pedro E. Melín (S’10) was born in Chillán, Chile,in 1982. He received the Eng. degree in elec-tronic engineering and the M.Sc. degree in electri-cal engineering from the University of Concepción,Concepción, Chile, in 2006 and 2010, respectively,where he is currently working toward the D.Sc. de-gree in electrical engineering in the area of multilevelcurrent source converters topologies and working inthe design and construction of an electrical vehiclefor solar challenges.

Daniel G. Sbárbaro (S’81–M’84–SM’01) was bornin Concepción, Chile. He received the degreein electrical engineering from the Universidad deConcepción, Concepción, Chile, in 1984, and thePh.D. degree from Glasgow University, Glasgow,U.K., in 1993.

He was an Alexander von Humbolt Fellow at theControl Engineering Laboratory, Ruhr University,Bochum, Germany, in 1998. He is currently a Profes-sor with the Department of Electrical Engineering,Universidad de Concepción. His current research

interests include design of observers for nonlinear systems and the developmentand industrial application of nonlinear control algorithms.