Demonstration and Characterization of Bipolar Monolithic Integrated Circuits in 4H-SiC

1946 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 8, AUGUST 2008

Demonstration and Characterization of BipolarMonolithic Integrated Circuits in 4H-SiC

Jeong-Youb Lee, Shakti Singh, and James A. Cooper, Fellow, IEEE

Abstract—A monolithic bipolar integrated circuit technologyemploying transistor–transistor logic (TTL) is demonstrated in4H-SiC for the first time. Operating on a 15-V power supply,as required by the higher base–emitter voltage of SiC bipolartransistors, TTL inverters with a fan-out of ten exhibit high-levelnoise margin (NMH ) of 1.5 V and low-level noise margin (NML)of 3.9 V at room temperature. The transient response of the fab-ricated SiC TTL gates is also characterized. The circuits operatesatisfactorily from room temperature to above 300 C, suggestingthat SiC bipolar integrated circuits are promising candidates forhigh-temperature applications.

Index Terms—High-temperature ICs, SiC ICs, silicon carbide,smart power, transistor–transistor logic (TTL).

I. INTRODUCTION

S ILICON CARBIDE (SiC) is a wide bandgap semiconduc-tor with outstanding electrical properties compared with

silicon [1], [2]. The superior physical properties of SiC includelow intrinsic carrier concentration, high breakdown electricfield, high thermal conductivity, low thermal generation rate,high intrinsic temperature, and high saturated electron driftvelocity. These characteristics make the SiC an attractive ma-terial for high-power and high-temperature electronic applica-tions. Because of its unique physical properties, SiC devicesare capable of good electrical performance at temperaturesabove 600 C. SiC is also physically robust, and reliable andsustained operation at high temperatures is possible, providedthat the device does not rely upon a gate oxide under high-field stress and assuming that high-temperature metallizationschemes are developed [3]–[6]. SiC MOS devices are limitedby gate oxide reliability to temperatures below about 200 C.However, SiC bipolar junction transistors (BJTs) do not rely ona critical oxide and can operate reliably at temperatures muchhigher than 200 C. Therefore, BJTs can form the basis foran integrated circuit family that is capable of sustained long-term high-temperature operation, with applications in military,power utility, aerospace, automotive, and well-logging systems.

Discrete SiC BJTs have already been demonstrated withhigh performance [7]–[11]. In this paper, we report a bipolar

Manuscript received December 22, 2007; revised March 22, 2008. This workwas supported by the U.S. Army TACOM under Grant W56HZV-06-C-0228,which is administered by Mr. Terrence Burke. The review of this paper wasarranged by Editor G. Pensl.

J.-Y. Lee is with Applied Materials, Inc., Santa Clara, CA 95054 USA.S. Singh and J. A. Cooper are with the Birck Nanotechnology Center, School

of Electrical and Computer Engineering, Purdue University, West Lafayette, IN47907 USA.

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TED.2008.926681

Fig. 1. Cross-sectional view of the BJT used in this experiment. The lateralpitch is 21.5 µm. The thickness and the doping of all epilayers are shown onthe left.

logic IC technology in 4H-SiC, based on the simple and robusttransistor–transistor logic (TTL) family, which is capable ofintegration levels of a few hundred transistors per chip. Thispaper demonstrates the feasibility of the circuit design andfabrication process and produces basic circuits. The fabricationtechnology developed in this paper will support any bipolarIC family, including, for example, emitter-coupled logic, inte-grated injection logic (I2L), or linear integrated circuits. Ourcircuits are characterized over a wide temperature range toverify their operation and quantify their performance.

II. SIMULATION AND DESIGN

We utilized the circuit simulation program SPICE [12] todesign the basic TTL circuits. To simulate a SiC TTL gate inSPICE, the model parameters for the SiC BJT first need to bespecified. For the initial designs, the SPICE model parameterswere obtained by fitting to theoretical current–voltage (I–V )characteristics obtained from MEDICI [13] 2-D simulations ofthe actual SiC BJT structure.

Fig. 1 shows a schematic cross section of the junction-isolated epitaxial bipolar transistor used in this paper. The thick-ness and the doping of all layers are indicated in the figure. Ourlateral design rules enforce a minimum feature size of 3 µm anda layer-to-layer alignment tolerance of 2 µm. Emitter, base, andcollector layers are epitaxially grown because carrier lifetimeis longer in epilayers than in implanted layers. The basic BJTcell has a width of 21.5 µm. To minimize recombination in theimplanted p+ base contact and enable a high common–emittercurrent gain, the p+ base contact is placed 4 µm away from theemitter edge.

To design SiC TTL circuits, it is necessary to specify cir-cuit parameters such as VCC, resistances, and device sizes. Inthis paper, the conventional silicon TTL circuit configuration

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LEE et al.: DEMONSTRATION AND CHARACTERIZATION OF BIPOLAR MONOLITHIC INTEGRATED CIRCUITS 1947

Fig. 2. Circuit diagram of the SiC TTL inverter implemented in this paper.Internal currents and voltages are shown for the inverter with a fan-out of ten in(a) the output-high state and (b) the output-low state.

is adopted, but the element values are modified to provideadequate noise margins in 4H-SiC and to produce similarcurrent levels as a silicon TTL gate under no-load conditions(FO = 0). The VCC supply is increased from 5 V (used insilicon) to 15 V. This is necessary because the voltage drop ofa forward-biased p-n junction is proportional to the bandgap,which is three times greater in 4H-SiC. All resistor values areincreased to achieve adequate noise margins in 4H-SiC. Theemitter length of all transistors except the output transistor(QO) is set at 100 µm. Fig. 2 shows the circuit diagram ofthe SiC TTL inverter, as implemented in this paper, alongwith internal currents and voltages in both the output-high andoutput-low states.

To support a fan-out of ten in a TTL gate, the output transistormust be larger than other transistors, and a 500-µm total emitterlength is used for the output transistor. In our layout, multipleinterdigitated emitter and base fingers are used so that the lengthof BJT cell can be maintained. Our design employs five emitterfingers and six base fingers, each 100 µm in length, and twocollector fingers on either side of the emitter and base fingers.Since our VCC is three times higher than in silicon, we designed

Fig. 3. SPICE simulations of the VOUT−VIN characteristics for the SiC TTLinverter with VCC = 15 V, L = 100 µm, and L(QO) = 500 µm at fan-outsof zero and ten. Static noise margins are also indicated.

for noise margins of NMH = NML = 1.2 V, which is threetimes higher than in silicon TTL.

The voltage transfer characteristic (VTC) for the SiC TTLinverter, as simulated in SPICE, is shown in Fig. 3. The stableoperating points are given by the intersections of the normaland inverted VTC curves, as illustrated in the figure. Withincreased fan-out, the output-high voltage VOH decreases, andthe output-low voltage VOL increases slightly. Under no-loadconditions (FO = 0), the high noise margin NMH is 4.7 V,and the low noise margin NML is 2.7 V. At a fan-out of ten, anNMH of 2.3 V and an NML of 2.8 V are observed, which aresatisfactory for normal circuit operation.

III. FABRICATION

All-epitaxial SiC TTL circuits with double-level metal in-terconnect are fabricated on 50-mm 4H-SiC wafers withn+/p/n-/n+ epilayers on p+ substrates. The doping and thethickness of each layer are shown in Fig. 1. To form the emittermesas, a Ti/Ni layer is deposited as an etch mask by e-beamevaporation and patterned by lift-off. Then, slightly over 0.5 µmof SiC is removed by reactive-ion etching (RIE) in SF6. Theetch mask is removed, and Ti/Au is evaporated and patterned asa p+ implant mask to define the base contact. Heavily dopedp+ base contact regions are formed by Al implantation at


Fig. 4. SEM photographs of (a) part of a single BJT and (b) a basic TTLinverter after collector isolation etch. There are a total of three vertical stepsin this pattern: The emitter isolation etch (≥ 0.5 µm), the base isolation etch(≥ 1.5 µm), and the collector isolation (≥ 1.0 µm).

650 C at normal incidence and a total dose of 1.05 ×1015 cm−2. After the removal of the mask and the postimplantcleaning, the implants are activated at 1600 C for 20 min in anAr ambient with a graphite cap. The base mesa is defined by aTi/Ni etch mask, and 1.5 µm of SiC is removed by RIE. Thisetch also exposes the n+ collector contact regions. Another RIEof 1.0 µm is performed to provide lateral isolation betweendevices. Fig. 4 shows SEM photographs of a portion of a singleBJT and a basic TTL inverter after all SiC RIE steps.

After RCA cleaning, a gate-quality passivation oxide isgrown by wet oxidation at 1150 C for 3.5 h, which is followedby an in situ reoxidation anneal at 950 C for 2 h in a pyrogenicoxidation system. The oxidation is followed by a postoxidationanneal in NO at 1175 C for 2 h to reduce the interface statedensity [14] and decrease the surface recombination velocity.Ni (70 nm) is deposited by e-beam evaporation and patternedby lift-off to form n-type ohmic contacts on the emitter andcollector fingers, and Ti/Al (33 nm/167 nm) is deposited as thep-type contact metal on the base fingers.

We next deposit a thick intermediate layer dielectric (ILD)consisting of 400 nm of phosphosilicate glass and 100 nm oflow-temperature oxide (LTO). Contact vias are defined by lift-off lithography using SC1827 photoresist, which is spun to athickness of 3 µm to insure step coverage, and vias are openedby RIE in SF6 followed by a BHF dip. To form the first layer of

interconnect metal, we deposit 900 nm of Al on 50 nm of Ti andpattern it by lift-off lithography. The first layer of interconnectmetal covers ohmic contact stripes along the emitter, base,and collector fingers, forms some of the connecting wires, andcreates pad regions for via holes to be formed in a subsequentstep. To prepare for the second level of metallization, a secondILD of 500-nm LTO is deposited. To connect the first andsecond layers of interconnect metal, vias are opened in the ILDby RIE and wet etching using a photoresist etch mask. Finally,the second interconnect metal is deposited (50-nm Ti/1-µm Al)to form bonding pads and establish the top-level interconnects.

Our test chip contains several test patterns, including individ-ual BJTs and basic gates (inverter, NAND, and NOR), that canbe used as building blocks to implement more complex logiccircuits. Each gate is designed with a standard height (260 µm)and a width that is a multiple of 10 µm. This modular designallows gates to be positioned side-by-side with wiring channelsalong either side. The gates share a common ground and powersupply (VCC) bus, and inputs and outputs are brought out tothe wiring channel on a 10-µm grid, allowing standardizedinterconnects.

IV. RESULTS AND DISCUSSION

DC I–V and VTCs are measured by using an HP-4156semiconductor parameter analyzer. Switching response is char-acterized by using an Agilent 33220A waveform generator anda Tektronix TDS5032B Oscilloscope with a Tektronix P6245low-capacitance FET probe.

A. Device Performance

Our TTL SiC gates employ two different size BJTs. Alltransistors except the output transistor (QO) have a fingerlength of 100 µm and an active area of 2.1 × 10−3 mm2.The output transistor is 500 µm long, with an active area of0.0105 mm2. Fig. 5 shows the dc I–V characteristics of BJTswith finger lengths of 100 and 500 µm. The common–emittercurrent gains (β) are approximately 22 for a 100-µm device and17 for a 500-µm device, and the specific on-resistances Ron,sp

are 5.63 and 27.7 mΩ · cm2, respectively. The reason for thelower β in the large device is not well understood, but it may bedue to material defects or defects introduced by the processing.The on-resistance of the 500-µm device is larger than that of thesmall device due to the more widely spaced collector contacts.The 500-µm BJT has five 100-µm interdigitated emitter andbase fingers, but it has only two collector contact fingers, one oneach side of the emitter-base array. This increases the collectorspreading resistance in the 500-µm device. The n+ emitter andcollector contact resistivities ρcn are 9.09 × 10−6 and 7.85 ×10−5 Ω · cm2, respectively. The emitter and collector sheetresistances ρS are 250 and 98 Ω/square, respectively, consistentwith the dopings and thicknesses of the layers. The n-typecontact resistivities are uniform across the wafer, but the p-typecontact resistivity is not uniform. The lowest ρcp measuredis 4.88 × 10−2 Ω · cm2, and the base sheet resistance ρS is49.8 kΩ/square, which is higher than expected based on thedoping and thickness of the base layer. We believe that the high


Fig. 5. DC current–voltage characteristics of the 100- and 500-µm BJTs. Thecommon–emitter current gains are 22 and 17, respectively. The base currentranges from 0 (bottom trace) to 400 µA (top trace) in 100-µA increments.

p+ contact resistivity in these devices may be due to the failureto reach a sufficiently high temperature during ohmic contactannealing.

Fig. 6(a) shows Gummel plots for the devices in Fig. 5.The current gain β is constant for VBE > 4 V in the forwardactive region, but it falls at low current levels in both devices.As shown in Fig. 6(b), the 100-µm BJT maintains β > 20 tocollector currents of 1000 A/cm2 at VCE = 10 V, whereas the500-µm BJT exhibits β > 15 over the same current range.

B. TTL Logic Gate Performance

Fig. 7 shows the VTC of SiC TTL inverters with fan-outs ofzero and ten. The FO = 0 inverter has an output-high voltageVOH of 11.3 V and an output-low voltage VOL of 0.4 V.As expected, the output-high level decreases (8.3 V), and theoutput-low level increases (1.3 V) for an FO = 10 inverter.The high-level noise margin (NMH) is 1.5 V, and the low-level noise margin (NML) is 3.9 V for an FO = 10 (VIL =5.2 V, VIH = 6.8 V), whereas both NMH and NML are 4.1 Vfor an FO = 0 (VIL = 4.5 V, VIH = 7.2 V). Compared with thesimulated results (NML = 2.7 V, NMH = 4.7 V for FO = 0;NML = 2.8 V, NMH = 2.3 V for FO = 10), the measured SiC

Fig. 6. (a) Gummel plots, and (b) current gain versus collector current for the100- and 500-µm BJTs at VCE = 10 V.

TTL inverters show good noise margins and meet the statedperformance goals (noise margins ≥ 1.2 V).

It is desirable to reduce VCC in order to reduce the powerdissipated in the TTL gate. In order to determine the lowestpractical VCC for the fabricated SiC TTL inverters, the VTCis measured as a function of VCC, and the noise margins aresummarized in Fig. 8. As shown in the figure, the SiC TTL in-verter with FO = 0 operates properly for VCC > 9 V (NML =1.5 V, NMH = 0.4 V), whereas the FO = 10 inverter operatesproperly for VCC > 12 V (NML = 4.6 V, NMH = 0.1 V).With assumed noise margin limits of NMH = NML = 1.2 V,the fabricated inverters maintain useful VTCs down to VCC of12 V for FO = 0 (NML = 4.3 V, NMH = 1.8 V) and 15 V forFO = 10 (NML = 3.9 V, NMH = 1.5 V).

Propagation delay (tpd) is defined as the time between the50% transition points of the input and the output waveforms.The low-to-high delay tpLH is the time for a low-to-high outputtransition, whereas the high-to-low delay tpHL is the time fora high-to-low output transition. Switching waveforms for SiCTTL inverters with FO = 0 and FO = 10 are shown in Fig. 9.The measurement is performed at VCC = 15 V with a peak-to-peak input voltage of 15 V. For an FO = 0 inverter, tpLH is102 ns, and tpHL is 92 ns. For an FO = 10 inverter, tpLH is98 ns, and tpHL is 118 ns. The overall propagation delay timestpd for the SiC TTL inverters with FO = 0 and FO = 10 are97 and 108 ns, respectively. The output rise time tr (measured


Fig. 7. VOUT−VIN characteristics of fabricated SiC TTL inverters for fan-outs of zero and ten at VCC = 15 V. Static noise margins are indicated.

Fig. 8. Noise margins versus VCC for the SiC TTL inverters of fan-outs ofzero and ten.

from 0.1 VOH to 0.9 VOH) and the fall time tf (measured from0.9 VOH to 0.1 VOH) are also shown in the figure, where therise and fall times of the input waveform are 66 and 86 ns,respectively. Waveforms verifying operation of the three-inputNAND and the two-input NOR gates are shown in Figs. 10 and11, respectively.

Fig. 9. Switching waveforms of SiC TTL inverters with fan-outs of zeroand ten.

C. Temperature Dependence

DC and transient response of the basic gates are also char-acterized as a function of temperature. Fig. 12 shows thecommon–emitter current gain as a function of current for 100-and 500-µm BJTs at room temperature, 148 C, and 323 C.The maximum current gain decreases with temperature for bothdevices: from 22 at 25 C to 15 at 323 C for a 100-µm BJTand from 18 at 25 C to 13 at 323 C for a 500-µm BJT. Themaximum current gain and specific on-resistances Ron,sp areshown as a function of temperature in Fig. 13, demonstrating anegative temperature coefficient of current gain and a positivetemperature coefficient of on-resistance, consistent with otherreports [7]. The decreasing current gain is mainly attributedto an increase in the ionization percentage of Al acceptorsin the base at higher temperatures, whereas the increasingresistance is due to the reduction of carrier mobility at highertemperatures.

Fig. 14 shows the VTC of SiC TTL inverters as a functionof temperature. In the FO = 0 inverter, the output-high voltageVOH increases with temperature, resulting in an increased high-level noise margin NMH while the low noise margin NML de-creases slightly with temperature. This is also true for the FO =10 inverter, as shown in the figure. All SiC TTL inverters exhibitstable noise margins from room temperature to over 300 C.

Switching waveforms of the SiC TTL inverters at three tem-peratures are shown in Fig. 15. Characterization is performed


Fig. 10. Three-input NAND gate operation: (Top) Input waveforms and(bottom) resulting output waveform.

Fig. 11. Two-input NOR gate operation: (Top) Input waveforms and (bottom)resulting output waveform.

by using a Tektronix P6245 low-capacitance FET probe withVCC = 15 V and a peak-to-peak input voltage swing of 15 V.Both the FO = 0 and FO = 10 inverters operate normally fromroom temperature to above 300 C, with almost no noticeablechange in propagation delay. The low-to-high transition times

Fig. 12. Current gain versus collector current for the 100- and 500-µm BJTsat different temperatures (VCE = 10 V).

Fig. 13. Temperature dependence of current gain and the specific on-resistance for the 100- and 500-µm BJTs.

tpLH increase slightly with temperature (from 98 ns at roomtemperature to 102 ns at 325 C for the FO = 10 inverter),whereas the high-to-low transition times tpHL decrease slightly(from 114 ns at room temperature to 100 ns at 325 C forthe FO = 10 inverter). As a result, the propagation delay tpd

decreases slightly with temperature (from 108 ns at roomtemperature to 101 ns at 325 C for the FO = 10 inverter). Thebehavior of the FO = 0 inverter is similar.

D. Design Optimization

This is the first report of monolithic bipolar TTL integratedcircuits in SiC, and the device structure, circuit design, andfabrication process have not been fully optimized. Our initialobjective was to fabricate a variety of logic gates and to demon-strate adequate noise margins for fan-outs up to ten from roomtemperature to over 300 C. We will report on an optimizeddesign that incorporates a semi-insulating substrate, reducedcircuit area, and lower propagation delay in another publication[15]. More work is also needed to incorporate high-temperaturemetallization schemes and to establish the long-term reliabilityof this technology at elevated temperatures.


Fig. 14. VOUT−VIN characteristics of the SiC TTL inverters with fan-outsof zero and ten at different temperatures.

V. CONCLUSION

In this paper, we report the first monolithic bipolar TTL inte-grated circuits in 4H-SiC. The VTCs of SiC TTL inverters op-erated at VCC = 15 V show a high-level noise margin (NMH)of 1.5 V and a low-level noise margin (NML) of 3.9 V at afan-out of ten. Noise margins remain relatively constant fromroom temperature to over 300 C. Propagation delays of 97and 108 ns are observed for the FO = 0 and FO = 10 invertersat room temperature. The propagation delay decreases slightlywith temperature from room temperature to above 300 C.These results indicate that the SiC bipolar integrated circuitsare promising candidates for high-temperature applications, butmore work is needed to establish the long-term reliability of thetechnology.

ACKNOWLEDGMENT

The authors would like to thank Dr. K. Matocha and thestaff of General Electric Global Research for the dielectricdepositions, Prof. M. A. Capano of Purdue University for theimplant annealing, and the staff of the Birck NanotechnologyCenter for their assistance with the fabrication.

Fig. 15. Switching waveforms of the SiC TTL inverters with fan-outs of zeroand ten at three temperatures.

REFERENCES

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[2] H. Matsunami, “Progress in wide bandgap semiconductor SiC for powerdevices,” in Proc. 12th Int. Symp. Power Semicond. Devices ICs, 2000,pp. 3–9.

[3] R. S. Okojie et al., “Reliability assessment of Ti/TaSi2/Pt ohmic contactson SiC after 1000 h at 600 C,” J. Appl. Phys., vol. 91, no. 10, pp. 6553–6559, May 2002.

[4] A. Baeri, V. Raineri, F. La Via, V. Puglisi, and G. G. Condorelli,“Environment influence on Ti diffusion and layer degradation of aSiC/Ni2Si/TiW/Au contact structure,” J. Vac. Sci. Technol. B, Microelec-tron. Process. Phenom., vol. 22, no. 3, pp. 966–970, 2004.

[5] A. Baeri, V. Raineri, F. Roccafortre, F. La Via, and E. Zanetti, “Studyof TiW/Au thin films as metallization stack for high temperature andharsh environment devices on 6H silicon carbide,” Mater. Sci. Forum,vol. 457–460, pp. 873–876, 2004.

[6] R. Kakanakov, L. Kasamakova–Kolaklieva, N. Hristeva, G. Lepoeva,J. B. Gomes, I. Avramova, and T. Marinova, “High temperature andhigh power stability investigation of Al-based ohmic contacts to p-type4H-SiC,” Mater. Sci. Forum, vol. 457–460, pp. 877–880, 2004.

[7] S.-H. Ryu, A. K. Agawal, R. Singh, and J. W. Palmour, “1800 V NPNbipolar junction transistors in 4H-SiC,” IEEE Electron Device Lett.,vol. 22, no. 3, pp. 124–126, Mar. 2001.

[8] J. A. Cooper Jr. and A. K. Agarwal, “SiC power-switching devices—Thesecond electronics revolution?” in Proc. IEEE, vol. 90, no. 6, pp. 956–968,Jun. 2002.

[9] C.-F. Huang and J. A. Cooper, Jr., “High current gain 4H-SiC npn bipolarjunction transistors,” IEEE Electron Device Lett., vol. 24, no. 6, pp. 396–398, Jun. 2003.


[10] F. Zhao, B. V. Zeghbroeck, K. Torvik, T. Shi, and M. Mallinger, “Demon-stration of long-pulse power amplification at 1 GHz using 4H-SiC RFBJTs on a conductive substrate,” IEEE Electron Device Lett., vol. 28,no. 5, pp. 398–400, May 2007.

[11] H.-S. Lee, M. Domeij, C.-M. Zetterling, M. Ostling, F. Allerstam, andE. O. Sveinbjornsson, “1200 V, 5.2 mΩ · cm2 4H-SiC BJTs with a highcommon–emitter current gain,” IEEE Electron Device Lett., vol. 28,no. 11, pp. 1007–1009, Nov. 2007.

[12] D. A. Hodges and H. G. Jackson, Analysis and Design of Digital Inte-grated Circuits, 2nd ed. New York: McGraw-Hill, 1988.

[13] MEDICI and User’s Manuals, Avant! Corporation, Fremont, CA, 2000.[14] C.-Y. Lu, J. A. Cooper, T. Tsuji, G. Y. Chung, J. R. Williams,

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[15] S. Singh, J.-Y. Lee, and J. A. Cooper, 2008. unpublished.

Jeong-Youb Lee received the B.S. and M.S. degreesfrom Hanyang University, Seoul, Korea, in 1994 and1996, respectively, and the Ph.D. degree from PurdueUniversity, West Lafayette, IN, in 2008.

From 1996 to 2002, he was a Member of TechnicalStaff with the Memory R&D Division, Hynix Semi-conductor Inc., Icheon, Kyoungki, Korea, where hewas a Process Engineer of the Advanced ProcessTeam. In January 2003, he joined the Schoolof Electrical and Computer Engineering, PurdueUniversity, as a Research Assistant. His research at

Purdue included SiC p+ ohmic contact formation, fabrication of a 4H-SiC-based BJT for power electronic applications, and development of a bipolar logicIC technology. He is currently with Applied Materials, Inc., Santa Clara, CA.

Shakti Singh received the B.S. degree in electricalengineering and the M.S. degree in electrical andcomputer engineering from Purdue University, WestLafayette, IN, in 2000 and 2003, respectively, wherehe is currently working toward the Ph.D. degree inthe Birck Nanotechnology Center, School of Electri-cal and Computer Engineering. His thesis focuses onthe design, development, optimization, fabrication,and characterization of high-speed monolithic bipo-lar integrated circuits in 4H-SiC.

James A. Cooper (S’66–M’69–SM’85–F’93) re-ceived the M.S. degree in electrical engineeringfrom Stanford University, Standford, CA, in 1969and the Ph.D. degree from Purdue University, WestLafayette, IN, in 1973.

From 1973 to 1983, he was a Member of theTechnical Staff with Bell Laboratories, Murray Hill,NJ, where he was the Principal Designer of AT&T’sfirst CMOS microprocessor and developed a time-of-flight technique to study high-field transport insilicon inversion layers. Since 1983, he has been with

the faculty of Purdue University, where he was the Founding Director of thePurdue Optoelectronics Research Center. Since 1990, he has been exploringthe device technology in SiC. His group demonstrated the first monolithicintegrated circuits in SiC (1993), the first DMOS power transistors (1996),and the first self-aligned short-channel DMOSFETs (2003). The group hasalso developed NVRAMs, charge-coupled devices, Schottky diodes, bipolarjunction transistors, IGBTs, SITs, and IMPATT diodes in SiC. He was theFounding Codirector of the Birck Nanotechnology Center, School of Electricaland Computer Engineering, Purdue University, where he is currently theJai N. Gupta Professor. He has graduated 24 Ph.D. students. He has coauthoredover 240 technical papers and conference presentations and five book chapters,and he is the holder of 13 U.S. patents.

Dr. Cooper served as the Associate Editor of the IEEE TRANSACTIONS ON

ELECTRON DEVICES from 1983 to 1986, the Coeditor of the 1999 and 2008Special Issues of the IEEE TRANSACTIONS ON ELECTRON DEVICES on SiCtechnology, and currently serves on the editorial advisory board of the IEEEPROCEEDINGS.

Demonstration and Characterization of Bipolar Monolithic Integrated Circuits in 4H-SiC

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