analog cmos ic design (professional elective – vi)

II Yr-ECE – II Sem. 1

ANALOG CMOS IC DESIGN (PROFESSIONAL ELECTIVE – VI)

COURSE PLANNER

I. COURSE OVERVIEW:

Analog circuits play a very crucial role in all electronic systems and due to continued

miniaturization; many of the analog blocks are not getting realized in CMOS technology.

II. PREREQUISITE:

1. Basic Mathematics

2. VLSI Design

3. Electronic Devices and circuits (EDC)

4. Analog and Digital Integrated Circuit

III. COURSE OBJECTIVE:

1. To understand most important building blocks of all CMOS analog Ics.

2. To study the basic principle of operation, the circuit choices and the tradeoffs involved in the

MOS transistor level design common to all analog CMOS ICs.

3 To understand specific design issues related to single and multistage voltage, current and

differential amplifiers, their output and impedance issues, bandwidth, feedback and stability.

4 To understand the design of differential amplifiers, current amplifiers and OP AMPs..

IV. COURSE OUTCOME:

SL.

NO DESCRIPTION

BLOOM’S

TAXANOMY

LEVEL

1. Design basic building blocks of CMOS analog ICs. L1, L2

2. Carry out the design of single and two stage operational amplifiers

and voltage references.

L3, L4, L5, L6

3. Determine the device dimensions of each MOSFETs involved. L3, L4

4 Design various amplifiers like differential, current and operational

amplifiers

L1, L4

V. HOW PROGRAM OUTCOMES ARE ASSESSED:

PROGRAM OUTCOMES (PO) Level Proficiency

assessed by

PO1 Engineering knowledge: Apply the knowledge of mathematics,

science, engineering fundamentals, and an engineering

specialization to the solution of complex engineering problems

(Fundamental Engineering Analysis Skills).

3 Assignments,

Tutorials

PO2 Problem analysis: Identify, formulate, review research

literature, and analyze complex engineering problems reaching

substantiated conclusions using first principles of mathematics,

3 Assignments

IV Yr-ECE – II Sem. 2

natural sciences, and engineering sciences (Engineering

Problem Solving Skills).

PO3 Design/development of solutions: Design solutions for

complex engineering problems and design system components

or processes that meet the specified needs with appropriate

consideration for the public health and safety, and the cultural,

societal, and environmental considerations (Social Awareness).

3

Mini Projects

PO4 Conduct investigations of complex problems: Use research-

based knowledge and research methods including design of

experiments, analysis and interpretation of data, and synthesis

of the information to provide valid conclusions (Creative

Skills).

2

Projects

PO5 Modern tool usage: Create, select, and apply appropriate

techniques, resources, and modern engineering and IT tools

including prediction and modeling to complex engineering

activities with an understanding of the limitations (Software

and Hardware Interface).

3 Projects

PO6 The engineer and society: Apply reasoning informed by the

contextual knowledge to assess societal, health, safety, legal

and cultural issues and the consequent responsibilities relevant

to the professional engineering practice (Social Awareness).

2 Development

of Prototype,

Projects

PO7 Environment and sustainability: Understand the impact of the

professional engineering solutions in societal and

environmental contexts, and demonstrate the knowledge of, and

need for sustainable development (Social Awareness).

3 Oral

Discussions

PO8 Ethics: Apply ethical principles and commit to professional

ethics and responsibilities and norms of the engineering practice

(Professional Integrity).

1 Inventions

and case

studies

PO9 Individual and team work: Function effectively as an

individual, and as a member or leader in diverse teams, and in

multidisciplinary settings (Team work).

2 Development

of Prototype,

Projects

PO10 Communication: Communicate effectively on complex

engineering activities with the engineering community and with

society at large, such as, being able to comprehend and write

effective reports and design documentation, make effective

presentations, and give and receive clear instructions

(Communication Skills).

3

Presentations

PO11 Project management and finance: Demonstrate knowledge

and understanding of the engineering and management

principles and apply these to one’s own work, as a member and

leader in a team, to manage projects and in multidisciplinary

environments (Practical Engineering Analysis Skills).

2

Development

of Prototype,

Projects

PO12 Life-long learning: Recognize the need for, and have the

preparation and ability to engage in independent and life-long

learning in the broadest context of technological change

(Continuing Education Awareness).

3 Seminars,

Discussions


VI. HOW PROGRAM SPECIFIC OUTCOMES ARE ASSESSED

Program Specific Outcomes (PSO) Level Proficiency

assessed by

PSO1 Professional Skills: An ability to understand the basic

concepts in Electronics & Communication Engineering and

to apply them to various areas, like Electronics,

Communications, VLSI in the design and implementation of

complex systems.

3

Lectures,

Assignments

PSO2 Problem-solving skills: An ability to solve complex

Electronics and communication Engineering problems, using

latest hardware and software tools, along with analytical

skills to arrive cost effective and appropriate solutions.

2

Tutorials

PSO3 Successful career and Entrepreneurship: An

understanding of social- awareness & environmental-

wisdom along with ethical responsibility to have a successful

career and to sustain passion and zeal for real-world

applications using optimal resources as an Entrepreneur.

3

Seminars and

Projects

1: Slight (Low) 2: Moderate (Medium) 3: Substantial (High) -: None

VII. SYLLABUS:

Unit – I

MOS Devices and Modeling The MOS Transistor, Passive Components- Capacitor &

Resistor, Integrated circuit Layout, CMOS Device Modeling - Simple MOS Large-Signal

Model, Other Model Parameters, Small-Signal Model for the MOS Transistor, Computer

Simulation Models, Sub-threshold MOS Model

Unit-II

Analog CMOS Sub-Circuits MOS Switch, MOS Diode, MOS Active Resistor, Current Sinks

and Sources, Current Mirrors-Current mirror with Beta Helper, Degeneration, Cascode

current Mirror and Wilson Current Mirror, Current and Voltage References, Band gap

Reference.

Unit-III

CMOS Amplifiers Inverters, Differential Amplifiers, Cascode Amplifiers, Current

Amplifiers, Output Amplifiers, High Gain Amplifiers Architectures.

Unit-IV

CMOS Operational Amplifiers Design of CMOS Op Amps, Compensation of Op Amps,

Design of Two-Stage Op Amps, Power- Supply Rejection Ratio of Two-Stage Op Amps,

Cascode Op Amps, Measurement Techniques of OP Amp.

Unit-V

Comparators Characterization of Comparator, Two-Stage, Open-Loop Comparators, Other

Open-Loop Comparators, Improving the Performance of Open-Loop Comparators, Discrete-

Time Comparators.

TEXT BOOKS:

1. CMOS Analog Circuit Design - Philip E. Allen and Douglas R. Holberg, Oxford University

Press, International Second Edition/Indian Edition, 2010.

2. Analysis and Design of Analog Integrated Circuits- Paul R. Gray, Paul J. Hurst, S. Lewis

and R. G. Meyer, Wiley India, Fifth Edition, 2010.


REFERENCES

1. Analog Integrated Circuit Design- David A. Johns, Ken Martin, Wiley Student Edn, 2013.

2. Design of Analog CMOS Integrated Circuits- Behzad Razavi, TMH Edition.

3. CMOS: Circuit Design, Layout and Simulation- Baker, Li and Boyce, PHI.

NPTEL Web Course/ Video Course:

1. https://nptel.ac.in/courses/117106030/

2. https://onlinecourses.nptel.ac.in/noc18_ee04

3. https://nptel.ac.in/content/syllabus_pdf/117106030.pdf

4. http://www.infocobuild.com/education/audio-video-

courses/electronics/AnalogICDesign-IIT-Madras/lecture-29.html

UGC-NET/GATE SYLLABUS

Energy bands in intrinsic and extrinsic silicon; Carrier transport: diffusion current, drift

current, mobility and resistivity; Generation and recombination of carriers; Poisson and

continuity equations; P-N junction, Zener diode, BJT, MOS capacitor, MOSFET, LED, photo

diode and solar cell; Integrated circuit fabrication process: oxidation, diffusion, ion

implantation, photolithography and twin-tub CMOS process.

VIII. COURSE PLAN (WEEK-WISE):

Lect

ure

No

.

Un

it N

o.

Dat

e

Top

ics

to b

e

cove

red

Lin

k fo

r P

PT

Lin

k fo

r P

DF

Lin

k fo

r

Smal

l P

roje

cts/

N

um

eric

als(

if

any)

C

ou

rse

lear

nin

g

ou

tco

mes

Teac

hin

g

Met

ho

do

log

y

Ref

eren

ce

1 I The MOS Transistor

https://drive.google.com/file/d/1TGi8eL64dzSNm9tyZf849TLJmy8fKOKs/view?usp=sharing

https://drive.google.com/file/d/17GL7Qhb4OKNYzyD7Bqn5RmojcbNBe35G/view?usp=sharing

To understand MOS device

Online platform, ppt, and video

T1,R2

2 Passive Components- Capacitor & Resistor, Integrated circuit Layout


https://drive.google.com/file/d/17GL7Qhb4OKNYzyD7Bqn5RmojcbNBe35G/view?usp=sharing

To understand passive devices


T1,R2

https://nptel.ac.in/courses/117106030/

https://onlinecourses.nptel.ac.in/noc18_ee04

https://nptel.ac.in/content/syllabus_pdf/117106030.pdf

http://www.infocobuild.com/education/audio-video-courses/electronics/AnalogICDesign-IIT-Madras/lecture-29.html

http://www.infocobuild.com/education/audio-video-courses/electronics/AnalogICDesign-IIT-Madras/lecture-29.html


3 CMOS Device Modeling

https://drive.google.com/file/d/1Oc3vIw_dNHLGCJfZLEpQjC99tJYSw1Sx/view?usp=sharing

https://drive.google.com/file/d/1ZH_TATBOmVuyEoEuKZkeWdAn_cZs4h9_/view?usp=sharing

To determine exact model of MOS


T1,R2

4 Simple MOS Large-Signal Model



To understand parameters based on large signal model


T1,R2

5 Numerical based on large signal model



To understand parameters based on large signal model


T1,R2

6 Small-Signal Model for the MOS Transistor



To understand parameters based on small signal model


T1,R2






























7 Sub-threshold MOS Model



To understand sub threshold mos model


T1,R2

8 Numerical based on Small signal MOS transistor


https://drive.google.com/file/d/1ksxNgN3AS5KuE8XbGQLAAHmtZh3n8v0E/view?usp=sharing

To analyze model


T1,R2

9 Numerical based on large signal model



To understand mos model


T2,R3

10 Numerical based on Sub threshold MOS model



To analyze sub threshold mos model


T2,R3









11 Modeling equation of MOS Level 1



To analyze model


T2,R3




To analyze model


T2,R3




To analyze model


T2,R3

14 Numerical based on large and small signal



To analyze model


T2,R3

MOCK TEST-1


II Unit-II

15 Unit –II MOS Switch, MOS Diode

https://drive.google.com/file/d/1QXuo4Df1_owmz4CFbFosFDWMdwgx6wev/view?usp=sharing

https://drive.google.com/file/d/1B4MDOIN-S-5EQxxzftBk5ZCCErVe8a_Y/view?usp=sharing

http://www.altera.co.kr/_hdl/2/RESOURCES/www.ee.ed.ac.uk/~gerard/Teach/Verilog/me5cds/me95chn0.html

To understand mos diode


T1,R3

16 MOS Active Resistor, Current Sinks and Sources

https://drive.google.com/file/d/1QXuo4Df1_owmz4CFbFosFDWMdwgx6wev/view?usp=sharing


To understand current sink using mos device


T1,R3

17 Current Mirrors-Current mirror with Beta Helper

https://drive.google.com/file/d/1BFUxmcS7NL2J-pam0CpGU0OQ3Dqs68Vu/view?usp=sharing

https://drive.google.com/file/d/18lmKp02UxSyu5b2qc49iE_EyCq5rSYyr/view?usp=sharing

To understand current mirror


T1,R3

18 BRIDGE CLASS 2


19 Degeneration, Cascode current Mirror and Wilson

https://drive.google.com/file/d/1BFUxmcS7NL2J-pam0CpGU0OQ3Dqs68

https://drive.google.com/file/d/1oDDWkVJEieSaic9wsqIAxTZzF4cCbovZ/view?us

To understand cascode current mirror


T1,R3


















Current Mirror,

Vu/view?usp=sharing

p=sharing

20 Current and Voltage References



To understand voltage reference circuit


T1,R3

21 BRIDGE CLASS 3

https://drive.google.com/file/d/1S1_ieRDf1hOkBJ8WhBgVx5U6ols1PrHQ/view?usp=sharing


22 Band gap Reference



To understand band gap reference circuit


T2,R3

23 Problem based on Current and Voltage References



To understand voltage reference circuit


T2,R3

24 Problem based on Voltage

https://drive.google.com/file/d/1S

https://drive.google.com/file/d/1o

To understand

Online platform, ppt, and

T2,R3


















reference 1_ieRDf1hOkBJ8WhBgVx5U6ols1PrHQ/view?usp=sharing

DDWkVJEieSaic9wsqIAxTZzF4cCbovZ/view?usp=sharing

voltage reference circuit

video

25 Problem based on Cascode current mirror


https://drive.google.com/file/d/1oDDWkVJEieSaic9wsqIAxTZzF4cCbovZ/view?usp=sharing

To understand cascode reference circuit


T2,R3

26 Problem based on Wilson current miror



To understand wilson circuit


T2,R3

27 Problem based on Current mirror



To understand current mirror circuit


T2,R3

28 BRIDGE CLASS 4

PPT Link


29 Problem based on Current sinks



To understand current sink using mos device


T2,R3


I Mid Examinations

30 III CMOS Amplifiers

https://drive.google.com/file/d/1vwA_N-K6iRrw-_m09jTovqiTu3wLk3qb/view?usp=sharing


To understand amplifier devices


T1,R5

31 Inverters, Differential Amplifiers



To understand differential amplifier


T1,R5

32 Cascode Amplifiers


https://drive.google.com/file/d/1NrV7PR6seOS3x1dBVqwW8ooifWg_JAJT/view?usp=sharing

To understand cascode devices


T1,R5
























33 BRIDGE CLASS 5



34 Numerical based on Cascode Amplifier



To analyze cascode devices


T1,R5

35 Numerical based on Differential Amplifier



To analyze differential amplifer devices


T1,R5
























36 Numerical based on amplifiers



To analyze differential amplifer devices


T1,R5

37 Current Amplifiers


https://drive.google.com/file/d/194HKunhpEzJ0zvkKea0L5d5WDrIEo1GP/view?usp=sharing

To analyze current amplifier


T1,R5

38 Output Amplifiers



To analyze output amplifier devices


T1,R2













39 High Gain Amplifiers Architectures



To analyze High gain devices


T1,R2

40 Numerical based on current amplifiers



To analyze current amplifier


T1,R2

41 IV Numerical based on High gain amplifiers



To analyze High gain devices


T1,R5


42 CMOS Operational Amplifiers

https://drive.google.com/file/d/1In7yHLR8LNuiXt9glk5thrZ4hqpr4ylB/view?usp=sharing

https://drive.google.com/file/d/1ijYG8aDh5-jg6Ctm9MMXkcXcGiUbLBqc/view?usp=sharing

To undestand cmos amplifier


T2,R3

43 Design of CMOS Op Amps



To understand cmos opamp


T2,R3

44 Compensation of Op Amps





T2,R3

45 Numerical based on Compensaion Op amps


https://drive.google.com/file/d/1mPpTcZHRgOOGo46cS_7eL-IXms0wER4U/view?usp=sharing



T2,R3


46 Design of Two-Stage Op Amps



To analyse opamp circuit based on cmos


T2,R3

47 Numerical based on two stage Op amps





T2,R3

48 Power- Supply Rejection Ratio of Two-Stage Op Amps





T2,R3

49 Numerical based on PSRR





T2,R3


50 MOCK TEST-2 https://drive.google.com/file/d/1In7yHLR8LNuiXt9glk5thrZ4hqpr4ylB/view?usp=sharing


51 BRIDGE CLASS 8


52 V Comparators https://drive.google.com/file/d/1H1HvHw-7DuwCdeJuficR-g6CqiLfWzLb/view?usp=sharing

https://drive.google.com/file/d/1hNgr2yfugmQ_Z4SxcjogMgZDW1W0kHjV/view?usp=sharing

To understand basic comparator design


T2,R2

53 Characterization of Comparator

https://drive.google.com/file/d/1H1HvHw-7DuwCdeJuficR-g6CqiLfWzLb/view?usp=sharing


To analyse characteristic of comparator


T2,R2


54 Two-Stage comparator



To understand two stage opamp


T2,R2

55 Open-Loop Comparators



To understand open loop comparator


T2,R2

56 Other Open-Loop Comparators



To understand open loop comparator


T2,R3

57 Improving the Performance of Open-Loop Comparators

https://drive.google.com/file/d/1H1HvHw-7DuwCdeJuficR-

https://drive.google.com/file/d/1hNgr2yfugmQ_Z4SxcjogMgZDW1W0kH

To analyze performance of open loop comparator


T2,R3


g6CqiLfWzLb/view?usp=sharing

jV/view?usp=sharing

58 Numerical based on open loop comparator



To analyze performance of open loop comparator


T2,R2

59 Numerical based on two stage comparator



To analyze performance of comparator


T2,R3

60 Discrete-Time Comparators



To understand discrete comparator


T2,R3

MID EXAM II


II Mid Examinations

IX. MAPPING COURSE OUTCOMES LEADING TO THE ACHIEVEMENT OF PROGRAM

OUTCOMES AND PROGRAM SPECIFIC OUTCOMES:

Course

Outcomes Program Outcomes Program Specific

Outcomes

PO1 PO2 PO3 PO

4 PO

5 PO6 PO7 PO8 PO9 PO1

0 PO11 PO1

2 PSO1 PSO2 PSO3

CO1 3 3 2 2 2 2 2 2 2 2 2 2 2 1 2

CO2 3 2 2 2 2 3 2 3 2 2 3 2 3 1 3

CO3 2 3 3 3 3 2 3 2 3 3 2 3 3 1 2

CO4 2 3 2 2 2 2 2 2 3 3 2 3 2 1 2

CO5 3 2 3 3 3 3 3 3 3 3 3 2 2 1 3

CO6 3 2 3 3 3 3 3 3 2 2 3 3 3 1 3

1: Slight (Low) 2: Moderate (Medium) 3: Substantial (High) -: None

QUESTION BANK (JNTUH)

UNIT I

Long Answer Questions S. No

Question Blooms

Taxonomy

Level

Course

Outcome

1 Explain the structure and behaviour of MOS Structure. Apply

2

2 Explain active and passive components. How capacitor and resistors

are fabricated in ICs

Apply 1

3 Discuss the importance of Stick diagram in the Integrated circuit

Layout

Apply 1

4 Give the detail information about the large scale modeling of CMOS

circuits.

Apply 2

5 Give the detail information about the small scale modeling of MOS

circuits.

Apply 1

6 What do you mean by sub-threshold model of the MOS Devices Apply 1


Short Answer Questions

S.

No.

Question Blooms

Taxonomy

Level

Course

Outcome

1 Compare between CMOS and bipolar technologies. Understand 1

2 What are the uses of Stick diagram? Understand 2

3 Why NMOS technology is preferred more than PMOS technology?? Knowledge 2

4 What are the different MOS layers? Knowledge 2

5 What are the different operating regions foe an MOS transistor? Understand 2

6 Define Threshold voltage in CMOS? Understand 1

7 Give the basic inverter circuit. Knowledge 2

8 What is Latch – up? Understand 2

9 What is Body effect? Understand 2

10 .Define Threshold voltage in CMOS? Understand 2

UNIT II

Long Answer Questions

S.N

o

Question Blooms

Taxonomy

Level

Course

Outcome

1 What do you mean by MOS device as a switch. Explain in detail. Understand 3

2 Discuss about the diode connected mode of the MOS device. Understand 2

3 How MOS active resistors are designed and fabricated on the ICs. Understand 3

4 Explain about the current source and current sink concept in detail. Understand 2

5 Discuss the concept of Current Mirrors. Explain the basic principal. Apply 2

6 Discuss the use of Beta helper circuit in the current mirror. Discuss

the basic operating

Understand 2

7 Discuss about the degeneration in the current mirror circuits. Understand 2

8 Discuss about the Cascode current Mirror and Wilson Current Mirror Understand 2

9 What are the basic band gap reference materials. Discuss in detail. Understand 2

10. What is Current Mirror. Explain the general properties of current

mirrors with block diagram.

Knowledge 2


S.N

o

Question Blooms

Taxonomy

Level

Course

Outcome

1 Discuss about Band gap references. Knowledge 2

2 Explain about current sink and current sources Knowledge 3

3 Design a CMOS current mirror load differential amplifier. Knowledge 3


4 Explain in details the MOS cascode current mirror with necessary

equations.

Understand 2

5 Explain the difference between cascade current mirror and Wilson

current mirror.

Understand 3

UNIT III


S.

No

Question Blooms

Taxonomy

Level

Course

Outcom

e

1 Discuss the basic principal of a inverter circuit. Apply 3

2 Discuss the CMOS interver in detail with the explanation of VTC. Knowledge 3

3 Discuss about the various differential amplifiers in detail. How inverter

is useful in the designing of Differential amplifiers.

Knowledge 2

4 What do you mean by Cascode amplifier? Discus its advantages over

other amplifiers.

Apply 3

5 Discuss the basic operating principle of the Current amplifiers with

suitable examples.

Apply 3

6 Discuss about the various output amplifiers in detail. Understand 3

7 Discuss in detail about the High Gain Amplifiers Architectures. Knowledge 2


S.

No

Question Blooms

Taxonomy

Level

Course

Outco

me

1 Perform the analysis of CMOS differential amplifiers Knowledge 2

2 Explain the various architectures of high gain amplifiers Apply 3

3 Briefly explain the differential amplifiers.With necessary equation give

the large signal analysis of CMOS differential amplifiers.

Understand 3

4 What is a current amplifier and perform the low frequency analysis of a

single ended current amplifier.

Apply 3

5 Derive the voltage gain expression of a cascade amplifier and discuss

about location of poles and zeros.

Knowledge 2

6 What is a current amplifier and perform the low frequency analysis of a

single ended current amplifier.

Understand 4


UNIT IV


S.

No

Question Blooms

Taxonomy

Level

Course

Outco

me

1 Discuss the basic principle of CMOS Operational Amplifiers. Understand 4

2 Discuss the basic terminology for the Design of CMOS Op Amps, Apply 4

3 Discuss the different Compensation techniques used for Op Amps. Understand 3

4 Discuss the basic steps of designing of Two-Stage Op-amps. Knowledge 4

5 Discuss about the different Measurement Techniques of OP Amp. Understand 4

6 How to measure Power- Supply Rejection Ratio of Two-Stage Op

Amps. Discuss in detail.

Knowledge 4

7 Discuss the basic concept of designing of Cascode Op Amps. Understand 5

8 Discuss about Miller compensation technique in op-amps Knowledge 3


S.

No

Question Blooms

Taxonomy

Level

Course

Outco

me

1 Discuss about the various types of comparators with suitable examples. Knowledge 2

2 Discuss about the different parameters for the Characterization of

Comparator.

Knowledge 3

3 Discuss about the basics of Two-Stage, Open-Loop Comparators. Knowledge 3

4 How the Performance of Open-Loop Comparators can be improved.

Discuss the various techniques used for the same.

Understand 3

5 Discuss the basic concepts of Discrete-Time Comparators. Where

Discrete-Time Comparators are used.

Knowledge 2

6 Explain any one of the concept of compensation of two stage CMOS

Op-Amp

Understand 4

7 Discuss about the cascade op-amp. Knowledge 3

8 With neat sketch explain the following

a) Characteristics of Op-Amp

b) Classification of Op-Amp

Understand 4

9 Derive the expression for power-supply rejection ratio of Two-stage

op-amps

Knowledge 3

10 Explain the Measurement technologies of Op-amp Understand 4


UNIT V

Long Answer Questions:

S.No. Question Blooms

Taxonomy

Level

Course

Outcome

1. Explain the auto zeroing concept of improving the

performance of a comparator.

Remember 1

2.

Explain the following terms with neat sketch.

a) Switched capacitor comparators

b) Regenerative comparators

Remember 1

3. Explain about Switched Capacitor Comparators Apply 1

4.

With neat sketch and necessary equations explain the

Design aspect of a two stage open loop comparator for

slewing response.

Remember 1

5. Explain about the different types of Open loop

comparator.

Understand 1

6. Discuss various types of open loop comparators. Understand 1

7. Explain the rising propagation time delay for a single

pole comparator.

Analyze 1

8. Define the minimum input voltage to the comparator

with mathematical expression.

Understand 1

9.

Find the propagation delay time of an open loop

comparator, that has a dominant pole at 103 radian/sec

dc gain of 104 and binary output voltage swing of 1V.

Assume the applied input voltage is 10mV.

Remember 1

10. Define the static and dynamic characteristic of open

loop comparators.

Understand 1

11. Draw the circuit of single stage dominant pole

comparator and write dominant pole expression.

Understand 1

12.

Explain maximum and minimum output voltage in open

loop comparator and explain the linear step response of

the two stage comparator.

Remember 1

Short Answer Questions:

S.No. Question Blooms

Taxonomy

Level

Course

Outcome

1. Define the input offset voltage of a comparator Understand 1

2. Define the comparator noise and Rms noise Understand 1


3. Explain dominant single pole in linear frequency

response of comparator.

Remember 1

4. Explain propagation time delay in dynamic characteristic

of comparator.

Understand 1

5. Explain the dominant pole in comparator. Remember 1

6. Draw the folded cascode comparator, and explain gain

and slew rate.

Evaluate 1

7. How to define the performance of the two stage open

loop comparator.

Remember 1

8. How to improve the speed in two stage compartor. Understand 1

9. Explain the finite and infinite gain in comparator. Understand 1

10. Explain the Input common mode range (ICMR) of

comparator.

Understand 1

OBJECTIVE QUESTIONS:

UNIT-I 1. conductivity of the pure silicon is raised by :

a) Introducing Dopants (impurities) b) Increasing Pressure c) Decreasing Temperature

d) Deformation of Lattice

2. The n-type semiconductor have _______ as majority carriers :

a) Holes b) Negative ions c) Electrons d) Positive ions

3. The majority carriers of p-type semiconductor are :

a) Holes b) Negative ions c) Electrons d) Positive ions

4. The n-MOS transistor is made up of:

a) N-type source, n-type drain and p-type bulk b) N-type source, p-type drain and p-

type bulk

c) P-type source, n-type drain and n-type bulk d) P- type source, p-type drain and n-

type bulk

5. The oxide layer formed in the MOSFET is :

a) Metal oxide b) Silicon dioxide c) Poly Silicon oxide d) Oxides of Non

metals

6. The drain current is varied by:

a) Gate to source voltage b) Gate current c) Source Voltage d) None of the

mentioned

7. he low voltage on the gate of p-MOSFET forms :

a) Channel of negative carriers b) Channel is not formed c) Channel is clipped d)

Channel of positive carriers

8. The n-MOSFET is working as accumulation mode when:

a) Gate is applied with positive voltage b) Gate is grounded

c) Gate is applied with negative voltage d) Gate is connected to source


9. In negative logic convention, the Boolean Logic [1] is equivalent to:

a) +VDD b) 0 V c) –VDD d) None of the mentioned

10. In positive logic convention, the true state is represented as:

a) 1 b) 0 c) -1 d) -0

11. In CMOS logic circuit the n-MOS transistor acts as_________

12. In CMOS logic circuit the p-MOS transistor acts as__________

13. When both nMOS and pMOS transistors of CMOS logic design are in OFF condition, the

output is____

14. When both nMOS and pMOS transistors of CMOS logic gates are ON, the output is

_____

Unit-II

1. Which among the following serves as an input stage to most of the op-amps due to its

compatibility with IC technology?

a. Differential amplifier b. Cascode amplifier

c. Operational transconductance amplifiers (OTAs) d. Voltage operational amplifier

2. PSSR can be defined as the product of the ratio of change in supply voltage to change in

output voltage of op-amp caused by the change in power supply & _______ of op-amp.

a. Open-loop gain b. Closed-loop gain c. Both a and b d. None of the above

3. According to the principle of current mirror, if gate-source potentials of two identical

MOS transistors are equal, then the channel currents should be _______

In two-stage op-amp, what is the purpose of compensation circuitry?

a. To provide high gain b. To lower output resistance & maintain large signal

swing

c. To establish proper operating point for each transistor in its quiescent state

d. To achieve stable closed-loop performance

4. An ideal op-amp has ________

5. In MOS devices, the current at any instant of time is ______of the voltage across their

terminals.

6. Which among the following is/are regarded as an/the active resistor/s_____

7. In MOS switch, clock feedthrough effect is also known as __________

8. Which among the following can be regarded as an/the application/s of MOS switch in an

IC desin?

a. Multiplexing & Modulation b. Transmission gate in digital circuits c. Simulation of a

resistor d. All of the above

10. PSSR can be defined as the product of the ratio of change in supply voltage to change in

output voltage of op-amp caused by the change in power supply & _______ of op-amp.

a. Open-loop gain b. Closed-loop gain c. Both a and b d. None of the above

Unit-II

1. The input output characteristic of an amplifier is :

a) Linear function b) Non Linear function c) Sinusoidal function with change of phase

d) None

2. The amplifier works as a linear system for:

a) High frequency signals b) Low frequency signals c) Small signals d) Large signals


3. In MOSFET amplifier, the input is applied as:

a) Voltage across gate and source b) Voltage across drain and source

c) Current at gate d) Current at Drain

4. In MOSFET amplifier, the parameter that changes due to the changes in input is:

a) Small signal drain current b) Large signal drain current

c) Voltage across substrate and source d) None of the mentioned

5. Input impedance of MOSFET amplifier in Common Source configuration is :

a) Very high at high frequencies b) Very high at low frequencies

c) Very low at high frequencies d) Very low at low frequencies

6. The voltage gain of the MOSFET is given by:

a) Av = -βRd b) Av = γRd c) Av = -gmRd d) None of the

mentioned

7. The MOSFET is said to be in diode connected configuration if:

a) A diode is placed between supply and drain b) A diode is placed between source and

ground

c) Source and gate are connected d) Drain and gate are connected

8. The diode connected MOSFET acts as:

a) Active element for amplification b) Voltage source c) Current Source d) Load

Impedance

9. The advantage of using source degeneration resistor in Common source amplifier is to

provide________________

10. A common-source amplifier is similar to which BJT amplifier?

11. When transistor is operated in cut-off and saturation, it acts like a_____

12. Movement of free electrons in semi conductive material is called______

13. A MOSFET is different from JFET because_____

14. Process of linearly increasing amplitude of an electrical signal is known as____

Unit-IV

1. In which of the following are operational amplifiers (op-amps) used?

a. Oscillators b. Filters c. Instrumentation circuits d. All of the above

2. In which of the following operations is the resulting output signal of the differential

amplifier near zero?

a. Single-ended b. Double-ended c. Common-mode d. None of the above

3. What is the level of the current through the amplifier input(s) to ground in an op-amp?

a. Virtually zero b. 1.7 mA c. 2.8 mA d. 3.3 mA

4. What is the scale multiplier (factor) of a basic integrator?

a. R/C b. C/R c. –RC d. –1/RC

5. In which of the following operations is the resulting output signal of the differential

amplifier near zero?

a. Single-ended b. Double-ended c. Common-mode d. None of the above


6. In the differential amplifier circuit, which of the following terminals are connected

together?

a. Bases b. Collectors c. One base to another collector d. Emitters

7. Which of the following circuits is referred to as a BiMOS circuit?

a. Bipolar and FET b. Bipolar and MOSFET c. Opposite-type MOSFETs d. None of

the above

8. An IC unit made using both _______ and _______ transistors is called a _______ circuit.

a. bipolar, MOSFET, BiFET b. bipolar, MOSFET, BiMOS c. TTL, MOSFET, TailFET d.

TTL, BiFET, BiMOS

9. What is the level of the voltage between the input terminals of an op-amp?

a. Virtually zero b. 5 V c. 18 V d. 22 V

10. What is the level of the current through the amplifier input(s) to ground in an op-amp?

a. Virtually zero b. 1.7 mA c. 2.8 mA d. 3.3 mA

11. If Rf = R1’, the voltage gain is ________.

12. What is the voltage gain of the unity follower?

a. 0 b. 1 c. –1

13. What is the scale multiplier (factor) of a basic integrator___

14. The summing amplifier contains an inverting amplifier____

15. What is the level of the roll-off in most op-amps____

Unit-V

1. The special designed comparators are compatible with

a) RTL b) MOS Logic c) TTL d) All of the mentioned

2. Response time of comparators is defined as

a) Time interval between input and output crossing upper threshold voltage

b) Time interval between input and output function

c) Time interval between input and output crossing threshold logic

d) Time interval between input and output crossing lower threshold voltage

3. The voltage level at which the comparator saturated by a differential input equal to

greater than a specified voltage is called

a) Zero output level b) Positive output level c) Negative output level d) All of

the mentioned

4. When the logic level of strobe output is at zero, then the output current is called

a) Strobe terminal current b) Strobe current c) Strobe threshold current d)

Strobe bias current

5. The strobe release time is defined as

a) Time required for output to rise to logic threshold


b) Time required for input to rise to logic threshold

c) Time required for output to rise to zero logic

d) Time required for output to rise to one logic

6. Which of the following comparator can operate from ±15 to down to +5v supply in op-

amp?

a) µA741 b) µA311 c) µA351 d) All of the mentioned

7. Find the comparator that has slow response time

a) LM1414 b) µF311 c) ICL8001 d) None of the mentioned

8. Why ICL8001 op-amp comparator is preferred for most applications?

a) Low power consumption b) High response time c) High input current d)

Balanced input offset voltage

9. Which op-amp is preferred for application like high speed A-D converter and zero

crossing detector.

a) ICL8001 b) LM1414 c) µA311 d) µA670

10. Response time of comparators is defined as_____

11. he voltage level at which the comparator saturated by a differential input equal to greater

than a specified voltage is called___

12. When the logic level of strobe output is at zero, then the output current is called___

13. The strobe release time is defined as________

14. From which category ‘Sigma comparator’ belongs______

15. Which colour of light is filtered by filter present in Zeiss Ultra-optimeter____

XIII. WEBSITES:

a. https://nptel.ac.in/courses/117106030/

b. https://ieeexplore.ieee.org/document/34152/

c. https://www.researchgate.net/publication/36371504_Analog_CMOS_integrated_circuit_d

esign

d. https://www.radioeng.cz/fulltexts/2018/18_01_0171_0185.pdf

e. https://link.springer.com/article/10.1007/s10470-019-01574-z

f. http://www.cmosedu.com/jbaker/courses/ece5411/f08/lec5411.htm

g. http://www.ee.iitm.ac.in/~ani/2013/ee5390/lectures.html

Books Written

1. “CMOS Analog Circuit Design - Philip E. Allen and Douglas R. Holberg, Oxford

University Press, International Second Edition/Indian Edition, 2010.

2. Analysis and Design of Analog Integrated Circuits- Paul R. Gray, Paul J. Hurst, S.Lewis

and R. G. Meyer, Wiley India, Fifth Edition, 2010.

3. Analog Integrated Circuit Design- David A. Johns, Ken Martin, Wiley Student Edn,

2013.

4. Design of Analog CMOS Integrated Circuits- Behzad Razavi, TMH Edition.

5. CMOS: Circuit Design, Layout and Simulation- Baker, Li and Boyce, PHI.

XIV. EXPERT DETAILS:

Dr. Raj Senani

Professor Emeritus

Electronics and Communications Engineering

Netaji Subhas University of Technology, Delhi, [email protected]

XV. JOURNALS:

International

https://nptel.ac.in/courses/117106030/

https://ieeexplore.ieee.org/document/34152/

https://www.researchgate.net/publication/36371504_Analog_CMOS_integrated_circuit_design

https://www.researchgate.net/publication/36371504_Analog_CMOS_integrated_circuit_design

https://www.radioeng.cz/fulltexts/2018/18_01_0171_0185.pdf

https://link.springer.com/article/10.1007/s10470-019-01574-z

http://www.cmosedu.com/jbaker/courses/ece5411/f08/lec5411.htm

http://www.ee.iitm.ac.in/~ani/2013/ee5390/lectures.html

mailto:[email protected]


1. Analog Integrated Circuits and Signal Processing, springer.

2. International Journal of Electronics, Taylore & Francis.

3. Nanoscale CMOS Technologie, MDPI Journal.

4. Microelectronic Engineering, Elsevier

5. International Journal of Bio-Inspired Computation, Inderscience

analog cmos ic design (professional elective – vi)

Documents

Transcript of analog cmos ic design (professional elective – vi)