TTL & CMOS Logic Levels

Noise Immunity

• The noise immunity of a logic circuit refers

to the circuits ability to tolerate noise

without causing spurious change in the

output voltage

• A quantitative measure of noise immunity is

called noise margin as shown in fig

Power Requirement

ICC (avg) = (ICCH + ICCL) /2

PD (avg) = ICC (avg) × VCC

Power Requirement

Speed Power Product (SPP)

• A common means for measuring and comparing

the overall performance of an IC family is SPP

• 10 ns × 5mW = 50 × 10-12 watt-second

= 50 picojules (pJ)

Current Sourcing and Current Sinking Action

Current Sourcing and Current Sinking Action (Fan in & Fan Out)

Numerical Example

Resistance Transistor Logic (RTL)

2-Input NOR gate using RTL

SR Flip Flop by Cross Coupling Two-NOR gates in RTL Family

Complete Circuit of TTL Gate (Inverter)

Analysis when Input is High

Analysis when Input is Low

TTL NAND Gate

TTL NOR Gate

TTL AND-OR-INVERT GATE

Tri-State TTL Gate

AND-OR-INVERT (AOI) Gate

Schottky Transistor

SCHOTTKY TTL NAND Gate

Tristate TTL Inverter

A

Enable

(a) Open Collector TTL Circuit (b) With External Pull-up Resister

Wired AND Operation using Open Collector Gates

An Open Collector buffer/Driver drives a High-Current, High-Voltage Load

(a) An Open Collector Output can be Used to drive an LED Indicator

(b) An Open-Drain CMOS Output

Basic ECL Circuit

Basic ECL Circuit with addition of Emitter Follower

ECL/ Current Mode Logic Emitter

• Logic levels are -1.7 V (Logic 0) and -.8 (Logic 1)

• Emitter follower performs two functions

• Subtract 0.8 volts from Vc1 and Vc2 to bring at

correct levels

ECL OR/NOR Circuit Logic Symbol

ECL Characteristics• Propagation delays of 500 ps (Some Devices 100 ps

at an average power of 5 mW)

• Transistor never saturates, switching speed is very

high. Typical Propagation delay is 365 ps

• Logic levels are -1.7 V (Logic 0) and -.8 (Logic 1)

• Worst case ECL noise margins are apprx. 150 mW

• Low noise margins make ECL somewhat unreliable

for use in heavy industrial environment

• ECL logic block produces o/ps & its complement

Vout1 = Vin & Vout2 = Vin (no need of invertor)

• Provides low o/p impedance (7Ω) to give large

fan-out (25) fast charging of load capacitance

• Power dissipation is 25 mW (higher than 74ALS)

• Current flow in ECL remains constant. Thus no

noise spikes are generated as in TTL & CMOS

• ECL doesn't include wide range of general

purpose devices as TTL or CMOS families

• Low noise margin

• High power drain

• Negative power supply

• ECL does include Complex special purpose ICs used in applications such as

• High speed data transmission

• high speed memories

• High speed arithmetic units

Demerits of ECL Family

Applications of ECL Family

Pseudo NMOS Logic Inverter

CMOS Transmission Gates as switches

Realization of a Two-to-one line Multiplexer using

PTL

Pass-Transistor Logic (PTL) Circuit Examples

Realization of a Exclusive-OR function using PTL

A PTL Gate utilizing both input variables and their

compliment. This type of circuit is known as CPTL. Here

both the o/p function and its Compliment are generated

Level Restorer Circuit

BiCMOS DIGITAL CIRCUITS

A BiCMOStwo-input NAND gate

Basic Structure of Dynamic-MOS Logic Circuits

Waveform of the Clock needed to operate the Dynamic-Logic Circuit

An Example Circuit

UNIT 4• DAC SPECIFICATIONS

Resolution / (%age Resolution) • Minim change in the o/p as change in digital I/N• %age Resolution of DAC depends No. of Bits• A 10 bit DAC has finer resolution than 8-bit DAC

ACCURACYFull Scale Error & Linearity Error

• Maximum Deviation of DAC O/P from its Ideal value. Expressed as %age of Full Scale O/P (% F.S)

.01 % (Accuracy ) x 9.375 V (F.S. O/P) = ±0.9375 mV

• Linearity Error• Offset Error• Settling Time• Monotonicity

DAC APPLICATIONS• CONTROL To control Speed Temp etc• AUTOMATIC TESTING• SIGNAL RECONSTRUCTION (SIGNAL DIGITIZING

AND RECONSTRUCTING)In DSO, Digital Audio & Video Recording, Audio Compact Disc System

• A/D CONVERSION• DIGITAL AMPLITUDE CONTROL

To control volume of an Audio System or Amplitude of a Function Generator

DIGITAL RAMP ADC

SAC

Three Bit Flash A/D Converter

Truth Table of 3-Bit Flash A/D Converter

Simplified Diagram of a Sample-and-Hold Circuit

To ADC Input

Continuous Conversion DVM Using a Digital-

Ramp ADC

Waveform for a DVM