R. E. JENKINS

I

Advanced Spacecraft Technology Program

Robert E. Jenkins

nsight is given into the APL Space Department’s Advanced Technology DevelopmentProgram for spacecraft. After 40 years in the business of developing spacecraft, new technologyand new methods entailing risk are still the lifeblood of the Laboratory’s contributions to thenational space program. Today’s political environment concerning the use of new techniquesin spacecraft and how we have come to that environment are briefly described. The underlyingtechnical thinking behind our current efforts is presented, with an emphasis on what we aredoing and why (rather than the details of how), and where these activities may lead us in thefuture. These efforts include scalable architectures, miniaturization, custom integrated circuits,spacecraft autonomy, and ultra-low-power electronics. (Keywords: Advanced spacecraft archi-tectures, Spacecraft autonomy, Spacecraft miniaturization, Spacecraft technology.)

CHANGING POLITICAL ENVIRONMENTSince the inception of the space age in 1958, when

APL first became involved in spacecraft developmentthrough the Navy Navigation Satellite Program, newtechnology development has been the primary focus ofthe world’s aerospace engineers. It’s easy to understandwhy. Spacecraft are mankind’s most sophisticated ro-bots, undergoing stressful vibrations during launch, andthen being expected to operate for years in an environ-ment that is not very friendly. Unshielded by the Earth’satmosphere and magnetic field, spacecraft are bom-barded by intense ultraviolet radiation that erodesorganic materials and by cosmic rays and energeticprotons and electrons from the Sun that wreak havocon silicon-based electronics. The structure is subjectedto temperature extremes as large as any environmenton Earth. For a low-Earth orbiter, communicationwith the ground is limited to windows of 15 minutesor so as the spacecraft whips by the ground station a

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few times a day. And for an interplanetary mission,round-trip communication times needed to simply es-tablish a connection can easily exceed 30 minutes. Ifanything onboard a spacecraft gets “hosed,” we cannotmerely sigh and hit control-alt-delete. Reliability anda high level of autonomy are at a premium with eventhe simplest spacecraft mission.

In the early days of space endeavors (the first decadeor so), the pressure of these difficulties to a large extentdrove the activities. Everyone understood what Presi-dent Kennedy meant when he said, “We will do thesethings not because they are easy, but because they arehard.” The government was willing and able to pourmoney into difficult missions in space, and a high levelof failure was understood and accepted. Whole missionswere sometimes undertaken just to prove that someproposed technology would work in a space environ-ment. During this period, the methods and engineering

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practices, as well as space-qualified materials, mecha-nisms, and instrumentation were developed to makespace ventures doable with a reasonably high degree ofsuccess, albeit at great expense by most standards.

These cost pressures led to a second phase in whichnew technology became less important than the successof the space missions. Since it could be argued that theaerospace industry now knew how to develop workablespacecraft, ever larger missions were conceived to ac-complish more and more per spacecraft launch. As thecost of these large and complex spacecraft skyrocketed,the space program became highly politicized and theenvironment generally shifted to paranoia about a fail-ure. The leadership for space missions at the timebecame deeply instilled with the culture of risk avoid-ance as opposed to risk mitigation; i.e., “Don’t tryanything new on my program. I have a schedule tomeet.” The level to which this environment extendedbegan to trouble many aerospace leaders, who wereconcerned that new capabilities were not being devel-oped quickly enough to meet the space challenges theyforesaw. They understood that the surface of potentialendeavors in space had barely been scratched.

This concern was epitomized in the late 1980s at anAIAA workshop in which the author was an invitedparticipant. The workshop examined possible ways toameliorate the “advanced technology bottleneck” thatpervaded the U.S. space program. One strong recom-mendation was to move toward a series of small missionsto accomplish the same goals that were being attemptedby very large, billion dollar missions. In a series of five$200 million missions, we could afford to have one (oreven two) fail and still achieve a good measure of suc-cess. With this much allowable risk, there would beelbowroom for trying many new advances.

As might be expected, the government didn’t in-stantly jump to implement the workshop’s suggestion.Nevertheless, the ensuing series of events in the early1990s rapidly drove them to the point where they sim-ply could no longer afford the big missions. With cur-rent federal budgets, NASA and DoD are struggling tokeep their space programs alive. In recent years, gov-ernment leaders pronounced that to meet the crisis ofbudget shrinkage they would undertake smaller mis-sions and would rely on new and innovative technologyto accomplish what once was done through large gov-ernment expenditures. Voila! A destination reached byany road is the same destination.

We are now in the early stage of an era in whichadvances in space technology are exceedingly impor-tant to our ability to further investigate and understandspace and apply that knowledge to societal needs.Performing difficult missions like the exploration ofMercury and Pluto with the limited public moneys nowavailable for such ventures requires very high-tech

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ADVANCED SPACECRAFT TECHNOLOGY PROGRAM

solutions and a good deal of innovation in the engineer-ing process.

At the same time, “standard” space technology hasmatured to the point where commercial investment inspace-based assets is now practical. Even a midsizedcompany can raise the $40 million or so needed tosuccessfully build and launch a small spacecraft, andlarge corporations are actively investing on the orderof $1 billion to put up large constellations. Commercialspace investment applying standard technology (devel-oped and paid for by the government during the pre-vious 30 years) is now larger than government spendingin unmanned space and is projected to swamp govern-ment spending in the future.1,2 The current environ-ment thus presents an interesting dichotomy in termsof opportunities: The application of tried and true, yetrelatively high-tech methods is leading to enormouscommercial spacecraft activity, while difficult missions(e.g., the exploration of other bodies in the solar sys-tem) are still quite risky and require new approaches tokeep costs low.

Throughout these various eras, APL has been in thethick of things, credited with an impressive number ofnew ideas and approaches that were engineering “firsts”in space3 (see the boxed insert). During the middle,more conservative era, APL was more successful thanmost in pushing new space methods into practice,concentrating on small, one-of-a-kind, difficult mis-sions requested by our sponsors that nearly always re-quired innovation to keep costs low and schedulesshort. This experience is precisely what is now neededin the government’s space ventures, and the SpaceDepartment has been aggressively pursuing new space-craft technology that will enable seemingly unafford-able new space missions, either by reducing costs or byallowing what is currently not technically feasible.

APL’S ADVANCED TECHNOLOGYPROGRAM PHILOSPHY

For efficiency of approach, the Laboratory has ad-hered to a few fundamental unifying themes in its ad-vanced space technology efforts that serve to glue itsprojects together and provide a necessary framework.These themes characterize the Space Department’sAdvanced Technology Development (ATD) Programfor spacecraft, and distinguish it from efforts in otherorganizations. Each theme will be discussed with a de-scription of some of the supporting work at APL overthe past few years. To stay within reasonable bounds,I have limited the discussion to the work associatedwith advanced spacecraft development. There are oth-er components to our ATD effort such as advancedspace instruments and space system applications thatare not included here.

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APL SPACE FIRSTSLaunch Date Innovation Spacecraft

25 Aug 1997 First 24-h/day real-time space weather, from L1 ACE24 Apr 1996 First hyperspectral sensor in space MSX

Closed-loop spacecraft pointing at targetsFirst real-time tracking of satellites from space

17 Feb 1996 First hemispherical resonant gyro in space NEARFirst solar-powered spacecraft beyond Mars orbitMost distant man-made object seen from Earth

5 Sep 1986 First space intercept of an accelerating target Delta-18012 Mar 1985 Bifilar helix antenna Geosat-A

May 1994 First issuance of Announcement of Opportunity electronically (Internet) NEAR16 Jul 1982 Autonomous satellite navigation by tracking GPS (GPSPAC R/PA) Landsat-D30 Oct 1979 First attitude and command systems using microprocessors Magsat

“Aerotrim” boom to counter aerotorques in low-Earth orbit27 Jun 1978 Quadrifilar helix antenna with beam shape to compensate for slant range Seasat

Synthetic aperture radar downlink27 Jun 1978 First microprocessor system in space Seasat Altimeter27 Jun 1977 Satellite-to-satellite tracking by Doppler signals (NAVPAC) 1977 56A12 Oct 1975 Crystal oscillator with all drift removed by programmable synthesizer TIP-II

First use of pulsed plasma microthrusters in spaceWorldwide time synchronization to 40 ns from a single satellite

7 May 1975 Delayed command system SAS-C 9 Apr 1975 First satellite-to-satellite tracking GEOS-C2 Sep 1972 First satellite compensated for drag and radiation pressure Triad

Single-frequency refraction-free satellite navigationQuadrifilar helix antenna

12 Dec 1970 Dual-spin control of satellite pointing SAS-A11 Jan 1968 Heat pipes for spacecraft thermal design GEOS-B

1 Jul 1967 First yaw stabilization of a satellite using pitch axis wheel DODGE29 Nov 1965 Magnetic spin/despin system DME-A

6 Nov 1965 First integrated circuits in space GEOS-AFirst heat pipes in spacecraft

16 Jun 1963 Gravity gradient stabilization Transit 5A-3Automatic temperature control of spacecraft

19 Dec 1962 First uplink authentication system Transit 5A-131 Oct 1962 Sublimation switches ANNA-1B

First gallium arsenide solar cell experiment15 Nov 1961 Damping of satellite libration by lossy spring-and-mass TRAAC15 Nov 1961 Spacecraft spin imparted by solar pressure vanes Transit 4-B29 Jun 1961 First nuclear power supply in a spacecraft Transit 4-A

First triple-satellite launch21 Feb 1961 First satellite electronic memory Transit 3-B22 Jun 1960 First dual-payload launch Transit 2-A13 Apr 1960 Two-frequency method for correcting ionospheric error Transit 1-B

First attitude-controlled spacecraft using permanent magnetsSolar attitude detectorsHysteresis damping of satellite libration

17 Sep 1959 Yo-yo despin mechanism Transit 1-A(1958) Development of satellite Doppler Navigation System —

4 Oct 1957 Satellite tracking by Doppler Sputnik-1

ACE = Advanced Composition Explorer; MSX = Midcourse Space Experiment; NEAR = Near Earth Asteroid Rendezvous; GPCPACR/PA = Global Positioning System Package Receiver/Processor Assembly; NAVPAC = Navigational Package; TIP = Transit ImprovementProgram; SAS = Small Astronomy Satellite; GEOS = Geodetic Earth Orbiting Satellite; DODGE = DoD Gravity Gradient Experiment;ANNA = Army, Navy, NASA, Air Force; TRAAC = Transit Research and Attitude Control.

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The author adds the following caveat: The funda-mental approaches described in this article are notunique. Other organizations have worked on differentapproaches, and within APL—as might be expected ina high-caliber technical organization—there are differ-ing opinions on how future spacecraft development canbest be improved. Nevertheless, after intense internalreview and discussion, the approaches highlighted inthe following sections have emerged as our framework.As the Program Manager for all of the Space Depart-ment’s ATD programs, I can truly say that once ourdirection was set, everyone pulled together to supportthe effort in a manner that belies any controversy.Many people in both the Technical Services Depart-ment (TSD) and Space Department have contributedto the work, and a more detailed acknowledgment isincluded at the end of the article.

Scalable ArchitectureOne key to major cost savings is the level of reuse

that can be achieved in spacecraft design. A seductivesolution to cost reduction is the concept of a universalspacecraft bus, a standard spacecraft shell whose designis frozen and can be used continually by having instru-ments or other mission-specific packages attached forthe ride. This approach has never really worked verywell because each bus resource, such as power or datastorage, must be overdesigned to handle all possiblemissions. This eliminates the possibility of systems-level trade-offs of the precious onboard resources toachieve mission goals with a minimal launch weight,the easiest operational demands, the highest reliability,or whatever other parametric constraints dominate themission requirements. In the past few years NASA hastried to overcome this limitation by cataloging a num-ber of existing spacecraft for rapid acquisition if anexisting design happens to match the requirements fora particular misssion. A number of aerospace companiesare submitting proposals to be included in this catalog.A mission match in the catalog can lead to considerablecost savings for that mission.

I believe the correct approach to high reuse is todesign the fundamental spacecraft architecture to beinherently scalable. That is, develop an architecturesuch that increasing or decreasing the capacity of allspacecraft resources can be done with minimal changesto the fundamental building blocks (or primitives) ofthe spacecraft. Thus, for example, we would increaseredundancy and the resulting overall reliability byadding more copies of the critical primitives in such away that there is essentially no impact on the spacecraftblock diagram. The primitives themselves must bedesigned to be standardized building blocks that can beused with minimal design change over a wide range ofmissions.

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The past and current industry methodology forspacecraft implementation is to integrate subsystempackages (boxes) into a spacecraft structure and theninterconnect them with harnessing. Power switching isgenerally centralized, with power carried through theharnessing to individual boxes. Although makingthings smaller and cheaper within this architecturehelps, the approach is inherently weight- and complex-ity-limited by harnessing, boxes, connectors, mountingstructures, and “spaghetti” communication paths.Whole boxes must be removed if rework is requiredafter integration. More importantly, changing require-ments from mission to mission necessitates continualredesign of subsystems, boxes, structure, and harnessingbecause the architectures are inherently not scalable.

After 40 years in the business of developing

spacecraft, new technology and new methods

entailing risk are still the lifeblood of the Lab-

oratory’s contributions to the national space

program.

The concept we are working toward (loosely referredto in the Space Department as the IEM or IntegratedElectronics Module) is intended to promote high reusein the next generation of APL spacecraft.4 Its centralidea is to eliminate the subsystem concept and utilizea set of standard-sized boards as new spacecraft prim-itives for all the core electronics (including RF func-tions). These boards are integrated by plugging theminto one or two card cages, communicating and beingpowered over a redundant, fault-tolerant backplane.The backplane/motherboard host would accommodateone or more identical processor cards, and allow com-munication among all spacecraft elements over a re-dundant high-speed serial bus using memory-mappedaddressing. Instruments spread over the spacecraftwould be connected to the backplane through standardinterface cards that plug into the card cage. This ap-proach lends itself to a distributed, loosely coupledmultiprocessor system, which is a scalable and, I be-lieve, preferable means to achieving a high processingcapability onboard the spacecraft. Embedded micropro-cessors can be easily used wherever appropriate in theinstruments or on the cards. Receiver and transmittercards that are adaptable to a range of communicationbands without major redesign are housed in the samecard cage. We envision the card cage as eventuallybeing part of the structure itself, rather than a box thatmounts on a bulkhead.

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One can achieve changes in computing power,redundancy, science payload, data storage, communi-cation bands, and fault tolerance by increasing or re-ducing the number of cards in the IEM without anysignificant change to the block diagram. Furthermore,as electronics integration, packaging, and connectortechnology methods improve, the benefit can be real-ized by simply building the same primitives as smallercards within the same architecture. However, a numberof engineering issues are associated with such an ap-proach, some of the more important being as follows:

• Heat must be removed from the card cage, and local-ized hot spots due to high power dissipation (on theprocessor cards especially) must be dealt with.

• Electromagnetic interference between cards, espe-cially between the RF and processor cards, must beconsidered.

• Testing must be done at the card level versus the card-cage level. The old subsystems were defined in a waythat made stand-alone functional and environmentaltesting of the boxes before delivery to the spacecraft anatural approach. Dealing with card-level primitivesthat must be plugged into a motherboard to functionwith other cards requires new approaches to integra-tion and test flow scheduling. Some of the testingchallenges are offset, since a failed board can bereplaced more easily very late in the program scheduleby swapping a spare into its motherboard slot.

• Carrying unregulated power on the backplane raisesissues at the spacecraft level in power conversion,isolation, grounding, and noise coupling.

• The high-speed serial communication bus imple-mented on the backplane must have a standardizedinterface and be truly fault tolerant. To accomplishthese goals we chose the IEEE 1394 standard andelected to implement the interface as a customVLSI chip that supports a redundant bus, with no

1 2 3 4 5

(a)

(b)

Figure 1. Integrated Electronics Module card cage: (a) original version (scaled in inches),and (b) the same card cage scaled down by chip-on-board fabrication.

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requirement for switching sides if one bus fails. Thisproved to be a challenging development, albeit apowerful feature of the architecture.

These issues have been worked over the past severalyears, and a demonstration card cage and motherboardwith two real and several dummy cards has been devel-oped and flight qualified to resolve the associated en-gineering problems. The first version, shown in Fig. 1a,was built by TSD using lightweight composite materialcontaining thermally directive fibers to control heatdissipation. The remaining ongoing effort now mostlyinvolves the implementation of the fault-tolerant 1394communications bus, which will be described later. Asecond version of the IEM architecture,5,6 shown in Fig.1b, is being implemented using miniaturization tech-niques that have been developed with TSD as anothercomponent of our ATD Program, leading us to thefollowing discussion.

Chip-on-Board PackagingSize and weight are premier factors in spacecraft

design. Launch costs per pound are so high that weightconsiderations dominate spacecraft development. Sev-eral years ago the Space Department targeted the sizeand weight of our flight electronics for an improvementof at least 1 order of magnitude, and preferably 2. Atthat time our packaging methods were the chief lim-itation to reducing electronics weight, and in a partner-ship with TSD, we decided to aim at chip-on-board(COB) as a future method of fabricating our spaceelectronics. For those not familiar with this term, COBmeans eliminating packaged parts and mounting baresilicon dice directly on printed circuit boards. A recentissue of the Technical Digest (Vol. 20, No. 1), devotedentirely to advanced packaging work at APL, providesmany excellent articles about this technology and therecent effort in COB (see also Refs. 7–12). Therefore,

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minimal technical detail is coveredhere, but the effort is broadly cri-tiqued to put it into the context ofour overall program.

There were three main reasonswe decided to focus on the COBapproach and made a significantinvestment toward the goal of aflight-qualified COB manufactur-ing process. First, the approachdid not overlap other NASApackaging ATD efforts. Whenthe effort began, the major focusof the NASA centers was on var-ious types of multichip modules(MCMs), which are hermeticallysealed packages a few inches on a

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side that contain several bare dice assembled on a sub-strate. MCMs are then mounted on circuit boards likelarge packaged parts. Second, COB represented a rev-olutionary rather than evolutionary step in our pack-aging goals. This is a general characteristic we stronglydesire in our internal ATD Program, but the environ-ment in which we find ourselves, as described earlier,inevitably throws roadblocks into plans too lofty. It washard to resist a chance to aim at a bold change thatproduced the highest weight/volume payoff of theavailable approaches. Furthermore, we knew that muchimprovement in our fabrication capability would spinout of such an effort, even if the ultimate goals werenot reached. Finally, and most importantly, COB pro-vides maximum flexibility in the use of components.Some parts in bare die form are very expensive, if notdownright impossible to acquire. Properly implement-ed, the COB process allows small-outline packagedparts, or even MCMs where appropriate, to be mixedon the same board with bare dice so that each part canbe optimally selected as packaged or unpackaged.

The entire goal of the COB effort has been to de-velop a process for fabricating flight-qualified electron-ics using bare dice on boards. The word “process” meanssomething very precise in spacecraft development: adocumented, detailed methodology for manufacturingthat is highly repeatable and reliable, independent of“special” key personnel, and transportable to otherorganizations. The success of the process may requirehighly skilled personnel, but shouldn’t depend on thatone indispensable genius to make it work. Such a pro-cess has all the same qualities as those touted by soft-ware engineers, who for years had pleaded on the deafears of their management for a disciplined and rigorousprocess to produce reliable, maintainable software onschedule. In the case of COB, many technical issueshad to be solved for such a flight-qualified process tobe in place. An example is the ability to protect theassemblies from contamination, which can cause com-ponent corrosion.8,11

The Space Department and TSD jointly undertookthe development of the COB flight process. We werehelped by grants from NASA Goddard that providedcrucial financial support to supplement the Laboratory’sinvestment, as well as very important moral supportfrom Goddard technical personnel. The early approachwas to rebuild to flight standards an existing APL elec-tronic subsystem that flew on the Freja spacecraft. Nochanges were made to the electrical design or the partsused other than to acquire as many as possible as baredice and then rebuild as COB. This was the ultimatein “learn by doing” with many failures along the way.By the time the APL shops had solved most of theproblems and successfully built some flight-tested COBassemblies several years later, a real process had been

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largely defined. The final touches are still being workedinto the current version.

The COB payoff in weight and volume has beensignificant, just about the initial factor of 10 we hopedfor. Figure 2 shows the size reduction of a typicalmultilayer board of packaged parts when it is fabricatedas COB. The IEM card cage shown in Fig. 1a is reducedto something like the one shown in Fig. 1b when fab-ricated by the current COB process. However, this pro-cess is just a step along the way to the author’s real goalfor APL electronics. The first hurdle is to eliminatechip carriers. The next step is to eliminate boards andsubstrates that constrain us to two-dimensional inter-connects. If we can stack the bare electronic dice, oneatop another, and connect them somehow along theedges or through the stack, then our electronics becomelittle cubes of silicon.13 The new IEM spacecraft elec-tronics primitives become the individual chips, and thecommunication/power distribution backplane becomessomething akin to built-in connectors along the edgesof the cubes. If we can make such an approach viablefor space, then we are really getting somewhere inminiaturization. Such an approach requires at least twoother technology advances:

1. The ability to replace an aggregate of commercialparts with a single custom VLSI chip that provides anatural primitive function in the same vein as acurrent IEM board

2. Ultra-low-power (ULP) versions of these CMOSchips so that the cubes do not overheat

Custom VLSI Electronics

For the past decade or more the Space Departmenthas engaged in developmental projects in custom VLSI,designing application-specific integrated circuits (ASICs)

Figure 2. Relative size reduction using COB fabrication shown inFig. 1b. The two boards hold identical electrical designs, the upperbeing an electrical breadboard for testing the design built usingcurrent APL multilayer board processes.

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to be fabricated by commercial sil-icon foundries. Several of thesechips have been used in past space-craft programs; however, until the1990s, the radiation susceptibilityof foundry-produced chips has im-peded their widespread use in space-craft. Five years ago, a major stepforward in CMOS radiation resis-tance occurred with the emergenceof cost-effective commercial found-ry sources of radiation-resistant bulkCMOS VLSI devices. Over severalsubsequent years, in the SpaceDepartment’s Independent Re-search and Development Program,we benchmarked the radiation re-sistance of these new foundry pro-cesses. We have also experimentedwith new VLSI circuit design tech-niques to improve latch-up resis-tance and to achieve mixed analog/digital functionality on the samechip.14–17 In addition, there arenow emerging commercial field-programmable gate

0.4 in.

0.4 in.

Figure 3. Improvema single, mixed-mod(TOF) measuremenused on Cassini, ACscopic Explorer), an

arrays (FPGAs) which have high radiation tolerance.In short, the Laboratory’s long and patient effort in

moving toward custom-designed ASICs for space ispoised for a real explosion if we do the right stuff. TheASIC products now coming out of this part of our ATDProgram have what can only be described as a startlingimpact on our spacecraft electronics. Our latest radia-tion-resistant time-of-flight (TOF) chip, for example,replaces an entire board of discrete analog and digitalcomponents and reduces power by more than an orderof magnitude over the traditional approach.18 (Themeasurement of the TOF of charged particles is a cru-cial capability of instruments for mass and particle spec-troscopy, ultraviolet imaging, and range finding.)

Figure 3 shows the complete picture of the TOF chippayoff, and can leave little doubt as to why I havecarried this vision for over 15 years. Comparing theAPL TOF chip (with all analog and digital electronicsin one chip) and a standard TOF system (all analog anddigital electronics typically on a double-sided board),weight is reduced from 240 to 3 g, resolution is en-hanced from 750 to 100 ps, power is reduced from 1000to 25 mW, and radiation hardness is increased from 100krad to 1 Mrad. In addition to such huge improvements,the reliability of electronics is actually improved byhigher levels of integration. The entire space industryneeds to move toward chips as spacecraft primitivesinstead of boards or, heaven forbid(!), boxes. However,there are remaining hurdles that are nontrivial.

Although the technology for custom analog anddigital chips stands poised to completely change the

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14.0 in.

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ents gained by integrating all required analog/digital electronics intoe CMOS devise are obvious when comparing the APL time-of-flightt chip on the left with the standard TOF system on the right, which wasE (Advanced Composition Explorer), FUSE (Far Ultraviolet Spectro-d other spacecraft.

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“ballgame” in spacecraft electronics, we are seriouslylimited by the number of people who can perform suchdesigns and who fully understand this approach. Aproblem to be overcome (for the entire space industry,not just APL) is the infusion of the appropriate exper-tise from the relatively small group of people nowcarrying out these new developments into the engineer-ing staff at large. Many of our experienced and keydesigners, through no fault of their own, are still lockedinto the old culture of implementing boards, and wehave yet to tap their creative energy in using customchips as the new spacecraft primitives. This changerequires training through hands-on developmental chipprojects and easier access to existing VLSI softwaredesign tools. The author’s vision for the Space Depart-ment in the next 5 years is to move almost entirely overto this approach, a difficult undertaking that requiresresources and entails risk.

One of those risks concerns the stability of thecommercial foundry sources for radiation-resistant cus-tom chips. The space industry is not a mass market byany stretch of the imagination. After investing in a veryhigh-tech process, it’s hard for a commercial siliconfoundry to make money on customers who want onlya half dozen radiation-resistant parts. They would preferto fabricate 10 million or so parts for cellular phonemanufacturers who have no need of radiation resis-tance. This problem requires the attention of bothNASA and DoD. The federal government, mainlythrough the Defense Advanced Research ProjectsAgency, helped create the silicon foundry industry inthe 1980s, and it is in their extreme interest to keep

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radiation-hard foundries in business for the country’sspace program. This is the scariest problem for APL,mainly because the Laboratory has no control over it.

Another hurdle is similar to the COB problem andis something the Laboratory could help solve. Atpresent, the development of custom chips is more likean R&D activity than an established technical process.It is more expensive to develop a flight-qualifiedcustom chip than the equivalent electronics as a flight-qualified board. A well-defined and repeatable flight-qualified process is lacking for custom chip develop-ment, whether it involves a radiation-hard FPGA or apure custom analog VLSI chip. Part of such a processinvolves the establishment of software tools that suffi-ciently automate the design process. Such commercial-ly available tools are emerging, but they are very ex-pensive and invariably have limitations that frustratedesigners and cause hang-ups. The lack of a predictablechip development process introduces both cost andschedule risks to spacecraft programs.

Despite these obstacles, I am confident that the cul-ture of spacecraft design engineers in the near futurewill be to think in terms of developing a spacecraftelectronic function as a VLSI chip, rather than as aboard or a package. With the three-dimensional stack-ing possibilities offered by the advanced packagingmethods now being perfected, we can truly envision afuture complex electronic system on a spacecraft as atiny cube.

Advanced Power Systems

The Space Department has just begun a technologyeffort involving advanced power systems, which I ex-pect will grow significantly in the next few years. It isdriven by a push toward ULP CMOS electronicsthroughout industry and academia. Since it is essential-ly out of the question politically to fly small, nuclearpower sources on spacecraft, we are relegated to carry-ing heavy, low-efficiency solar arrays and batteries. Thisputs us all in the position of being chronically powerstarved in designing a spacecraft, and everyone (espe-cially the spacecraft system engineer) is delighted atanything that can reduce power demands onboard.However, in my view, the impact of ULP, and the realopportunity for payoff, does not lie in simply scalingback the size of the spacecraft power system. Rather,ULP electronics offer the opportunity to completelychange the architecture of spacecraft power systems.Some background is helpful to an appreciation of thisargument.

The power dissipation of electronics is proportionalto the square of the supply voltage, typically 5 V fortoday’s CMOS. The thrust of ULP research is to drivethe required supply voltage down to values as low as0.1 V. Let’s assume this effort will eventually succeed,

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and that essentially all the internal electronics will takezero power. We still will not have a major effect onspacecraft power system weight, simply because otherpower needs dominate the onboard requirements.These needs come from communications to the ground,momentum wheels to control attitude, firing thrusters,and the like. What, then, is the big advantage of ULP?It opens the possibility of going to a distributed onboardpower system rather than the central system tradition-ally flown.

The traditional system (typically) operates every-thing onboard off a 28-V bus supplied by solar cellarrays in which cells are wired in series to produce theneeded voltage level. The battery cells are likewise sodesigned. Voltage-regulation electronics is required tomaintain the bus within acceptable limits. Redundantsubsystems (or boards in the IEM approach) are pow-ered on and off through banks of switches connectingthem to the power bus, and the 28-V power is DC-DCconverted down to the specific levels around the 5 Vneeded by each electronic subsystem. The power con-verters are generally inefficient and heavy, the switch-ing must be designed to avoid failure in the “on” con-dition, and, to prevent an electrical short from killingthe whole system, fusing is required in all circuits.

The same techniques now being explored to allowextremely low electronics supply voltages may be di-rected to achieving a more modest decrease (say toaround 1 V), accompanied by a proportionally muchwider tolerance to supply voltage variations. Thiswould open the possibility of using battery-driven elec-tronics, where the individual electronics primitives inthe spacecraft could each survive 5 or more years (likeyour watch) off a small primary cell. (Primary, nonre-chargeable cells have generally much higher energydensity than their secondary, rechargeable counter-parts.) In such an approach, many switches and powerconverters would be eliminated. A failure in a redun-dant piece of electronics would not require switchingor fusing to protect a central power supply, potentiallymaking operation much simpler and easier. Maybeother systems (e.g., a momentum wheel) that wouldstill require solar arrays and a battery could each operateoff their own power circuit that was optimally tuned totheir voltage requirements, eliminating yet moreswitches and converters. If the electronic supply volt-ages are low enough, it might even be possible to tapspacecraft temperature gradients using tiny Sterlingengines to produce the needed power (reader, pleasestop laughing).

Other interesting ideas flow out of this line ofthought, but I will stop here since you get the idea. Inbrief, perhaps a power system comprising many individ-ual, unconnected power circuits, each tuned to its ownload requirements, would end up simpler, lighter, andcheaper; it may also be scalable in a more graceful way.

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I have no idea if this is true, but wouldn’t it be excitingto find out? Along the way I’m sure some great improve-ments would emerge, like those resulting from ourpreviously described packaging efforts. My instincts tellme that this would be a good approach if the technol-ogy could support it. Long ago I became convinced thatdistributed control invariably works better than cen-tralized control, and I can see an analogy for power.

The Biological Paradigm for AutonomyAs described earlier, a high level of autonomy is

important to successful spacecraft missions. However,autonomy must be built on reliability and fault toler-ance. In the author’s opinion, the correct architecturefor building autonomy is to be found in biologicalsystems. Consider, for example, placing your hand ona red-hot stove. You will jerk that hand back before youare even consciously aware of pain, faster than anysignal could possibly propagate along relatively slowneurons to your brain. The processing for this reactionis embedded locally in the tactile system, and the samekind of reaction processing causes us to blink if some-thing comes flying at our face. Although the brain doesa lot of very sophisticated processing to produce highlevels of autonomy, a huge amount of sensory informa-tion processing occurs right in the eyeball, the opticnerve, and the cochlea of the inner ear, completelyindependent of the brain. Biological systems thus havetwo main characteristics that are models for an auton-omous spacecraft:

1. Processing is distributed and loosely coupled, and ac-tions are not all controlled by a single giant processor.

2. The sophisticated, autonomous functions performedby the central processor are overridden by simple,hard-wired “safing” behavior that allows the programin the central processor to fail gracefully (i.e., dosomething stupid like try to touch a hot stove).

The promise of radiation-resistant spacecraft proces-sors with huge processing rates has been around foryears, but it will never materialize because the expenseof building such electronics is high and the spacecraftmarket is too small. Consequently, the capability offlight-qualified processors always lags a decade or morebehind the processing power of commercial computers.One way to get higher effective processing rates on-board with currently available flight processors is toembed more loosely coupled processors into the archi-tecture. This makes the processing power onboard scal-able, which is the goal of our IEM approach. We arenow using the Mongoose V flight processor as the IEMprocessor primitive. If we are doing anything right,switching to a different processor card in the future willhave minimal impact on the architecture or the otherIEM primitives.

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The second characteristic of the biological paradigmis more crucial, and it has been the fundamental ap-proach of APL for years. The message it delivers is thatthe sophisticated functions implemented in softwaremust be built on a layer of “bulletproof” and highlyreliable hardware to provide safing. At the lowest level,this hardware must be simple, finite-state logic so it canbe tested for all conditions, and it must be fully redun-dant in a manner that is fault tolerant. That is, itcannot require ground intervention to keep runningthrough a failure of one copy. This layer of logic pro-vides bare survival in one piece if anything goes wrongonboard.

A second, more sophisticated layer can operate ontop of the first, whose job it is to “watchdog” the layerabove it, and so on. The most likely component to failon a spacecraft is the most sophisticated autonomysoftware, simply because it is the most complex and thehardest to test. Many people claim (frequently forpolitical purposes) that complex software can never befully debugged. The APL layered approach to autono-my in a sense is designing the system so that the mostcomplex functions can safely fail, even though we workhard to make them reliable. This approach is ingrainedin the IEM architecture. We are attempting to designthe architecture by assuming that at some point in thespacecraft’s life the onboard software will inevitablyhave a glitch (I’m trying to put this kindly for the sakeof our software engineers).

The lowest levels of this layered architecture are, inmy opinion, the most difficult, the most critical, andalso the most interesting. I believe that if we get thelowest levels working well, almost anything done at thehighest, complex software levels will work, with occa-sional loss of data as the spacecraft “recovers itself.”Unfortunately, the highest-level “stuff” is the most en-ticing to software engineers; at this level, glamorousterms like artificial intelligence and expert systemsbegin to be bandied about. Yet I am firmly convincedthat software experts are the most qualified to definethe lowest levels of safing, but this does not alwayshappen. Notice the words “recovers itself” in the state-ment above. This is the next major step that APLshould take in spacecraft autonomy. With the correcttype of layered autonomy, after a glitch the spacecraftcan reliably get going on its own. Up to now the low-level safing in our spacecraft only parks them in a safepower mode and then relies on commands from theground to get back in business.

Recent APL spacecraft such as NEAR (the NearEarth Asteroid Rendezvous) and MSX (the MidcourseSpace Experiment) have exhibited highly successfulsafing of this type through the application of rule-basedprocessing at the lowest levels (decisions based onmultiple-clause rules applied to telemetry data19).Autonomy experts are now suggesting that model-

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based reasoning (i.e., decisions based on a comparisonof observed spacecraft behavior to an onboard digitalmodel of the spacecraft) is superior. For this new areaof investigation, the Space Department is joining forceswith the APL Research and Technology DevelopmentCenter to focus on spacecraft modeling. However, theuse of model-based reasoning at the lowest levels of thelayered autonomy architecture conflicts with the strin-gent requirements of simplicity, reliability, and faulttolerance. The lowest levels of spacecraft safing cannotbe eliminated or migrate to model-based processing.This type of processing must be relegated to the highestsoftware level for complex decisions that generally donot involve survival.

Within the IEM, the first low-level element thatmust be fault tolerant is the 1394 serial communicationbus. We began development of a single-chip interfaceto a redundant backplane bus (two channels) wherebyif either channel failed, the interface would continueto operate on the other channel with no ground inter-vention. There are two versions of the IEEE 1394 busstandard—cable and backplane. We specifically select-ed the simpler backplane version because the issues offault tolerance and “node clobbering” (i.e., one nodeclobbering the software on another node) were morecomplex in the cable version. The development of thisASIC, which APL calls the bus interface unit chip, hasgone through several design iterations and is nearingfinal form. Handling all possible cases to make it truly“bulletproof” has been difficult. The IEM architectureincludes a special card primitive called the safer card,which will have access to all 1394 bus transactions andto the command processing on the receiver card. Inaddition, it will implement the low-level rule-basedsafing functions mentioned earlier. This is a currentlyactive area of IEM development.

FINAL REMARKSAlas, we must stop here for the editor’s axe, having

discussed only a portion of the Space Department’s ef-forts in ATD. Other DoD-oriented ATD activities aregoing on that I have not touched upon. Embryonicefforts are under way that involve much more interest-ing and speculative ideas. One of these is for a spacecraftthat would live for 100 years. This is the sort of lifetimeneeded to reach the nearest star or to stand as a sentinelthat could give early warning of dangerous near-Earthobjects. My approach to such a requirement would beto again fall back on the biological paradigm—thespacecraft, like our bodies, would repair itself. Sometechniques to achieve this goal might be to periodicallyraise the temperature of the electronics to anneal radi-ation damage, or to make all the electronics micro-programmable so that failures could be eliminated byself-reconfiguration. This one requirement to make a

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ADVANCED SPACECRAFT TECHNOLOGY PROGRAM

spacecraft live longer than a person is interestingenough to be the subject of an entire future article.

Embryonic efforts are under way that involve

much more interesting and speculative ideas.

One of these is for a spacecraft that would

live for 100 years.

The jury is still out on most of the material describedin this article. The first Laboratory spacecraft usingthe card-cage approach for the core electronics isTIMED (Thermosphere-Ionosphere-Mesosphere Ener-getics and Dynamics), which is scheduled for launch inearly 2000. Doing things this new way did lead to testand integration difficulties as expected. In the past 24months, the IEM approach was proposed for three verydifferent missions for the NASA Discovery Program ininterplanetary science. We found that the architecturewas indeed applicable to all three missions with verylittle difference, leading us to believe we are on theright track toward a truly scalable approach.

The general environment for using advanced tech-nology and new methods in space missions is probablythe best it has been in decades. However, an advancedtechnology “funding gap” still exists that seems polit-ically unavoidable. Under government rules, plans canbe developed only so far under R&D-type fundinggrants, and programs that pick up immature technologystill experience a certain level of pain, cost, and risk.There is little doubt that the Laboratory has felt theseeffects on the TIMED Program’s use of the card cageand new card-level primitives for the RF communica-tions system. On the other hand, this is probably as itshould be, lest the people working on advanced tech-nology become too complacent. The extreme cost-competitiveness of, for example, the NASA unmannedprogram definitely discourages new approaches. How-ever, the missions that APL is proposing and will con-tinue to propose cannot be achieved easily withoutsuch new approaches. Consequently, we will continueto live in this exciting, yet taxing environment, andjustifiably so if we expect to do truly challenging workfor our sponsors.

Finally, I would like to acknowledge the many peo-ple who performed the work described here, and men-tion the key people by name. Martin Fraeman has beenleading the development of the scalable architecturewith a lot of help from Richard Conde. Robert Bokulichas led the effort to develop a new set of card-levelprimitives for the RF communications functions in theIEM approach. Binh Le has been leading our thrust in

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advanced packaging, and Jay Dettmer and his group inTSD have been key to creating a flight-qualified COBprocess. Kim Strohbehn and Nikolaos Paschalidis havebeen heading the Space Department’s effort in mixed-mode ASICs for some time. The TOF chip described(Fig. 3) was developed by Dr. Paschalidis in collabora-tion with students from the University of Thrace,Greece. Many of the Space Department’s ideas aboutlow-level safing, and surely a good deal of influence onmy views, come from James Perschy and Ark Lew, andfrom Susan Lee, who has since transferred to anotherdepartment at APL. Ms. Lee has had a valuable influ-ence on the design of the APL dual-bus 1394 bus in-terface unit chip and on the development of the SpaceDepartment’s general approach to safing. Ralph Mc-Nutt and Robert Gold have recently been developingmission concepts for spacecraft visiting a star or actingas sentinels against dangerous near-Earth objects.

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3Hoffman, E. J., “Spacecraft Design Innovations in the APL Space Depart-ment,” Johns Hopkins APL Tech. Dig. 13(1), 167–181 (1992).

4Fraeman, M., “A Fault Tolerant Integrated Electronics Module for SmallSatellites,” in Proc. 11th AIAA/USU Conf. on Small Satellites, Logan, UT (Sep1997).

5Conde, R. F., Le, B. Q., Bogdanski, J. F., Lew, A. L., and Darrin, M. A.,“Command and Data Handling In Your Palm,” in Proc. 11th AIAA/USUConf. on Small Satellites, SSC97-I-6, Logan, UT, pp. 1–13 (Sep 1997).

6Ling, S. X., Le, B. Q., and Conde, R. F., “Thermal Assessment of aMiniaturized Spaceborne Command & Data Handling In Your Palm

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(C&DHIYP),” in Proc. 4th Int. Workshop on Thermal Investigations of ICs andMicrostructures, Cannes, France, pp. 165–170 (Sep 1998).

7Le, B. Q., “Chip-on-Board Technology,” in Proc. Electronic PackagingWorkshop for Space Applications, Pasadena, CA (Nov 1996).

8Le, B. Q., Nhan, E., Maurer, R. H., Lew, A. L., Lander, J., Lehtonen, S. J.,and Darrin M. A., “Evaluation of Die Coating Materials for Chip-on-BoardTechnology Insertion in Spaceborne Applications,” in Proc. 6th Int. Conf. onMultichip Module, IMAPS, Denver, CO, pp. 142–147 (2–4 Apr 1997).

9Maurer, R. H., Le, B. Q., Nhan, E., Lew, A. L., and Darrin, M. A.,“Fabrication and Qualification of Coated Chip-on-Board Technology forMiniaturized Space Systems,” in Proc. Third ESA Electronic Components Conf.,ESTEC, Noordwijk, The Netherlands, pp. 199–204 (22–25 Apr 1997).

10Le, B. Q., Schwartz, P. D., Peacock, K., Strohbehn, K., and Scholar, T., “TheJHU/APL Miniaturized Scientific Imager Design with Lightweight ReflectiveOptics and Chip-on-Board Packaging,” in Advances in Electronic Packaging,Vol. 1, ASME, New York, pp. 835–841 (15–19 Jun 1997).

11Le, B. Q., Darrin, M. A., and Kadesch, J., “Study of Conformal Coating onChip-on-Board Technology for Space Applications,” NASA IEEE Links 3(2),2–5 (Jun 1997).

12Nhan, E., Le, B. Q., Maurer, R. H., and Lew, A. L., “Reliability of Chip-on-Board Technology for Space Systems,” in Proc. Int. Workshop ElectronicsComponents for the Commercialization of Military and Space Systems, HuntingtonBeach, CA, pp. 102–108 (2–4 Feb 1998).

13Nhan, E., Le, B. Q., Maurer, R. H., Lew, A. L., Lander, J., Schwartz, P. D.,and Garrison, M. A., “Reliability Study of Chip-on-Board Technology forSpace Applications with a 3-D Stacked DRAM As Test Vehicle,” Adv.Electron. Packag. 1, 1679–1684 (Jun 1997).

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THE AUTHOR

ROBERT E. JENKINS joined APL in 1961 and has more than 30 years ofexperience in space systems. A past member of the APL Principal Staff, he hasrecently retired as Assistant Supervisor for Advanced Technology in the SpaceDepartment’s Engineering Branch and as Program Manager for the Department’sadvanced technology programs. He served as a member of the APL IR&DCouncil for the past 17 years, leading the Department’s IR&D program duringthat period. Mr. Jenkins is now a Senior Lecturer in the JHU School ofEngineering, a member of the Program Committee for the Part-Time Master’sDegree Program at APL, and a self-employed consultant. He continues as amember of the Space Department Steering Group for Advanced Technology anda member of the Kershner JHU-CTY Scholarship Committee. His e-mail addressis robert.jenkins@jhuapl.edu.

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