Version: V1.9 Renergy Technology Co., Ltd. of Shenzhen

RN8318_RN8615_RN8613_RN8612_RN8611_RN8610BUser Manual

Version: V1.9

Renergy Technology Co., Ltd. of Shenzhen

Renergy RN8318_RN8615_RN8613_RN8612_RN8611_RN8610B

Renergy Technology Co., Ltd.Shenzhen page of 149 Rev 1.92

Modification records

VersionProposed/modi

fied personProposed/modified date

Reasons for

changesMain changes

V1.0 Service Dept of Renergy

2016-10-09 Create

2017-03-01 Modify 1. Add new model RN8612, and modify relevant chapters;

2. Change the packaging definitions of RN8613 and RN8615, and adjust definitions of PIN98/99/100/14/15;

3. Improve the manual and correct some errors.V1.2 Service Dept

of Renergy2017-03-12 Modify Improve the manual, supplement and modify descriptions

of ench chapter.V1.3 Service Dept

of Renergy2017-03-15 Modify 1. Adjust some indexes of electrical characteristics in

chapter 2.2. More detailed descriptions of reset section of 3.5.3. More detailed descriptions of analog peripherals in

chapter 9.4. Adjust some instructions of LCD/INTC/KBI.

2017-3-28 Modify 1. Modify errors in the description of bitband in section 4.3.

2. Modify P66/SEG10 and P67/SEG11 in pin arrangement drawing of RN8611 of Fig 1.4 to P66/P67.

3. Add descriptions of AIN input impedance of analog peripherals in chapter 9.

4. High speed mode is not supported under 1.8432MHzclock in section IIC of cheapter 15.

5. The card clock output does not support 32/64/128 frequency division in section 7816 of cheapter 14.

6. Modify the description error of LVD threshold voltage setting register in Chapter 9 analog peripheral.

7. Add descriptions of RAM address space occupied by BOOTROM and description of CACHE opening in section 4.3.1.

8. Limit parameter descriptions and more parameter indexes are added for electrical characteristics inchapter 2.

9. P30 port description is modified in chapter 1.4. 10. Add product appearance descriptions in chapter 19.

2017-6-17 Modify 1. Revise the pen error BIAS in 7.2.6 to RES.2. Modify the boundary temperature of secondary

temperature compensation t5-t93. Modify the description of power monitoring circuit

in 3.5.2.4. Modify the pen error LVDVP1 of pin 51/66 in pin

description 1.4 (P18) to LCDVP1.5. Add RCL in the clock block diagram to connect

LCD and CPU clocks.6. Modify the description of 9.2.1 REF_WAIT and add

remarks to the description of SAR_WAIF.7. Add descriptions in 3.6.6.8. Modify HBM CDM MM Latch-up test parameters in

chapter 2 “electrical characteristics” to be separately tabulated.

9. Modify definitionS of reference voltage, comparator threshold, temperature compensation time, working voltage and other indicators in chapter 2 “electrical characteristics”.

10. Modify the pin arrangement in section 1.4, and change PIN10~PIN13 of RN8613/8615 from NC to P104~P107.

2017-8-10 Modify 1. Change the definition of RN8611, packaging from LQFP64 to LQFP80.

2. Add RN8610B (LQFP64).3. Modify comparator indexs in the second chapter of

electrical characteristics and add an index of 0.9V;At the same time, comparator related register description in section 3.6.3 is modified.

2017-8-28 Modify 1. Add VBAT power domain software reset operation instructions.

2. Removed the instruction that the software needs to open the cache manually.

3. Modify SPI definition of P112/P113 of pin description in pin arrangement to be consistent with pin arrangement diagram.

4. SPI base address name is wrong (the original written error is UART0).

5. Delete eepromPageErase and eepromSectorErase library function support.

6. Add one non gate to the open drain output selection terminal of IO type PBULD3 and PABULD3.

2017-10-09 Modify 1. Add NC mark for RN8612 on the pin drawing P104-P107 in chapter 1.4.

2. Add stack top application note for RN8612 in section 4.2.1.

3. Add descriptions of temperature conversion formula for the current temperature register in 6.3.

2018-12-13 Modify 1. Change ANA_PAD register bit name in section 9.2.7.

2. 10.1.11 PCB2 registers P44 and P45 retain SAR function configuration; Add remark to PCB register.

3. 9.2.2 SAR_START register adds SAR_ADC start precautions.

4. Add the flowchart of library function clock switch in section 3.3.

5. Add descriptions of welding conditions.6. Add precautions for second pulse and second register

in section 5.3.14.7. Modify temperature register description.8. Add descriptions of the relationship between second

pulse interrupt and RTC->CNT1 interrupt and second register.

9. Add notes for RTC register writing. For one time writing, writing six complete registers (month, day, hour, minute and second) instead of just updating parts (such as writing minute and second only).

CONTENTS

Version: V1.9 .................................................................................................................................................................... 1

1 Overview................................................................................................................................................................. 10

1.1 Summary ................................................................................................................................................. 10

1.2 Product Features...................................................................................................................................... 10

1.3 Implementation architecture.................................................................................................................... 13

1.4 Pin Configuration .................................................................................................................................... 14

1.5 IO Port Function Block Diagram ............................................................................................................ 27

2 Electrical Characteristics......................................................................................................................................... 33

3 System Control........................................................................................................................................................ 36

3.1 Power Domain Division.......................................................................................................................... 36

3.2 Clock Source ........................................................................................................................................... 37

3.3 Clock Switch ........................................................................................................................................... 39

3.4 MCU Low-power Mode.......................................................................................................................... 41

3.5 Reset........................................................................................................................................................ 42

3.5.1 External PIN reset ........................................................................................................................... 42

3.5.2 Power-on and power-off reset ......................................................................................................... 42

3.5.3 Software reset.................................................................................................................................. 42

3.5.4 Watchdog reset ................................................................................................................................ 42

3.6 Register Description................................................................................................................................ 42

3.6.1 System OSC control register1 OSC_CTL1(0x0) ............................................................................ 43

3.6.2 System Mode Setting Register SYS_MODE(0x4) ......................................................................... 44

3.6.3 System Power Down Control Register SYS_PD(0x8).................................................................... 45

3.6.4 System OSC Control Register 2 OSC_CTL2(0x10) ....................................................................... 46

3.6.5 System Reset Register SYS_RST(0x14)......................................................................................... 48

3.6.6 System Mapping Control Register SYS_MAPCTL (0x18) ............................................................ 49

3.6.7 Module Enable 0 Register MOD0_EN(0x1C) ................................................................................ 49

3.6.8 Module 1 Enable Register MOD1_EN(0x20)................................................................................. 51

3.6.9 INTC Enable Register INTC_EN(0x24)......................................................................................... 52

3.6.10 KBI Enbale Register KBI_EN(0x28).............................................................................................. 53

3.6.11 Device ID Register CHIP_ID(0x2C) .............................................................................................. 54

3.6.12 3.6.12 System Control Password Register SYS_PS (0x30) ............................................................ 54

3.6.13 Infrared Configuration Register IRFR_CTL (0x34) ....................................................................... 54

3.6.14 Clock Correction Configuration Register TRIM_CFG1 ( 0x78) .................................................... 54

3.6.15 Clock Correction Start Register TRIM_START ( 0x7C) ................................................................ 55

4 CPU Architecture .................................................................................................................................................... 57

4.1 Overview................................................................................................................................................. 57

4.2 Cortex-M0 Processor .............................................................................................................................. 57

4.2.1 Interrupt Configuration ................................................................................................................... 58

4.3 MCU Memory Mapping ......................................................................................................................... 61

4.3.1 SRAM ............................................................................................................................................. 63

4.3.2 FLASH ............................................................................................................................................ 63

4.3.3 EEPROM ........................................................................................................................................ 64

4.4 Interrupt Application ............................................................................................................................... 64

5 RTC......................................................................................................................................................................... 64

5.1 Overview................................................................................................................................................. 64

5.2 Features ................................................................................................................................................... 65

5.3 Register Description................................................................................................................................ 65

5.3.1 RTC Control Register RTC_CTL(0x00) ......................................................................................... 66

5.3.2 Second Register RTC_SC (0x04).................................................................................................... 68

5.3.3 Minute Register RTC_MN(0x08) ................................................................................................... 68

5.3.4 Hour Register RTC_HR(0x0c)........................................................................................................ 69

5.3.5 Date Register RTC_DT(0x10) ........................................................................................................ 69

5.3.6 Month Register RTC_MO(0x14) .................................................................................................... 69

5.3.7 Year Register RTC_YR(0x18) ........................................................................................................ 69

5.3.8 Date Week Register RTC_DW(0x1c) ............................................................................................. 69

5.3.9 RTC Timing Register 1 RTC_CNT1(0x20) .................................................................................... 70

5.3.10 RTC Timing Register 2 RTC_CNT2(0x24) .................................................................................... 70

5.3.11 Second Alarm Register RTC_SCA(0x28)....................................................................................... 71

5.3.12 Minute Alarm Register RTC_MNA(0x2c)...................................................................................... 71

5.3.13 Hour Alarm Register RTC_HRA(0x30).......................................................................................... 71

5.3.14 RTC Interrupt Enable Register RTC_IE(0x34) ............................................................................... 71

5.3.15 RTC Interrupt Flag Register RTC_IF(0x38) ................................................................................... 73

5.3.16 Current Temperature Register RTC_TEMP(0x3c).......................................................................... 74

5.3.17 LOSC Configuration Register LOSC_CFG1(0x6c)........................................................................ 74

5.3.18 VBAT Domain IO Configuration Register VBAT_IOMODE(0x88).............................................. 75

5.3.19 VBAT Domain IO Configuration Register Writing enable VBAT_IOWEN(0x8C) ....................... 75

5.4 RTC clock R/W steps .............................................................................................................................. 76

5.5 RTC calibration steps .............................................................................................................................. 76

5.6 RTC timer operation steps....................................................................................................................... 76

6 WDT ....................................................................................................................................................................... 77

6.1 Overview................................................................................................................................................. 77

6.2 Configuration of Watchdog Timer .......................................................................................................... 77

6.3 Registers Descriptions............................................................................................................................. 78

6.4 WDT operation steps............................................................................................................................... 78

7 LCD......................................................................................................................................................................... 79

7.1 Overview................................................................................................................................................. 79

7.1.1 Scan Clock Frequency..................................................................................................................... 79

7.1.2 Flash Mode...................................................................................................................................... 80

7.1.3 LCD Driving Waveform.................................................................................................................. 80

7.1.4 Bias Voltage of LCD ....................................................................................................................... 86

7.1.5 LCD Frame Buffer Mapping........................................................................................................... 87

7.2 Register Descriptions .............................................................................................................................. 87

7.2.1 LCD Control Register LCD_CTL (0x00) ....................................................................................... 87

7.2.2 LCD Status Register LCD_STATUS (0x04) ................................................................................... 88

7.2.3 LCD Clock Control Register LCD_CLKDIV (0x08) ..................................................................... 89

7.2.4 LCD Flash Control Register LCD_BLINK (0x0c) ......................................................................... 89

7.2.5 LCD setting time of charge pump Register LCD_PS (0x10).......................................................... 89

7.2.6 LCD internal Resistor String Control Register LCD_RESCTL (0x14) .......................................... 90

7.2.7 LCD Data Register LCD_BUF[i] (8-bit register) ........................................................................... 91

7.3 LCD operation steps................................................................................................................................ 91

8 Timer....................................................................................................................................................................... 92

8.1 Overview................................................................................................................................................. 92

8.2 Function Block Diagram......................................................................................................................... 93

8.3 Register Descriptions .............................................................................................................................. 93

8.3.1 The current count values Register TC_CNT (0x00) ....................................................................... 94

8.3.2 Prescale Register TC_PS (0x04) ..................................................................................................... 94

8.3.3 Target count value Register TC_DN(0x0C).................................................................................... 94

8.3.4 Capture comparison channel 0 data Register TC_CCD0(0x014) ................................................... 94

8.3.5 Capture comparison channel 1 data Register TC_CCD1 (0x018) .................................................. 94

8.3.6 Clock Configuration Register TC_CCFG (0x01C)......................................................................... 94

8.3.7 Control Register TC_CR (0x020) ................................................................................................... 96

8.3.8 Capture comparison channel 0,1 mode Register TC_CM0/1(0x024 and 0x028) ........................... 97

8.3.9 IERTC_IE(0x2C) ............................................................................................................................ 98

8.3.10 State Register TC_STA(0x30) ........................................................................................................ 98

8.4 Typical Applications................................................................................................................................ 98

8.4.1 Automatic Operation Mode, Timing Function ................................................................................ 98

8.4.2 Input Capture Mode, Function of Pulse Width Measurement ......................................................... 99

8.4.3 Comparison Output Mode, Function of Square Wave Output ........................................................ 99

8.4.4 Mode of Compare Output, Function of PWM Output .................................................................. 100

8.4.5 Slave Mode, External Clear and Gating Functions ....................................................................... 102

8.5 Operation steps...................................................................................................................................... 102

9 Analog Peripherals................................................................................................................................................ 103

9.1 Features ................................................................................................................................................. 103

9.2 Register ................................................................................................................................................. 103

9.2.1 ADC Control Register SAR_CTL (0x00) ..................................................................................... 104

9.2.2 SAR-ADC Start Register SAR_START (0x04) ............................................................................ 105

9.2.3 SAR-ADC Status Register SAR_STATUS (0x08)........................................................................ 105

9.2.4 ADC DAT Register SAR_DAT(0x0c) .......................................................................................... 106

9.2.5 LVD Control Register LVD_CTL (0x10)...................................................................................... 106

9.2.6 LVD Status Register LVD_STAT (0x14) ...................................................................................... 107

9.2.7 ANA_PAD .................................................................................................................................... 107

9.2.8 ANA_RST..................................................................................................................................... 108

9.3 ADC voltage detection steps ................................................................................................................. 108

9.4 VBAT voltage detection ........................................................................................................................ 108

9.5 Low Voltage Detection Application ...................................................................................................... 109

10 GPIO ............................................................................................................................................................. 109

10.1 Overview............................................................................................................................................... 109

10.2 Register description............................................................................................................................... 110

10.2.1 PA port mode register PMA(input or output)(0x00) ..................................................................... 111

10.2.2 PA port data register PA(0x04)...................................................................................................... 111

10.2.3 PA port reuse 0 register PCA0 (0x08) ........................................................................................... 112

10.2.4 PA port reuse 1 register PCA1(0x0C) ........................................................................................... 113

10.2.5 PA port pull-up select register PUA(0x10).................................................................................... 114

10.2.6 PA port input mode configuration register PIMA(0x14)............................................................... 115

10.2.7 PA port input enable register PIEA (0x18) .................................................................................... 115

10.2.8 PB port mode register PMB(input or output)(0x1C)..................................................................... 115

10.2.9 PB port data register PB(0x20) ..................................................................................................... 116

10.2.10 PB port reuse register PCB (0x24) ........................................................................................ 116

10.2.11 PB port reuse register 2PCB2 (0x4CH) ........................................................................................ 117

10.2.12 PB port pull-up/pull-down selection register PUB (0x28) .................................................... 119

10.2.13 PB port input mode register PIMB (0x2C) ........................................................................... 119

10.2.14 PB port input enable register PIEB (0x30)............................................................................ 120

10.2.15 PC port mode register PMC (input or output)(0x34) ............................................................ 120

10.2.16 PC port data register PC(0x38) ............................................................................................. 120

10.2.17 PC port reuse register PCC (0x3C) ....................................................................................... 121

10.2.18 PC port pull-down selection register PUC (0x40)................................................................. 121

10.2.19 PC port input enable register PIEC (0x44)............................................................................ 122

10.2.20 PC port input mode register PIMC (0x48) ............................................................................ 122

10.2.21 SEGCOM port reuse register PCE (0x60) ............................................................................ 122

10.2.22 PA port data set register PASET(0x64) ................................................................................. 123

10.2.23 PA port clear set register PACLR (0x68)............................................................................... 123

10.2.24 PB port data set register PBSET (0x6C) ............................................................................... 123

10.2.25 PB port clear set register PBCLR(0x70) ............................................................................... 124

10.2.26 PC port data set register PCSET (0x74) ................................................................................ 124

10.2.27 PC port clear set register PCCLR(0x78) ............................................................................... 125

10.3 GPIO operation procedure .................................................................................................................... 125

11 External Interrupt Controller................................................................................................................................. 125

11.1 Introduce ............................................................................................................................................... 125

11.2 Register Description.............................................................................................................................. 126

12 KBI................................................................................................................................................................ 128

12.1 Feature................................................................................................................................................... 128

12.3 KBI operation steps............................................................................................................................... 129

13 UART............................................................................................................................................................ 129

13.1 Introduce ............................................................................................................................................... 129

13.3 UART Data Receiving and Sending Procedure..................................................................................... 133

14 ISO7816 ........................................................................................................................................................ 134

14.1 Introduce ............................................................................................................................................... 134

14.3 7816 and ESAM communication steps ................................................................................................. 144

14.4 7816 and card communication steps ..................................................................................................... 144

15 IIC Interface .................................................................................................................................................. 144

15.1 Overview............................................................................................................................................... 145

15.2 Register Descriptions ............................................................................................................................ 145

16 SPI Interface.................................................................................................................................................. 148

16.1 Overview............................................................................................................................................... 148

16.2 Descriptions of Functions ..................................................................................................................... 148

16.3 Register Descriptions ............................................................................................................................ 150

17 Option Byte ................................................................................................................................................... 152

17.1 Chip Protection Settings........................................................................................................................ 153

17.2 WDT Setting ......................................................................................................................................... 153

17.3 RTC Setting........................................................................................................................................... 154

18 Programming Support ................................................................................................................................... 155

18.1 Overview............................................................................................................................................... 155

18.2 Flash Protection Mechanisms................................................................................................................ 155

18.3 In System Programming (ISP) .............................................................................................................. 156

18.3.1 ISP Communications Protocol ...................................................................................................... 156

18.3.2 The Used Resources...................................................................................................................... 157

18.3.3 ISP Command ............................................................................................................................... 157

18.3.4 ISP Return Code............................................................................................................................ 162

18.4 In-Application Programming (IAP) ...................................................................................................... 163

18.4.1 IAP Command............................................................................................................................... 164

18.4.2 IAP Instructions............................................................................................................................. 164

18.5 Production Platform .............................................................................................................................. 164

19 Package size and soldering conditions .......................................................................................................... 165

19.1 Package size .......................................................................................................................................... 165

19.2 Reflow oven temperature setting conditions ......................................................................................... 172

1 Overview

1.1 SummaryRN8318 Integrated ARM Cortex-M0 core, 512KB Flash, 32KB SRAM, independent power supply hardware

temperature compensation RTC and LCD support 8*36/6*38/4*40. Packaging LQFP128, typical application fields: State Grid 698 protocol three-phase meter (using LCD) and overseas high-end three-phase meter.

RN8615 Integrated ARM Cortex-M0 core, 512KB Flash, 32KB SRAM, independent power supply hardware temperature compensation RTC and LCD support 8*30/6*32/4*34. Packaging LQFP100, typical application fields:State Grid 698 protocol single-phase meter (using LCD), State Grid 698 protocol three-phase meter (not using LCD)and overseas high-end single three-phase meter.

RN8613 Integrated ARM Cortex-M0 core, 256KB Flash, 32KB SRAM, independent power supply hardware temperature compensation RTC and LCD support 8*30/6*32/4*34. Packaging LQFP100, typical application fields:State Grid 698 protocol single-phase meter (using LCD) and overseas high-end single three-phase meter.

RN8612 Integrated ARM Cortex-M0 core, 128KB Flash, 8KB SRAM, 32KB EEPROM, independent power supply hardware temperature compensation RTC and LCD support 8*30/6*32/4*34. Packaging LQFP100, typical application fields: South Grid meter and overseas single-phase meter.

RN8611 Integrated ARM Cortex-M0 core, 256KB Flash, 32KB SRAM, independent power supply hardware temperature compensation RTC and not support LCD. Packaging LQFP80, typical application fields: State Grid 698 protocol single-phase meter (not using LCD).

RN8610B Integrated ARM Cortex-M0 core, 128KB Flash, 8KB SRAM, independent power supply hardware temperature compensation RTC and not support LCD. Packaging LQFP64.

1.2 Product FeaturesFundamental Features:

Highly integrated: 32bit ARM M0 CPU+maximum 512KB Flash/32KB SRAM+independent power supply hardware temperature compensation RTC+LCD controller;Wide voltage range: Under typical conditions, voltage range of 2.3V~5.5V ensures the normal operation of CPU;

Under typical conditions, voltage range of 2.7V~5.5V ensures the accuracy of RTC.Under typical conditions, voltage range of 1.8V~5.5V is maintained for the perpetual

calendar time;High performance: Under the condition of 32768 single crystal oscillator, the highest working frequency of CPU is 14.7456MHz (32KHz, 1.8432MHz, 7.3728MHz and 14.7456MHz are optional). Under the condition of 32768 crystal oscillator+external high-frequency crystal oscillator, the highest working frequency of CPU is 29.4912mhz (32KHz, 1.8432MHz, 7.3728MHz, 14.7456MHz and 29.4912MHz are optional).Low power:The power consumption of CPU subsystem at 32KHz is better than 18 A (with cache);The total power consumption of the chip in sleep mode is about 7 A (RTC automatic temperature compensation; Ram to keep; CPU and digital peripherals do not lose power; Interrupt wake up);The typical power consumption in VBAT domain is about 1.5 A.The power consumption of LCD is about , and the constant chip’s is 13uA (resistance series voltage division

mode, including 6COM display power consumption);The power consumption of LCD is about 10 , and the constant chip’s is 18uA (charge pump mode, including

8COM display power consumption);High precison: The second pulse error of RTC in the whole temperature range (-40 ~85 ) is less than 10 ppm;RTC can still guarantee the accuracy of second pulse under the condition of battery power supply.Package typeRN8318 LQFP128RN8613/RN8612 LQFP100RN8611 LQFP80RN8610B LQFP64Processor-related:ARM Cortex-M0 core;RN8318: 512KB FLASH memory; RN8615: 512KB FLASH memory;RN8613/RN8611: 256KB FLASH memory; RN8612/RN8610B:128KB FLASH memory;RN8612/RN8610B supply 8KBytes SRAM (all open to users);RN8612/RN8610B supply 32KBytes EEPROM, supporting word programming (not byte programming), 1 million programming cycle;Other series provide 32kbytes SRAM, of which 2kbytes is used as Cache;Single-cycle multiplier(32bit*32bit);System timer is embedded in the CM0;Support for external interrupts and other ways to wake up;Complete hardware and software for the integrated development environment is provided.

RTC:Hardware’s automatic temperature compensation, precision and power consumption meet the national standard,and CPU is not required to participate in the temperature compensation;Accurate 1Hz output under battery power supply;Temperature Sensor: Provide accurate temperature, temperature measurement accuracy is ±1 in the range of -25 ~70 ;RTC perpetual calendar and automatic temperature compensation circuit are powered by VBAT pin independently;The typical power consumption in VBAT domain is better than 1.5 A;The opening temperature compensation time is about 2ms, and the typical power consumption of temperature is

A.LCD:RN8318: 4*40, 6*38 and 8*36;RN8615/RN8613/RN8612: 4*34, 6*32 and 8*30;RN8612 only supports resistance voltage division mode. Other series support ChargePUMP and built-in resistance column voltage division mode. 6COM/3V screen is recommended under resistance column voltage division mode;If you need to support more segments, you can choose 8COM/5V screen (Charge pump mode); if you need lower display power consumption, you can choose 6COM/3V screen (resistor series voltage sharing mode). Both are compatible in hardware, just change the software configuration;The power sonxumption of LCD module is better than (resistor series voltage division scheme).

Other peripherals

High speed GPIO, supports interface of peripheral devices with different voltage: RN8318: 93; RN8615/RN8613/RN8612: 64; RN8611: 65; RN8610B: 50;10bit ADC: Temperature sensor / battery voltage detection / generic ADC time division multiplexing;Voltage detecting LVD: chip supply voltage detection; external voltage detection.Two low power comparators CMP: external voltage detection.Extended timer: two 32bit timers.UART 6, supporting automatic baud rate, supporting infrared modulation, supporting UART wakes up,supporting level reversal.7816 port:2.I2C:1.SPI:1.Hardware watchdog.Button Interrupts: 8, pin multiplexing.External interrupts: 8, pin multiplexing.

Encryption:Hardware true random number generator meets U.S. NIST FIPS140-2 standard;AES128/192/256 hardware encryption meets the FIPS197 standards, supporting EBC/CBC/CTR/GCM/GMAC mode;ECC192 hardware accelerators;RN8612 does not support encryption;Encryption documentation refers to Renergy application notes.

Renergy MCU model division:MCU series FLASH RAM EEPROM Encrypting PackagingRN8318 512KB 32KB X Y LQFP128RN8615 512KB 32KB X Y LQFP100RN8613 256KB 32KB X Y LQFP100RN8611 256KB 32KB X Y LQFP80RN8612 128KB 8KB 32KB X LQFP100RN8610B 128KB 8KB 32KB X LQFP64

Table of dofferences between RN8612 and RN8613/RN8615:RN8612 RN8613/RN8615

FLASH 128KB 256KB/512KBRAM 8KB (All for customers) 32KB (30KB for customers,2KB for cache)EEPROM 32KB NoneEncryption None Yes

Only resistor partial voltage is supported, not 5V screen, 6COM 3/3.3v screen is recommended.

Support two ways of resistance partial voltage and charge pump

Pin definition differences

PIN50/51 is NC.PIN50/51 is LCDVP2 and LCDVP1, LCD needs to be connected with 100nF capacitor in series when using charge pump mode, and can be

suspended when using resistance series partial voltage mode.

SIG/IO is a multiplexing pin, when used as IO port, it is a common IO port structure.

SIG/IO is a multiplexing pin, when used as IO port, it is an open-leak structure.

PIN10~PIN13 is NC. PIN10~PIN13 is P104~P107.Note: RN8612 is compatible with RN8613/RN8615 pins, the main differences are shown in the table above.

1.3 Implementation architecture

32.768KHz

7MHz~30MHzoptional

System WideResources

Clock system

POR/BOR

1.8V LDO

Power system

3.6V battery

LCD driver

Memory System

System Bus

128/256/512KBFLASH

8/32KBRAM

CPU System

Cortex M0CPU

InterruptController

MemoryController

Program & Debug

Program

6 UART

Digital System

2Timer/PWM

SPI I2C7816

KEY GPIOLCD control

X X X X X X X X X

XXXXXXXXXXXX

TemperatureSensor

10bit SAR ADC LOSC

CalendarSAR controller

VBAT power domain

Key/IO

32.768KHz

1.8V LDO

Power monitoring

Encryption

Coprocessor

Fig 1.1. The Structure Diagram of RN Series MCU

1.4 Pin Configuration

RN8318

Fig 1.2. RN8318 Pin ConfigurationNote:VBAT domain pins:VBAT, LDO_VBAT, REFV, P56, P44, P45, GND_VBAT, XO and XI.Note that the pin P56/P44/P45 output a high level equal to the VBAT voltage.The pin in red is the pin that is different from RN8318 and RN8312.

Renergy

RN8612/8613/8615

Fig 1.3. RN8612/RN8613/RN8615 Pin Configuration

Note:1.VBAT domain pins: VBAT, LDO_VBAT, REFV, P56, P44, P45, AGND_VBAT, DGND_VBAT, XO and XI.2.Note that the pin P56/P44/P45 output a high level equal to the VBAT voltage.3. PIN50/51 of RN8612 is NC, and PIN50/51 of RN8613/RN8615 is LCDVP2/LCDVP1.4.The multiplexing pin SEG / IO of rn8613 / 8615 is an open drain structure when used as an IO port, and rn8612 is a common structure.5.PIN10~PIN13 of RN8612 is NC, PIN10~PIN13 of RN8613/RN8615 are P104~P107 ports.

Fig 1.4. RN8611 Pin Configuration

Note:1.VBAT domain pins: VBAT, LDO_VBAT, REFV, P56, P44, P45, AGND_VBAT, DGND_VBAT, XO and XI.2. Note that the pin P56/P44/P45 output a high level equal to the VBAT voltage.3. The total red font pins in the above figure are an open drain structure when used as IO port. If the output is high level, pull-up resistance shall be added.

RN8611LQFP80

Renergy

RN8610B

Fig 1.5. RN8610B Pin ConfigurationNote:1. RN8610B IO port marked with red font is a common structure, not an open drain structure.2.VBAT domain pins: VBAT, LDO_VBAT, REFV, P56, P44, P45, AGND_VBAT, XO and XI.3. Note that the pin P56/P44/P45 output a high level equal to the VBAT voltage.

Pin Type Description:

Type A B I O U STTL/CMOS

OpenDrain

MDrive

PBUS6 6mA

PBULD3 3mAPABULD

PABUS3 3mAPUXI

PBUSG3 3mAPAM

Pin Description: RN8612

RN8613

RN8615

RN8318 RN8611 RN8610B Name FeaturesFunction Description

1 1 1 64 SWDCLK/P24/RX2 PBULD3 SWD clock, P24 port and RX2input multiplexing pin.

2 2 2 1 SWDIO/P25/TX2 PBULD3 SWD data port, P25 port and TX2input multiplexing pin.

3 P13/KEY3/TC0_P[1]/TCIN PBULD3 IO port, KEY input, timer output and input multiplexing; Pull up optional, TTL/CMOS level optional, open drain optional.

4 P33/ INT3/ TCIN PBUS6 P3 port and external interrupt timer reuse; Pull up optional,schmidt input and 6mA drive capability.

3 5 3 2 LDO18 Source The output of built-in 1.8V LDO shall be connected with external

capacitor decoupling.4 6 4 3 P00/AIN0/KEY2/RX2 PABUS3 P00 port, SAR-ADC input, KEY2

and RX2 multiplexing pins.5 7 5 4 P01/AIN1/KEY3/TX2 PABUS3 P01 port, SAR-ADC inoput,

KEY3 and TX2 multiplexing pins.6 8 6 5 AIN2/CMP1/P02 PABUS3 SAR-ADC input, comparator 1

input, P02 multiplexing.7 9 7 AIN3/CMP2/P03 PABUS3 SAR-ADC input, low power

comparator 2 input, P03 multiplexing.

8 10 8 AIN4/LVDIN0/P04/KEY4 PABUS3 SAR-ADC input, LVDIN input,P04 and KEY4 multiplexing.

9 11 9 6 RSTN Reset External reset pin, built-in about 50K pull-up resistor.

10 12 10 P104 PBUS6 P104 port, pull-up optional, schmidt input, 6mA drive capability.

11 13 P105 PBUS6 P105 port, pull-up optional, schmidt input, 6mA drive capability.

16 P117 PBULD3 P117 port, pull-up optional, schmidt input, 6mA drive capability.

14 17 11 7 AGND Ground Analog ground.15 12 VCC Source 2.3V~5.5V power source input

should be connected with capacitor in parallel and 0.1capacitor decoupling (same as 16 feet).

18 NC Not connect16 19 12 8 VCC Source 2.3V~5.5V power source input

should be connected with capacitor in parallel and 0.1capacitor decoupling.

17 20 13 9 VBAT Source 3.6V battery or super capacitor input pin; only supply power to RTC part. At the same time, it is also the input of SARADC. When measuring the pin, there are two 300K resistances in the pin for voltage division, and the gain is 0.5 times. It is suggested to

18 21 14 10 LDO_VBAT Source LDO output in VBAT domain, external needscapacitance.

19 22 15 11 REFV Reference voltage

SARADC’s built-in reference output, external needs to connect

.20 23 16 12 P56/RTCOUT/TCI/TC1_N[

1]PBULD3 P56, RTCOUT and TCIO

multiplexing.The multiplexing relationship of RTCOUT is determined by RTC chapter register, independent of

GPIO chapter multiplexing configuration register. When VCC is not powered on and VBAT is powered on, the pin outputs 1Hz by default. Once the VCC is powered on, the 1Hz output is turned off.

21 24 17 13 P44/AIN5/KEY6 PABULD3

P44, AIN5 and KEY6multiplexing. If you want to use the AIN5, you need to configure the ANA_ PAD (Chapter 9) register.

22 25 18 14 P45/AIN6/KEY7 PABULD3

P45, AIN6 and KEY7multiplexing.AIN6 can directly measure the input 3.6V signal, similar to the measurement of VBAT pin voltage by SAR_ADC. When the measurement is started, two 300K resistors are used internally to divide 3.6V to 1.8V. If you want to use the AIN6 function, you need to configure the ANA_PAD(Chapter 9) register.

23 26 19 15 AGND_VBAT Ground VBAT domain analog ground.24 DGND_VBAT Ground VBAT domain didital ground.25 27 20 16 XO Clock 32.768KHz passive crystal output

and input;Should be isolated by ground wire,external resistor and capacitor are not needed; recommend to select a crystal with a load capacitance of 12.5pF.

26 28 21 17 XI Clock

29 P14/KEY4/TC1_N[0]/TCIN PBULD3 IO port, key input, timer outputand timer input multiplexing.Pull up optional, TTL/CMOS level optional, open drain optional.

30 P15/KEY5/TC1_P[0]/TCIN PBULD3 IO port, key input, timer outputand timer input multiplexing;Pull up optional, TTL/CMOS level optional, open drain optional.

31 P16/KEY6/TC1_N[1]/TCIN PBULD3 IO port, key input, timer outputand timer input multiplexing.

Pull up optional, TTL/CMOS level optional, open drain optional.

32 P17/KEY7/TC1_P[1]/TCIN PBULD3 IO port, key input, timer outputand timer input multiplexing;Pull up optional, TTL/CMOS level optional, open drain optional.

27 33 22 18 DGND Ground Digital ground34 23 P110/SPI-SCSN PBULD3 P11 port and SPI multiplexing35 24 P111/SPI-SCLK PBULD3 SPI of P11 port and SPI of P4 port

cannot be used simultaneously.36 25 P112/SPI-MISO PBULD3 Pull up optional, TTL/CMOS level

optional, open drain optional.37 26 P113/SPI-MOSI PBULD3 Pull up optional, TTL/CMOS level

optional, open drain optional.38 27 P114 PBULD3 P114 port, pull up optional,

TTL/CMOS level optional, open drain optional.

28 39 28 19 P46/SPI_ MISO/RX4 PBULD3 P4 port, SPI and UART4multiplexing.

29 40 29 20 P47/SPI_MOSI/TX4 PBULD3 Pull up optional, TTL/CMOS level optional, open drain optional.

41 NC Not connect.42 P97/SEG35 PBUSG3 LCD/GPIO multiplexing.43 P96/SEG34 PBUSG3 LCD/GPIO multiplexing.

30 44 P95/SEG33 PBUSG3 LCD/GPIO multiplexing.31 45 P94/SEG32 PBUSG3 LCD/GPIO multiplexing.32 46 P93/SEG31 PBUSG3 LCD/GPIO multiplexing.33 47 DGND Ground Ground.34 48 21 P92/SEG30 PBUSG3 LCD/GPIO multiplexing.35 49 22 P91/SEG29 PBUSG3 LCD/GPIO multiplexing.36 50 23 P90/SEG28 PBUSG3 LCD/GPIO multiplexing.37 51 24 P87/SEG27 PBUSG3 LCD/GPIO multiplexing.38 52 25 P86/SEG26 PBUSG3 LCD/GPIO multiplexing.39 53 30 26 P85/SEG25 PBUSG3 LCD/GPIO multiplexing.40 54 31 27 P84/SEG24 PBUSG3 LCD/GPIO multiplexing.41 55 32 28 P83/SEG23 PBUSG3 LCD/GPIO multiplexing.42 56 33 29 DGND Ground LCD/GPIO multiplexing.43 57 34 30 P82/SEG22 PBUSG3 LCD/GPIO multiplexing.44 58 35 31 P81/SEG21 PBUSG3 LCD/GPIO multiplexing.45 59 36 32 P80/SEG20 PBUSG3 LCD/GPIO multiplexing.46 60 37 P77/SEG19 PBUSG3 LCD/GPIO multiplexing.47 61 38 P76/SEG18 PBUSG3 LCD/GPIO multiplexing.48 62 39 P75/SEG17 PBUSG3 LCD/GPIO multiplexing.

49 63 40 P74/SEG16 PBUSG3 LCD/GPIO multiplexing.64 DGND Ground Ground

50 65 LCDVP2 Analog Analog output, 100nF capacitor should be connected between LCDVP2 and LCDVP1.LCD can be suspended if the use of resistance partial voltage.

51 66 LCDVP1 Analog Analog output, 100nF capacitor should be connected between LCDVP2 and LCDVP1.If LCD uses the resistance voltage division mode, it can be suspended.

52 67 LCDVA Analog LCD voltage output requires external 470nf capacitor. Nomatter charge pump or resistance voltage division mode is used, this capacitor needs to be connected externally.

53 68 LCDVB Analog LCD voltage output requires external 470nf capacitor. No matter charge pump or resistance voltage division mode is used, this capacitor needs to be connected externally.

54 69 LCDVC Analog LCD voltage output requires external 470nf capacitor. No matter charge pump or resistance voltage division mode is used, this capacitor needs to be connected externally.

55 70 LCDVD Analog LCD voltage output requires external 470nf capacitor. No matter charge pump or resistance voltage division mode is used, this capacitor needs to be connected externally.

71 DGND Ground Ground56 72 41 33 P52/SCL/TCIN/TC0_N[1] PBULD3 P5 port, I2C and TCIO

multiplexing.57 73 42 34 P53/SDA/TCIN/TC0_P[1] PBULD3 Pull up optional, TTL/CMOS level

optional, open drain optional.58 74 43 35 P54/RX5/TCIN/TC1_N[0] PBULD3 P54, UART5 input and TCIO

multiplexing.

59 75 44 36 P55/TX5/TCIN/TC1_P[0] PBULD3 P55, UART5 output and TCIOmultiplexing.

60 76 45 37 P40/7816CLK/INT1 PBULD3 IO port, 7816 and interrupt port multiplexing pin.

Pull up optional, TTL/CMOS level optional, open drain optional.Notes: supports two interfaces of 7861.78160_IO is bidirectional data port of 7816 0.78161_IO is bidirectional data port of 7816 1.

Besides,7816 1 can be configured by register as follows:78161_IO as 7816 1 data output;78161_I as 7816 1 data input.

61 77 46 38 P41/78160_IO/INT3 PBULD378 P115 PBULD3 P115 port.

62 79 47 39 P42/78161_IO/INT4 PBULD380 P116 PBULD3 P116 port.

63 81 48 40 P43/78161_I/INT5 PBULD364 82 49 41 DGND Ground Ground.65 83 50 42 P20/RX0 PBULD3 UART port and P2 port

multiplexing.66 84 51 43 P21/TX0 PBULD3 Pull up optional, TTL/CMOS level

optional, open drain optional.85 DGND

67 86 52 44 P22/RX1 PBULD3 UART port and P2 port multiplexing.

68 87 53 45 P23/TX1 PBULD3 Pull up optional, TTL/CMOS level optional, open drain optional.

69 88 54 P73/SEG15 PBUSG3 LCD/GPIO multiplexing.70 89 55 P72/SEG14 PBUSG3 LCD/GPIO multiplexing.71 90 56 P71/SEG13 PBUSG3 LCD/GPIO multiplexing.72 91 57 P70/SEG12 PBUSG3 LCD/GPIO multiplexing.73 92 58 46 P67/SEG11 PBUSG3 LCD/GPIO multiplexing.74 93 59 47 P66/SEG10 PBUSG3 LCD/GPIO multiplexing.

94 P103/SEG39 PBUSG3 LCD/GPIO multiplexing.95 P102/SEG38 PBUSG3 LCD/GPIO multiplexing.

75 96 60 48 P37/INT7/HOSCI PUXI P3/interrupt port/high-frequency crystal multiplexing

76 97 61 49 P36/INT6/HOSCO PUXI high-frequency crystal port should connect a 10Mresistor in serial and 2 15pf capacitors in parallel.

98 P101/SEG37 PBUSG3 LCD/GPIO multiplexing.77 99 P65/SEG9 PBUSG3 LCD/GPIO multiplexing.78 100 50 P64/SEG8 PBUSG3 LCD/GPIO multiplexing.79 101 62 51 P63/SEG7 PBUSG3 LCD/GPIO multiplexing.80 102 63 52 P62/SEG6 PBUSG3 LCD/GPIO multiplexing.81 103 64 53 P61/SEG5 PBUSG3 LCD/GPIO multiplexing.82 104 65 54 P60/SEG4 PBUSG3 LCD/GPIO multiplexing.83 105 66 55 DGND Ground Ground.84 106 SEG3/COM7 PAGM SEG/COM multiplexing port.85 107 SEG2/COM6 PAGM SEG/COM multiplexing port.86 108 SEG1/COM5 PAGM SEG/COM multiplexing port.87 109 SEG0/COM4 PAGM SEG/COM multiplexing port.88 110 COM3 PAM COM port.89 111 COM2 PAM COM port.90 112 COM1 PAM COM port.91 113 COM0 PAM COM port.

114 P100/SEG36 PBUSG3 LCD/GPIO multiplexing.92 115 67 56 P10/KEY0/TC0_N[0]/TCIN PBULD3 IO/KEY input/timer input output

multiplexing;Pull up optional, TTL/CMOS level optional, open drain optional.

93 116 68 57 P11/KEY1/TC0_P[0]/TCIN PBULD3 IO/KEY input/timer input output multiplexing;Pull up optional, TTL/CMOS level optional, open drain optional.

117 69 P12/KEY2/TC0_N[1]/TCIN PBULD3 IO/KEY input/timer input output multiplexing;Pull up optional, TTL/CMOS leveloptional, open drain optional.

94 118 70 58 P30/INT0/ TCIN/ TX4/ ISPEN

PBUS6 IO/external interrupt input and timer input multiplexing.Pull up optional, Schmitt input, 6mA drive capability. After the reset, the bootrom will detect the status of the port. If the low level is input, the system will enter the ISP. This problem should be paid attention to in practical application.

119 71 P31/ INT1/TCIN/ RX4 PBUS6 IO port, external interrupt input,

timer input, RX4 multiplexing;95 120 72 59 P32/ INT2/ RTCOUT /

KEY5PBUS6 IO port, external interrupt input,

timer input multiplexing;Pull up optional, Schmitt input, 6mA drive capability.

96 121 73 60 P26/RX3 PBULD3 UART/P2 multiplexingPull up optional, TTL/CMOS level optional, open drain optional.

97 122 74 61 P27/TX3 PBULD3 UART3/P2 multiplexing;Pull up optional, TTL/CMOS level optional, open drain optional.

123 75 P57/TCIN/TC1_P[1] PBULD3 P57 port and TC input multiplexing

98 124 76 62 P51/QF/RTCOUT/SPI_SCLK/SF2

PBUS6 P51 port, QF, RTC output,SPI_SCLK and SF2 multiplexingPull up optional, Schmitt input, 6mA drive capability.PF is the direct output after INT0 input;SF2 is the direct output after INT7input;This function is used to input the pulse from the metering chip and then output it directly for verification.

99 125 77 63 P50/PF/RTCOUT/SPI_SCSN/SF1

PBUS6 P50 port, PF, RTC output,SPI_SCSN and SF1 multiplexingPull up optional, Schmitt input, 6mA drive capability.PF is the direct output after INT2input;SF1 is the direct output after INT6input;This function is used to input the pulse from the metering chip and then output it directly for verification.

126 78 P34/INT4 PBUS6 P34 and external interrupt multiplexing pin.

127 79 P35/ INT5/ TCIN PBUS6 P35, external interrupt and timer input multiplexing.Pull up optional, Schmitt input, 6mA drive capability.

100 128 80 DGND Ground Ground.

Key Pin Description:1. AGND is analog ground, DGND is digital ground, which can be rationally distributed according to the actual use

experience.

2. LDO18 .

3. REFV is the reference input of SAR-ADC and should be connected with 0.22muon capacitor externally.

4. VBAT is 3.6V battery or super capacitor input pin: suggest external RC filter, R: 10 , C: 1 F.

5. VCC is the main power input, the normal operating range 2.3V~5.5V, external connects both 4.7uf capacitor and

0.1uf capacitor for decoupling.

6. LDO_VBAT: VBAT domain LDO output, which should be connected external 0.22 f capacitor.

7. 32.768KHz crystal connects crossover between XO and XI, which should be isolated by the ground wire, external

resistors and capacitors are not necessary.

8. LCDVD, LCDVC, LCDVB and LCDVA is the voltage output of LCD, which should be connected external 470nf

capacitor.

9. LCD CHARGEPUMP mode a 100nf capacitor should be connected between LCDVP1 and LCDVP2; internal

resistance column mode: LCDVP1 and LCDVP2 can be suspended, or LCDVP1 suspended and LCDVP2

grounded.

10. In addition to RN8612/RN8610B, when SEG/IO multiplexing pin is used as IO port, it is an open drain structure,

and the output must be connected with external pull-up.

11. When measuring the input voltage of VBAT pin and AIN6 pin, there are two 300K resistors in the internal part as

voltage divider, and the input voltage will be reduced by half and input to SAR_ADC.12. When P36 and P37 are used as IO ports, they can only be used as input pins, not as output13. P56/p44/P45 pin is in the VBAT power domain, and the output high level is equal to VBAT.

1.5 IO Port Function Block Diagram

2 Electrical CharacteristicsPower Sources(temperature range:-40 +85 )

Main source VCC2.4 5/3.3 5.5 V Recommend to choose

5V±5% or 3.3V±5% as main source

Minimum CPU operating voltage

Vil2.2 2.3 2.4 V Full temperature range

VBAT power supply

2.5 3.6 5.5 V Normal operation of RTC temperature compensation circuit, voltage operation range guaranteed by RTC accuracy.

1.8 3.6 5.5 V RTC calendar turns normally, temperature compensation circuit is not guaranteed.

Digital current DIdd 2.2 mACPU operating at 3.6864MHz (PLL)

VCC sleep power consumption

SIdd 5.5 A

RAM hold; CPU and digital peripherals are power on; WDT open; Source monitor open; interrupt wake up;Typical conditions: Vcc=3.6V; Tc= 25

VBAT power consumption

SIdd 1.5 2 uA

Typical conditions : Vbat=3.6V; Tc=25Limit conditions:Vbat=3.6V; Tc=85

Instantaneous temperature compensation power consumption

TPSIdd 300 uATypical conditions : Vbat=3.6V;Tc=25 ;

LDO18 V1P8 1.62 1.8 1.98 VCPU core voltage, full temperature range 10%.

Limit Parameters(temperature range:-40 +85 )Main source voltage Vvcc -0.3 -- 7 VBattery input voltage Vvbat -0.3 -- 7 V

DVDD to DGND -0.3 -- 7 VDVDD to AVDD -0.3 +0.3 VDigital IO output high voltage

VOH -- VCC+0.3

Digital IO output low voltage

VOL -0.3 --V

Digital IO input high voltage

VIH 0.7VCCCMOS

Digital IO input low voltage

VIL 0.3VCCCMOS

Digital IO input high voltage

VIH 0.4VCCTTL

Digital IO input low voltage

VIL 0.2VCCTTL

Isource of digital IO Isource 5 10 mA 6mA TypeIsink of digital IO Isink 7 15 mA 6mA TypeIsource of digital IO Isource 3 5 mA 3mA TypeIsink of digital IO Isink 5 10 mA 3mA TypeAnalog input voltage with respect to AGND

VINA -0.3 -- AVDD

Operate temperature range

TA -40 -- 85

Storage Temperature Range

Tstg -65 -- 150

Reference Voltage(VCC=3V~5.5V, temperature range:-40 +85 )

min. typ. max. unit NotesOutput Voltage Vref 1.25 1.26 1.27 VTemperature Coefficient Tc 5 15 ppm/

Analog Peripherals (temperature range:-40 +85 )Low power comparatorCMP1/CMP2/LVDINThreshold ViL1

CMP 1.23 1.28 1.33 V

In the default configuration, the threshold is the comparator output low level comparison result threshold. The threshold value of the output high level comparison result is 220mv higher than the threshold value.

Low power comparatorCMP1/CMP2/LVDINThreshold ViL2

CMP 0.8 0.84 0.88 V

When 0.9V is selected and hysteresis is selected, the threshold is the comparator output

low level comparison result threshold; the output high level comparison result threshold is 140mv higher than the threshold.

SAR ADC input rangeSAR-IN

0 BGR VBGR is the internal reference voltage, typical value is 1.26V.

LCD output voltageLCDV

D4.85 5 5.15 V

5V charge pump, full temperature range test.

LCD output voltageLCDV

D3.135 3.3 3.465

3.3V resistor series voltage division, full temperature range.

VBAT measureVBATD

0 3.6 5 V

3.3V resistor series voltage division, full temperature range SAR ADC to Vbat pin voltage measurement range.

Time of each temperature compensation

Ttps 2 ms

Clock Parameters(temperature range:-40 +85 )Clock frequency range at low-frequency input

XI 32.768 KHz

Clock frequency range at high-frequency input

HOSI 3.6864 7.3728 29.4912 Mhz

Internal PLL clock frequency range

PLL 7.3728 14.7456 MHz

Internal high frequency RCH

RCH 2.8 3.2 3.6 MHz Default clock after chip reset

Internal low frequency RCL

RCL 20 32.768 40 KHzClock for WDT

Measuring project

Name Test condition Value Unit

electrostatic discharge

Human body model (HBM), according to standard JEDEC EIA/JESD22-A114, on all pins.

4000 V

Mechanical model (MM), according to standard JEDEC EIA/JESD22-A115C, on all pins

Charger device model (CDM), according to standard JEDEC EIA/JESD22-C101F, on all pins

Latch up test LatchUP

According to the standard JEDEC STANDARD NO.78D NOVEMBER 2011, it is carried out on all pins

200 mA

Humidity sensitivity

MSDEvaluated according to the standard IPC/JEDEC

J-STD-020D.13 level /

3 System Control

3.1 Power Domain Division

Reset circuit

Core and peripheral

1.8V Analog

Calendar1.8V Digital

Aut Tem Com

SAR Controller

Key IO

Power Monitor

Tem Sensor

SAR ADC

Fig 3.1 Internal power managementVCC and VBAT are powered independently, RTC related circuits (32768 crystal oscillator/perpetual

calendar/automatic temperature compensation circuit, etc.), SAR-ADC measurement related circuits, P44/P45/P56 are powered by VBAT, CPU system and other peripherals are powered by VCC.

In practical application, VCC or VBAT can be connected to supply power together or independently. The typical working range of VCC is 2.3V~5.5V, and the typical working range of VBAT is 2V~5.5V.

Note that the three IO ports P44, P45 and P56 are powered by VBAT, the output high level is equal to VBAT, the input high level cannot be higher than VBAT, and meet the requirements of VIH level (0.7 * VBAT). If only VBAT is powered on, VCC does not power on to initialize VBAT domain. Port P56 outputs 1Hz by default. Once VCC finishes power on to initialize VBAT domain, port P56 returns to default high resistance state.

Because some configuration registers (crystal oscillator parameter setting, etc.) of RTC module need to be configured by CPU during power on initialization (bootloader calls parameters in flash option bytes, and these parameters are written by customers in mass production programming), it is necessary to ensure that the configuration parameters can be written normally. If VBAT power on is too slow, when VCC power on initializes the configuration of VBAT, VBAT is not ready, so the temperature compensation parameters cannot be written normally. It is recommended that CPU software manages VBAT domain configuration register effectively, and calls Reenergy library function to do secondary configuration for relevant registers, so as to ensure that configuration parameters are written correctly.

CPU can read bit9 of system reset register SYS_RST(0x14), and know whether VBAT domain power supply is normal and whether power failure has occurred.

3.2 Clock SourceTwo external clocks:LOSC: external 32.768KHz crystal oscillator, used for RTC clock and CPU clock under low frequency operation,

never shut down. 32.768KHz crystal oscillator does not need external capacitance and resistance, and the chip has been built-in. It is recommended to select 12.5pF external crystal oscillator.

HOSC: external high-frequency crystal oscillator can support external 7.3728MHz, 14.7456MHz, 29.4912MHzcrystal oscillator.

Three internal clocks:RCH: internal high-frequency RC clock (typical value is 3.2MHz). After the CPU is powered on and reset, the

clock defaults to RCH; RCH can choose 1/2 frequency division or not.RCL: internal low frequency RC clock, used for WDT clock, CPU clock and LCD clock under battery power

supply.PLL: internal PLL clock, multiplying 32.768KHz to 7.3728MHz or 14.7456MHz.Low frequency operation mode can be selected as LOSC or RCL.LCD clock can be selected as LOSC or RCL.The above four clock sources can be used for CPU main system clock.In the operation mode, the clock source can be PLL or high frequency crystal oscillator.CPU switches from low frequency clock to high frequency clock by instructions. The system master clock can be switched between RC, PLL (or HOSC) and LOSC clocks. In order to ensure the clock accuracy, PLL or external high frequency clock shall be selected as the main clock of the system under normal operation mode.For clock switching, users must call Renergy library function. Users should not write to the OSC_ CTL1 (0x0) and SYS_Mode (0x4) registers in the application program. If write operation is performed on OSC_CTL2(0x10),only the bit bit to be operated shall be changed, and the value of other register bits shall not be changed.

Internal RC3.2MHz

CrystalOscillator

X XOSCI OSC

Internal RC of clock source: 1.6MHz

32.768KHz

PrimaryCrystal

Oscillator

X XPOSCI

High frequencycrystal

oscillator

Fre_Dou

Internal system clock

Clock source PLL: 14.7456MHz

low frequency crystal oscillator:

Encryption Timer Coproce

Internal RC32KHz

Not be closed

CPUWake-

upHighest frequency crystal:

System internal clock

3.3 Clock SwitchInclude switchings as follows:

1. Default is RCH after reset;2. PLL and RCH switching, completed by CPU instructions;3. PLL and LOSC/RCL switching, completed by CPU instructions;4. LOSC/RCL and RCH switching, completed by CPU instructions.

Please call the library function provided by Renergy to complete clock switching.If external high-frequency crystal HOSC is selected as system main clock, OSC_CTL2 register should be configured before calling library function.If PLL is selected as system main clock at first power-on, calling the clock switching library function need to wait for 32KHz crystal oscillator start-up (start-up time is approximately 0.5s).

Library function clock switching diagram

Detecting parameter correctness

Get the current clock frequency

Set the EEPROM FLASH operation

wait time according to the clock

frequency to be switched.

Return clock switch failed, exit function

Waiting for EEPROM FLASH is not busy

Check if switching to

Check if LOSC starts to vibrate

Switch to LOSC and turn off RC, PLL and

Start up

YES Check if you switch to RC

Check if switching to 3.2MHz high frequency RC

Configure RC to high frequency mode

Turn on the RC clock

Check if the RC clock starts to

vibrate

Switch clock to RC and turn off PLL and

Start up

Turn on the RC clock

Check if the RC clock starts to

vibrate

Clock switch to RC

Check if switching to PLL

Check if LOSC starts to vibrate

Open HOSC

No (switch to PLL or HOSC)

Start up

Waiting for 10ms

Check if HOSC starts to vibrate

Switch to HOSC and turn off RC

Start up

No (switch to HOSC)

Flag clock switch failed

Mark clock switch failed

Unstarted

Return clock switch result, exit function

Check if the high frequency PLL is

Configure the PLL to high frequency

Switch clock to PLL and turn off RC

Start up

Unstarted

3.4 MCU Low-power ModeThe low power modes of M0 are Sleep and DeepSleep. The differences between these two instructions are:1. After the CPU runs the Sleep instruction, it will only turn off the CPU core clock, and the peripheral clock needs

a register to turn off (see MODE0 and MODE1);2. After the CPU runs the DeepSleep command, it will not only turn off the CPU core clock, but also automatically

turn off most of the peripheral clocks (see MODE0 and MODE1);It is recommended that the software not distinguish between Sleep and DeepSleep, use Sleep directly, and other

peripheral clocks are closed by program.In addition to the low-power mode of M0 itself, the MCU provides a flexible mechanism to achieve the user's

different power consumption modes:1. The CPU can switch between the high frequency clock mode HCM, the low frequency clock mode LCM and the

system default mode RCH by calling the library function mode;2. The clock of the CPU and peripherals can be turned off;3. In the lowest power mode (CPU sleep, SRAM and digital peripherals are not powered down, RTC operation)

power consumption is about 7uA;

In the lowest power mode (CPU sleep, SRAM and digital peripherals are not powered down, RTC operation) power consumption is about 7uA;

Main Module Default State

1.8V Digital domain (powered from VCC)

M0 core Open, closable clock, never power down

Interrupt system Open, closable clock, never power down

SRAM Open, closable clock, never power down

ROM Open, closable clock, never power down

FLASH Open, automatically power off after CPU sleep

WDT Open, can not be closed

Other peripherals Open, closable clock, never power down

VCC domain

3.3V LDO Close, closable power supply1.8V LDO Open, can not be closedRCL Open, can not be closedRCH Open, can not be closedLCD Close, closable power supplyLVD Close, closable power supplyComparator CMP1 Open ,closable power supplyComparator CMP2 Close, closable power supplyReset circuit Always openPLL Close, closable power supplyHOSC Close, closable power supplyVBAT domainRTC Open, calendar can not be closed, no

resetTemperature measurement ADC

Timing on

LOSC Always openThe default closed modules can be chosen to open or close under the three clocks.

3.5 Reset3.5.1 External PIN resetThe external pin RSTN has a built-in 50K ohm pull-up resistor and the input level are CMOS level. The internal

filter time is 1ms, and resetting occurs when the external input is low for more than 1ms.3.5.2 Power-on and power-off reset

Three power-on reset (POR) circuits and two brown-out reset (BOR) circuits are built to monitor VCC, LDO18 (1.8V LDO) and VBAT, respectively. Among them, there is only POR circuit in VBAT.

The circuit is always active and cannot be turned off to ensure that the system will operate normally when the threshold is exceeded (about 2.6V); below the threshold (about 2.35V), the device is in reset. It is no longer necessary to use an external reset circuit.

This product also has a built-in programmable voltage monitor LVD that monitors VCC and compares it to a set threshold that generates an interrupt when VCC is below or above the threshold.

3.5.3 Software reset The Cotex M0 has a built-in SCB_AIRCR register. Simply set the SYSRESETREQ bit of this register to cause a reset of the entire chip system. The reset effect is equivalent to the external PIN reset. See the M0 documentation for details.

3.5.4 Watchdog resetIf you can't feed the dog within the specified time, or use an illegal command to feed the dog, the built-in hardware

watchdog will reset the entire chip, and the reset effect is equivalent to the external PIN reset.

3.6 Register DescriptionThe base address of system control module:Module Name Physical Address Mapping AddressSYSC 0x40034000 0x40034000Register Name Address Offset DescriptionOSC_CTL1 0x0 System OSC control register1SYS_MODE 0x4 System mode switch registerSYS_PD 0x8 System power down control registerADC_CTL 0xC ADC control registerOSC_CTL2 0x10 System OSC control register2SYS_RST 0x14 System reset registerMAP_CTL 0x18 Address Mapping control registerMOD0_EN 0x1C Module enable 0 registerMOD1_EN 0x20 Module enable 1 registerINTC_EN 0x24 Module enable 1 registerKBI_EN 0x28 INTC enable registerCHIP_ID 0x2C Device ID register

SYS_PS 0x30 System control register password protection bit

IRFR_CTL 0x34 Infrared clock division factor in RCH mode

TRIM_CFG1 0x78 Clock TRIM configuration registerTRIM_START 0x7C Clock TRIM result registerThe 0x00~0x28, 0x34/0x78/0x7C registers can be written only when SYS_PS(0x30)=8’h82

3.6.1 System OSC control register1 OSC_CTL1(0x0)Offset address 0x00

Bit Name Description write/read flag

Resetvalue

31:16 --- Reserve R 0

15:11 CLOCK_FLAGSystem clock open flag: if clock opened, this bit is 1:{HOSC, RCL, RCH, PLL, LOSC}

R 01101

10:8 SYSCLK_STAT

System main clock frequency instruction:000: current system master clock is 7.3728MHz;001: current system master clock is 3.6864MHz;010: current system master clock is 1.8432MHz;011: current system master clock is 32.768KHz;100: current system master clock is 14.7456Mhz;(only support external crystal oscillator)101: current system master clock is 29.4912Mhz;(only support external crystal oscillator)Others reserve

7 PLL_LOCKPLL Lock Status0: Unlocked1: Locked

6 PLL_HOSC_ONSystem operating at external high frequency or internal PLL clock, this bit is 1;System operating at other clocks, this bit is 0.

5 IRCH_ONSystem operating at internal high frequency clock, this bit is 1;System operating at other clocks, this bit is 0.

4 LOSC_ONSystem operating at external low frequency clock, this bit is 1;

System operating at other clocks, this bit is 0.

3:2 PLL_HOSC_DIV

System master clock divide select:(Only valid for high frequency clock mode)00: PLL, HOSC as CPU master clock;01: Two Division of PLL, HOSC as CPU master clock;10: Four division of PLL, HOSC as CPU master clock;11: Eight division of HOSC (clock select as 14MHz and 29MHz) as CPU master clock. Ifthe HOSC is 7.3728MHz or the PLL is selected, it is represented as four-way;Note: Can only be changed under RC or LC mode.Note: These registers only decide division factor, and specific system master frequency is determined by the frequency division factor and current clock source.

R/W 01

1 IRCH_PD1.6MHz internal RC enable bit:0: open; 1: close.

0 PLL_PDPLL module enable bit0: open;1: close.

When users switch clock, it is recommended to call Renergy library functions. And it is not recommended write OSC_CTL1 (0x0) register in applications.

3.6.2 System Mode Setting Register SYS_MODE(0x4)Offset address 0x04

Bit Name Description Read /write flag

Resetvalue

31:6 --- Reserved R 0

5 FLASH_BUSY

Flash busy status, can not enter the mode switch:0: idle1: busy

4 EEPROM_BUSY

eeprom busy status, can not enter the mode switch:0: idle1: busyThis register is only valid for RN8612/RN8610B

3:0 MODE

Write D, set enter high frequency mode HCM,bit2 read is 1;Write E, set enter RC mode RCM, bit1 read is1;Write F, set enter 32.768KHz mode LCM, bit0 read is1.The register read value is:{0, HCM, RCM, LCM}.

Note: The instructions of current mode status should be read from LOSC_ON, IRCH_ON, PLL_HOSC_ON (OSC_CTL register bit4~6) these three status. But not from this register. This register represents the mode switch command is written, which does not mean that has been switched to the desired mode.

When users switch clock, it is recommended to call Renergy library functions. And it is not recommended write SYS_MODE(0x4) register in applications.

3.6.3 System Power Down Control Register SYS_PD(0x8)Offset address 0x08

Bit Name Description Read/write flag

Resetvalue

31:12 --- Reserved R 015 Reserved Reserved R/W 014 Reserved Reserved R/W 013 Reserved Reserved R/W 012 Reserved Reserved R/W 0

11 hysen_cmp2

Cmplp2 internal hysteresis comparator hysteresis switch0x1: Open hysteresis0x0: Close hysteresis

10 hysen_cmp1

Cmplp1 internal hysteresis comparator hysteresis switch0x1: Open hysteresis0x0: Close hysteresis

9 PWD_CMP2R

CMP2 internal 600K resistance sampling switch0: CMP2 internal resistance sampling is turned on, the peripheral circuit needs to pay attention to the internal 600K to ground resistance, the comparator Vil typical value is 1.28V, hysteresis is 0.22V, do not configure bit11 to 1 at this time;1: CMP2 internal resistance sampling is off, the comparator threshold is 0.9V, no hysteresis by default; bit11 can be set to 1 with a hysteresis of 0.14V, and the typical value of Vil is 0.84V;

8 PWD_CMP1RCMP1 internal 600K resistance sampling switch0: CMP1 internal resistance sampling is turned on,

the peripheral circuit needs to pay attention to the internal 600K to ground resistance, the comparator Vil typical value is 1.28V, hysteresis is 0.22V, do not configure bit10 as 1 at this time;1: CMP1 internal resistance sampling is off, the comparator threshold is 0.9V, no hysteresis by default; bit10 can be set to have a hysteresis of 0.14V, and the typical value of Vil is 0.84V;

7 Reserved Reserved R/W 06 Reserved Reserved R/W 0

5 CMP2_PD

Comparator 2(low power comparator)power switch0: power on1: power down

4 CMP1_PD

comparator1 power switch0: power on1: power downNote:RN8211 doesn’t support, it’s reset value shouldn’t be changed;

3 LVD_PDLVD power switch0: power on1: power down

2:0 Reserved Reserve R 0

3.6.4 System OSC Control Register 2 OSC_CTL2(0x10)Offset address 0x10

Reset value

31:15 Reserve Reserve

16 RCH_FREQ

=0: RCH frequency is 1.6MHz in RC mode;=1: RCH frequency is 3.2MHz in RC mode;Remark: This register can only be cleared by power-on and reset.The client should call the library function to select the chip operating frequency and do not change the value of this bit in the application.

15 RCL_LOSC_FLT_SELFilter clock source selection0: Filter clock selection LOSC1: Filter clock selection RCL

14 Reserved Reserved R 013 RCL_LCD =0: LCD selects LOSC external low R/W 0

frequency crystal as the clock source;=1: LCD selects RCL internal low-frequency crystal as the clock source;

12 RCL_STB

=0: Low frequency operation mode LCM selects LOSC external low frequency crystal oscillator as the clock source;=1: Low frequency operation mode LCM selects RCL internal low frequency crystal oscillator as the clock source;This register can only be modified in RC mode or high frequency mode.

11:10 ReservedWritable, internal test register, the user should not change the default value of this register.

R/W 00

9 Reserved Reserved R 08 Reserved Reserved R 0

7:5 PLL_FREQ

The PLL frequency is fixed at 14.7456Mhz, and the frequency is selected by digital frequency division:000: The operating frequency is selected to be 7.3728MHz;001: The operating frequency is selected to be 14.7456Mhz;Other: reservedThe client should call the library function to select the chip operating frequency and do not change the value of this bit in the application.

R/W 000

4 PLL_HOSC_SEL

System master clock selection at full speed:0: Select the PLL output as the system master clock;1: Select the spare high frequency crystal as the system master clock.This configuration item can only be configured in RC mode and low frequency mode.

3 HOSC_PDExternal high frequency oscillator enable bit:0: open1: off

2:0 HOSC_ FREQ

000: external high-frequency crystal oscillator 7.3728MHz 001: external high-frequency crystal oscillator 14.7456MHz010: Reserved

R/W 000

011: External high-frequency crystal oscillator 29.4942MHz

System clock configuration truth table:PLL_HOSC_DIV=00

No frequency division

PLL_HOSC_DIV=01

Two-way

PLL_HOSC_DIV=10

Four-way

PLL_HOSC_DIV=11

Eight-way frequency

PLL_FREQ=000

PLL_HOSC_SEL=0

7.3728Mhz 3.6864MHz 1.8432MHz Does not support

eight-way, if the

configuration is

1.8432Mhz

PLL_FREQ=001

PLL_HOSC_SEL=0

14.7456Mhz 7.3728MHz 3.6864MHz 1.8432Mhz

PLL_FREQ=000

PLL_HOSC_SEL=1

HOSC_ FREQ =000

7.3728Mhz 3.6864MHz 1.8432MHz Does not support

eight-way, if the

configuration is

1.8432Mhz

PLL_FREQ=000

PLL_HOSC_SEL=1

HOSC_ FREQ =001

14.7456Mhz 7.3728Mhz 3.6864Mhz 1.8432Mhz

PLL_FREQ=000

PLL_HOSC_SEL=1

HOSC_ FREQ =011

29.4912Mhz 14.7456Mhz 7.3728Mhz 3.6864Mhz

3.6.5 System Reset Register SYS_RST(0x14)Offset address 0x14(10 to 5 bits of this register can only be reset by power-on reset)

Resetvalue

31:11 Reserved Reserved R 0

10 boi_vbat_ie

VBAT domain power-down interrupt enable bit:=0 turn off interrupt=1 enable interrupt

9 boi_vbat_flag=0, VBAT domain is powered normally.=1, VBAT domain has been powered downWrite 1 clear

8 MCU_RST

CPU reset flag(occur software reset or LOCK UP reset):=1 represents that the reset occurred,=0 represents un happen. Write 1 to clear

7 WDT_RSTWDTreset flag:=1 represents that the reset occurred,=0

represents un happen. Write 1 to clear

6 PIN_RSTExternal pin reset flag:=1 represents that the reset occurred,=0 represents un happen. Write 1 to clear

5 POWEROK_RST

Power reset flag Source power on/down reset flag=1 represents that the reset occurred,=0 represents un happen. Write 1 to clear

2 LOCKUP_ENRST

LOCKUP enable reset(CPU occurs twice Hard Fault will cause LOCKUP, if enable this bit, can cause system reset):0: LOCKUP doesn’t cause system reset1: LOCKUP cause system reset

3.6.6 System Mapping Control Register SYS_MAPCTL (0x18)Offset address 0x18

Resetvalue

2:0 REMAP

Address mapping:000: FLASH mapping to 0 address (normal mode)001: FLASH maps in 1/2 capacity address (only 512KB capacity supports this function) or FLASH and EEPROM mapped address interchange (only supported by RN8612/8610B)010: FLASH and SRAM mapping address interchange011: BOOTROM maps at address 0100: FLASH maps at 1/2 capacity address (only 512KB capacity supports this function)Other: Reserved.

R/W 000

3.6.7 Module Enable 0 Register MOD0_EN(0x1C)Offset address 0x1C

Reset value

15 SPI_EN

SPI module enables clear, clock gating, cm0 enter deepsleep synchronous close this clock:0: Clock stop, module clear1: Clock start, module enable

14 I2C_EN

I2C module enable clear, clock gating, cm0 enter deepsleep synchronous close this clock:0: Clock stop, module clear1: Clock start, module enable

13 ISO7816_EN

ISO7816 module enable clear, clock gating, cm0 enter deepsleep synchronous close this clock:0: Clock stop, module clear1: Clock start, module enable

12 UART38K _EN

UART38K infrared modulated clock open enable, cm0 enter deepsleep synchronous close this clock:0: Clock stop, module clear1: Clock start, module enable

11 UART3_EN

UART3 module enable clear, clock gating, cm0 enter deepsleep synchronous close this clock:0: Clock stop, module clear1: Clock start, module enable

10 UART2_EN

9 UART1_EN

8 UART0_EN

7 UART5_EN

6 UART4_EN UART4 module enable clear, clock gating, cm0 R/W 0

enter deepsleep sync to turn off this clock:0: the clock is stopped and the module is cleared.1: clock starts, module is enabled

5 TC1_EN

TC1 module enable clear, clock gating, cm0 enter deepsleep synchronous close this clock:0: Clock stop, module clear1: Clock start, module enable

4 TC0_EN

TC0 module enable clear, clock gating, cm0 enter deepsleep synchronous close this clock:0: Clock stop, module clear1: Clock start, module enable

3 CPC_EN

Coprocessor module enable clear, clock gating, cm0 enter deepsleep synchronous close this clock:0: Clock stop, module clear1: Clock start, module enable

Reserved Reserved, other models except RN8612 R 0

EEPROM_EN

Only RN8612/RN8610B support:EEPROM module enable clear, clock gating, cm0 enter deepsleep synchronous close this clock:0: Clock stop, module clear1: Clock start, module enable

3.6.8 Module 1 Enable Register MOD1_EN(0x20)Offset address 0x20

Bit Name Description R/W

Resetvalue

11 CMPLVD_ENCMPLVD module enable clear, abb clock gating:0: clock stop1: clock start

10 RTC_SAR_EN

RTC/SAR apb clock gating, cm0 enters deepsleep sync to turn off this clock:0: clock stop1: clock start

9 WDT_ENWDT apb Bus Clock Gating. cm0 enters in deepsleep and closes this clock synchronously:0: Clock Stops

1: Clock Starts8 Reserved Reserved R 07 Reserved Reserved R 0

6 LCD_ENLCD Nodule Enable Cleared, clock gating:0: Clock Stops, module cleared1: Clock Starts, module enabled

5 GPIO_EN

GPIO Module Enable Cleared, clock gating. cm0 enters in deepsleep and closes this clocksynchronously:0: Clock Stops, module cleared1: Clock Starts, module enabled

4 --- Reserved R 03 --- Reserved R 02 --- Reserved R 01 --- Reserved R 00 --- Reserved R 0

3.6.9 INTC Enable Register INTC_EN(0x24)Offset address 0x24

Resetvalue

8 INTC_EN

INTC apb module clock gating, cm0 enters deepsleep sync to turn off this clock:0: clock stop1: clock start

7 INTC7_ENINTC7 module enable clear, clock gating:0: clock stop1: clock start

6 INTC6_ENINTC6 module enable clear, clock gating:0: clock stop1: clock start

5 INTC5_ENINTC5 module enable clear, clock gating:0: The clock is stopped and the module is cleared.1: clock starts, module is enabled

3 INTC3_ENINTC3module enable clear, clock gating:0: The clock is stopped and the module is cleared.1: clock starts, module is enabled

2 INTC2_EN INTC2 module enable clear, clock gating: R/W 0

0: The clock is stopped and the module is cleared.1: clock starts, module is enabled

3.6.10 KBI Enbale Register KBI_EN(0x28)Offset address 0x28

Resetvalue

8 KBI_EN

KBI apb module clock gating, cm0 enters deepsleep sync to turn off this clock:0: clock stop1: clock start

7 KBI7_ENKBI7 module enable clear, clock gating:0: clock stop1: clock start

6 KBI6_ENKBI6 module enable clear, clock gating:0: clock stop1: clock start

5 KBI5_ENKBI5 module enable clear, clock gating:0: The clock is stopped and the module is cleared.1: clock starts, module is enabled

3.6.11 Device ID Register CHIP_ID(0x2C)Bit Name Description R/W Reset value31:24 --- Reserved R 015:0 CHIP_ID Chip model: xxxx R xxxx

3.6.12 3.6.12 System Control Password Register SYS_PS (0x30)Bit Name Description R/W Reset value31:8 --- Reserved R 0

7:0 SYS_PSW

When SYS_PSW=0x82, the 0x00~0x28 registers can be written;When SYS_PSW=other values, the 0x00~0x28 registers are not writable;This register reads the value written.It is recommended that the user turn off write enable as soon as the write operation is complete.

R/W 00

3.6.13 Infrared Configuration Register IRFR_CTL (0x34)Bit Name Description R/W Reset value31:6 --- Reserved R 0

5:0 IRFR_CYCLE

The password for this register is 0x82In RCH mode, the infrared clock division factor is based on RCH of 3.6864MHZ....0x19: infrared output clock 36.9K;0x18: infrared output clock 38.4K;0x17: infrared output clock 40K;...The calculation formula is:IRFR value = RCH measured frequency / 4/38K

R/W 0x18

3.6.14 Clock Correction Configuration Register TRIM_CFG1 ( 0x78)

Bit Name DescriptionR/W

Reset value

28 CAL_OV_IE

Calibrated Clock Counter Overflow Flag Interrupt Enable:0: Interrupt is not enabled;1: enable interrupt;

27 CAL_DONE_IE Clock Calibration Completion Flag Interrupt Enable: R/W 0

0: Interrupt is not enabled;1: enable interrupt;

26 CAL_CLK_SELCorrected clock source selection0: The corrected clock source selects RCH;1: The RCL is selected by the corrected clock source;

25:24 REF_CLK_SEL

Reference clock source selection00: Select the LOSC with reference clock source;01: Select the reference clock source to select HOSC;10: Select the RCH with reference clock source;11: low power mode;

R/W 11

19:0REF_CLK_CNT[19:0]

Reference clock count R/W0x10000

3.6.15 Clock Correction Start Register TRIM_START ( 0x7C)

Bit Name DescriptionR/W

Reset value

27 STOP

Clock calibration termination bit:0: no operation;1: Terminate the clock calibration;Note: If you terminate the clock calibration, you need to write a 0 to this bit to restart the clock calibration.

26 START

Clock calibration start bit:0: no operation;1: Start clock calibration;Note: This bit is automatically cleared when the clock calibration is completed or terminated.

25 CAL_OV

Corrected clock counter overflow flag:0: no overflow;1: overflow;Note: Write 1 clear 0.

24 CAL_DONE

Clock calibration completion flag:0: not completed;1: completed;Note: Write 1 clear 0.

19:0CAL_CLK_CNT[19:0]

The count value returned by the calibrated clock R 0

Example:

1. Select the reference clock as LOSC and select the clock to be calibrated as RCH;2. Select the reference clock counter REF_CLK_CNT to 0x1000 and the count time to 0.125S;3. Start the clock correction operation, query the flag bit or wait for the system to control the interrupt generation;4. Assume that the count value returned by the corrected clock is CAL_CLK_CNT=0x 61A80, and the decimal is

400000;5. Then the measured RCH frequency value is:

(CAL_CLK_CNT/REF_CLK_CNT)*32768Hz=(400000/4096)*32768Hz=3200000Hz=3.2MHz

4 CPU Architecture

4.1 OverviewThere are two ways (two master devices) which can initiate access to MCU built-in device.Cortex-M0:

Instruction Access and Data Access;Accessible to all slave devices.

External SWD Controller (JLINK or similar function devices):Debug Interface and Resource Access;Accessible to all slave devices.

MCU built-in slave device resources include memory (FLASH, EEPROM and SRAM) and various peripherals (UART, Timer, Watchdog, etc.).

Part of the peripherals can initiate the interrupt request, such as UART, timer, etc.Figure 4-1 MCU device physical interconnection architecture

Cortex-M0

System Bus Interconnection

Peripheral 1

Peripheral n

Interrupt Request

External SWD DAP Controller

MCU chip

DSWD System Bus

System Bus

4.2 Cortex-M0 ProcessorCortex-M0 processor is a 32-bit processor which is designed for the embedded systems, and has the following

characteristics:Easy-to-use programming modelHigh code density, with 32-bit propertiesTool and binary code upward compatible with cortex-m processor series, easy to upgrade and

expandA low-power sleep mode integratedHighly efficient code execution allows that the processor clock is more low, or extend the time for sleep mode32-bit single-cycle hardware multiplierZero jitter interrupt handlingInterrupt timing determination, interrupt processing efficiencySupporting interrupt / exception nesting and seizingSupporting 24-bit system beats counterProviding four interrupt prioritiesSupporting two observation points, four hardware breakpointsSupporting serial debug interface (swd), to achieve the internal state of the processor highly visible and controllableCM0 embedded system timer, please refer to the ARM documentation for details.

See the ARM document for more information on the Cortex-M0.4.2.1 Interrupt Configuration

32 interrupts are supported, including 8 external interrupts, respectively 0~7.For details of interrupts, such as priority masking registers, nested vector interrupt controllers (NVIC), refer to the

arm-m0 manual.Table 4-1 Interrupt/exception inventory and its configuration information

Abnormal number

Interrupt number

Vectors’ name Address Priority Activate way

- - MSP initial value 0x00 - -

1 - Reset 0x04 -3, Highest Asynchronous with processor

2 -14 Non-shielded interrupt

0x08 -2 Asynchronous with processor

3 -13 Hardware failure 0x0C -1 Synchronize with processor

4-10 -12~-6 Keep 0x10~0x28 -

11 -5 System calls 0x2C Configurable Synchronize with processor

12-13 -4~-3 Keep 0x30~0x34 -

14 -2 PendSV 0x38 Configurable Asynchronous with processor

15 -1 System beat counter 0x3C Configurable Asynchronous

with processor

16 0 System control 0x40 Configurable Asynchronous with processor

17 1 Comparator 1 and 2, LVD

0x44 Configurable Asynchronous with processor

18 2 Keep 0x48 -

19 3 RTC 0x4C Configurable Asynchronous with processor

20 4 Keep 0x50 -

21 5 Multiplexing ADC 0x54 Configurable Asynchronous with processor

22 6 UART0 0x58 Configurable Asynchronous with processor

23 7 UART1 0x5C Configurable Asynchronous with processor

26 10 SPI 0x68 Configurable Asynchronous with processor

27 11 I2C 0x6C Configurable Asynchronous with processor

28 12 7816_0 0x70 Configurable Asynchronous with processor

29 13 7816_1 0x74 Configurable Asynchronous with processor

30 14 TC0 0x78 Configurable Asynchronous with processor

31 15 TC1 0x7C Configurable Asynchronous with processor

34 18 Guard dog 0x88 Configurable Asynchronous with processor

35 19 KBI 0x8C Configurable Asynchronous with processor

36 20 LCD 0x90 Configurable Asynchronous with processor

37 21 0x94 Configurable Asynchronous with processor

38 22 Keep 0x98 -

39 23 Keep 0x9C -

40 24 External interrupt 0 0xA0 Configurable Asynchronous with processor

43 27 External interrupt 3 0xAC Configurable Asynchronous with processor

44 28 External interrupt 4 0xB0 Configurable Asynchronous with processor

45 29 External interrupt 5 0xB4 Configurable Asynchronous with processor

46 30 External interrupt 6 0xB8 Configurable Asynchronous

with processor

47 31 External interrupt 7 0xBC Configurable Asynchronous with processor

Note: the actual stack top of RN8612 is two words higher than that allocated by the compiler. For example, the stack top allocated by the compiler is 0x10001918, which is actually 0x10001920.Be careful not to assign these two words to other variables when you apply them.

4.3 MCU Memory MappingPlease refer to "Figure 4-2 MCU memory mapping" for the memory mapping of MCUHigh-speed peripherals of MCU include:

GPIOLow-speed peripherals of MCU include:

6 UART interfacesTwo 32-bit timers1 SPI interface1 I2C interface1 KEY controller1 universal ADC interface1 guard dog unit1 system control unitTwo 7816 ports1 RTC interfaceAn interrupt control interface1 LCD controller

Figure 4-2 MCU storage mapping

Note: RN8612/RN8610B supports EEPROM, and the address space is 0x08000000~0x08008000 to store the re-mapping

8KB ROM

32KB SRAM

The low-speed peripherals

The high-speed peripheral

Kernel private peripheral

TC0TC1

UART4UART5

I2CSPI

UART0UART1UART2UART3

Guard dog

Analog peripheralsKeyboard controller

GPIOReserved spaceReserved space

System control unit

Except bitbandReserved Space

Except bitbandReserved space

Except bitbandReserved Space

Reserved Space

512KB FLASH 0x000000000x00080000

0x10000000

0x10008000

0x180000000x18002000

00000000

0x400000000x40080000

Reserved space

0x500000000x50014000

0xE00000000xE0100000

0xFFFFFFFF4GB

Th1.25GB

Re0.125GB

0.25GB

0x50008000

0x500000000x50004000

Reserved space

0x400000000x400040000x400080000x4000C000

0x400100000x400140000x400180000x4001C0000x400200000x40024000

0x4002C0000x40028000

0x400300000x400340000x400380000 400380000x4003C0000x400400000x400440000x400480000x4004C000

0x40080000

Interrupt control interface

Reserved space

Co-processor0x5000C0000x50010000

Reserved space

0x40050000

0x50014000

Reserved Space

Reserved space0x50018000

The MCU supports swapping base addresses for two storage areas, including FLASH and SRAM.Switching is done by configuring the REMAP register in the system controller.The address allocation of devices other than FLASH and SRAM is not affected by the memory re-mapping.

Table 4-2 Store the re-mapped configurationMemory device REMAP Mapping addressFLASH 0 0x00000000

1 0x000000002 0x100000003 0x18000000

SRAM 0 0x100000001 0x100000002 0x000000003 0x10000000

Bitband functionThe system supports bitband function of the following address space:

0x10000000~0x10007FFF mapped to 0x12000000~0x120FFFFF0x40000000~0x4004FFFF mapped to 0x42000000~0x423FFFFF;0x50000000~0x50007FFF mapped to 0x52000000~0x5203FFFF;

Access to the bitband region is equivalent to access to the special location in the external register.Btband address corresponding to the y bit of storage unit with address x:

4.3.1 SRAMIn-chip static RAM (SRAM) with a capacity of 32KB (2KB for CACHE) or 8KB (all available to customers),

running at the same frequency as the processor, supporting random access to 8-bit, 16-bit or 32-bit data, and can be used as code or data storage;2KB of 32KB of RAM at a high address can be used as a CACHE and is not accessed by the CPU when used as a CACHE.

WDT, external tap, software reset, etc., will not clear the data of SRAM, but it should be noted that BOOTROM USES address space 0x1000_0300 ~ 0x1000_03ef, a total of 240Bytes. Once the system reset occurs, CPU will execute the startup program from BOOTROM, and the data of this address space will be occupied.

4.3.2 FLASHMaximum 512KB FLASH on the chip, supporting:

At least 100,000 erasures;Data should be kept for at least 10 years;RN8613 storage area contains 16 blocks, each block contains 64 pages, each page 256 bytes;RN8612 storage area contains 16 blocks, each containing 64 pages of 128 bytes per page.Support 8-bit, 16-bit and 32-bit random reading;Support page erasing, block erasing, page programming, specific operations need to call library function (nvm.a(IAR)/nvm.lib(KEIL));FLASH will automatically turn off or on for low-power applications;

The FLASH operation function interface provided by the Renergy library function (nvm.a(IAR)/nvm.lib(KEIL) is as follows:

uint8_t flashPageErase(uint32_t pg)uint8_t flashSectorErase(uint32_t sec)uint8_t flashProgram(uint32_t dst_addr, uint32_t src_addr, uint32_t len)

4.3.3 EEPROMChip 32KB EEPROM, supporting:

Minimum 1 million erasures;Data should be kept for at least 10 years;Random access to any address, access data width support 8 bits, 16 bits or 32 bits;Support page erasing, block erasing, word programming, specific operations need to call library function (nvm.a(IAR)/nvm.lib(KEIL));It is divided into 4 sections, each section has 64 pages and each page has 128 bytes;

In low-power applications, customers need to call the R Energy library function to close or open EEPROM;The interface of EEPROM operation function provided by library function (nvm.a(IAR)/nvm.lib(KEIL) is as follows:

uint8_t eepromProgram(uint32_t dst_addr, uint32_t src_addr, uint32_t len)void eepromStandby(void)void eepromWakeup(void)

For detailed operation, please see the R Energy application notes.Note: RN8612 contains EEPROM only.

4.4 Interrupt ApplicationSOC header file #include < rn8x1x.h > in the header file, you can use SOC interrupt, rn821x.h file

contains cortex-m0 defined part of the header file, core_cmfunc.h, core_cmfunc.h, core_cmInstr. H.All the above documents can be found in the header file provided by the R Energy.

Close interrupt enable:__disable_irq();Enable total interruption:__enable_irq();Interrupt operationThe interrupt program of each module can be written completely in C language, and users do not need to consider the problems of pushing and pushing. The interrupt operation steps are as follows:Take the KBI interrupt as an example:1 Total interruption of enable:__enable_irq();2 Configure modules that need to generate interrupts, such as the KBI module, and set KBI_MASK to

enable interrupts.3 Enable KBI interrupt: find the interrupt number in rn821x.h file and start the interrupt, for example,

KBI interrupt number is KBI_IRQn, start KBI interrupt is NVIC_EnableIRQ(KBI_IRQn), if you need to set the interrupt priority, use void NVIC_SetPriority(IRQn_t IRQn, uint32_t priority).

4 For different interrupts, the function name has been fixed and can be found in startup_rn821x.s. For example, the KBI interrupt service program function named KBI_HANDLER can be written as:void KBI_HANDLER(void)

{/* Start adding user code. Do not edit comment generated here */

}5 Close interrupt enable: void NVIC_DisableIRQ0(IRQn_t IRQn).

5.1 OverviewBaseAddr is 0x4003C000;

RTC module provides real-time clock, oscillator temperature compensated, calendar, alarm, clock pulse output, etc.

Real-time clock tracks time through swparate hour, minute, second registers. Calendar includes year, month, day and week registers with leap year and leap moth automatically calibrated. Clock pulse output has a variety of selectable frequency for clock calibration. Alarm is also provided.

Integrates a temperature sensor and provides a digital temperature measurement result.The module is powered independently by VBAT.

5.2 FeaturesProvides accurate temperature value, and temperature measurement accuracy is ± 1 in the range of -25 ~70Achieves initial temperature calibration of RTC at room temperature.Automatically completes temperature compensation calibration of RTC without CPU involvement.Low Power Design.The accuracy of frequency regulation is up to 0.00678ppm.High stability oscillator.RTC is not closed in different modes, and still works in low power.Provides clock and calendar function: the output register, including seconds, minutes, hours, date, month, year and

week, etc.Provides automatic leap year leap month adjustment function, and the time range is 100 years (00-99).1 crystal vibration stops interruption function, 1 alarm clock interruption function, 2 timer periodic interruption

function, 5 time interruption function (seconds, minutes, time, month, day)Can output un-calibrated frequency: 1024/32768HzCan output calibrated frequency: 1/2/4/8/32/128Hz

5.3 Register Description

Base Address of RTCModule Name Physical Address Mapping AddressRTC BaseAddr 0x4003C000 Base1

Register Offset Address of RTCRegister Name Address Offset Value Description

RTC Register GroupRTC_CTL Offset+0x00 RTC Control RegisterRTC_SC Offset+0x04 Second Register, Write ProtectRTC_MN Offset+0x08 Minute Register, Write ProtectRTC_HR Offset+0x0C Hour Register, Write ProtectRTC_DT Offset+0x10 Day Register, Write ProtectRTC_MO Offset+0x14 Month Register, Write ProtectRTC_YR Offset+0x18 Year Register, Write ProtectRTC_DW Offset+0x1C Week Register, Write ProtectRTC_CNT1 Offset+0x20 Counter 1 RegisterRTC_CNT2 Offset+0x24 Counter 2 RegisterRTC_SCA Offset+0x28 Second Alarm Register

RTC_MNA Offset+0x2C Minute Alarm RegisterRTC_HRA Offset+0x30 Hour Alarm RegisterRTC_IE Offset+0x34 RTC Interrupt Enable RegisterRTC_IF Offset+0x38 RTC Status RegisterRTC_TEMP Offset+0x3C Current Temp Register, Readable

and Writable, Write ProtectRTC_CALPS Offset+0xCC RTC secondary compensation

register write protection, write 8'hA8, t0 ~ T9 register will work.

RTC_CAL_T0 Offset+0xD0 T0 ~ T9 is an 8bit register, which compensates the error of RTC twice on the basis of hardware automatic temperature compensation. The scale is 0.25ppm, in binary complement format;Compensation temperature range: T < - 30

RTC_CAL_T1 Offset+0xD4 Compensation temperature range:-30<= T <-20

RTC_CAL_T2 Offset+0xD8 Compensation temperature range:-20<= T < -10

RTC_CAL_T3 Offset+0xDC Compensation temperature range:-10<= T < 0

RTC_CAL_T4 Offset+0xE0 Compensation temperature range:0<= T <= 10

RTC_CAL_T5 Offset+0xE4 Compensation temperature range:35< T <=45

RTC_CAL_T6 Offset+0xE8 Compensation temperature range:45<T <= 55

RTC_CAL_T7 Offset+0xEC Compensation temperature range:55< T <=65

RTC_CAL_T8 Offset+0xF0 Compensation temperature range:65< T <=75

RTC_CAL_T9 Offset+0xF4 Compensation temperature range:75< T < =85

LOSC_CFG1 Offset+0x6C LOSC configuration registerVBAT_IOMODE Offset+0x88 VBAT domain IO configuration

registerVBAT_IOWEN Offset+0x8C VBAT_IOMODE writing enable

register

5.3.1 RTC Control Register RTC_CTL(0x00)Offset Address: 0x00

Bit Name Description R/WReset value

31:12 --- Reserved R 011 Losc_cps Reserved bit, read only. R 0

10 Cal_busy

RTC Calibration Busy. When Cal_busy=1, RTC is ongoing calibration; when Cal_busy=0, RTC has completed calibration. The bit read only, each correction will be set high, no practical significance.

9 Wr_busy

RTC register write operation is busy. Write multiple registers without waiting.But read after writing, you need to wait for the busy bit to change from 1 to 0 before reading back the correct value.Therefore, it is recommended that the application wait for 300us to read after writing the perpetual calendar.

8 WRTC

Allowable RT register group writing:0: disable RTC register write operation;1: allow RTC register write operation.Note: this bit is valid for RTC register group 00 ~ 1C/3C/C4, and for RTC < CTL [7:0].There are two ways to write the time register of the perpetual calendar:1 write according to the sequence of "month, day, hour,

minute, second". When the second register is written, the time starts to accumulate from the time of writing. Note that this method may flip the minute before the second is written, so read it out for verification after writing;

2 write according to the sequence of "seconds, minutes, months, days", write the second register first, and the perpetual calendar counter is cleared. As long as other values are written in one second, it can ensure successful writing.

Note 1: the hardware has made a legal judgment on "year month day", which can not be written in the order of "day month year", only "year month day" can be written continuously.Note 2: the time registers of the perpetual calendar must be written in the above order, and the complete 6 registers (month, day, hour, minute and second) must be written in a time write, instead of just updating the part (such as only writing minutes and seconds).

7:6 TSE

Allowable bit of temperature sensor00: prohibit automatic temperature compensation01: start automatic temperature compensation. Conduct periodic temperature compensation according to the settings

R/W 00

of TCP.10: start the user's temperature compensation mode 0, the temperature register can be changed, and the user fills in the temperature value, and the user starts the temperature compensation every time he writes the temperature register;11: start users’ temperature compensation mode 1, the temperature register cannot be changed, and the temperature compensation operation will be started every time the temperature register is written. The value of the temperature register is measured by MCU.Note: this register only works with power on reset.

5:3 TCP

Temperature Compensation Cycle:000:2S 001:10S Default010:20S 011:30S100:1M 101:2M110:5M 111:10M

R/W 001

02:00 FOUT

000:Output Disable001:1Hz Outputs010:1/30Hz Outputs011:32768Hz Outputs100:16Hz Outputs101:8Hz Outputs110:4Hz Outputs111:ReservedThis register only works on power-on reset.

R/W 000

5.3.2 Second Register RTC_SC (0x04)Offset Address: 0x04

Bit Name Description R/WReset value

06:00 SC

Store the second value of the clock.BCD Format, SC[6:4] is the tens of the second value, SC[3:0] is the units of the second value. The second value ranges from 0~59.

5.3.3 Minute Register RTC_MN(0x08)Offset Address: 0x08

Bit Name Descriptions R/WReset Value

06:00 MNStore the minute value of the clock.BCD Format, MN[6:4] are the tenth of minute value,

MN[3:0] are the bits of minute value. The Rang of Minute Value is 0~59.

5.3.4 Hour Register RTC_HR(0x0c)Offset Address: 0x0C

05:00 HRStore the hour value of the clock.BCD Format, HR[5:4] are the tenth of hour value, HR[3:0]are the bits of hour value. The Rang of Hour Value is 0~23.

5.3.5 Date Register RTC_DT(0x10)Offset Address: 0x10

05:00 DTStore the date value of the clock.BCD Format, DT[5:4] are the tenth of date value, DT[3:0]are the bits of date value. The Rang of date value is 1~31.

5.3.6 Month Register RTC_MO(0x14)Offset Address: 0x14

04:00 MO

Store the month value of the clock.BCD Format, MO[5:4] are the tenth of month value,MO[3:0] are the bits of month value. The rang of month value is 1~12.

5.3.7 Year Register RTC_YR(0x18)Offset Address: 0x18

07:00 YRStore the year value of the clock.BCD Format, YR[7:4] are the tenth of year value, YR[3:0]are the bits of year value. The rang of year value is 0~99.

5.3.8 Date Week Register RTC_DW(0x1c)Offset Address: 0x1C

02:00 DWStore the week corresponding to the current date. The counting cycle of DW[2:0] is 0-1-2-3-4-5-6-0-1-2-....

5.3.9 RTC Timing Register 1 RTC_CNT1(0x20)Offset Address: 0x20

08 CNT1PD

=0: 1 second timing from the perpetual calendar second interrupt.=1: turn off timer 1. When it is turned on again, the counter will start again (the scale is 1s, independent of the interruption of the perpetual calendar second)

07:00 CNT

Timer 1 counter preset.An unsigned number in 1s. When the count value = (CNT + 1), set the RTCCNT1F (interrupt can be generated every 1 second at least and every 256 seconds at most).Note1:The timer is accurate after RTC correction.Note2:When RTC-IE-> RTC_1S_SEL is 0, i.e. pll_1hz is selected as the second interrupt source, the second interrupt is not synchronized with the update of the second register. The second interrupt may not be generated at the start of the second count, but at any time of the second count. When RTC-IE-> RTC_1S_SEL is 1, i.e. RTC second pulse is selected as the second interrupt source, the second interrupt is consistent with the second register update. It is recommended to select RTC-IE-> RTC_1S_SEL as 1.

5.3.10 RTC Timing Register 2 RTC_CNT2(0x24)Offset Address: 0x24

09CNT2_CLK_SEL

Colck source of CNT2_CLK.0:32768Hz1:RCL

08 CNT2PD= 0: timer from internal fixed 1 / 256s interrupt.= 1: turn off timer 2. When it is turned on again, the counter will start again (scale 1 / 256s).

07:00 CNTTimer 2 counter presetAn unsigned number in 1/256s. When the count value = (CNT + 1), set the RTCCNT2F (interrupt can be generated

once every 1 / 256 seconds at least and once every 1 second at most).Note: the timer is from 32768Hz crystal, uncorrected, with certain error.

5.3.11 Second Alarm Register RTC_SCA(0x28)Offset Address: 0x28

06:00 SCA

Second alarm clock value.BCD Format, SCA[6:4] is the tens of the second value, SCA[3:0] is the units of the second value. The second value ranges from 0~59.

5.3.12 Minute Alarm Register RTC_MNA(0x2c)Offset Address: 0x2C

06:00 MNA

Minute alarm clock value.BCD Format, MNA[6:4] are the tenth of minute value,MNA[3:0] are the bits of minute value. The Rang of Minute Value is 0~59.

5.3.13 Hour Alarm Register RTC_HRA(0x30)Offset Address: 0x30

05:00 HRA

Hour alarm clock valueBCD Format, HRA[5:4] are the tenth of hour value,HRA[3:0] are the bits of hour value. The Rang of Hour Value is0~23.

Note:04~30H register has no reset value.

5.3.14 RTC Interrupt Enable Register RTC_IE(0x34)Offset Address: 0x34

31:10 Reserved Reserved R 09 RTC_1S_SEL Second interrupt source selection: R/W 0

=0: according to the system clock mode: select pll_1hz in high frequency mode and RTC second pulse in non high frequency mode.=1: always select the second pulse of RTC.Note: the update of pll_1hz and second register is not synchronized, and the second pulse of RTC is synchronized with the second register. It is recommended that the customer configure the register as 1 and select the second pulse of RTC.

08 IECLKEN

RTC interrupt generate clock enable;

When anyone of the RTC [IE 8-0] is high, the interrupt module clock would open;When anyone of the RTC [IE 8-0] is low, the interrupt module clock would close;

7 MOIEMonth Interrupt Enable0 : Disable1 : Enable

6 DTIEDate Interrupt Enable0 : Disable1 : Enable

5 HRIEHour Interrupt Enable0 : Disable1 : Enable

4 MNIEMinute Interrupt Enable0 : Disable1 : Enable

3 SCIE

Second Interrupt Enable0 : Disable1 : EnableNote: When RTC-IE-> RTC_1S_SEL is 0, i.e. pll_1hz is selected as the second interrupt source, the second interrupt is not synchronized with the update of the second register. The second interrupt may not be generated at the start of the second count, but at any time of the second count. When RTC-IE-> RTC_1S_SEL is 1, i.e. RTC second pulse is selected as the second interrupt source, the second interrupt is consistent with the second register update. It is recommended to select RTC-IE-> RTC_1S_SEL as 1.

2 RTCCNT2IERTC Timer2 Interrupt Enable0 : Disable1 : Enable

1 RTCCNT1IERTC Timer1 Interrupt Enable0 : Disable1 : Enable

0 ALMIEAlarm Event Interrupt Enable0 : Disable1 : Enable

5.3.15 RTC Interrupt Flag Register RTC_IF(0x38)Offset Address: 0x38

Month Interrupt Flag0 : Month Counter not plus 11 : Month Counter plus 1Note: Write 1 Cleared

Date Interrupt Flag0 : Date Counter not plus 11 : Date Counter plus 1Note: Write 1 Cleared

Hour Interrupt Flag0 : Hour Counter not plus 11 : Hour Counter plus 1Note: Write 1 Cleared

Minute Interrupt Flag0 : Minute Counter not plus 11 : Minute Counter plus 1Note: Write 1 Cleared

Second Interrupt Flag0 : Second Counter not plus 11 : Second Counter plus 1Note: Write 1 Cleared

2 RTCCNT2F

RTC Timer2 Interrupt Flag0 : Timer1 Interrupt Unhappen1 : Timer1 Interrupt HappenNote: Write 1 Cleared

1 RTCCNT1F

RTC Timer1 Interrupt Flag0 : Timer1 Interrupt Unhappen1 : Timer1 Interrupt HappenNote: Write 1 Cleared

0 ALMF

Alarm Event Flag, alarm event that matches with real-time clock occurs0 : Alarm Event Unhappened1 : Alarm Event HappenedNote: Write 1 Cleared

5.3.16 Current Temperature Register RTC_TEMP(0x3c)Offset Address: 0x3C

09:00 TEMP

The Present Temperature Value.Bit 9 is Sign Bit; Bit 8~2 are Integer Bits; Bit 1~0 are Decimal Place.// Temp[9] Temp[8:2] Temp[1] Temp[0]// Symbol -128Range: -128 (0x200)~+127.75 (0x1ff).Temperature conversion formula: if the symbol bit is 0, the temperature is TEMP/4. If the symbol bit is 1, the temperature is (2^10- TEMP)/4.TSE=00: Disable temperature compensation automatic. This register RTC_TEMP is invalid, read the value is meaningless.TSE=01: Carry out automatic temperature compensation according to the cycle set by RTC_CTL_> TCP. At this time, RTC_TEMP register displays the temperature value of the temperature compensation period. The update period of RTC_TEMP register is the temperature compensation period set by RTC_CTL _> TCP.TSE=10: Start user warm compensation mode 0. At this time,RTC_TEMP register can be changed, and user fills in the temperature value. User starts the temperature compensation every time he writes the temperature register.TSE=11: Start user warm mode 1. At this time, RTC_TEMPregister cannot be changed. Each time the temperature register is written, the temperature compensation operation is started. The value of the RTC_TEMP register is measured bythe SOC.

RTC automatic temperature compensation needs to define the following registers, and these register values are obtained in the mass production of customers.1. Initial frequency deviation register RTC_DOTA0: modify the initial frequency deviation of the crystal; (each table needs to be obtained, and the library function provided by Renergy can complete the operation of this register).

2. Quadratic curve vertex temperature register RTC_XT0 (get crystal batch parameters, configure option bytes, write through programming interface).3. Crystal temperature coefficient register RTC_ALPHA (get crystal batch parameters, configure option bytes, write through programming interface).

5.3.17 LOSC Configuration Register LOSC_CFG1(0x6c)

Bit Name Descriptions R/W Reset Value31:11 --- Reserved R 0

10 VCC_BOI_FLAG

=0: normal;=1: Power failure occurred in VCC power domain;Write 1 to reset

9 LOSC_FAIL=0: normal;=1: LOSC has stopped vibrationWrite 1 to reset

8 LOSC_WEN=0: LOSC_PD is not writable=1: LOSC_PD writable

7:0 LOSC_PD

LOSC enable bit:=Others: open;=8'ha8: off.Note: it is also the external clock enable signal, = 1 enable external clock.

5.3.18 VBAT Domain IO Configuration Register VBAT_IOMODE(0x88)

Bit Name Descriptions R/W Reset Value31:12 --- Reserved R 011:8 --- Reserved, not open register bit R/W 0

7:4 P56_MODE

=4'ha, enable P56 port to output RTC_outfunction;=Other values, P56 functions are defined by GPIO chapter registers.The priority of this function is higher than the reuse configuration of P56 in GPIO chapter.When VBAT is powered on independently and VCC is not powered on, P56 outputs 1Hz by default;When VCC is powered on, CPU initialization will configure this register to 0.

3:0 --- Reserved, not open register bit R/W 0

5.3.19 VBAT Domain IO Configuration Register Writing enable VBAT_IOWEN(0x8C)

Bit Name Descriptions R/W Reset Value31:8 --- Reserved R 0

7:4 IOWEN

=4'hb, VBAT_IOMODE register write operation is enabled;=Otherwise, VBAT_IOMODE register is not allowed to be written.

3:2 --- Reserved R 01 --- Reserved, not open register bit R/W 00 --- Reserved, not open register bit R/W 0

5.4 RTC clock R/W steps1. Set the 10th bit RTC_EN of the module enable 1 register MOD1_EN in the system control chapter to 1.2. Clock reading: read the second, minute, hour and other time registers of RTC.3. Clock writing.Set the 8th WRTC of RTC_CTL to 1, and turn on the write enable operation.Write according to the sequence of "month, day, hour, minute and second". When the second register is written,

the time begins to accumulate from the time of writing. Note that this method may flip the minute before the second is written, so read it for verification after writing.

Or write according to the sequence of "seconds, minutes, months, days", write the second register first, and the perpetual calendar counter is cleared. As long as other values are written in one second, the successful writing can be guaranteed.

Note that the hardware has made a legitimacy judgment on "years months days", which can not be written in the order of "days months years", but can only write "years months days" continuously.

In order to enhance the reliability of software, it is recommended to read and confirm after writing.

5.5 RTC calibration stepsUser only needs to calibrate the initial deviation of 32.768KHz. The error is written through Renergy programmer

interface or by using the library function.

5.6 RTC timer operation stepsTake timer 1 as an example to generate 1s interrupt. The operation steps are as follows:1. Set the 10th bit RTC_EN of the module enable 1 register MOD1_EN in the system control chapter to 1 clock

start.2. Set the 8th WRTC of RTC < CTL to 1, and turn on the write enable operation.3. Set RTC - > CNT1 = 0x00, i.e. 1s generates 1 interrupt.4. Set RTC - > IE= 0x02; RTC timer 1 interrupt enable.5. Enable RTC interrupt enable, NVIC enable IRQ (RTC IRQN);6. Write interrupt service program:

void RTC_HANDLER (void){

If (RTC->IF&0x02) // Timer 1{/* Start adding user code. Do not edit comment generated here */}

7. Finally, 1s interrupt can be generated after configuration.

6 WDT To built-in hardware watchdog for detect abnormal execution of the program.

6.1 OverviewThe watchdog has the following characteristics:

Overflow time can be set:16ms ,32ms,128ms,512ms,1s,2s,4s,8s;Dog window period can be set;

Generated watchdog reset when any of the following conditions:The watchdog timer counter overflow;The outside of the 0xBB data write into WDT_EN;Writing the data in WDT_EN during the dog windows closed;Writing the data in WDT_EN by bitband space;

6.2 Configuration of Watchdog Timer

WDT is hardware watchdog, cannot be configured directly by registers, need by setting the option byte way to configure it. Configuration of watch dog have interval interrupt, window opened cycle, Overflow Time, CPU sleep setting, CPU debug setting. etc.

Name DescriptionsFactory default values

Interval interrupt

0:Disable(Disable interval interruption)1:Enable(When reach the 75% of overflow events, generate interval interruption)

Window opened cycle

0:25%1:50% 2:75% 3:100%Write 0xBB in WDTE register during the window opened, the watchdog cleared and re-count;Write 0xBB in WDTE register during the window closed, would generate internal reset signal.

Overflow Time

0:16ms1:32ms2:128ms3:512ms4:1s5:2s6:4s7:8s

CPU Sleep Settings

0:Disable(When the CPU is in sleep or deep sleep not open WDT)1:Enable(When the CPU is in sleep or deep sleep open WDT)

CPU Debug Settings

0:Disable(When the CPU is in debug status is not open WDT)1:Enable(When the CPU is in debug status is open WDT)

Note: CPU is in the debug state refers to users would stop Cortex M0 through debugging interface(PC pointer stops counting).If the chip is in the development process ,enabling this setting is not recommended. For if this setting is enabled, WDT still accounting number when the chip is in debug state, it will generate an interrupt overflow occurs, will cause the debugging cannot be.

The definition of window open cycle as shown in the figure below, For example, with 25% of the window open cycle:

Started to count Overflow time

Window openedcycle 25%Window closed cycle 75%

6.3 Registers DescriptionsWDT Register base addressModules Name Physical Address Mapping AddressWDT 0x40030000 0x40030000WDT Register Offset AddressRegisters Name Address Offset DescriptionsWDT_EN 0x0 Enable Register

WDT_EN(0x0)

8 WR_BUSYWDT Busy

Feeding watchdog is not related to the BUSY bit.R 0

7:0 WDTE0XBB is written to reset the watchdog timer and start countingoperation again. The generation of reset signal sets this register to 0x55.

R/W 55

6.4 WDT operation steps1. Configure the system control section. The module enables the 9th bit of the 1 register MOD1_EN to be 1,

and turns on the WDT APB clock.2. The default configuration of WDT is startup. The timer overflow time is 1S, and the window open period is

75%. The user program does not require a WDT initialization configuration.3. Operation of “Feeding watchdog ”: WDT->EN = 0xbb.4. When the WDT sleeps, the WDT is turned off by default. The WDT clock in MOD1_EN is not required to

be turned off. If the WDT clock needs to be turned off, the DT clock must be turned off after waiting for the 8th bit of WDT_EN to be 0.

5. If the program is interrupted by hardware emulation, the WDT count will be suspended and will not affect the hardware emulation.

6. Finish.Suggestions:The WDT consumes very little power. When the CPU is hibernated, the additional power consumption of the

WDT is less than 1uA. Considering the higher reliability of the system, it is recommended that the customer turn on the WDT while the CPU is sleeping. The second timer in the RTC can be used to wake up the CPU for Feeding watchdog.

7 LCD MCU is built-Segment type LCD controller.

Support for 8COM*36SEG. Supports both charge pump and resistor divider.

7.1 OverviewLCD has the following characteristics:

RN8318: 4*40,6*38,8*36;RN8615/RN8613/RN8612: 4*34,6*32,8*30;Support for type A and B two driving waveforms;Support 1/3 and 1/4 bias;Supports up static, 1/2, 1/3, 1/4, 1/6, 1/8 duty;Support 16-level contrast adjustable LCD drive mode;After the LCD module is turned off, the configured COM and SEG pins are automatically pulled down to the ground.(Note: when the display stops, keep the COM and SEG status unchanged, can’t switch the pin reuse relationship to IO port, and do not change bias with duty);The RN8318/RN8615/RN8613 supports the charge pump and internal resistor series voltage division to achieve the LCD Bias voltage;The RN8612 only supports the internal resistor series divider method to achieve the LCD Bias voltage.

7.1.1 Scan Clock Frequency

The LCD unit's clock is derived from Fosc or RCL (selected by the system-controlled OSC_CTL2 register) at a frequency of 32768 Hz. After the Fosc or RCL is divided, it is used as the LCD waveform scanning frequency flcd, and the waveform scanning frequency flcd can be configured through the register LCD_CLKDIV [7:0].

Ffram = flcd / (number of com). Generally, the refresh rate of the LCD screen is slightly larger than 60 Hz. Table 7-1 shows the clock settings for different duty. (Green is marked with the normal used frame rate).

Table 7-1 Scan frequency and frame frequency of LCD

LCD_CLKDIVScan frequency

Static Duty ratio

1/2 Duty ratio

1/3 Duty ratio

1/4 Duty ratio

1/6 Duty ratio

1/8 Duty ratio

0xff 64Hz 64Hz 32Hz 21.3Hz 16Hz 10.7Hz 8Hz0x7f 128Hz 128Hz 64Hz 42.7Hz 32Hz 21.3Hz 16Hz0x54 192.8Hz 192.8Hz 96.4Hz 64.3Hz 48.2Hz 32.1Hz 24.0Hz0x3f 256Hz 256Hz 128Hz 85.3Hz 64Hz 42.7Hz 32Hz0x2a 381.3Hz 381.3Hz 190.5Hz 127.0Hz 95.3Hz 63.5Hz 47.6Hz0x1f 512Hz 512Hz 256Hz 170.7Hz 128Hz 85.3Hz 64Hz

7.1.2 Flash ModeLCD supports two kinds of flash modes: Internal flash and Outside flash. These two modes can be enabled

simultaneously.Figure 7-1 LCD flash mode

As shown in figure 7-1, After LCD enabled, it would according to the defined length of time LCD BLINK register TON bit field to open the display, and then it would according to the defined length of time LCD BLINK register TON bit field to close the display.

When the display is open or closed, LCD can send interrupt request or DMA request. Users can use these events to update the frame buffer.

7.1.2.1 Internal Flash Mode

LCD supports that insert flash mode in display time which is specified length by the LCD_BLINK register TON bit field. The interval of flashing is given by bit field of BLINK_TIME of LCD_BLINK register. When BLINK_TIME is equal to 0, internal flash mode is prohibited; and when BLINK_TIME is not equal to 0, TON must be an even multiple of BLINK_TIME.

7.1.2.2 Outside Flash Mode

When TOFF of the LCD_BLINK register is not equal to 0, Blink mode is enabled. According to the TON and TOFF values of LCD BLINK registers determine the flicker frequency after Blink mode enabled.

7.1.3 LCD Driving WaveformThe LCD driving waveform is related to the LCD Type, Duty number, and Bias number (LCD_CTL register) set

by the software.The MCU supports two types of driving waveforms, Type A and Type B respectively. The Type A driver is a line

inversion mode, that is, an alternating of positive and negative driving is completed in one frame time. The Type B drive is a frame in version mode, that is, an alternate of positive and negative drive can be completed within 2 frames. For details, refer to the LCD drive waveforms described in this section. When the driving duty number is high, the Type B driving mode display effect is better.

The user needs to select the duty ratio of LCD output waveform according to application of the number of COM:One COM: When select static duty ratio, only use COM0;Two COMs: When select 1/2 duty ratio, use COM0,COM1;Three COMs: When select 1/3 duty ratio, use COM0 COM2;

Display the first screen

DMA or Cortex-M0 update theframe buffer zone

Close the display Display the second screen Close the display Display the NO.N screen Close the display

Open the display Close the displayOpen the display Close the displayOpen the display Close the displayOpen thOpen thOpen th

Internal Flash Mode

Outside FlashMode

Four COMs: When select 1/4 duty ratio,useCOM0 COM3;Six COMs: When select 1/6 duty ratio, use COM0 COM5;Eight COMs: When select 1/8 duty ratio, use COM0 COM7.

7.1.3.1 Driving waveform of type A

Figure 7-2 LCD driving waveform (1/4 Duty,1/3 Bias, Type A)

Figure7-3 LCD driving waveform (1/4 Duty,1/4 Bias, Type A)

7.1.3.2 Driving Waveform of type B

Figure7-4 LCD driving waveform (1/4 Duty,1/3 Bias, Type B)

Figure7-5 LCD driving waveform (1/4 Duty,1/4 Bias, Type B)

7.1.4 Bias Voltage of LCD

7.1.4.1 Charge Pmup mode provides LCD bias voltage

The bias voltage of LCD can use Charge Pump to provide. Charge Pump is required to produce 4 voltage(Va,Vb,Vc,Vd)in order to meet the 1/4 bias Application. For different settings of bias ratio, the Charge Pump outputvoltage mode is different, as shown in table 7-2.

Table 7-2 The relationships between drive voltage of LCD and bias ratioBias ratio

Grayscale Select

VaVb Vc

Vd Vd(MAX)

1/3Bias ratio

BIASLVL[5] = 0

Va = Vref*(32+BIASLVL[4:0])/63

Vb = Va Vc = 2*Va

Vd = 3*Va

3.75 V

BIASLVL[5] = 1

Va = Vref*(1 + BIASLVL[4:0]/63)

Vb = Va Vc = 2*Va

Vd = 3*Va

5.59 V

1/4Bias ratio

BIASLVL[5] = 0

Va = Vref*(32+BIASLVL[4:0])/63

Vb = 2*Va

Vc = 3*Va

Vd = 4*Va

BIASLVL[5] = 1

Va = Vref*(1 + BIASLVL[4:0]/63)

Vb = 2*Va

Vc =3*Va

Vd = 4*Va

6.032V

Example: The maximum of LCD for Vd is 5.2 V. When the selection is 1/4 bias ratio and the set of BIASLVL [5:0] is larger than 6’h2d, LCD controller BIASLVL [5:0] clamped to 6'h2d automatically.LCD select LBGR as the reference default, the typical output value of LBGR is 1.27V.

Applied voltage selection of 1/3 and 1/4 bias ratio, as shown in figure 8-6:Figure8-6 Bias voltage selection

1/3 Bias ratio 1/4 Bias ratio

7.1.4.2 Internal resistor series divider provides LCD bias voltage

Built-in LDO, the output is adjustable from 2.7 to 3.6 V, the adjustment step is 60mV, and supports 3.0V and 3.3V LCD screens. See the LCD Internal Resistor String Control Register (LCD_RESCTL) for specific configuration.

The selection of the 1/3 and 1/4 bias ratio application voltage is shown in Figure 7-6.The LCD internal resistor string mode supports two modes. The large/small resistor string split start mode and the

small resistor/open time split start mode. It is recommended to use a small resistor/open mode, which requires external

470nf capacitor filtering.Fast charging only works on the first boot screen, which has no effect on the normal display. The purpose of fast

charging is to make the off-chip capacitor fully charged as soon as possible. By default, it is recommended to enable this bit.

7.1.5 LCD Frame Buffer MappingThe mapping relationship between the LCD_BUFx register and the LCD screen of different segment

specifications is as follows.i.When using the 8COM,it is need 36 LCD_BUFs, LCD screen can support up to 8 * 36

LCD_BUF[i]i=0~35SEG maximum 36

SEG[i+4]COM7

SEG[i+4]COM6

SEG[i+4]COM5

SEG[i+4]COM4

SEG[i+4]COM3

SEG[i+4]COM2

SEG[i+4]COM1

SEG[i+4]COM0

ii.When using the 6COM,it is need 38 LCD_BUFs, LCD screen can support up to 6 * 38LCD_BUF[i]i=0~37SEG maximum 38

- - SEG[i+2]COM5

SEG[i+2]COM4

SEG[i+2]COM3

SEG[i+2]COM2

SEG[i+2]COM1

SEG[i+2]COM0

iii.When using the 4COM,3COM,2COM,1COM,it is need 20 LCD_BUFs, LCD screen can support up to 4*40

LCD_BUF[i]i=0~19SEG maximum 40

SEG[2*i+1]COM3

SEG[2*i+1]COM2

SEG[2*i+1]COM1

SEG[2*i+1]COM0

SEG[2*i]COM3

SEG[2*i]COM2

SEG[2*i]COM1

SEG[2*i]COM0

7.2 Register DescriptionsLCD Register Base AddressModules Name Physical Address Mapping AddressLCD 0x40048000 0x40048000LCD Register Offset AddressRegisters Name Address Offset DescriptionsLCD_CTL Offset+0x0 LCD Control RegisterLCD_STATUS Offset+0x4 LCD Status RegisterLCD_CLKDIV Offset+0x8 LCD Clock Control RegisterLCD_BLINK Offset+0xc LCD Flash Control RegisterLCD_PS Offset+0x10 LCD PUMP setting time RegisterLCD_RESCTL Offset+0x14 LCD internal Resistor String

Control RegisterLCD_BUF[i] Offset+0x20+i*1(i=0-37) LCD Data Register(A total of 38

8-bit Registers)7.2.1 LCD Control Register LCD_CTL (0x00)

Offset Address 0x00

12 PWD_PUMP

LCD PUMP Switch0: Open PUMP, LCD voltage generate from internal PUMP1: Close PUMP, use the resistor string divider schemeNote: The RN8612 is a reserved register bit and should not be operated by the user.

11 TYPE LCD Drive Type Select0:Type A 1:Type B

10:5 BIASLVL

LCD Bias voltage regulationControl charge pump output voltages of different magnitudes in order to control LCD contrast.Note: The RN8612 is a reserved register bit and should not be operated by the user.

4 BIASLCD Bias Control0:1/3 Bias1:1/4 Bias

3:1 DUTY

LCD Duty ratio Control000:Static Output(COM0)001:1/2 Duty ratio(COM0~1)010:1/3 Duty ratio(COM0~2)011:1/4 Duty ratio(COM0~3)100:1/6 Duty ratio(COM0~5)101:1/8 Duty ratio(COM0~7)Other: Reserved

LCD Module Enable0:LCD Module Close1:LCD Module EnableNote: When the LCD module is turned off, the LCD enters standby mode and the associated analog circuitry is also turned off to ensure low power consumption.

7.2.2 LCD Status Register LCD_STATUS (0x04)Offset Address 0x04

6 LCD_BUSY

LCD Busy Bit0:Not Busy1:Busy

Note: When LCD_BUSY=1,LCD_CTRL(In addition to EN Bit),LCD_CLKDIV,LCD_BLINK,LCD_PS registers cannot be modified.

5 Reserved Reserved register bits, users do not operate R/W 04 Reserved Reserved register bits, users do not operate R/W 0

3 IRQOFFENDisplay Off IRQ Enable Bit0:Disable1:Enable

2 IRQONEN Display On IRQ Enable Bit0:Disable1:Enable

1 DOFF

Display Off Pending Bit0:No interruption event1:Set when display off by the light changedNote: Write 1 Cleared

Display On Pending Bit0:No interruption event1:Set when display off by the brighterNote: Write 1 Cleared

7.2.3 LCD Clock Control Register LCD_CLKDIV (0x08)Offset Address 0x08

7:0 CLKDIVLCD Clock divider modulusLCD_CLK=fosc/(2*(CLKDIV+1)) (fosc is 32768Hz)

7.2.4 LCD Flash Control Register LCD_BLINK (0x0c)Offset Address 0x0c

25:18 BLINK_TIME

Step is 0.25s,Support 0~63.75sSet TON display a cycle, the time of ON and OFF is equal to 0.25*BLINK_TIMENote: When set to 0, it is represented TON long bright in the display cycle, do not flash. When the value of setting greater than 0, TON must be 2n times BLINK_TIME (n is an integer greater than 0).

17:9 TOFFStep is 0.25s,Support 0~127.5s,When using this function, set to be > 3s;The actual time is:0.25s*TOFF

8:0 TONStep is 0.25s,Support 0~127.5s,When using this function, set to be > 3s;The actual time is::0.25*TON

7.2.5 LCD setting time of charge pump Register LCD_PS (0x10)Offset Address 0x10

11:0 PSLCD PUMP Setup timeTime = Tosc * (PS+4) (Tosc is30.5uS)

R/W 0xccc

Note: This register is not supported by RN8612.7.2.6 LCD internal Resistor String Control Register LCD_RESCTL (0x14)

Offset Address 0x14

12:9 LDOS

LDO output level selection signalLDO output as LCDVD voltage, and through the resistor divider to produce LCDVC, LCDVB, LCDVA;LDO output level is from 2.7V to 3.6V, a total of 16 files, and the gear step is 0.06V;

LDO output 3.0V at reset

R/W 0101

Fast charge control0: Close the fast charging function1: Open the fast charging functionSelect the internal resistor divider, the node voltage is connected to the 470nf capacitor. When the LCD module is turned on, the internal resistor is adjusted to 5k and held for 100ms to complete the fast charging of the capacitor.

7 RES_AO

Resistor string timing drive switch0: The resistor is divided and driven, and the drive signal is generated according to RES_DT and RES _FT1: The resistor string is always driven and the RES_DT and RES_FT configurations are invalidWhen TYPE A is selected, RES _AO is always 1.

6:4 RES_DT Resistor string divider mode, 20k resistor drive time R/W 000

configuration in the brush cycleDrive time Td= (BIAS_DT [2:0] +1)* Tosc (Tosc is 30.5uS).

3:2 RES_FT

Resistor string divider mode, 20k resistor drive times configuration during the screen cycle00: Drive 1 time01: Drive 2 times10: Drive 3 times11: Drive 4 times

R/W 00

Internal resistor divider resistor mode selection signal0: Small resistance + open circuit, 20k resistance is timed on, 200k resistance is always shorted1: Sze resistance switching, 20k and 200k resistance time division switching

0 IRSN

Resistance divider mode selection0 internal resistor divider mode1 reservedIf resistor divider is used, this register can only be configured as 0. A configuration of 1 has no meaning.

If you choose to use the resistor divider method, it is recommended to configure LCD_RESCTL as follows:Typical 3V screen, LCD->RES_CTRL register configuration value: 0xb14.For a typical 3.3V screen, the LCD->RES_CTRL register configuration value is: 0x1514.

7.2.7 LCD Data Register LCD_BUF[i] (8-bit register)Offset Address 0x20-0x45

7:0 LCD_BUFx

SEG display data LCD screen, Each bits of the physical meaning is as follows:

0:Corresponding to the display unit does not display

1:Corresponding to the display unit do display

7.3 LCD operation steps1. Set the 6th bit of the MOD1_EN module enable 1 register to 1 in the system control section to turn on the LCD

module clock gating.2. Set the LCD control register LCD_CTL to 0 to turn off the LCD module.3. Wait for the 6th bit of the LCD_STATUS status register to be 0, idle state. If it is idle, go to the next step,

otherwise wait, the waiting time is about 16MS.4. Set LCD control register LCD_CTL, set LCD display mode, LCD display voltage, and turn on PUMP. For

example, using 8COM, 5v liquid crystal, the LCD_CTL value is 0x3fb. LCD_RESCTL can also be configured to select the resistor divider method.

5. Set the LCD clock control register LCD_CLKDIV to set the division ratio of the LCD.6. Set the LCD flashing control register. If no flashing function is required, it can be directly configured as 0x01.7. After the initial setting is completed, the display data can be directly sent to LCD_BUF[i].

8 Timer

It is built-in two 32-bit timers. Each timer can be completely independent work, not shared any resources between timer, but can operate synchronous.

The timer is suitable for a variety of uses, with the following features:Interval timing;Square wave output;External, internal event countThe single pulse output;PWM OutputPulse width measurement

8.1 OverviewTimer has the following characteristics:

Two 32-bit timers, each timer:Has a 32-bit incremental auto-reload counter.Has a 16-bit programmable prescaler, Frequency coefficients are optional from 1~65535.Support count value dynamic access to.Support free-running mode.Support single run.

Each has 2capture,compare channels, and each channel can be independently configured to :Input capture.Output Compare.Single pulse output.The complementary PWM.

Dead zone length is programmable :The dead zone length of two edge can be set up independently.The polarity of the output is configurable.

Configurable invalid processing :Output disabled.Output cleared.Output three states.

Slave mode support for:External reset and restart.External gating.

Input capture support for:Positive edge capture.Negative edge capture.Double edge capture.Cycle measurement.Pulse width measurement.Optional filtering.

Comparison of output support for:Three state output.

Inverted output.Fixed level output;The pulse width can configure pulse output.Compare register update at any time.

Support interrupt:Counter overflow.Input capture.Output comparison.

8.2 Function Block DiagramThe function block diagram of Counting timer shown below, please refer to. Each counter timer contains a 32-bit

counter and 4 32-bit capture, compare channels.

8.3 Register DescriptionsModule registers base AddressModule Name Physical Address Mapping AddressTC0 0x40010000 0x40010000TC1 0x40014000 0x40014000TC module registers Offset AddressRegisters Name Address Offset DescriptionsTC_CNT 0x0 Instructions of the current

count valuesTC_PS 0x4 Prescale Register

TC_DN 0xC Target Count Value RegisterTC_CCD0 0x14 Capture Comparison Channel 0

Data RegisterTC_CCD1 0x18 Capture Comparison Channel 1

Data RegisterTC_CCFG 0x1C Clock Configuration RegisterTC_CTRL 0x20 Control RegisterTC_CM0 0x24 Capture Comparison Channel 0

mode RegisterTC_CM1 0x28 Capture Comparison Channel 1

mode RegisterTC_IE 0x2C IERTC_STA 0x30 Status Register

8.3.1 The current count values Register TC_CNT (0x00)

31:0 CNT The current count values R 08.3.2 Prescale Register TC_PS (0x04)

31:16 - Reserved R 015:0 PS Frequency coefficient, divide values(PS+1),0 for not division R/W 0

8.3.3 Target count value Register TC_DN(0x0C)

31:0 DN Target count value, The actual count clock cycle is DN+1 R/W 08.3.4 Capture comparison channel 0 data Register TC_CCD0(0x014)

31:0 CCD Comparative Capture Data R/W 0Note: When configuration of channel 0 is capture function (That is CCM bit field of TC_CM0 register is

0),TC_CCD0 register cannot be written8.3.5 Capture comparison channel 1 data Register TC_CCD1 (0x018)

31:0 CCD Comparative Capture Data R/W 0Note: When configuration of channel 1 is capture function (That is CCM bit field of TC_CM1 register is 0),

TC_CCD1 register cannot be written8.3.6 Clock Configuration Register TC_CCFG (0x01C)

31:24 - Reserved R 023:16 FLTOPT The settings of external clock input filter parameter, setting R/W 0

number of clock cycles of filter.15 - R 0

14:13ECLKMODE

External input clock mode:00:Positive Edge01:Negative Edge10:Double Edge11:Reserved(is equal to double edge)

12:8 CS

Selection of external input:0:UART0 RXD1: UART1 RXD2: UART2 RXD3: UART3 RXD4: The output outn[0] of another timer (TC0 or TC1)5: The output outp[0] of another timer (TC0 or TC1)6: The output outn[1] of another timer (TC0 or TC1)7: The output outp[1] of another timer (TC0 or TC1)8: UART4 RXD9: UART5 RXD10:7816_0 Input P4111:7816_1 Input P4212:7816_1 Input P4313 15: Reserved16:sf_out17: qf_out18: pf_out19: rtc_out20: p1[0] Outer IO21: p1[1] Outer IO22: p1[2], P5[2] Outer IO23: p1[3], P5[3] Outer IO24: p1[4], P5[4] Outer IO25: p1[5], P5[5] Outer IO26: p1[6], P5[6] Outer IO27: p1[7], P5[7] Outer IO28: p3[0],Outer IO29: p3[1],Outer IO30: p3[3],Outer IO31: p3[5],Outer IO

7:2 - Reserved R 0

1 FLTENFiltering enables of external clock input

0:Disable1:Enable

0 CMSelection of count clock source:

0:Internal system clockR/W 0

1:External system clock(Select clock source by the CS)8.3.7 Control Register TC_CR (0x020)

Bit Name Descriptions R/wReset Value

31:29 - Reserved R 028 DBGSTBDIS The counter is enabled when in debug:

0:Disable(When the CPU is in debug state ,the counter stops counting)

1:Enable(When the CPU is in debug state, the counter continues to count)Note: CPU is in debug state refers to users would stop Cortex M0 through debugging interface (PC pointer stops counting).

27 -- Reserved R/W 026 -- Reserved R/W 025 -- Reserved R/W 024 -- Reserved R/W 023:21 -- Reserved R 0

20SLVGATELVL

Effective level of slave mode gated mode: 0:Effective level is Low level 1:Effective level is High level

19:12 SLVFLTOPT Slave Mode input filter parameters R/W 0

11:10SLVTRGMODE

Selection of slave Mode control mode : 00:Positive edge cleared the internal counter 01:Negative edge cleared the internal counter 10:Double edge cleared the internal counter 11:Gated mode(The internal counter counts when the external input signal is effective level )

9:5SLVCHANSEL

Election of slave mode external input events:Consistent with definitions of external input clock which clock configuration register (0x01C) bit field in CS definition.

Election of single count mode:0:Disable single count mode(Not stop after counter

overflow ,the loop count);1: Enable single count mode(Stop after counter overflow)

3 SLVFLTENFiltering enables of slave mode external input events:

0:Disable1:Enable

2 SLVENSlave mode enable:

0:Disable1:Enable

1 -- Reserved R 0

0 STARTTimer start:

0:StopR/W 0

1:Start 8.3.8 Capture comparison channel 0,1 mode Register TC_CM0/1(0x024 and 0x028)

31:30 - Reserved R 0

29 DFTLVLThe default level of comparison output:

0:Low level1:High level

28 EFELVLEffective level of comparison output:

0:Low level1:High level

27:25 OM

Mode of comparison output :000:No output(Three states)001:Set to effective level010:Set to invalid level011:Flip flop100:Forced to effective level101:Forced to invalid level110:PWM mode1111:PWM mode2

24:20 CSSelection of capture external input events:Consistent with definitions of external input clock which clock configuration register (0x01C) bit field in CS difinited.

19 FLTENFiltering enables of capture external input events:

0:Disable1:Enable

18:11 FLTOPT Filtering parameter of capture external input events R/W 0

10:9 CPOL

Polarity selection of capture external input events: 00:Positive Edge 01:Negative Edge 10:Double Edge 11:Reserved

8:3 DLLength of output dead zone of comparison (Only support PWM mode 1 and PWM mode 2,this bit is invalid in other modes)

2 DIEN

Insert enable of output dead zone of comparison:(Only support PWM mode 1 and PWM mode 2,this bit is invalid in other modes )

0:Disable1:Enable

1 CCMSelection of capture or comparison mode:

0:Capture1:Comparison

0 ENABLEChannel enables:

0:Disable1:Enable

8.3.9 IERTC_IE(0x2C)

31:4 -- Reserved R 0

3 SLVIESlave Mode Interrupt Enable: 0:Disable 1:Enable

2 CC1IECapture Comparison Channel 1 Interrupt Enable:

0:Disable1:Enable

1 CC0IECapture Comparison Channel 0 Interrupt Enable:

0:Disable1:Enable

0 OVIEOverflow Interrupt Enable:

0:Disable1:Enable

8.3.10 State Register TC_STA(0x30)

Bits Name Descriptions R/WReset Value

31:4 -- Reserved R 0

3 SLVFSlave Mode Event Flag:(Write 1 cleared)

0:No Slave Mode Event 1:Slave Mode Event

2 CC1F

Event Flag of Capture Comparison Channel 1:(Write 1 cleared)

0:No capture or compare event1:Has capture or compare event

1 CC0F

Event Flag of Capture Comparison Channel 0:(Write 1 cleared)

0:No capture or compare event1:Has capture or compare event

0 OVFEvent Flag of Overflow:(Write 1 cleared)

0:No Overflow Event1:Overflow Event

8.4 Typical Applications8.4.1 Automatic Operation Mode, Timing Function

The automatic operation mode is the interval timer function.The basic timing functions, only need to set the following register:

1. Target count value register is the timing length, which counted by the clock of counting.

2. Enable overflow of interrupt enable register which interrupts enable.3. Control register which starts timer.

The timer will take target count values as cycle generates interrupt.

Configuration instructions of commonly used selectable function:1. Can modify the prescaler register values and change the frequency of timer counter clock .2. Configurable clock configure register, CM modify the configuration is external input clock, modify the

external input clock options of CS bit configuration at the same time. External input clock frequency can not be higher than two frequency divider of internal system clock frequency.

3. Single count mode, when the timer overflow and then stop; OPS bit of configuration control register is 1,that is single count mode.

4. External input clock source as the output of another timer, and it can be connected in cascade mode for the two timer, also can increase the register bits width of the timer.

8.4.2 Input Capture Mode, Function of Pulse Width MeasurementThe main function of input capture mode is measure the width of the pulse.The basic function of pulse width measurement, only need to set the following register:1. Target count value register, counted by counting clock and it can be set to the maximum value.2. Settings of capture comparison channel 0, 1 mode register, ENABLE channel 0,1 enable it, CCM is

configured to capture mode, CPOL select the polarity of the capture, CS select external input event.3. Enable capture comparison channel 0, 1 of interrupt enable register which interrupts enable.4. Control Register which starts timer.When the timer capture to capture polarity of the external input event, then generate an interrupt, the current

count is saved in the capture comparison channel data register at the same time. If using two channels, a channel to capture positive edge and another channel to capture negative edge, the pulse width can be calculated through data register of two channels.Configuration instructions of commonly used selectable function:

1. Can modify the prescaler register values and change the frequency of timer counter clock .2. Configurable clock configure register, CM modify the configuration is external input clock, modify the

external input clock source of CS bit configuration at the same time. External input clock frequency can not be higher than two frequency divider of internal system clock frequency.

3. Filtering function of external input event, enabled the FLTEN filtering function of capture comparison channel mode register and set filter cycle number by configuring the FLTOPT.

4. External input clock source as the output of another timer, and it can be connected in cascade mode for the two timer, also can increase the register bits width of the timer.

8.4.3 Comparison Output Mode, Function of Square Wave OutputFunction of square wave output that is dividing the frequency output to the count clock of TC .Each timer has two

output channels, each channel has two output terminals P and N, where P is the positive output port, N is the reverse of the output port P.

Function of square wave output, only need to set the following register:1. Target count value register, counted by counting clock and it can be set to the maximum value.2. Settings of capture comparison channel 0, 1 data register, ENABLE channel 0,1 enable it, CCM is configured

to comparison mode, DFTLVL is configured to default level, EFELVL is configured to effective level, the output of OM is configured to flip function.

3. Set the capture comparison channel 0,1 data register.(The setting values less than target count value register)4. Enable capture comparison channel 0, 1 of interrupt enable register which interrupts enable.5. Control Register which starts timer.

The values of the target count value register decided to cycle of square wave output, the value of capture comparison channel 0, 1 data register is the flip flop point of output.

Configuration instructions of commonly used selectable function:1. Can modify the prescaler register values and change the frequency of timer counter clock.2. Configurable clock configure register, CM modify the configuration is external input clock, modify the

external input clock source of CS bit configuration at the same time. External input clock frequency cannot be higher than two frequency divider of internal system clock frequency.

3. Filtering function of external input clock, enabled the FLTEN filtering function of clock configuration register and set filter cycle number by configuring the FLTOPT.

8.4.4 Mode of Compare Output, Function of PWM OutputThe mode of pulse width measurement (PWM) can generates a signal which is determined the frequency by a

TC_DN register and is determined the duty ratio by a TC_CCDx register .It support two PWM modes: PWM mode 1 and PWM mode 2:PWM mode 1: If TC_CNT<TC_CCDx, the output is effective level, otherwise it is invalid level.PWM mode 2: If TC_CNT>=TC_CCDx, the output is effective level, otherwise it is invalid level.

Below is the typical application diagram of PWM mode 1.

Function of PWM output, only need to set the following register:1. Target count value register, counted by counting clock.2. Settings of capture comparison channel 0, 1 mode register, ENABLE channel 0,1 enable it, CCM is

configured to comparison mode, DFTLVL is configured to default level, EFELVL is configured to effective level, the output of OM is configured to PWM mode 1 or PWM mode 2.

3. Set the capture comparison channel 0,1 data register, must be smaller than target count value register.4. Control Register which starts timer.To output positive waveform of PWM mode 1/PWM mode 2 in the channel of the P-ternimal, and in the channel

of the N-terminal, and which output the reverse waveform to the P-side in the channel.PWM mode 1: Cycle is values of target count value register plus 1, effective level cycle is the number of cycles

of channel data register values plus 1.PWM mode 2: Cycle is values of target count value register plus 1, invalid level cycle is the number of cycles of

channel data register values plus 1.Configuration instructions of commonly used selectable function:

1. Can modify the prescaler register values and change the frequency of timer counter clock.2. Configurable clock configure register, CM modify the configuration is external input clock, modify the

external input clock source of CS bit configuration at the same time. External input clock frequency cannot

be higher than two frequency divider of internal system clock frequency.3. Complementary output of dead zone insertion, DIEN dead zone insertion enables, DL is to configure length

of dead zone insertion. Add the delay in switch between P and N, that is do not let the two edges flip flop at the same time.When effective level EFELVL is Low level: Output negative edge of P and N delayed DL cycles.When effective level EFELVL is High level: Output positive edge of P and N delayed DL cycles.

8.4.5 Slave Mode, External Clear and Gating FunctionsThe salve mode adds an external input evens to control the internal counter clear and gating functions in the

original feature.External clear function, you need to set the following registers:

1. Target count value register, counted by the count clock.2. Enable overflow in the interrupt enable register interrupt enable.3. Control register, SLVEN slave mode enable, SLVTRGMODE slave mode control mode selection,

SLVCHANSEL the external input events of slave mode selection.4. Control, start the timer.

This in the free running mode to add an external reset internal CNT function.Common optional functions configuration instructions:

1. The prescaler register value can be modified, the timer count clock frequency can be changed.2. Configurable clock configuration register, CM modify the configuration to the external input clock, while

modifying the external input clock source of the CS bit configuration. The frequency of external input clock source cannot higher than the two frequency of internal system clock.

3. Single count mode, the timer stop after overflowing; configuration control register OPS bit is 1 is the single count mode.

4. It can be connected two timer to cascade mode when external input clock source is another timer output, which increases the timer register bits wide.

5. In the slave mode control mode selection, if you choose to gated mode, SLVGATELVL slave mode gated active level configuration, the internal counter of slave mode input will count when gating level is effective.

6. Configurate input capture mode in slave mode, capture mode select one edge are slave mode polarity select another edge when the external input events of slave mode and capture is in same configuration, it can access to the pulse width from capture/compare channel data register.

8.5 Operation stepsBriefly describe the operation steps as an interval timer, setting TC0 to 1MS interval timer interrupt:1. In the Configure System Control section, the module enable 0 register MOD0_EN bit 4 starts the TC0 clock.

Note that to write the system control chapter register, first write SYS_PS to 0x82, open the write enable. After the system control register to be written is completed, write SYS_PS to 0 and turn off the write enable.

2. Set the TC0 module register:The clock configuration register TC_CCFG is configured as the internal system clock, TC0->CCFG = 0;Configure the prescaler register TC_PS;Configure the target value register TC_DN;Configure the control register TC_CR, TC0->CTRL = 0x01; start the TC0 timerSet interrupt enable register TC_IE, TC0->IE = 0x01; configured as overflow interrupt enable;When the system clock is 3.6864MHZ, TC0->PS = 255; TC0->DN = 13 can generate 1MS interrupt after

configuration. (3.6864MHZ/(255+1))/(13+1) = 1MS.3. Enable TC0 interrupt enable, NVIC_EnableIRQ(TC0_IRQn).4. Write the interrupt service routine:Void TC0_HANDLER (void){/* Start adding user code. Do not edit comment generated here */}5. A 1MS interrupt can be generated after the configuration is completed.

9 Analog Peripherals

9.1 Features10bit SAR ADC;

When the voltage input to the VBAT pin and AIN6 pin is started, there are two 300K resistors inside to divide the voltage. The input voltage is reduced by half to the SAR ADC. The SAR ADC uses the 0.5x PGA to double the signal. Namely: 3.6V battery, the measured signal is about 0.9V. If the measurement is not started, the internal partial resistor will be turned off.9-channel analog multiplexer, where AIN0 – AIN6 channels are used for external analog signal measurement, VBAT is used for battery voltage measurement, Temp Sensor is used to measure temperature sensor output, and temperature sensor has the highest priority.The input impedance of AIN0~AIN5 is about 3M ohms.In addition to AIN6, other AINs support up to 1.25V input. Gain support 0.5 times, 1 time, 1.5 times, 2 times.When the ADC is not sampling, it automatically enters the power saving mode; each sampling is about 2ms from startup to completion.

The main features of one LVD circuit are as follows:The input of LVD can choose the power for the chip or an external input PIN;LVD threshold is adjustable, which is divided into 14 files from 2.3V to 4.9V;When selecting an external PIN as input, the threshold value is fixed at about 1.25V, and the internal resistance is about 1M ohm.

The main features of two comparator circuit CMP1 and CMP2 are as follows:External PIN input, the threshold is about 1.28V;The power consumption is better than 1uA. The comparator can be used to monitor the main power;Note that there are 600K pull-down resistors inside CMP1 and CMP2, and the internal resistor can be turned off by register (SYS_PD (0x08)).

9.2 Register

Base address of analog peripheral moduleModule Name Physical Address Address MappingANA 0x4002C000 0x4002C000

Register offset address of analog peripheral moduleRegister Name Address Offset Description

SAR_CTL Offset+0x0 SAR-ADC Control RegisterSAR_START Offset+0x4 SAR-ADC Start RegisterSAR_STAT Offset+0x8 SAR-ADC Status RegisterSAR_DAT Offset+0xC SAR-ADC Data RegisterLVD_CTL Offset+0x10 Comparator Control RegisterLVD_STAT Offset+0x14 Comparator Status Register

ANA_PAD Offset+0x3cVBAT domain analog PADconfiguration register

ANA_RST Offset+0x40 VBAT domain software reset register

9.2.1 ADC Control Register SAR_CTL (0x00)Offset Address 0x00

Bit Name DescriptionR/W Sign

Reset Value

16:12 REF_WAIT

The wait time from REF started to ADC started:The typical value of the minimum waiting time is 122us5’d0: 122us5’d31: (31+1)*122usNote: It is recommended that the client application configure this register to 0x10, which is 2074us.

11:7 SAR_WAIT

The wait time from SAR ADC started to sampling convert started:5’d0: 30.5us5’d31: (31+1)*30.5usWait Time=(SAR_WAIT+1)*30.5usNote: Step of start ADC measurement:Start REF, wait time of REF_WAIT;Start ADC and Temperature Sensor, wait time of SAR_WAIT;Input clock and reset single, the sampling results obtained after 16 clock cycles.The above steps are achieved from hardware automatic control.Note 1: Due to the deviation of the internal time base, if the software setting waits for the timeout and waits for the timeout, it is recommended to leave a margin of 3-5 times.Note 2: It is recommended that the client application configure this register to the default value of 0xE, which is 457.5us.

R/W 0xE

6 SAR_CH3

The SAR-ADC Channel is selected to form a 4-bit register with SAR_CH [2:0].{SAR_CH3, SAR_CH[2:0]}=0xxx: See SAR_CH definition{SAR_CH3, SAR_CH[2:0]}=1000: Select AIN6{SAR_CH3, SAR_CH[2:0]}=Other: Reserved

5 SAR_IESAR-ADC Interrupt Control:1:Enable ADC interrupt output;

0:Unable ADC interrupt output.

4:3 SAR_PGA

SAR-ADC Gain Control:00: 0.5 01: 1 10: 1.5 11: 2

2:0 SAR_CH

SAR-ADC Channel Choose000: Temp Sensor001:VBAT(For 3.6V battery, obtain 1.8V after 1/2 patrial pressure, PGA use 0.5 times, measure input 0.9V)010:AIN0011:AIN1100:AIN2101:AIN3110:AIN4111:AIN5Note: Regardless of which channel is selected, automatic temperature measurement is the highest priority.

Remark: the above registers could write only when ST=0 in SAR_START.

9.2.2 SAR-ADC Start Register SAR_START (0x04)Offset Address 0x04

Reset Value

SAR-ADC Start Bit0:SAR-ADC No Operation;1:Start SAR-ADC sampling one time, automatically clear after the completion of the sampling.Note:1. Automatic temperature measurement controlled by the RTC

is not controlled by the bit, and a higher priority than the configuration bits.

2. When the ADC_START bit is 1, the software is forbidden to write 1 again to start the SAR-ADC measurement; after the last SAR-ADC conversion is completed, the bit is 0 after 100us (that is, after detecting 0, then delay 100us), the new can be started. SAR-ADC measurement; recommended timeout wait time = 2* (REF_WAIT + SAR_WAIT) + 3ms.

9.2.3 SAR-ADC Status Register SAR_STATUS (0x08)Offset Address 0x08

Reset Value

1 TPS_BUSY

Automatical temperature measurement bit,=1:Automatical temperature measurement in process;=0: No automatical temperature measurement.When TPS_BUSY =1,software write ADC_START register,hardware operations will work after TPS_BUSY is 0.

0 DREADY

ADC Date Ready Pending Bit0:ADC The conversion result is not completed1:ADC The conversion result is completedNote:1. Write 1 clear;2. Automatical temperature measurement controlled by the

RTC is not indicated in this state;

9.2.4 ADC DAT Register SAR_DAT(0x0c)Offset Address 0x0c

Reset Value

15:10 Reserved Reserved R 09:0 SAR-DAT The conversion result of ADC R 0

9.2.5 LVD Control Register LVD_CTL (0x10)Offset Address 0x10

Reset Value

7 CMP2IEComparator 2 enable interrupt:=0:Enable uninterrupted;=1:Enable interrupt;

6 CMP1IEComparator 1 enable interrupt:=0:Enable uninterrupted;=1:Enable interrupt;

5 LVDIELVD enable interrupt:=0:Enable uninterrupted;=1:Enable interrupt;

4 Reserved Reserved R 0

3:0 LVDS

Set LVD threshold voltage:0000 2.7 0001 2.7 0010 2.7 0011 2.90100 3.1 0101 3.3 0110 3.5 0111 3.7 1000 3.9 1001 4.1 1010 4.3 1011 4.51100 4.7 1101 4.9 1110 Detect voltage of external pin LVDIN0 to compare with LBGR(1.25V);1111 Reserved;

Note:LVD,Comparator 1 and Comparator 2 merge an interrupt vector; SAR is a single interrupt vector.

9.2.6 LVD Status Register LVD_STAT (0x14)Offset Address 0x14

Reset Value

6 CMP2IIF

Comparator 2 interrupt flag=0:No interrupt is generated;=1:Generate an interrupt;Interrupt is generated when the input voltage is low relative to the threshold or becomes high, cleared by writing 1;

5 CMP1IIF

Comparator 1 interrupt flag=0:No interrupt is generated;=1:Generate an interrupt;Interrupt is generated when the input voltage is low relative to the threshold or becomes high, cleared by writing 1;

4 LVDIIF

LVD interrupt flag=0:No interrupt is generated;=1:Generate an interrupt;Interrupt is generated when the input voltage is low relative to the threshold or becomes high, cleared by writing 1;

3 Reserved Reserved R 0

2 CMP2IFComparator 2 status flag=0:Below threshold;=1:Above threshold, only read;

1 CMP1IF

Comparator 2 status flag=0:Below threshold;=1:Above threshold;only read;

0 LVDIFLVD status flag=0:Below threshold;=1:Above threshold, only read;

9.2.7 ANA_PADANA PAD RegisterOffset=0x3c

Reset Value

1 P45_AENSAR ADC Measuring input switch0:close; 1:open:

R/W 1’b0

0 P44_AENSAR ADC Measuring input switch0:close: 1:open:

R/W 1’b0

Note: If you want to use the AIN function of the P44/P45 port (SAR ADC measurement input), you must configure the ANA_PAD register (0x3C).

9.2.8 ANA_RSTANA RST RegisterOffset=0x40

Reset Value

15:8 psWrite password protection bit for [7:0]=0xa5, [7:0] can be written= other values, [7:0] cannot be written

7:0 ana_rst

Forced reset of all registers with reset on VBAT power domain, excluding perpetual calendar register=0xa8, reset all registers with reset terminal in VBAT power domain= other, does not work

Note: To reset the registers of the VBAT power domain, proceed as follows:Open the password protection bit of the ANA RST register: ANA RST = 0xa500;1. Put the VBAT power domain in the reset state: ANA RST = 0xa5a8;2. Delay 300us;3. Release the VBAT power domain reset state: ANA RST = 0xa500;4. Disable the password protection bit of the ANA RST register: ANA RST = 0x0000.

9.3 ADC voltage detection steps1. Configure the system control chapter module enable 1 register MOD1_EN bit 11 to 1, turn on the SAR_EN

clock.2. Determine whether the first bit of SAR_ADC status register SAR_STATUS is 0. No automatic temperature

measurement is performed. If it is 0, it will enter the next step. If it is 1, it will wait.3. Configure the ADC control register SAR_CTL, configure the wait time and gain, and select the

corresponding ADC channel for the channel.4. The SAR-ADC start register SAR_START is configured to 1 to initiate ADC conversion.5. Determine the 0th bit of the SAR-ADC status register SAR_STATUS and wait for the conversion to

complete.6. Read the ADC conversion data register SAR_DAT.7. Calculation: The ADC reference voltage source is 1.25V, and the ADC DAT register value is 1024 when the

ADC is full. The calculation formula is (ADC DAT *1.25) / 1024. When the voltage value exceeds the full scale of the ADC, the conversion value is 1024.

8. Conversion and calculation is completed.

9.4 VBAT voltage detection1. Configure the system control chapter module enable 1 register MOD1_EN bit 11 to 1, turn on the SAR_EN

clock.2. Determine whether the first bit of SAR_ADC status register SAR_STATUS is 0. No automatic temperature

measurement is performed. If it is 0, it will enter the next step. If it is 1, it will wait.3. Configure the ADC control register SAR_CTL channel to be VBAT, configure the waiting time;4. The SAR-ADC start register SAR_START is configured to 1 to initiate ADC conversion.5. Determine the 0th bit of the SAR-ADC status register SAR_STATUS and wait for the conversion to

complete.6. Read the ADC conversion data register SAR_DAT.7. Calculation: The ADC reference voltage source is 1.25V, and the ADC DAT register value is 1024 when the

ADC is full. The 3.6V battery is directly connected to the VBAT pin, and the MADC->AD_CTRL is configured to 0x01. At this time, the gain is 0.5 times, then the voltage is The value is (ADC DAT *1.25*4) / 1024, where the gain is 0.5 times, the internal VBAT access has 1/2 partial pressure, so the actual voltage needs to be multiplied by 4.

8. Conversion and calculation are completed.

9.5 Low Voltage Detection Application1. For the energy meter with battery, in order to save battery power, it is necessary to judge the external power

state, and let the system enter sleep mode when the power is low. The power detection module needs to be always on. The CMP2/CMP1 comparator is a very low power comparator. This comparator can be used to detect the power supply voltage and operate in battery mode. The CMP input pin voltage is compared with the reference 1.25V and an interrupt is generated. And status flags.

2. Configure the system control chapter module enable 1 register MOD1_EN bit 11 to 1, turn on the SAR_EN clock.

3. Configure the system control section. The 5th position 0 of the system power-down control register SYS_PD turns on the CMP2 power supply.

4. Configure the LVD control register LVD_CTL to enable the CMP2 interrupt. Enable CMP2 interrupt NVIC_EnableIRQ (CMP_IRQn).

5. Write the interrupt service program:Void CMP_HANDLER (void){If(!(MADC->LVD_STAT & 0x04)){}Else{}MADC->LVD_STAT = 0x01ff;}Since LVD, CMP1, and CMP2 use the same interrupt service routine, the interrupt status needs to be judged

based on LVD_STAT.6. Complete.The CMP hardware filtering time is 100 system clocks. It is recommended that the software confirm and filter the

CMP status after the interrupt wakes up.

10 GPIO

10.1 OverviewContain PA,PB,PC three GPIOPA ports include 5 P0 ports,8 P1 ports, 8 P2 ports, 8 P3 portsPB ports include 8 P4 ports, 8 P5 ports, 8 P6 ports, 8 P7 portsPC ports include 8 P8 ports, 8 P9 ports ,8 P10 ports,8 P11 portsGPIO is peripheral of AHB

Support bitband operation;Note: The SEG/IO multiplexed pin of the RN8611/8613/8615/8318 is an open-drain structure when used as an IO port. The RN8612/RN8610B is a common structure.

10.2 Register descriptionGPIO Register Base Address:

Module Name Physical Address Address Mapping

GPIO 0x50000000 0x50000000

GPIO Register Offset Address

Register Name Address Offset Description

PMA 0x00H PA port mode register(input or output)

PA 0x04H PA port data register

PCA0 0x08H PA port reuse register 0

PCA1 0x0CH PA port reuse register 1

PUA 0x10H PA port pull-up selection register

PIMA 0x14H PA port input mode configuration

PIEA 0x18H PA port input enable selection

PMB 0x1CH PB port mode register(input or output)

PB 0x20H PB port data register

PCB 0x24H PB port reuse register

PUB 0x28H PUB port pull-up selection register

PIMB 0x2CH PB port input mode configuration

PIEB 0x30H PB port input enable selection

PMC 0x34H PC port mode register(input or output)

PC 0x38H PC port date register

PCC 0x3CH PC port reuse register

PUC 0x40H PUC port pull-up selection register PCC PC port reuse

register

PIEC 0x44H PC port input enable selection

PIMB 0x48H PC port input mode register

PCB2 0X4CH PB port multiplexes register 2

PCE 0x60H SEGCOM port multiplexes register

PASET 0X64H PA port data reset register, write 1 to this register, a correspond bit in PA port will be write 1;

PACLR 0X68H PA port data clear register, write 1 to this register, a correspond bit in PA port will be cleared;

PBSET 0X6CH PB port data reset register, write 1 to this register, a correspond bit in PB port will be write 1;

PBCLR 0X70H PB port data clear register, write 1 to this register, a correspond bit in PB port will be cleared;

PCSET 0X74H PC port data reset register, write 1 to this register, a correspond bit in PC port will be write 1;

PCCLR 0X78H PC port data clear register, write 1 to this register, a correspond bit in PC port will be cleared;

Note: IO port type, see Chapter 1.4 Pin Arrangement.Recommends using bitband function (see chapter 4.3.2) to access GPIO registers, facilitate the IO port

register bit operations related.Also can be SET / CLR register (0x64H ~ 0x78H) write GPIO data register;If the IO port configuration options for the multiplexing function outside the IO port, mode register, the

data register, input enable register is invalid, the pull-up selection, input mode selection is valid in all multiplex configuration.

10.2.1 PA port mode register PMA(input or output)(0x00)

Reset Value

31:24 PM37~PM30=0 Output Mode=1 Input ModePM37 and PM36 are read only, read 1, only can be input model;

R/W FF

23:16 PM27~PM20=0 Output Mode=1 Input Mode

R/W FF

R/W 1F

10.2.2 PA port data register PA(0x04)

Reset Value

31:30 P37~P36 P36 and P37 data input register, read-only; R 0

29:24 P35~P30Define data needed in the chip output port.If you read in the input mode, the pin level is read. If you read in the output mode, then read the output latch value

R/W 00

4:0 P04~P00

Define data needed in the chip output port.If you read in the input mode, the pin level is read. If you read in the output mode, then read the output latch valueIf defined as an analog input, the input mode to read a value of 0.

R/W 00

10.2.3 PA port reuse 0 register PCA0 (0x08)When selected as an analog input, the input mode is automatically selected, PMA register is invalid.

Reset Value

31 --- Reserved R 0

30UART2_SEL

=0: P24 and P25 can be selected as UART2 interface when PC245=1;=1: When PC00 and PC01 are valid, they can be selected as UART2 interface;

29 SWD_SEL=0:P24 and P25 don’t select SWD, define by PC245(bit27);=1:P24 and P25 select SWD;

28 PC267Define the port P26 and P27 multiplex configuration:=0:select IO port;=1:select UART3 port.

R/W 00

24:9PC17[1:0]PC16[1:0]PC15[1:0]

Define the port P10~P17 multiplex configuration:=00:select IO port;=01:select KEY input port;

R/W 00

PC14[1:0]PC13[1:0]PC12[1:0]PC11[1:0]PC10[1:0]

=10: select TC output port;=11: select TC input port.The TC outputs corresponding to P17~P10 are {tc1_p[1], tc1_n[1], tc1_p[0], tc1_n[0], tc0_p[1], tc0_n[1], tc0_p[0], tc0_n[0]} respectively.

8 KEY4_SEL=0: The function of P04 is determined by PC04 bit;=1: P04 is selected as KEY4 (PC14 is selected as KEY4 with high priority);

R/W 00

7 --- Reserved R 0

6:4 PC04~PC02Define the port P04~P02 multiplex configuration:=0:select IO port;=1:select analog input port

3:2 PC01

Define the port P01 multiplex configuration:=00:select IO port;=01:select analog input port;=10: Select KEY3 (PC13 selects KEY3 as high priority);=11: Select as TX2 ;

1:0 PC00

Define the port P00 multiplex configuration:=00:select IO port;=01:select analog input port=10: Select KEY2 (PC12 selects KEY2 as high priority);=11: Select as RX2 ;

10.2.4 PA port reuse 1 register PCA1(0x0C)

Reset Value

15:14 PC37[1:0]

Define the port P37 multiplex configuration:=00:select IO port;=01:select an external interrupt input port INT7;=1x:select pin crystal POSCINote: Just PC36 [1] and PC37 [1] in any one of the high, then choose to POSC

13:12 PC36[1:0]

Define the port P36 multiplex configuration:=00:select IO port;=01:select an external interrupt input port INT6;=1x:select pin crystal POSCONote:Just PC36 [1] and PC37 [1] in any one of the high, then choose to POSC

11:10 PC35[1:0]

Define the port P35 multiplex configuration:=00:select IO port;=01:select an external interrupt input port INT5;=10: select input for TC;=11: Reserved;

9:8 PC34[1:0]

Define the port P34 multiplex configuration:=00:select IO port;=01:select an external interrupt input port INT4;=10:select as the apparent energy pulse output SF_OUT;=11: Reserved;

7:6 PC33[1:0]

Define the port P33 multiplex configuration:=00:select IO port;=01:select an external interrupt input port INT3;=10: select input for TC;=11: Reserved;

5:4 PC32[1:0]

Define the port P32 multiplex configuration:=00:select IO port;=01:select an external interrupt input port INT2;=10:select as RTC output RTC_OUT (the default choice for the RTC output)=11: select IO port.

R/W 10

3:2 PC32[1:0]

Define the port P32multiplex configuration:=00:select IO port;=01:select an external interrupt input port INT1;=10: select input for TC;=11: select RX4;

1:0 PC30[1:0]

Define the port P30 multiplex configuration:=00:select IO port;=01:select an external interrupt input port INT0;=10:select TC input;=11:Reserved;

10.2.5 PA port pull-up select register PUA(0x10)Note:When the IO port in output mode or analog PAD mode, regardless of how the configuration register PU, PIN not enable pull-up.

Reset Value

31:24 PU37~PU30Define port pull-up configuration:=0:Don't select pull-up;=1:Select pull-up;

R/W 00

23:16 PU27~PU20

Define port pull-up configuration:=0:Don't select pull-up;=1:Select pull-up;Note:P24 and P25 as SWD default pull-up enable.

R/W 30

15:8 PU17~PU10Define port pull-up configuration:=0:Don't select pull-up;=1:Select pull-up;

R/W 00

7:5 -- Reserved R 04:0 PU04~PU00 Define port pull-up configuration: R/W 00H

=0:Don't select pull-up;=1:Select pull-up;

10.2.6 PA port input mode configuration register PIMA(0x14)

Reset Value

31:24 PIL27~PIL20Define port P20~P27 input buffer type:=0:CMOS buffer, Vil=0.3VCC Vih=0.7VCC;=1:TTL buffer, Vil=0.16VCC Vih=0.4VCC;

R/W 00

15:8 PID27~PID20Define port P20~P27 whether is N-ch open-drain output:=0:Normal mode;=1:N-ch open-drain output mode;

R/W 00

7:0 PID17~PID10Define port P10~P17 whether is N-ch open-drain output:=0:Normal mode;=1:N-ch open-drain output mode;

R/W 00

10.2.7 PA port input enable register PIEA (0x18)

ResetValue

31:24 PIE37~PIE30

Input Enable:=1:No input enable;=0:Input enable;Note: The P30 is set to enter the electricity needs BOOTROM enabled, ISP is easy to detect.

R/W FF

23:16 PIE27~PIE20Input Enable:=1:No input enable;=0:Input enable;

R/W FF

4:0 PIE04~PIE00Input enable:=1:No input enable;=0:Input enable;

R/W 3F

10.2.8 PB port mode register PMB(input or output)(0x1C)

Reset Value

31:24 PM77~PM70=0 Output mode=1 Input mode

R/W FF

When the IO port is set to 7816 port or SPI port, direction register does not work, it controls by the communication module itself.

10.2.9 PB port data register PB(0x20)

Reset Value

R/W 00

10.2.10 PB port reuse register PCB (0x24)

Reset Value

31:24 PC77~PC70PC77~PC70 define port multiplex configuration:=0: select IO port;=1: select LCD.

R/W 00

23:16 PC67~PC60PC67~PC60 define port multiplex configuration:=0: select IO port;=1: select LCD.

R/W 00

15:8 PC57~PC50

PC57~PC50 define port multiplex configuration:=0: select IO port;=1: select others.P50-PF(INT2 pin output),P51-QF(INT0 pin output),P52-SCL,P53-SDA,P54- UART5-RX,P55-UART5-TX,P56- Reserved,P57- ReservedNote: The RTCOUT multiplexing relationship of port P56 is determined by the RTC chapter register and is independent of the GPIO chapter multiplexing configuration register.When VCC has no power and VBAT is powered on, P56 outputs 1Hz by default. Once VCC is powered up, the 1Hz output will be turned off. Peripheral circuit design needs to pay attention to this problem.

R/W 03

7:0 PC47~PC40

P47~P40 define port multiplex configuration:=0:select IO port;=1:P40~P43 select 7816 P44~47 select SPI.Default Select GPIO.The P44/P45 is originally multiplexed as SPI. This function is reserved (not recommended for customers). P50/P51 adds this multiplexing relationship; its analog input port multiplexing relationship (AIN5/AIN6) is determined by the analog peripheral chapter register.

R/W 00

10.2.11 PB port reuse register 2PCB2 (0x4CH)

Bit Name Description R/W SignReset Value

31:30 PC57_2

P57 port multiplexing configuration 2:=00: The P57 port function is determined by the PC57 register bit (0x24).=01: P57 is selected as TCIN.=10: P57 is selected as TC1_P[1];=11: Reserved

R/W 00

29:28 PC56_2

P56 port multiplexing configuration 2:=00: The P56 port function is determined by the PC56 register bit (0x24).=01: P56 is selected as TCIN.=10: P56 is selected as TC1_N[1];=11: ReservedNote: The RTCOUT multiplexing relationship of port P56 is determined by the RTC chapter register and is independent of the GPIO chapter multiplexing configuration register.When VCC has no power and VBAT is powered on, P56 outputs 1Hz by default. Once VCC is powered up, the 1Hz output will be turned off. Peripheral circuit design needs to pay attention to this problem.

R/W 00

27:26 PC55_2

P55 port multiplexing configuration 2:=00: The P55 port function is determined by the PC55 register bit (0x24);=01: P55 is selected as TCIN.=10: P55 is selected as TC1_P[0];=11: Reserved

R/W 00

25:24 PC54_2

P54 port multiplexing configuration 2:=00: The P54 port function is determined by the PC54 register bit (0x24);=01: P54 is selected as TCIN.=10: P54 is selected as TC1_N[0];=11: Reserved

R/W 00

23:22 PC53_2

P53 port multiplexing configuration 2:=00: The P53 port function is determined by the PC53 register bit (0x24);=01: P53 is selected as TCIN.=10: P53 is selected as TC0_P[1];=11: Reserved

R/W 00

21:20 PC52_2

P52 port multiplexing configuration 2:=00: The P52 port function is determined by the PC52 register bit (0x24);=01: P52 is selected as TCIN.=10: P52 is selected as TC0_N[1];=11: Reserved

R/W 00

19:18 PC51_2

P51 port multiplexing configuration 2:=00: The P51 port function is determined by the PC51 register bit (0x24);=01: P51 is selected as RTC_OUT.=10: P51 is selected as SPI_SCLK;=11: SF2; (INT7 pin output)

R/W 00

17:16 PC50_2

P50 port multiplexing configuration 2:=00: The P50 port function is determined by the PC50 register bit (0x24);=01: P50 is selected as RTC_OUT.=10: P50 is selected as SPI_SCSN;=11: SF1 (INT6 pin output)

R/W 00

15:14 PC47_2

P47 port multiplexing configuration 2:=00: The P47 port function is determined by the PC47 register bit (0x24);=01: P47 is selected as TX4.=1x: reserved

R/W 00

13:12 PC46_2

P46 port multiplexing configuration 2:=00;The P46 port function is determined by the PC46 register bit (0x24);=01;P46 is selected as RX4.=1x;reserved

R/W 00

11:10 PC45_2

P45 port multiplexing configuration 2:=00: The P45 port function is determined by the PC45 register bit (0x24);=01: P45 is selected as KEY7 (PC17 has a higher priority).=10: Reserved=11: Reserved

R/W 00

9:8 PC44_2

P44 port multiplexing configuration 2:=00: The P44 port function is determined by the PC44 register bit (0x24);=01: P44 is selected as KEY6 (PC16 has a higher priority).

R/W 00

=10: Reserved=11: Reserved

7:6 PC43_2

P43 port multiplexing configuration 2:=00: The P43 port function is determined by the PC43 register bit (0x24);=01: P43 is selected as INT5. (PC35 has a high priority)=1x: reserved

R/W 00

5:4 PC42_2

R/W 00

3:2 PC41_2

R/W 00

1:0 PC40_2

R/W 00

10.2.12 PB port pull-up/pull-down selection register PUB (0x28)

Reset Value

31:24 PU77~PU70PU77~PU70 define P7 port whether is internal pull-down:=0:No pull-down;=1: Internal pull-down.

R/W 00

23:16 PU67~PU60PU67~PU60 define P6 port whether is internal pull-down:=0:No pull-down;=1: Internal pull-down.

R/W 00

15:8 PU57~PU50PU57~PU50 define P5 port whether is internal pull-down:=0:No pull-up;=1: Internal pull-up.

R/W 00

7:0 PU47~PU40PU47~PU40 define P4 port whether is internal pull-down:=0:No pull-up;=1: Internal pull-up.

R/W 00

10.2.13 PB port input mode register PIMB (0x2C)

Reset Value

31:24 PIL57~PIL50Define port P50~P57 input buffer type:=0:CMOS buffer, Vil=0.3VCC Vih=0.7VCC;

R/W 00

=1:TTL buffer, Vil=0.16VCC Vih=0.4VCC;Which PIL51 and PIL50 read-only bit 0;

R/W 00

15:8 PID57~PID50

Define port P50~P57 whether is N-ch open-drain output:=0:Normal mode;=1:N-ch open-drain mode;Which PID51 and PID50 read-only bit 0;

R/W 00

7:0 PID47~PID40Define port P40~P47 whether is N-ch open-drain output:=0:Normal mode;=1:N-ch open-drain mode;

R/W 00

10.2.14 PB port input enable register PIEB (0x30)

Reset Value

R/W FF

10.2.15 PC port mode register PMC (input or output)(0x34)

Reset Value

R/W FF

10.2.16 PC port data register PC(0x38)

Reset Value

31:24 P117~P110Define the data that the chip port needs to output.If the port is read in input mode, the pin level is read. If the port is read in output mode, the value of the output latch is read.

R/W 00

23:16 P107~P100Define the data that the chip port needs to output.If the port is read in input mode, the pin level is read. If the port is read in output mode, the value of the output latch is read.

R/W 00

10.2.17 PC port reuse register PCC (0x3C)

Reset Value

31:29 Reserved ----------- R 0

28 SPI_MUXSPI_MUX defines whether P4 is used as SPI or P11.=0:select P4 as SPI;=1: select P11 as SPI;

27:24PC113~PC110

PC113~PC110 define port multiplex configuration:=0:select IO port;=1: select SPI .

23:20 Reserved ----- R 0

19:16PC103~PC100

PC103~PC100 define port multiplexing configuration:=0: select as IO port;=1: select LCD.

15:8PC97~PC90

PC97~PC90 define port multiplex configuration:=0:select IO port;=1: select LCD.

R/W 00

7:0PC87~PC80

PC87~PC80 define port multiplex configuration:=0:select IO port;=1: select LCD.

R/W 00

10.2.18 PC port pull-down selection register PUC (0x40)

Reset Value

31:24PU117~PU110

PU113~PU110 define port whether is internal pull-down:=0:No pull-down;=1: Internal pull-down.

R/W 00

23:16PU107~PU100

R/W 00

15:8 PU97~PU9 PU97~PU90 define port whether is internal pull-down: R/W 00

0 =0:No pull-down;=1: Internal pull-down.

7:0PU87~PU80

R/W 00

10.2.19 PC port input enable register PIEC (0x44)

Reset Value

R/W FF

10.2.20 PC port input mode register PIMC (0x48)

Reset Value

31:16 --- Reserved R/W 00

15:12PIL117~PIL114

Define port P117~P114 input buffer type:=0: CMOS buffer, Vil=0.3VCC Vih=0.7VCC;=1: TTL buffer, Vil=0.16VCC Vih=0.4VCC;

R/W 00

11:8PID117~PID114

Define whether ports P117~P114 are N-ch open-drain outputs:=0: normal mode;=1: N-ch open drain mode;

R/W 00

7:4PIL113~PIL110

Define port P113~P110 input buffer type:=0:CMOS buffer, Vil=0.3VCC Vih=0.7VCC;=1:TTL buffer, Vil=0.16VCC Vih=0.4VCC;

R/W 00

3:0PID113~PID110

Define port P113~P110 whether is N-ch open-drain output:=0:Normal mode;=1:N-ch open-drain mode;

R/W 00

10.2.21 SEGCOM port reuse register PCE (0x60)

Reset Value

31:4 --- Reserved R 03:0 SEG3/COM SEG3/COM7~SEG0/COM4 define port multiplex R/W 00

7~SEG0/COM4

configuration:=0:select SEG;=1:select COM.

10.2.22 PA port data set register PASET(0x64)

31:30 Reserved ----------- R 0

29:24 P35~P30Set chip port status0:No effect1:The port is set, output high level

R/W 00

Note: Read value is meaningless

10.2.23 PA port clear set register PACLR (0x68)

31:30 Reserved ----------- R 00

29:24 P35~P30Clear chip port status0:No effect1:The port is cleared, output low level

R/W 00

10.2.24 PB port data set register PBSET (0x6C)Bit Name Description R/W Sign Reset

R/W 00

10.2.25 PB port clear set register PBCLR(0x70)

R/W 00

Note: Read value is meaningless10.2.26 PC port data set register PCSET (0x74)

R/W 00

7:0 P87~P80 Set chip port status R/W 00

0:No effect1:The port is set, output high level

10.2.27 PC port clear set register PCCLR(0x78)

31:24 P117~P110Clear chip port status0:No effect1:The port is cleared, output high level

R/W 00

23:16 P107~P100Clear chip port status0:No effect1:The port is cleared, output high level

R/W 00

10.3 GPIO operation procedure1. Configure the system control chapter module enable 1 register MOD1_EN bit 5 is 1 to turn on the GPIO

module clock.2. Configure the GPIO input and output mode.3. Configure the GPIO port data register.4. Configure the GPIO port multiplexing function. After selecting the GPIO multiplexing function, the GPIO

input and output functions will follow the GPIO multiplexing configuration.5. When the MCU is powered by 5v, and the peripheral I2C, SPI or other device operates at 3.3V, you can

select GPIO that can be configured as an N-ch open-drain output and an input buffer type with TTL mode.6. When using as an input IO port, configure the corresponding bit of the input enable register to 0 to enable

the input enable. In low power mode, the IO port can be configured as input mode and the input enable can be turned off.

11 External Interrupt ControllerA built-in external interrupt controller (INTC) is used to process the interrupt request input from the chip pin,

and can automatically wake up the CPU by interrupt when the CPU is hibernating.

11.1 IntroduceExternal interrupt controller has the following features:

Supports 48 external interrupt mode setting: up and down along the edge and can be set up bilateral;Support for external interrupt status indication;Support for external interrupt trigger by software;Support for external interrupt status;

Support for external interrupt mask;Supports external interrupt filtering. The filtering time in running mode is about 10 us.

11.2 Register DescriptionModule register base address

Module Name Physical Address Address MappingINTC 0x40044000 0x40044000INTC Module register address offsetRegister Name Address Offset DescriptionINTC_CTL 0x0 INTC Control RegisterINTC_MODE 0x4 INTC Mode RegisterINTC_MASK 0x8 INTC Mask RegisterINTC_STA 0xc INTC Status Register

INTC_CTLINTC Control Register Address 0x40044000+0x0

7:0 Enable

Enable signal, Enable[7:0] corresponds to the external interrupt request 7~0;Corresponding external pin is: P37~P30;0:Close correspond external interrupt;1:Enable correspond external interrupt;

INTC_MODEINTC Mode Register Address 0x40044000+0x4

15:14 MODE7

External interrupt request 7 (INT7)mode select00:Rising edge01:Falling edge10:Double edge11:Reserved

13:12 MODE6

11:10 MODE5

9:8 MODE4

7:6 MODE3

5:4 MODE2

3:2 MODE1

1:0 MODE0

External interrupt request 0(INT0)mode select00:Rising edge01:Falling edge10:Double edge11:Reserved

INTC_MASKINTC Mask Register Address 0x40044000+0x8

7:0 MASK

MASK[7:0] correspond to the external interrupt request 7~00:Interrupt disabled1:Interrupt enabled

INTC_STAINTC Status Register Address 0x40044000+0xc

7:0 STA

STA[7:0] correspond to the external interrupt request 7~00:Interrupt event has not occurred1:Interrupt event has occurredNote: Write 1 cleared

12 KBIA built-in button interface controller is used to process the interrupt request input from the chip pin, and can

automatically wake up the CPU by interrupt when the CPU sleeps.

12.1 FeatureKey interface controller has the following feature:

Support for 8 keys, corresponding pin is KEY0~KEY7;Support for each key state check;Support each key input filter, filter time is 24ms;Support each key individually masked interrupts.

12.2 Register DescriptionTable 12-1 KBI Register Base Address

Module Name Physical Address Address MappingKBI 0x40028000 0x40028000

Table 12-2 KBI Register Address OffsetRegister Name Address Offset DescriptionKBI_CTL 0x0 Control RegisterKBI_SEL 0x4 SEL RegisterKBI_DATA 0x8 Data RegisterKBI_MASK 0xc Mask Register

Control Register(0x0)Table 12-3 KBI Control Register KBI _CTL

7:0 EN

Enable signal, EN [7:0] correspond to the KEY [7:0],Correspond to the external pins: P17/KEY7~P10/KEY0.

0: Close correspond KEY1: Enable correspond KEY

SEL Register(0x4)Table 12-4 KBI SEL Register KBI _SEL

7:0 SELSEL [7:0] correspond to the KEY [7:0]

0: Rising edge active1: Falling edge active

Date Register(0x8)Table 12-5 KBI Data Register KBI _DATA

31:8 --- Reserved R 07:0 DAT DAT [7:0] correspond to the KEY [7:0]. Write 1 cleared R/W 0

0: Key is not pressed1: Key is pressed

Mask Register(0xC)Table 12-6 KBI Mask Register KBI _MASK

7:0 MASKMASK [7:0] correspond to the KEY [7:0]

0: Interrupt disabled1: Interrupt enabled

12.3 KBI operation stepsConfigure the system control section KBI enable register KBI_EN to configure the 8th bit and the corresponding KBI clock bit to 1 to enable the clock;Set the KBI control register KBI_CTL to enable the corresponding KBI;Set the KBI select register KBI_SEL to configure the corresponding KBI as the rising or falling edge;Configure KBI_MASK to enable the corresponding interrupt enable, and open the KBI interrupt NVIC_ Enable IRQ (KBI _IRQ n);Write the KBI interrupt service routine:

void KBI_HANDLER (void){If (KBI->DATA&0x01) {

}KBI->DATA = 0xff;

}All KBI interrupts are one entry and it is necessary to determine the KBI interrupt based on KBI_DATA.Completed.

13 UART SoC internally installed 6 UART interface for external asynchronous serial communication.

13.1 IntroduceUART interface controller has the following feature:

Six full-duplex UART interface;Internally installed baud rate generator, the baud rate is configured to support different;Data bits wide support 5/6/7/8bit;Stop bits can set 1 or 2bit;Optional 38kHz modulated IR;Supports automatic baud rate detection;Support IR wake;

13.2 Register DescriptionTable 13-1 UART Register Base Address

Module Name Physical Address Address MappingUART0 0x40000000 0x40000000UART1 0x40004000 0x40004000UART2 0x40008000 0x40008000UART3 0x4000C000 0x4000C000UART4 0x40018000 0x40018000UART5 0x4001C000 0x4001C000

Table 13-2 UART Register Address OffsetRegister Name Address Offset DescriptionUART_CTL 0x0 UART Control RegisterUART_BAUD 0x4 UART Baud Rate Configuration

RegisterUART_STAT 0x8 UART Status Indication RegisterUART_TXD 0xC UART Transmit data registerUART_RXD 0x10 UART Receive data register

Control Register(0x0)Table 13-3 Control Register UART_CTL

14 NEG

UART polarity selection:0: Positive polarity, the default drive level is high, the polarity of

the transmitted/received data remains unchanged.1: Negative polarity, the default drive level is low,

transmit/receive data polarity is reversed.

13 LMSB

LSB/MSB selection method0: LSB transmission first1: MSB transmission first

Note: When PARS is selected as user-defined check, the check digit is regarded as the highest bit of data expansion. At this time, MSB is selected, and the first bit transmitted will be the check digit.

12 IRSEL

Infrared modulation polarity selection:0: Positive polarity, that is, low-level modulation output, high level (default state) remains 1: negative polarity, that is, data is inverted, high-level modulation output, low-level holdNote: IRSEL only determines the level of the idle output (inactive level) and does not affect the level during the valid data period.

11 ILBEEnable internal loop back0: Internal loop back unable1: Internal loop back enable, TXD and RXD shorted inside the

module

10 IRE

Infrared modulation enable bit0: Close infrared modulation output1: Open infrared modulation output, low-carrier modulation with

38k output data

9:7 PARS

Select the parity bit000: No parity001: Odd parity010: Even parity011: Fixed zero parity100: Fixed one parity

Other: User-defined parity

6:5 DATLEN

Transmission bit data width00:5-bit01:6-bit10:7-bit11:8-bit

4 STOPSStop bit wide select

0:1-bit stop bit1:2-bit stop bit

3 ERRIE

Error interrupt enable bit, the corresponding flag bit is the status indicator register bit5~bit2.0: Close interrupt1: Open interrupt

2 RXIE

Receive data interrupt enable bit, the corresponding flag bit is the status indicator register bit1.0: Close interrupt1: Open interrupt

1 TXIE

Transmit data interrupt enable bit, the corresponding flag bit is status indicator registers bit0.0: Close interrupt1: Open interrupt

0 ENModule Enable0: Close1: Open

Baud Rate Configuration Register(0x4)Table 13-4 Baud Rate Configuration Register UART_ BAUD

11:0 CLKDIVUART x clock divideThe formula of baud rate is: System Clock/[16*(CLKDIV+1)]

Status Indication Register(0x8)

Table 13-5 Status Indication Register UART_STA

Reset Value

9 tx_ fifo_ fullTransmit FIFO is full:

0: Not full1: Full

8 tx_fifo_emptyTransmit FIFO is empty:

0: Not empty1: Empty

7 TBSend state flag

0: Did not send1: Sending data

6 RBReceive status flag

0: Did not receive1: Receiving data

Data errors, write 1 clearedAfter the UART transmit FIFO is full, continue to write to the UART transmit register or write new transmit data during transmission. This bit will be set.0: No error1: Error

Frame error, write one clearedThe data received by the UART does not match the frame format flag. If the received stop bit is 0 instead of 1, the bit will be set.0: No error1: Error

Overflow error, write one clearedThe UART receive data register is not read in time and causes a receive overflow. This bit will be set.0: No error1: Error

Parity error, write one clearedThe data checksum error received by the UART, this bit will be set0: No error1: Error

1 TXSend flag, write one cleared0: Data not yet been sent or no data to be transmitted1: Date has sent

0 RXReceive flag, write one cleared0: No receive data1: Data has received

Transmit data register(0xC)

Table 13-6 Baud Rate Configuration Register UART_ TXD

31:9 --- Reserved R 08 UP User defined parity bit R/W 07:0 TXDATA Transmit data register R/W 0

Receive data register(0x10)Table 13-7 Receive data register UART_ RXD

Reset Value

31:9 --- Reserved R 08 UP Parity bit R 07:0 RXDATA Receive data register R 0

Baud rate fractional configuration register (0x14)Table 13-8 Receive Data Register UART x _FDIV

Reset Value

13:0 FDIV

Fractional division factor. The calculation formula is:

Where fi is the input clock (cpu current running clock), fo is the

output clock, is the downward integer operator. For

example, if the input clock is 1.8432MHz and the output clock is

9837Hz, then:

Find F=11647.

13.3 UART Data Receiving and Sending ProcedureEnable the corresponding UART clock in the 0 register MOD0_EN in the system control chapter module enable module.Configure the baud rate configuration register UART x_ BAUD. For example, when the system clock is 3.6864MHz and the communication baud rate is 9600, the baud rate configuration register can be set to: UART0->BAUD = 3686400 / (9600*16)-1;Configure the communication control register UART x _CTL to select the data bit, stop bit, check mode and interrupt enable.Write 0x3f to clear the UART status indication register (UART x_ STA) status.Configure the UART interrupt enable, open the UART interrupt NVIC_ Enable IRQ (UART x_IRQ n);Write an interrupt service routine, such as the UART0 interrupt service routine:

void UART0_HANDLER (void)

{u32 status;u8 temp;

status = UART0->STA;

/* UART error irq */if((UART0->CTRL & 0x8) && (status & 0x3c)){

/* Start adding user code. Do not edit comment generated here */

}/* receive data complete irq */

if((UART0->CTRL & 0x4) && (status & 0x1)) {/* Start adding user code. Do not edit comment generated here */}/* transmit data complete irq */if((UART0->CTRL & 0x2) && (status & 0x2)){/* Start adding user code. Do not edit comment generated here */}}The UART receive, transmit, and error interrupts are the same interrupt entry. The interrupt

Enable bit and status flag opened by the control register should be used to determine which interrupt is active at this time.Process the received or sent data and complete it.Note: The UART port is full-duplex mode, which can transmit and receive at the same time. When RS485 half-duplex communication mode is used, when the RS485 chip is transmitting, there will be interference signal at the receiving end. In this case, it is recommended to turn off the MCU when sending. The reception is interrupted, and the transmission interrupt is turned off during reception to eliminate interference.

14 ISO7816

SoC internal installed two ISO7816 channels, support for external 2 7816 protocol interface device.

14.1 IntroduceISO7816 interface controller has the following features:

Support standard ISO7816 protocol, working in master mode;Support card clock output, frequency can be set between 1 ~ 5MHz;Support 7816 various frequency division ratio setting;Support MSB first output logic low and logic high output LSB first data encoding;Support 1, 2 ETU width set the width of the error signal;Support 0~254 ETU width EGT configuration;Supports sending data transmission error retransmission mechanism, the number of

retransmissions can be set between 0 to 7;7816 card stack supports two interfaces (Esam and card): esam modules receive and transmit ports with a pin;Support card interface for receiving and sending separation;

14.2 Register DescriptionTable 14-1 ISO7816 Register Base Address

Module Name Physical Address Address MappingISO7816 0x40038000 0x40038000

Table 14-2 ISO7816 Register Address OffsetRegister Name Address Offset DescriptionISO7816_CTL0 0x0 Control Register 0ISO7816_CTL1 0x4 Control Register 1ISO7816_CLK 0x8 Clock Configuration RegisterISO7816_BDDIV0 0xc Baud Rate Configuration Register 0ISO7816_BDDIV1 0x10 Baud Rate Configuration Register 1ISO7816_STAT0 0x14 Status Indication Register 0ISO7816_STAT1 0x18 Status Indication Register 1ISO7816_DAT0 0x1c Data Transmit Register 0ISO7816_DAT1 0x20 Data Transmit Register 1

Control Register(0x0)Table 14-3 ISO7816 Control Register 0 ISO7816_CTL0

Reset Value

27 RX_GT0Receive data GT select bit, when sending fixed 2etu1: Receive data GT is 1etu0: Receive data GT is 2etu

26 --- Reserved R/W 025 --- Reserved R/W 0

24:17 EGT0

EGT width selection value (0 to 255), that the extra guard time N, the default value N = 0.

In the range of 0 to 254, N is used to calculate the delay between two consecutive data of a start edge: 12 etu + (Q × (N / f)).

Formula, Q should take one of two values below:When T=15 does not exist in answer to reset, take F/D;When T=15 exit in answer to reset, take Fi/Di;

N = 255 means that during transport protocol, a minimum of two consecutive characters start edge delay between the two directions of transmission are the same. The minimum delay value is:

T=0,12etuT=1,11etu

16: 14 REP_CNT0

Odd Even parity data automatically control the number retransmissions when error000:0 time 001:1 time010:2 times 011:3 times 100:4 times 101:5 times 110:6 times 111:7 times

R/W 011

13 RXPAR_ESEL0

Receive data parity error handling mode selection1: Parity error, according to the T = 0 protocol post back error signal. Set RX_PAR_ERR flag, interrupt.0: Parity error, do not send error signal, set RX_PAR_ERR flag, direct interrupt.

12:11 ERRWTH0

Error signal width select bit applies only to receive, and RXPAR_ESEL0 = 100:2 etu01:1 etu10:1.5 etu11:2etu

R/W 01

10:8 PARSEL0

Parity bits select000: No parity001: Odd parity010: Even parity011: Fixed zero parity100: Fixed one parityOther: Reserved

R/W 010

7 BGT_EN0

Data received BGT control bits transmitted0: Close BGT function, data between transmission and reception don’t insert BGT1: Open BGT function, data between transmission and reception insert BGT (22etu)

6 ERR_IRQ_EN0

Transmission error interrupt enable bit, data collision when transmitting data, the data is received and the received data frame format overrun error0: Prohibit transmission error interrupt is generated1: Enable transmission error interrupt is generated

5 RX_IRQ_EN0

Data receive interrupt enable bit, enables data is shifted from the shift register to the receive buffer register to generate an interrupt0: Prohibit data reception interrupt is generated1: Enable data reception interrupt is generated

4 TX_IRQ_EN0

Data transmit interrupt enable bit to enable the completion of the data from the transmit shift register to generate an interrupt0: Prohibit sending data to generate an interrupt1: Enable data transmission interrupt is generated

3 RX_EN0 Receive data enable R/W 0

0: Prohibit data reception1: Enable data reception

2 TX_EN0Enable sending data0: Prohibit data transmission1: Enable data transmission

1 DIRSEL0Data coding mode selection bit0: LSB first pass being logical data encoding1: MSB first pass negative logic data encoding (data negated)

0 EN0ISO7816 The controller enable bit0: Controller close1: Controller open

ISO7816 control register1(0x04)Table 14-4 ISO7816 control register1 ISO7816_CTL1

31 CARD1_CHECK_EN

Card out Detect Flag, it is only active after the detection function of OLD is enable1: Enable card out detection interrupt function0: Disable card out detection interrupt function

30 OLD1_IRQ_EN

OLD detection interrupt function flag, it is only active after detection function of OLD is enable1: Enable OLD detection interrupt function0: Disable OLD detection interrupt function

29 OLD1_ENOLD detection function flag1: Enable OLD detection function0: Disable OLD detection function

28 RX1_GT0

GT of received data choice bit, it is always 2etu when data is transmitted1:GT of received data is 1etu0:GT of received data is 2etu

27 --- preserve R/W 026 --- preserve R/W 0

25 IO1_EN

bidirectional data enable signal1:78161_IO port is a bidirectional signal0:78161_IO port is a one-way signal, output only, the data are input at 78161_I port

24:17 EGT1

EGT width selection (0~255), extra protection time NDefault N=0.

In the range of 0 to 254, N: before it was ready to receive the next character, the card need the delay(it sent by card or interface device) which start with onset of the first character:

12 etu +(Q×(N/f))In the formula, Q should be one of two values:

F/D, it is used to compute the value of etu. When T = 15 don't exist in the reset reply,

Fi/Di, When T = 15 exist in the reset reply.N=255when the transmission protocol is effective,

Minimize Delay between onset of two continuation character in either direction remains the same.

Minimize Delay:When T=0,12etu

When T=1,11etu

16: 14 REP_CNT1

When Parity selection is wrong, the times of automatic repeat request000:0time 001:1time010:2times 011:3times 100:4times 101:5times110:6times 111:7times

R/W 011

13 RXPAR_ESEL1

Receive data parity error handling mode selection1: Parity check is wrong, According to T = 0 protocol, error signal will be post back, RX_PAR_ERR flag bit will be set and generate the interrupt.0: Parity check is wrong, do not send error signal,RX_PAR_ERR flag bit will be set, generate the interrupt.

12:11 ERRWTH1

Width selection bit of the error signal00:2etu01:1etu10:1.5etu11:2etu

R/W 01

10:8 PARSEL1

Parity select bit000: No parity001: Odd010: Even011: Fixed to zero check100: Fixed to one checkOther: Reserved

R/W 010

7 BGT_EN1

BGT control bit between data transmission and reception 0: Disable BGT function, do not insert the BGT between data reception and transmission1: Enable BGT function, insert the BGT between data reception to transmission

6 ERR_IRQ_EN1

Transmit error interrupt flag, Data conflicts when data is transmitting, Data overflow when data is receiving and the received data frame is error0: Disable the interrupt when data transmission is error 1: Enable the interrupt when data transmission is error

5 RX_IRQ_EN1 Receive interrupt flag, data transfer from shift registers to R/W 0

receive buffer registers 0: Disable data reception interrupt to generate1: Enable data reception interrupt to generate

4 TX_IRQ_EN1

Transmit interrupt flag, set by hardware after completion of a serial transfer from shift registers 0: Disable the interrupt between data transmission 1: Enable the interrupt between data transmission

3 RX_EN1Receive data enable0: Disable receive data1: Enable receive data

2 TX_EN1Transmit data enable0: Disable transmit data1: Enable transmit data

1 DIRSEL1

Data coding mode selection bit0: LSB first pass that is positive logic data coding method1: MSB first pass negative logic data coding method(negate values)

0 EN1ISO7816 Controller flag 0: Disable the controller1: Enable the controller

ISO7816_CLK(0x08)Table 14-5 ISO7816 Clock Control Register1 ISO7816_CLK

3 CLKO_ENCard clock output flag0: Disable card clock output1: Enable card clock output

2:0 CLKDIV

ISO7816 Divider factor of clock output (CLK_O)ISO7816 source clock of module gain from fsyspll of system clock000: No frequency division; 001:2 frequency division;010:4 frequency division; 011:8 frequency division;100:16 frequency division 101:32 not support;110: not support; 111:128 not support;

ISO7816 Baud rate coefficient 0 Register(0x0c)Table 14-6 ISO7816 Baud rate coefficient 0 Register ISO7816_BDDIV0

21 FDS0_EN

Enable soft configuration coefficient of F/D1: Baud rate coefficient will be determined by FDS0 which is written by software0: Baud rate coefficient will be determined by FD0

20:8 FDS0 Baud rate coefficient which are configured by software, this bit can R/W 13’d372

be written only when FDS0_EN is 1, In other cases, it is13’d372.7:0 FD0 8bit FI and DI is transmitted from answer to reset R/W 8’h01

ISO7816 Baud rate coefficient1 Registers(0x10)Table 14-7 ISO7816 Baud rate coefficient1 Registers ISO7816_BDDIV1

21 FDS0_EN

Enable soft configuration coefficient of F/D1: Baud rate coefficient will be determined by FDS0 which is written by software0: Baud rate coefficient will be determined by FD0

20:8 FDS0Baud rate coefficient which are configured by software, this bit can be written only when FDS0_EN is 1, In other cases, it is13’d372.

R/W 13’d372

7:0 FD0 8bit FI and DI is transmitted from answer to reset R/W 8’h01ISO7816 State 0 Registers(0x14)

Table 14-8 ISO7816 State 0 Registers ISO7816_ STAT0

11FRAME_ERR0

Receive data frame format error interrupt flag this bit will be reset by writing '1'1: Send the error frame format error of receiving data , it will generate the interrupt when transmission error interrupt is enable0: Unsent the error frame format error of receiving data

10 BDDIV_R0

Baud rate matching instruction, the matching instructions between FI and DI, FD default is 8’h01, clock matching, it will be set as 1 when FD unmatched.1: matched0: unmatched

9 TX_FLAG0

Transmit data buffer empty flag. The automatic set after power-onreset, and it shows Buffer is empty and can be written. The flag will be automatically cleared after MCU is written. After shift data from transmit buffer registers to shift registers, this bit will be set as 1 1: Data transmit buffer is empty0: The data transmit buffer has data to be transmitted

8 RX_FLAG0

Data buffer full flag,7816 Interface controller receives every bit data, hardware automatic clear settings, it shows Interface controller receives 1 bit data, Reading data receive buffer register will be reset.1: 1byte data is received, data buffer is full0: There is no data received, data buffer is empty

7 RXBUSY0

Reception data busy flag. Set by hardware, reset by softwareHardware automatic clear settings0: Receive data idle1: RSR are receiving data, it will be set as 1 after start bit is received, it

will automatic clear zero after stop bit is received

6 TXBUSY0

Transmit data busy flag. Set by hardware, reset by softwareHardware automatic clear settings0: Transmit data idle1: TXSHF are sending data, it will be set as 1 after start bit is send, it will automatic clear zero after stop bit is send

5TXPAR_ERRIF0

Send data parity error flag, there is still parity error after retry, then this bit is turned on.this bit will be reset by writing '1'1: Parity error occurred when data is transmitted.0: Parity error didn’t occur when data is transmitted.

4RXPAR_ERRIF0

Receive data parity error flag bit, there is still parity error after retry, then this bit is turned on.this bit will be reset by writing '1'1: Parity error occurred when receiving data is received0: Parity error didn’t occur when data is received

3 COL_IF0

Send data conflict error interrupt flag. Set by hardware, reset by software, this bit will be reset by writing '1'0: No interrupt1: Interrupt occurs

2 OVL_IF0

Receive data overflow flags. Set by hardware, reset by softwarethis bit will be reset by writing '1'0: No overflow1: Interrupt occurs, the receive buffer register didn’t be read, and received the new data. Overflow flag bit is enable

1 RXIF0

Transmit data interrupt flag bit. After shift data from shift registers to transmit buffer registers, it will be set as 1. Set by hardware, reset by softwarethis bit will be reset by writing '1'0: No interrupt1: Interrupt occurs

0 TXIF0

Transmit data interrupt flag. After move data from send buffer registers to shift registers, it will be set as 1, set by hardware, reset by software,this bit will be reset by writing '1'0: No interrupts1: Interrupt occurs

ISO7816 Status 1 Registers(0x18)Table 14-9 ISO7816 Status 1 Registers ISO7816_ STAT1

13CARD_OUT_FLAG

This bit is Effective, after CARD_CHECK_EN enabled. this bit will be reset by writing '1'.1:Detected card was uprooted (the width of high level pulse of input

port is more than 40mS)0: Pulling out the card is not detected (the width of high level pulse of input port is not more than 40mS)

12 OLD_FLAG

After OLD_EN enabled, this bit is Effective, to match the received RA9105 signal of OLD interrupt flag bit, this bit will be reset by writing '1'.1:OLD signal has been received.0:OLD signal hasn’t been received.

11FRAME_ERR0

Receive data overflow flag, this bit will be reset by writing '1'1: Send received data frame format error, Interrupt occurs when the transmit error interrupt is enabled0: Unsent received data frame format error

10BDDIV_R1

Baud rate matching direction, FI and DI matching direction; FD defaults to 8’h01, clock matching, it will be set as 1 when FD unmatched.1: matched0: unmatched

9 TX_FLAG1

Send Buffer empty flag. It automatic setting after power-on reset, And it shows Buffer is empty, and it can be written. The flag will be automatically clean after MCU is written, After move data from send buffer registers to shift registers, this bit will be set as 1 1: Buffer is empty0: There is data which are ready to send in the buffer

8 RX_FLAG1

The data reception complete flag,7816 Interface receives every bit data,receiver channel generate the interrupt. Set by hardware, reading data receiving buffer register clean.Interface controller receives every bit data, Hardware automatic Clear Settings, it shows Interface controller receives 1 bit data, Read data receiving buffer register will be reset.1:1byte data is received, receive data buffer is full0: There is no data received, receive data buffer is empty

7 RXBUSY1

Receive data busy flag. Hardware set, reset by softwareHardware automatic clear settings0: Data reception go idle1: RSR are receiving data, it will be set as 1 after start bit is received, itwill automatic clear zero after stop bit is received

6 TXBUSY1

Transmit data busy flag. Hardware set, reset by softwareHardware automatic Clear Settings0: Data transmission go idle 1: TXSHF are sending data, it will be set as 1 after start bit is transmitted, it will automatic clear zero after stop bit is transmitted

5TXPAR_ERRIF1

Transmit data parity error flag bit. Hardware set, reset by softwarethis bit will be reset by writing '1'1: Parity error occurred data is transmitted

0: Parity error didn’t occur data is transmitted

4RXPAR_ERRIF1

Receive data parity error flag bit. Hardware set, reset by softwarethis bit will be reset by writing '1'.1: Parity error occurred data is received0: Parity error didn’t occur data received

3 COL_IF1

Send data conflict error interrupt flag bit. set by hardware, reset by softwarethis bit will be reset by writing '1'0: No interrupts1: Interrupt occurs

2 OVL_IF1

Receive data overflow flag bit. Set by hardware, reset by softwarethis bit will be reset by writing '1'0: There is no overflow1: Interrupt occurs, the receive buffer register don’t be read, and received the new data. Overflow flag bit is Enable

1 RXIF1

Receive data interrupts flags bit. After move data from shift registers to send buffer registers, it will be set as 1, set by hardware, reset by softwarethis bit will be reset by writing '1'0: No interrupts1: Interrupt occurs

0 TXIF1

Sending data interrupts flag bit. After move data from send buffer registers to shift registers, it will be set as 1.Set by hardware, reset by softwarethis bit will be reset by writing '1'0: No interrupts1: Interrupt occurs

ISO7816 Data Register0(0x1C)Table14-10 ISO7816 Data Register0 ISO7816_ DAT0

Reserved

-- -- R 0

8 DATA0[8]It is PARITY bit of data frames,when parsel is in User-defined mode

7:0 DAT0 Data Register0 R/W 0ISO7816 Data Register1(0x20)

Table 14-11 ISO7816 Data Register1 ISO7816_ DAT1

Reserved

-- -- R 0

8 DATA1[8]It is PARITY bit of data frames,when parsel is in User-defined mode

7:0 DAT1 Data Register1 R/W 0

14.3 7816 and ESAM communication stepsThe 7816 communicates with the ESAM. There is no need to consider the isolation problem. The data IO can share one line. It is recommended to use the 7816 module 0.Configure the system control chapter module to enable the 0 register MOD0_EN, set the 13th position to 1, and turn on the 7816clock.The 7816control register is configured as ISO7816_CTL0. Using the national network ESAM, the register can be configured as 0x00000201.Clear the ISO7816 status register ISO7816_STAT0.Turn on the 7816bus clock. For example, when the system clock is 3.6864MHZ, ISO7816 ->CLK=0x09; at this time, the 7816module clock is 1.8432MHZ.Data can be read and written to the 7816 bus by interrupt mode or query status mode.

14.4 7816 and card communication stepsFor the card table, the card needs to be isolated from the main power, and the 1-5MHZ clock isrequired to work normally. Most of the existing SOC uses a high-speed optical scheme to isolate the main power from the card. This solution has high cost and use high-speed optocouplers are used to isolate high-frequency clocks, which are less reliable at high and low temperatures. We provide a dedicated chip RN8501 for connection to the card, which uses two common optocouplers for data communication with the MCU.Configure the system control chapter module to enable the 0 register MOD0_EN, set the 13th position to 1, and turn on the 7816clock.The 7816control register is configured as ISO7816_CTL1. Because it is isolated from the card, it is separated from the transmission. ISO7816->CTRL1 can be configured as 0x60000201.Clear the ISO7816 status register ISO7816_STAT0.Turn on the 7816bus clock. For example, when the system clock is 3.6864MHZ, ISO7816 ->CLK=0x09; at this time, the 7816module clock is 1.8432MHZ.Can read and write data to the 7816 bus through interrupt mode or query status mode.

The insertion and extraction detection of the card after using the RN8501 and the reading of the reset information of the card are different from the separation scheme:

Card insertion detection: Connect the detection pin of the card holder to the CHK of the RN8501. When the card is inserted into the card holder, the CHK pin is low level, and the RN8501 sends a low level signal of about 9MS through the 7816 port connected to the RN821x. When the OLD detection enable of ISO7816_CTL1 is turned on, an interrupt is generated and it is considered that there is a card inserted outside.Card pull-out detection: After the card of the ISO7816_CTL1 is pulled out to detect the enable bit, the card can be pulled out. Note: The card pull-out detection interrupt can be turned on after the card operation is completed.The reading of the reset information of the card is read after the communication handshake between the MCU and the RN8501 is completed.More specific steps can be found in the RN8501 data sheet.

15 IIC Interface

An I2C Interface embedded in Soc.

15.1 OverviewThe controller of I2C Interface has the following features:

Master and slave mode were supported;7-bit address were supported;Many types of the divider setting were supported;100kbps and fast mode(400kbps) were supported;

15.2 Register DescriptionsTable 15-1 I2C register address

Module Name Physical Address Mapping AddressI2C 0x40024000 0x40024000

Table 15-2 I2C register offset addressRegister Address Offset DescriptionsI2C_CTL 0x0 Control RegisterI2C_CLK 0x4 Clock configuration registersI2C_STAT 0x8 Status RegisterI2C_ADDR 0xC Slave device address RegisterI2C_DATA 0x10 Transmits and receives data

RegisterControl Register(0x0)

Table 15-3 Control Register I2C_CTL

5 MODEMASTER/SLAVE1: MASTER0: SLAVE

ACK sending enable1: After received the signal of the ninth SCL,

generate ACK 0: After received the signal of the ninth SCL, don't

generate ACK

3 IRQEI2C interrupt enable

0: Disable interrupt1: Enable interrupt

2:1 BUSCON

A bus control bit, start command is effective when bus is idle or host is posted. Start command is effective when host is postedWhen timing of the stop or start is detected, command bit will be clear

00:no action01: Producing the time for START10: Producing the time for STOP11: Reserved

0 ENModule Enable1: Enable I2C0: Disable I2C

Clock configuration register(0x4)Table 15-4 Clock configuration register I2C_ CLK

2:0 CLKDIV

I2C clock separate frequency parameters selection bit:I2C calculating formula for communication clock rate:SCL=APBCLK/m, there into m produced by CLKDIV,shown in the table below. It generated High-speed mode or Normal-mode communication clock according to different System frequency and Separate frequency parameters.If configuration option is not in the table below, it defaults to divide-by-ten.

System frequency

Separate frequency parameters /CLKDIV(m)High-speed mode

Normal-mode

1.8432Mhz Not support

010(20)

3.6864Mhz 010(10) 011(38)7.3728Mhz 010(20) 100(76)14.7456Mhz 011(38) 101(152)29.4912Mhz 100(76) 110(304)

R/W 001

Status describing register(0x8)Table 15-5 Status describing register I2C_ STAT

8 DIRDirection of Reading or writing flag

1: Write.0: Read.

7 MATCH

Address matching, when timing of the stop or start is detected, command bit will be clear

0: Address mismatch1: Address matching

6 BUSYTraffic Status flag

0: IIC is idle1: IIC is busy

5 COLSending conflict interrupt. this bit will be reset by writing '1'

Sending data register is not empty or When receiving data, user write new data to data register. Trigger sending interrupt flag0: No trigger send conflict interrupt1: Trigger send conflict interrupt

4 OVERF

Receive overflow interrupt flag. this bit will be reset by writing '1'When receiving data, a new data is received before previous data don’t be took away, Trigger overflow interrupt flag0: No trigger overflow interrupt1: Trigger overflow interrupt

3 TXEMPT

Sending data register is empty error flag. this bit will be reset by writing '1'In slave mode, the host asked slave to send data, when send buffer is empty, trigger send data is empty error interrupt flag

0: No trigger send data is empty error interrupt1: Trigger send data is empty error interrupt

2 TRANC

Transfer complete interrupt flag. this bit will be reset by writing '1'When sending data, send buffer is empty , or when receiving data , receive buffer is full. Trigger transfer complete interrupt flag

0: Transfer has not been completed1: Transfer has been completed

1RX_NACK

Received NACK interrupt flag. this bit will be reset by writing '1'1: Received NACK0: No NACK was received

0 STPD

STOP time sequence inspection interrupt flag. this bit will be reset by writing '1'When timing of the start is detected or module is power off, this bit will be clear0: No STOP timing detected1: Detect STOP timing

Slave device address register(0xC)Table 15-6 Slave device address register I2C_ ADDR

7:1 SADRDevice address, it can’t be written during the transport address.

In host mode, it is slave device address;R/W 0

In slave mode, this address is used to compare with address which host send.

0 RWDirection of Reading or writing of host flag0: write1: read

Send/receive data register(0x10)Table 15-7 Send/receive data register I2C_ DATA

7:0TRDAT

Send/receive data R/W 0

16 SPI InterfaceSoc has an in-built SPI Interface.

16.1 OverviewThe controller of SPI Interface has the following features: Full-duplex mode of SPI were supported; master / slave mode were supported Setting the clock polarity and phase were supported; Send and receive independent double buffer were supported; Transfer mode of LSB and MSB can be 8bit or 16 bit or 32bit 256 kinds of baud rate can be set, up to 3.6864MHz; Complete interrupt of data transmission is supported; Conflict interruption of data transmission were supported; Error interruption of SCSN mode were supported;

16.2 Descriptions of FunctionsSPI Interface meets the SPI HOST protocol standard, SPI clock mode is depending on the setting of CPOL(Clock

Polarity) and CPHA(Clock Phase) parameter:CPOL shows front edge seat of clock is positive edge or negative edge,CPHA shows front edge seat of clock is data sampling or data setup.

Figure 16-1 How the SPI clock worksDetailed working mode is as follows Table:

Table 16-1 SPI clock modeSPI MODE CPOL/CPHA Front edge seat Rear edge0 0/0 positive edge, data sampling negative edge, data setup1 0/1 positive edge, data setup negative edge, data sampling2 1/0 negative edge, data sampling positive edge, data setup3 1/1 negative edge, data setup positive edge, data sampling

The width of the data transmission can be 8bit or 16 bit or 32bit, SPI clock source from the system clock,generate the communication clock After a divider coefficient.

Support data transmission interrupt conflicts, data reception overflow interrupt, transmission end interrupt and SS mode error interrupt other four interrupts.

Send data conflicts, when data is transmitting (txbusy1), then there is a write command , then TXCOLIF set as 1.

If COL_IRQ_EN=1, interrupt occurs, meanwhile this send command wouldn't be response, the data which is sending will transferred over. Receive data overflow: Before the data over which to receive don’t enter into shifting register,RXDATA register is not read, data overflow will generate ,RXCOLIF will be set as 1,if COL_IRQ_EN=1,interrupt occurs, meanwhile new receiving data will be save into receive data register,the old data will be overwritten.End Of transmission interrupt: End Of transmission(sck_end), if TR_IRQ_EN=1, interrupt occurs, meanwhile, TRIF will be set as 1.

SCSN mode error interrupt: In the slave mode, SCSN must be input, When data is transmitted, SCSN become high, SCSN mode error flag will be set as 1;In the host mode, only enable the host model SCSN error detection(SCSN_EN=1),meanwhile SCSN is low, SCSN mode error flag will be set as 1. When SCSN mode error

1 2 3 4 5 6 7 8

SCK(CPOL=0)

SCK(CPOL=1)

Sample Point

MOSI(from master)

MISO(from slave)

bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7

SS(to slave)

1 2 3 4 5 6 7 8

SCK(CPOL=0)

SCK(CPOL=1)

Sample Point

MOSI(from master)

MISO(from slave)

SS(to slave)

CPHA=0

CPHA=1

flag is 1, transmission is terminated, SOI module is reset, if ERR_IRQ_EN=1, interrupt occurs.Note: After the control register is configured, when it is in the host mode, the SPI read/write operation will be

started only when data is written to the data transmission register.

16.3 Register DescriptionsTable 16-2 SPI register address

modules physical address mapping addressSPI 0x40020000 0x40020000

Table 16-3 SPI register offset addressRegister Address Offset DescriptionsSPI_CTL 0x0 Control RegisterSPI_STAT 0x4 Status RegisterSPI_TXDATA 0x8 Transmit Data RegisterSPI_RXDATA 0xC Data Receive Register

Control Register(0x0)Table 16-4 SPI Control Register SPI_CTL

31:22 --- Reserved R 021 TX_DMA_EN Reserved R/W 020 RX_DMA_EN Reserved R/W 0

19:12 CLKDIVSCK clock division factorSCK frequency=system clock frequency/( 2*(CLKDIV + 1))

11:10 WIDTH

Data width selection0:8bit1:16bit2:32bit3: Reserved,8bit

9 SCSN_EN

SCSN model error detection enable, Works only in the master mode

0: Disable SCSN model error detection in the master mode,SCSN is GPIO

1: Enable SCSN model error detection in the master mode, SCSN as the input of SPI

8 CPHAClock phase selection

0: Former edge sampling data1: Former edge data is established

7 CPOLClock polarity selection

0: “SCK” will be set as low, when idle1: “SCK” will be set as high, when idle

6 LMSBLSB/MSB selection

0: MSB is transferred first1: LSB is transferred first

5 TXCOL_IRQ_ Data conflict interrupt enable R/W 0

EN 0: Disable write conflict interrupt1: Enable write conflict interrupt

4RXCOL_IRQ_EN

Data conflict interrupt enable0: Disable read conflict interrupt1: Enable read conflict interrupt

3 ERR_IRQ_ENSCSN mode error interrupt enable

0: Disable mode error interrupt 1: Enable mode error interrupt

2 TR_IRQ_ENData transmission interrupt enable

0: Disable transmit data interrupt1: Enable transmit data interrupt

1 MAST/SLAVMASTER/SLAVE

1: MASTER0: SLAVE

0 ENEnable0: Disable SPI Interface1: Enable SPI Interface

Status Register(0x4)Table 16-5 SPI Status Register SPI_ STAT

4 TXBUSY

Sending data busy state flag.0: Sending data is idle, bus can write command of SPITX

register1: Data is sending, bus can’ t write command of SPITX

register

3 TXCOLIF

Write conflict flag. this bit will be reset by writing '1'When data is sending (TXBUSY is 1), user write new sending data to SPI, then new sending data will be lost. Write conflict flag will be set as 1.

0: No write data conflict interrupt1:Generate the interrupt of write data conflict

2 RXCOLIF

Receiving data overflow flag. this bit will be reset by writing '1'When receiving data in a row, if user don’t read RXDATA register, generate the receiving data overflow

0: No receiving data overflow interrupt1:Generatethe receiving data overflow interrupt

1 ERRIF

SCSN mode conflict interrupt flag bit: when SPI is in host mode, only when SCSN_EN is 1,meanwhile“SCSN”is low, this bit will be set as 1;when SPI is in slave mode, “SCSN” as slave input, When the data was transmitted, if “SCSN” is high, this bit will be set as 1;if ERR_IRQ_EN=1,interrupt occurs, ifgenerate the mode conflict, SPI module will be reset. this bit

will be reset by writing '1'0: No mode conflict interrupt1:Generatethe mode conflict interrupt

0 TRIF

Sending data interrupt flag bit, When the data transfer is finished, this bit will be set as 1, if TR_IRQ_EN=1,interrupt occurs, this bit will be reset by writing '1'0: No sending data interrupt1:Generatethe sending data interrupt, send data register is empty.

Transmit Data Register(0x8)Table 16-6 SPI Transmit Data Register SPI_ TXDATA

31:0 TXDATA Transmit Data Register R/W 0Data Receive Register(0xC)

Table 16-7 SPI Data Receive Register SPI_ RXDATA

31:0 RXDATA Data Receive Register R 0

17 Option ByteIt built in an area of option byte, when the chip is reset, it will automatically configuration option byte and perform specific function. It include protection of the chip, WDT, EMAP and RTC setting.Programming of option byte can be setting by the programming tool from Renergy (MINIPRO programming unit or ISP programming tools),What an example to MINIPRO programming unit,open the dialog, you can set option byte, As shown in the figure(Please see the detailed operation method from “MINIPRO instruction manual of programmingunit”).

17.1 Chip Protection SettingsProtect function of option byte can protect built-in Flash ,user can protect the chip by protection lever setting

and ISP password setting. The following protection levels are provided:

Protection level

Name description

0 CP0 Without any protection (no password is required for ISP access)1 CP1 SWD Interface can access chip, password is required for ISP

access2 CP2 Disable access chip by SWD Interface, password is required for

ISP access3 CP3 Disable access chip by SWD and ISP Interface (ISP only have the

function of the whole erase FLASH (Erase operation will reduce the protection level to CP0 in CP3)

17.2 WDT SettingOption byte provide interval interrupt of WDT, window open cycle, overflow time, CPU sleep setting, CPU debug setting, See detailed meaning on the section of WDT. As shown in the table below:

Name Description defaultInterval interrupt

0: Disable (Disable interrupt of intervals)1: Enable (When reaches 75% of the spills, interval interrupt occurs)

Window open 0:25% 3

cycle 1:50% 2:75% 3:100%During the window open, write 0xBB to WDTE register, watchdog reset and count again; During the window close, write 0xBB to WDTE register, The internal reset signal generate.

Overflow time

0:16ms1:32ms2:128ms3:512ms4:1s5:2s6:4s7:8s

CPU sleep setting

0: Disable (When CPU is sleep or deepsleep, WDT is off)1: Enable (When CPU is sleep or deepsleep, WDT is on)

CPU debug setting

0: Disable (When CPU in a state of commissioning, WDT is off)1: Enable (When CPU in a state of commissioning, WDT is on)Notes: When CPU in a state of commissioning, it shows user stop Cortex M0 by debug interface (PC pointer stop counting).

In order to support a program space more than 192 KB, RN821 X (RN8215 can support setting of EMAP. but RN8211/RN8213 can’t) set 32K EEPROM as program space of 192K Flash by option byte. If select EEPROM as program space of 192K Flash. The program space of RN821X may be extended to 224KB.Read address of EEPROM was right behind FLASH, begin with 0x30000(REMAP=0x0).

17.3 RTC SettingWith temperature compensation ,the RTC of RN821X can make a automatic compensation to the 32K crystal ,

so it can provide the exact second pulse in the range of -25 70Among them, the temperature frequency curve of the crystal as shown below, is the vertex of a quadratic curve

25 degrees (f=f0-alpha*(T-T0)), T0 is 25 degrees). However, The alpha of quadratic curve is different between the high temperature section (25 -temperature (-25separately the parameter RTC_ALPHAL and RTC_ALPHAH ,Each of them is filled with round (alpha * 32768) ,which means rounding operation.

If the choice is high consistency crystals (VT-200-F) provided by Seiko, then ALPHAL = 0x3ee, ALPHAH = 0x4cf.

18 Programming Support SoC support the built-in programming of the internal EEPROM and FLASH . We recommend that customers can call our library functions to achieve IAP function and use our

programmer to complete the ISP function.

18.1 OverviewSoC programming system has the following features:

18.2 Flash Protection MechanismsFlash protection is to allow users to enable different levels of security to restrict the access to the on-chip Flash

and ISP. Protection mechanisms protect the different level of protection in the following table. Users can set chip protection class by set the “option byte”.

Table 18-1 The protection level of SoCProtection level

Name description

0 CP0 Without any protection (no password is required for ISP access)

1 CP1 SWD Interface can access chip, password is required for ISP access

2 CP2 Disable access chip by SWD Interface, password is required for ISP access

3 CP3 Disable access chip by SWD and ISP Interface (ISP

only have the function of the whole erase FLASH(Erase operation will reduce the protection level to CP0 in CP3)

18.3 In System Programming (ISP)The user can pull P30 signal to low, and reset the SoC, let SoC into the ISP mode. ISP mode of connection

diagram as shown in figure 18-1.Figure 18-1 ISP hardware configuration diagram

ISP major process:1 According to the connection diagram configuration and connect the target system and control host;2 Reset the target system;3 Control host configuration of serial port for a start bit, 8 data bits, 1 stop bit the baud rate is not more

than 115200bps;4 Control the host to send “e”;5 The target system response “Synchnonized /r/n”;6 Control the host to send “Synchnonized /r/n”;7 The target system response “7373(1843)/r/n”;(If the current system frequency is 7.3728M,send 7373;If

the current system frequency is1.8432M,send 1843)8 Control host can perform the corresponding ISP commands according to need;

18.3.1 ISP Communications ProtocolAll command of ISP send in the form of a ASCII text. Text use (/r) or (/n)as end mark.All ISP response is <

CR > < LF > the end of the ASCII string sent. The data were sent and received in the original format (not converted to ASCII) .

Command formatcommand parameter0 parameter1 ... parametern/r/n{DATA}

command formatreturn code/r/nresponse 0/r/nresponse 1/r/n ...Response /r/n{DATA}

data formatAfter starting the orders of WM and RM, the data transmission of ISP will start up. The data transmits in a unit

Target system

control PC

P30serial line

of line, and the maximum of 32 bit data in a line is 16(If the number of the data less than 16, the actual number will be sent); When each a block data is transmitted (the maximum line of one block is 32, and if the line number less than 32, the actual number will be sent), a check line will be sent, which is the .

When chip received a complete block of data, the data will be verified. If the check is passed, send a "OK / r / n" command; If the validation is error or the data packets is illegal, then sent a "RS / r / n" command. If the programmer receives “RS/r/n” command, you need to re-send the Block data.

When the row data is 0x7e, it means 0x7d, 0x5e sent; When the row data is 0x7d, it means 0x7d, 0x5d sentData line format: (B behalf transmit data Byte, hexadecimal)

Table 18-2 ISP data transmission formatThe first row

1 2 3 4 5 6 …… 64 65 The last row

0x7e Num B0 B1 B2 B3 B4 …… B62 B63 0x7eCorrection line format:(ASCII code. S represent the cumulative checksum SUM)

Table 18-3 ISP data validation formatThe first row

1 2 3 4 5 The last row

0x7e 0xff S0 S1 S2 S3 0x7e18.3.2 The Used Resources

RAM resources usedISP uses the RAM within the range 0x10001000 to 0x10002800 on chip, Stack is located at the top of RAM.

Flash can use the RAM within the scope 0x10000000-0x10001000 (4KB) for programming.18.3.3 ISP Command

Each ISP commands support specific status code. When receive the undefined command, command processor to send the return codeINVALID_COMMAND.

Command and return code are ASCII format. Only when receives the ISP command execution is completed, the ISP command processor will send CMD SUCCESS, the host can send a new ISP commands.

ISP command can be divided into three types:1. Normal command: Only under the CP0, or CP1, CP2 and password is right, it can be access2. UN command Under the CP0, CP1, CP2 level of protection (password does not provide), it can be access3. In any case, FC, AL command can access

Table 18-4 ISP commandCommand Instruction NatureBaud rate setting BS <Baud rate> <stop bit> Normal commandEcho RD <switch settings> Normal commandWrite memory WM <Address> <Byte size> <Mode> Normal commandRead memory(including flash, sram)

RM <Address> <Byte size> <Mode> Normal command

Flash page erase FP <Page address> Normal commandFlash block erase FS <Block address> Normal commandFlash chip erase FC Special commandsFlash block blank FQ <Block address> Normal command

checkMemory compare MC <Address1> <Address2> <Byte size> Normal commandRunning GO <Address> Normal commandUnlock UN <password> Special commandsAccess to confidential level

AL Special commands

Enable PFPM PM <switch settings> Normal commandReset by software RS Normal commandEnable NVM(FLASH) NV <NVM option> Normal command

Baud rate setting

Table 18-5 ISP commandCommand BS <Baud rate> <stop bit>Input Baud rate:9600 or 19200 or 38400 or 57600 or 115200

Stop bit:1 or 2Return code CMD_SUCCESS or INVALID_BAUD_RATE or INVALID_STOP_BIT or

INVALID_PARAMAnnotation Change ISP communication serial frame format, including baud rate and stop bit.

Serial port start bit is 1, data bit is 8. New frame format is effectiveAfter return CMD SUCCESSS.

Example “BS 9600 2” Serial port baud rate will be set as 9600bps, two stop bits.Echo

Table 18-6 ISP commandCommand RD <switch settings>Input Switch setting: 0 (off) or 1 (on)Return code CMD_SUCCESS or INVALID_PARAMAnnotation Command and data echo. Default is on. When echo on, SoC send command and

data which to receive back to host.Example “RD 0” echo off.Write memory

Table 18-7 ISP commandCommand WM <Address> <Byte size> <mode>Input Address: address to start, it should be 32 bits;

Byte size: the number of bytes, must be in multiples of four;mode:0 as a serial port,1 as parallel

Return code CMD_SUCCESS or FM_MODE_ERROR or ADDR_NOT_ALIGN or COUNT_ ERROR or COUNT_ERROR or ADDR_NOT_MAPPED or INVALID_PARAM

Annotation Write data to SRAMExample “WM 268436224 4 0”

“78”“56”

“34”“12”Write 0x12345678 to address 0x10000300 via a serial port

Read memory Table 18-8 ISP command

Command RM <Address> <Byte size> <Mode>Input Address: address to read, it should be 32 bits;

Byte size: To compare the number of bytes, must be in multiples of four;mode:0 as a serial port,1 as parallel

Return code CMD_SUCCESS or FM_MODE_ERROR or ADDR_NOT_ALIGN or COUNT_ERROR or COUNT_ERROR or ADDR_NOT_MAPPED or INVALID_PARAM

Annotation Read the content of SARM of SoCExample “RM 268436224 4 0” Read the content which SRAM address is 0x10000300 via

a serial portFlash page erase

Table 18-9 ISP commandCommand FP <Page address>(FPGA version is 0 to 3071)Input Page address: Optional between 0 to 1535;Return code CMD_SUCCESS or INVALID_PAGE or INVALID_PARAMAnnotation Erase the content of the specify page of Flash of SoCExample “ES 1” Erase the content of the page 1Flash block erase

Table 18-10 ISP commandCommand FS <Block address>Input Block address: Optional between 0 to 47;Return code CMD_SUCCESS or INVALID_SECTOR or INVALID_PARAMAnnotation Erase the content of the specify block of EEPROM of SoCExample “FS 0” Erase the content of the block 0Flash chip erase

Table 18-11 ISP commandCommand FCInput NCReturn code CMD_SUCCESS or INVALID_PARAMAnnotation Erase all the content of Flash of SOC.Example “FC” erase all the content of Flash.Flash block blank check

Table 18-12 ISP commandCommand FQ <Block address>Input Block address: Optional between 0 to 47;Return code CMD_SUCCESS or INVALID_SECTOR or INVALID_PARAMAnnotation Check if the content of the specify block of EEPROM is empty (Unprogrammed

after erase it)Example “FQ 1” Check if the content of the 1 block is emptyEEPROM page erase

Table 18-13 ISP commandCommand EP <Page address>Input Page address: Optional between 0 to 511;Return code CMD_SUCCESS or INVALID_PAGE or INVALID_PARAMAnnotation Erase the content of the specify page of EEPROM of SoCExample “ES 1” Erase the content of the page 1EEPROM block erase

Table 18-14 ISP commandCommand ES <Block address>Input Block address: Optional between 0 to 7;Return code CMD_SUCCESS or INVALID_SECTOR or INVALID_PARAMAnnotation Erase the content of the specify block of EEPROM of SoCExample “ES 1” Erase the content of the block 1EEPROM page erase

Table 18-15 ISP E commandCommand ECInput NCReturn code CMD_SUCCESS or INVALID_PARAMAnnotation Erase all the content of the block of FLASH of SoC. This command will remove

key and the protection level settings, the chip will be set back to factory state.Example “EC” Erase all the content of the block of EEPROM.EEPROM block blank check

Table 18-16 ISP commandCommand EQ <block address>Input Page address: Optional between 0 to 7;Return code CMD_SUCCESS or INVALID_SECTOR or INVALID_PARAMAnnotation Check if the content of the specify block of EEPROM is empty (Unprogrammed

after erase it)Example “EQ 1” Check if the content of the 1 block is emptyFlash Programming

Table 18-17 ISP commandCommand FW <FLASH address> <RAM address> <Byte size>Input FLASH address: target address of FLASH to write

RAM address: the SRAM address of source bufferByte size: the number of bytes written(If Byte size is different from number ofbytes of Flash page, the rest of this Flash will be set as 0

Return code CMD_SUCCESS or COUNT_ERROR or SRC_ADDR_NOT_ALIGN or SRC_ADDR_NOT_MAPPED or DST_ADDR_NOT_ALIGN or DST_ADDR_NOT_MAPPED or INVALID_PARAM

Annotation It is used to program FLASH.Example “FW 0 268436224 128” copy 128 bytes data which SRAM address is

0x10000300 to FLASH address 0.EEPROM Programming

Table 18-18 ISP commandCommand EP <EEPROM address> <RAM address> <Byte size>Input EEPROM address: target address of FLASH/EEPROM to write

SRAM address: the SRAM address of source bufferByte size: the number of bytes written

Return code CMD_SUCCESS or COUNT_ERROR or SRC_ADDR_NOT_MAPPED or DST_ADDR_NOT_MAPPED or INVALID_PARAM

Annotation It is used to program EEPROM.

Memory compare Table 18-19 ISP command

Command MC <Address1> <Address2> <byte size>Input Address1(DST): Starting address of to compare the memory region 1, it should

be with the word alignment;Address2(SRC): Starting address of to compare the memory region 2, it should be with the word alignment;Byte size: To compare the number of bytes, must be in multiples of four;

Return code CMD_SUCCESS or COUNT_ERROR or SRC_ADDR_NOT_ALIGN or SRC_ADDR_NOT_MAPPED or DST_ADDR_NOT_ALIGN or DST_ADDR_NOT_MAPPED or COMPARE_ERROR or INVALID_PARAM

Annotation This command is used to compare the content of the two regions of memory. Example “MC 268436224 268436224 4” Compare 4 bytes data which SRAM address is

0x10000300 with 4 bytes data which SRAM address is 0x10000300Running

Table 18-20 ISP commandCommand GO <Address>Input Address: Address of Code execution start Flash or RAM. This address must be

Thumb addressReturn code CMD_SUCCESS or ADDR_NOT_THUMB or ADDR_NOT_MAPPED or

INVALID_PARAMAnnotation This command is used to execute the program in RAM or Flash.Once

successfully execute the command, it could no longer return to the ISP command handler.

Example “GO 5” Jump to address 0 x00000004 to executeUnlocked

Table 18-21 ISP commandCommand UNInput Password:32bit Hexadecimal numberReturn code CMD_SUCCESS or INVALID_PASS or INVALID_PARAM

Annotation This command is used to unlock ISP. Example “UN 567” Enter the password 567 to unlock the ISP Access to confidential level

Table 18-22 ISP commandCommand ALInput NCReturn code CMD_SUCCESS or INVALID_PARAMAnnotation This command is used to access to confidential level of ISPExample “AL” will return confidential level of SoCEnable PFPM

Table 18-23 ISP commandCommand PM <switch settings>Input switch settings:0(OFF)or 1(ON)Return code

CMD_SUCCESS or INVALID_PARAM

Annotation This command enable/disable PFPM (parallel programming pattern)Example “PM 1” enable PFPMReset by software

Table 18-24 ISP commandCommand RSInput NCReturn code

Annotation This command enable reset by softwareExample “RS” will enable reset by software

Enable NVMTable 18-25 ISP command

Command NV <NVM option>Input NVM option:0(Flash)or 1(EEPROM)Return code

Annotation This command enable Flash or EEPROMExample “NV 0” Enable Flash write, programming.

18.3.4 ISP Return Code

Table 18-21 ISP commandReturn code(ASCII code)

Mark Description

0 CMD_SUCCESS Successfully executed command. Only after successfully executed command, ISP will send this code

1 INVALID_COMMAND Invalid command2 INVALID_PARAM Invalid parameter (ASCII of parameter is not 0-9)3 INVALID_BAUD_RATE Invalid baud rate4 INVALID_STOP_BIT Invalid stop bit5 ADDR_NOT_ALIGN Address is not for boundary with byte6 COUNT_ERROR Byte count is not in multiples of four7 ADDR_NOT_MAPPED Address have space of crossing the line8 INVALID_SECTOR/INVALID_PAGE Invalid SECTOR_NUM or PAGE_NUM9 SECTOR _NOT_BLANK SECTOR is not empty10 SRC_ADDR_NOT_ALIGN Source address is not for boundary with byte11 SRC_ADDR_NOT_MAPPED Source address have space of crossing the line12 DST_ADDR_NOT_ALIGN Destination address is not for boundary with byte13 DST_ADDR_NOT_MAPPED Destination address have space of crossing the line14 COMPARE_ERROR Contrast Error15 FM_MODE_ERROR Memory model error16 ADDR_NOT_THUMB The address is not Thumb command17 INVALID_PASS Wrong password

18.4 In-Application Programming (IAP)About In-Application Programming, we should call programs of IAP by word pointer in the register r0, the word

pointer point to RAM that contains the command code and parameters. Result of IAP command return to results table which register r1 is pointing to. User can give the same value to pointer in the register r0 and r1, so we can reuse the command table to hold the result. Parameter table should be big enough to save all the result. About parameterpassing , please see table 21-7.The number of parameters and the results depend on IAP command. “Flash programming”, The maximum number of for command parameters, the number of result is 1.Command processor send status code(INVALID_COMMAND) after receive an undefined command. Program of IAP is Thumb code,address is 0x1800_1c01.

Figure 19-2 IAP parameter passing

18.4.1 IAP Command

Table 18-22 ISP commandIAP command Command code InstructionsFlash page erase 0x50 See the section of ISPFlash block erase 0x51 See the section of ISPFlash chip erase 0x52 See the section of ISPFlash block blank check 0x53 See the section of ISPFlash programme 0x58 See the section of ISPEnable NVM 0x5a See the section of ISPAnalog reset by software 0x5b See the section of ISP

18.4.2 IAP InstructionsIAP is use as follows:

Online Updater (update FLASH);When online upgrade, it needs to erase or write Flash. It will last about 4 milli second to erase Flash, Increase

processing delays about the interrupt.An implementation method of the IAP:When the user needs to online upgrade, he needs to add a procedures section of IAP upgrade with software. This

program is used to receive programs or data from remote host by the communication port (example UART). By IAP Interface SOC supplied. These programs or data is written to FLASH in the SOC.

18.5 Production PlatformRenergy provides a variety of programming methods, Specific elaborate can refer to “Renergy programming

platform instructions”.

Register r0 of ARM

Command code

Register r1 of ARM

The 1st parameter

The 2nd parameter

The nth parameter

Status code

The 1st result

The 2nd result

The nth result

List of parameters of command

List of results of command

19 Package size and soldering conditions

19.1 Package size

LQFP128L14.00×14.00×1.40 e=0.40

SYMBOLMILLIMETER

MIN NOM MAXA --- --- 1.6

A1 0.05 --- 0.20A2 1.35 1.40 1.45A3 0.59 0.64 0.69b 0.15 --- 0.23

b1 0.14 0.16 0.19c 0.13 --- 0.18

c1 0.12 0.13 0.14D 15.80 16.00 16.20

D1 13.90 14.00 14.10E 15.80 16.00 16.20E1 13.90 14.00 14.10eB 15.05 --- 15.35e 0.40BSCL 0.45 --- 0.75L1 1.00BSC

0 ----- 7º

LQFP100L

(0707×1.4)14.00×14.00×1.40

SYMBOLMILLIMETER

A1 0.05 --- 0.20A2 1.35 1.40 1.45A3 0.59 0.64 0.69b 0.19 --- 0.27

b1 0.18 0.20 0.23c 0.13 --- 0.18

c1 0.12 0.13 0.14D 15.80 16.00 16.20

D1 13.90 14.00 14.10E 15.80 16.00 16.20E1 13.90 14.00 14.10eB 15.05 --- 15.35e 0.50BSC

L 0.45 --- 0.75L1 1.00BSC

0 ----- 7º

LQFP64L7.00×714.00×1.40 e=0.40

SYMBOLMILLIMETER

A1 0.05 --- 0.20A2 1.35 1.40 1.45A3 0.59 0.64 0.69b 0.17 --- 0.25

b1 0.16 0.18 0.20c 0.13 --- 0.18

c1 0.12 0.127 0.14D 8.80 9.00 9.20

D1 6.90 7.00 7.10E 8.80 9.00 9.20E1 6.90 7.00 7.10eB 8.10 --- 8.25e 0.40BSCL 0.40 --- 0.65

L1 1.00BSC0 ----- 7

LQFP80L

(1212×1.4)12.00×12.00×1.40 e=0.50

SYMBOLMILLIMETER

A1 0.05 --- 0.15A2 1.35 1.40 1.45A3 0.59 0.64 0.69b 0.18 --- 0.26

b1 0.17 0.20 0.23c 0.13 --- 0.19

c1 0.12 0.13 0.16D 13.80 14.00 14.20

D1 11.90 12.00 12.10E 13.80 14.00 14.20E1 11.90 12.00 12.10eB 13.05 --- 13.25

e 0.50BSCL 0.45 0.6 0.75L1 1.00REF

0 ----- 7º

19.2 Package Information

Line1: Company TrademarkLine2: Corporate nameLine3: Product NameLine4: Product Lot numberThe Product Lot number consists of 10 characters including number and letter. The first 5 characters shows production code of WAFER, in which:

The 1st character shows the wafer out year, showed by numbers 1 to 9 and letters which A indicates 2010 and the like, pls see details in follower “Year Code Table”.

The 2nd character shows the wafer out month, showed by numbers 1 to 9 and letters which A indicates 10 and the like, pls see details in follower “Month Code Table”.

The 3rd to 5th characters show the serial number of wafer lot (begin with 001 and increase by one).The 6th character is reserved.The 7th and 8th characters shows the chip packaging company and production line.The 9th character shows the month for chip packaging, showed by numbers 1 to 9 and letters which A indicates 10

and the like, pls see details in follower “Month Code Table”.The 10th character shows the date for chip packaging, showed by numbers 1 to 9 and letters which A indicates 10

and the like, pls see details in follower “Date Code Table”.Lower left quarter: PIN1 flag

Year Code TableYear 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010Code 1 2 3 4 5 6 7 8 9 A

Year 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020Code B C D E F G H J K L

Year 2021 2022 2023 2024 2025 2026 2027 2028 2029Code M N P R S T U V W

Month Code TableMonth 1 2 3 4 5 6 7 8 9 10 11 12Code 1 2 3 4 5 6 7 8 9 A B C

Date Code TableDate 1 2 3 4 5 6 7 8 9 10Code 1 2 3 4 5 6 7 8 9 A

Date 11 12 13 14 15 16 17 18 19 20Code B C D E F G H J K L

Date 21 22 23 24 25 26 27 28 29 30Code M N P R S T U V W X

Date 31Code Y

19.3 Reflow oven temperature setting conditions

parameter valueHolding temperature TLPeak temperature TpAverage tilt rate (TL to Tp)

217260Max 3 /second

Warm upMinimum temperature (Ts min)Maximum temperature (Ts max)Time max-min ts

15020060-180 second

Ts max -TL Inclined rate (Ts max to TL) Max 3 / second

Version: V1.9 Renergy Technology Co., Ltd. of Shenzhen

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