Improvement in the performance of an InGaZnO thin-film transistor by controlling interface

trap densities between the insulator and active layer

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Semicond. Sci. Technol. 26 (2011) 085012 (8pp) doi:10.1088/0268-1242/26/8/085012

Improvement in the performance of anInGaZnO thin-film transistor bycontrolling interface trap densitiesbetween the insulator and active layerThanh Thuy Trinh1, Van Duy Nguyen1, Kyungyul Ryu1, Kyungsoo Jang1,Wonbeak Lee1, Seungshin Baek1, Jayapal Raja1 and Junsin Yi1,2

1 Information and Communication Device Laboratory, School of Information and CommunicationEngineering, Sungkyunkwan University, Korea2 Department of Energy Science, Sungkyunkwan University, Korea

E-mail: yi@yurim.skku.ac.kr

Received 6 January 2011, in final form 15 April 2011Published 10 May 2011Online at stacks.iop.org/SST/26/085012

AbstractAn amorphous InGaZnO film fabricated by radio frequency magnetron sputtering in only anAr-reactive gas shows high conductivity, and a thin-film transistors (TFTs)-based IGZO activelayer expresses a poor on/off current ratio with a high off current and high subthreshold swing(SS). This paper presents the post-annealing effects on IGZO thin films to compensate theoxygen deficiencies in films as well as on TFT devices to reduce the densities of the interfacetrap between the active layer and insulator. The ratio of oxygen vacancies over total of oxygen(O2/Otot) in IGZO estimated by the XPS measurement shows that they significantly diminishfrom 24.75 to 17.68% when increasing the temperature treatment to 350 ◦C, which is relatedto the enhancement in resistivity of IGZO. The TFT characteristics of IGZO treated in air at350 ◦C show a high ION/IOFF ratio of ∼1.1 × 107, a high field-effect mobility of7.48 cm2 V−1 s−1, and a low SS of 0.41 V dec−1. The objective of this paper is to achieve asuccessful reduction in the interface trap density, �Dit, which has been reduced about 3.1 ×1012 cm−2 eV−1 and 2.0 × 1012 cm−2 eV−1 for the 350 and 200 ◦C treatment samplescompared with the as-deposited one. The resistivity of the IGZO films can be adjusted to theappropriate value that can be used for TFT applications by controlling the treatmenttemperature.

(Some figures in this article are in colour only in the electronic version)

1. Introduction

Transparent oxide-based thin-film transistors (TFTs) haveattracted much attention due to their excellent electrical andoptical characteristics. In particular, amorphous indiumgallium zinc oxide (a-IGZO) TFTs have shown a betterthreshold voltage (VTH) and field-effect mobility (μFE) dueto the lack of grain boundaries, making this type of transistora very promising alternative to an amorphous silicon TFT(a-Si TFT) [1]. The high mobility in a-IGZO material isattributed to the electron transport by the conduction band,

whose minima in a-IGZO are composed of spatially spreadnanosecond orbitals of post-transition cations (In, Ga, andZn) without directionality, in addition to the fact that theirspherical symmetry makes the issue of structural disorderingin the amorphous state non-critical [2].

In fabricating the a-IGZO-based TFTs, IGZO is depositedwidely using magnetron sputtering. This technique generallyprovides such benefits as high deposition rates and has lowprocessing temperatures [3]. Therefore, IGZO has greatpotential to replace the existing silicon-based semiconductorsand organic-based semiconductors that are employed as an

0268-1242/11/085012+08$33.00 1 © 2011 IOP Publishing Ltd Printed in the UK & the USA

Semicond. Sci. Technol. 26 (2011) 085012 T T Trinh et al

Figure 1. Schematic cross section of the a-IGZO-based TFTbottom-gate structure with SiNx/SiO2 gate dielectric on siliconsubstrates.

active layer of the TFT backplane in the flat panel display[4]. However, despite these merits, magnetron sputteringoccasionally results in lower TFT performances due to theincrease in surface morphology roughness [5]. The interfacecharge trapping, scattering, and a rough surfacing result ina decrease in the saturation mobility (μsat) of TFTs [6],on/off current ratio (ION/IOFF) [7], and on drain current [8],as well as increasing VTH. Moreover, the IGZO-sputteredfilms, especially the only-Ar-reactive gas sample, show thehigh conductivity caused by the excess of oxygen deficiency,which degrade the TFT performance. Thermal annealingis a very useful technique to overcome these problems [9].Annealing in an appropriate environment, such as O2 or air,could supply the oxygen component needed to compensatefor the oxygen vacancies (VO) in the films [10]. Althoughsome studies [11] have already reported the effect of thermalannealing on the electrical properties of IGZO thin films, theeffective mechanism was seldom clearly presented for thisphenomenon.

In this work, the correlation between resistivity interms of the number of oxygen vacancies and the treatmenttemperature was conducted. a-IGZO TFTs were prepared ona SiNx/SiO2/p-Si substrate and the rapid thermal annealing(RTA) process is performed on these structures. Two differenttypes of devices are compared: as-deposited a-IGZO TFT andRTA-treated a-IGZO TFT at 200 and 350 ◦C, respectively.In this paper, we propose that the decrease in interface trapdensity originates from the rearrangement of particles infilms after treatment and the mechanism by which treatmentcan influence the TFT characteristic. Superior performancecompared to that of other reports [12, 13] was achieved.

2. Experimental details

Figure 1 presents a schematic cross-sectional view of the TFTstructure. This was fabricated using the p-type silicon waferwith very low resistivity (ρ∼0.001 � cm) as the gate electrode.The ICP CVD technique was adopted to deposit a 150 nmlayer of SiO2 and SiNx on the Si substrate at a temperature of160 ◦C, radio frequency (rf) power of 140 W, and working

20 30 40 50 60

Annealed at 350oC

Inte

nsit

y (

arb.

uni

ts)

2θ (deg.)

As depositedAnnealed at 200oC

Figure 2. (a) XRD patterns of IGZO films at different annealingtemperatures and (b) SEM images of IGZO films annealed at 350 ◦C.

pressure of 50 mTorr. These substrates were then cleanedby acetone, iso-propyl-alcohol, and de-ionized water in anultrasonic bath. a-IGZO thin film of 100 nm is deposited as theactive layer using rf magnetron sputtering at room temperature.The initial vacuum level is lower than 5 × 10−5 Torr, whilethe working pressure and rf power are maintained at 5 mTorrand 140 W, respectively, during sputtering. Pre-sputtering isperformed to remove any contamination on the target surfacefor 10 min prior to the active layer deposition. The activelayer is patterned according to the conventional mask process.The post-annealing process is performed in an air atmosphereusing RTA equipment at temperatures of 200 and 350 ◦C.Then, as the source/drain (S/D) electrodes, Ag of 100 nmwas deposited via thermal evaporation at a base pressure of5 × 10−5 Torr. In this paper, the TFT channel width andlength ratio (W/L) was fixed at 40.

The electrical characteristics of IGZO films and TFTdevices were measured by a semiconductor parameter analyzer(EL 420C). Structural and surface analyses were performedusing a scanning electron microscope (SEM) and x-raydiffraction (XRD). The chemical compositions and oxygenvacancies in IGZO films were analyzed by x-ray photoelectronspectroscopy (XPS) with an x-ray Al-Ka source.

3. Results and discussions

3.1. Thin films’ characterization

Figure 2(a) shows the XRD patterns of the as-deposited andannealed a-IGZO films (at 200 and 350 ◦C) deposited on a Siwafer. As shown in the figure, no sharp peaks correspondingto a crystalline phase (such as InGaZnO4, Ga2O3, In2O3 orZnO) were observed for all three samples that agree with otherreports [14]. In this study, the Si wafer peak was not observedin the range of 15–60◦, but at 32◦, as in some reports [15];however, this is still consistent with other research [16, 17]because it is not obligatorarily detected. As is widely known,the amorphous structure of the a-IGZO films is stable up to∼500 ◦C [18]. This feature guarantees that the structuralcharacteristics of the films remain unchanged during a follow-up heating procedure and work at relatively high temperatures.

2

Semicond. Sci. Technol. 26 (2011) 085012 T T Trinh et al

As-deposited 200 350

102

103

104

105

Res

isti

vity

(Ω

-cm

)

Annealed temperature (oC)

Oxygen vacancy: acted as the non-radiative center

O-stabilized on surface

IGZO bulk

O

O

O

O2

O2

O2

Figure 3. Electrical properties of films at different annealingtemperatures.

It is known that the amorphous films have the advantage oflarge-area uniformity, low interface state density and lowelectronic-defect domain [19]. From this result, one canconclude that the films that annealed at 350 ◦C still have anamorphous structure and can be used appropriately as an activelayer in the TFTs’ field. The inset of figure 2 presents the SEMimage which shows the surface morphology of 350 ◦C IGZO-annealed film. In the case of an a-IGZO-sputtered thin film,thermal energy is required to rearrange the atoms on the localsites. That is, the annealing temperature is attributed to theinternal modifications in the semiconductor structure, resultingin an improved local atomic rearrangement. The SEM imageshows a clear and uniform surface morphology. There wereno grains or grain boundaries due to its amorphous nature.This reveals that quite a uniform film can be prepared in thismanner.

The resistivity of IGZO films at different annealingtemperatures was estimated by current–voltage measurementusing the Ag/IGZO/glass structure. In this measurement, weestablished the current–voltage measurement and estimatedthe resistivity of the single layer of IGZO using the followingequation:

ρ = V

I× W

L× t, (1)

where W , L are the width and the length of the electrodes, t isthe IGZO thickness, and V and I are the input voltage and theoutput current, respectively.

As is shown in figure 3, while the as-deposited samplesshow a low resistivity of 9.71 × 101 � cm, the samplesannealed at 200 and 350 ◦C achieved the high resistivitiesof 7.7 × 102 and 2.9 × 104 � cm, respectively. The annealingtemperature dependence on resistivity can be explained basedon oxygen composition, as well as the oxygen vacancies inthe IGZO films that are the main factor for the conductionmechanism in oxide-based semiconductors.

XPS measurements were performed to determine thequantitative and qualitative chemical properties of the IGZOfilms. Figure 4 shows the representative XPS spectra of IGZO

thin films for all samples at different annealing temperatures.The In 3d, Ga 2p, Zn 2p and O 1s peaks can be easilyobserved. The In 3d, Ga 2p, Zn 2p and O 1s signals areshown in figures 4(a), (b), (c) and (d), respectively. The In3d5/2 peak at 444.4 eV, the Ga 2p3/2 peak at 1116.6 eV, andthe Zn 2p3/2 peak at 1020.8 eV indicate In-O, Ga-O, and Zn-O bonds, respectively. The intensities of these peaks seem toincrease with increasing treatment temperature, implying thatmore oxygen bonded with metal ions in the IGZO surface andbulk. The O 1s peak can be fitted by three nearly Gaussiandistributions, respectively, centered at 529.96 ± 0.1, 531.55 ±0.1, and 532.7 ± 0.1 eV [20]. The low binding energy peak(O1) at 529.96 eV is related to the O2− ion in the latticesurrounded by the Zn, Ga and In atoms in the IGZO compoundsystem [21]. That is, the intensity of this component is ameasure of the amount of oxygen atoms in a fully oxidizedstoichiometric atmosphere. The binding energy component(O2) at 531.55 eV is associated with O2− ions that are in oxygendeficient regions within the matrix of IGZO [21]. Therefore,the change in the intensity of this component may be connectedto variation in the concentration of oxygen vacancies. Thehigh binding energy component (O3) located at 532.7 eV isusually attributed to the presence of loosely bound oxygenon the surface of a film termed the specific chemisorbedoxygen, such as −CO3 or adsorbed O2 [21]. Generally, O2-related oxygen vacancies supply free-electron carriers in theIGZO film resulting in the increase of electron concentration[22]. The decrease in the O2 peak (in figure 4(f )) withincreasing temperature was attributed to the reduction inoxygen vacancies, where the surface was compensated withO atoms. The ratio of oxygen vacancies over total oxygen(O2/Otot) in IGZO significantly diminishes from 24.75% forthe as-deposited sample to 20.62% and 17.68% for the samplesannealed at 200 and 350 ◦C, respectively. The reductionin oxygen vacancies leads to the resistivity of IGZO beingenhanced. It is well known that the conductivity mechanismof ZnO-based material, such as IGZO, is due to the oxygenvacancy [23]. As described in the inset of figure 3, oxygenvacancy could be the origin of the carrier and non-radiativecenter [24] in ZnO-based materials. During annealing underO2 or air ambient, O is supplied through the O-stabilizedsurface and diffuses into the layer of IGZO to an inactivateoxygen vacancy state. To conclude, thermal treatment will bean easy method to improve the properties of IGZO for activelayer application in the TFT field. We note that the contactresistance and contact type should affect the resistivity of films.More studies are needed to arrive at a specific conclusion.

3.2. IGZO thin-film transistors

The TFT-bottom gate devices at various annealing temperaturehave been fabricated with double layers of the insulatorSiNx/SiO2. The use of the double insulators SiNx/SiO2 inthis study is to achieve both stability properties of SiNx [25]and high breakdown voltage properties of SiO2 [26] insulators.Figure 5 shows all the transfer characteristics of three TFTsat different annealing temperatures. The drain current (IDS)was measured in a dark box as the gate voltage (VGS) swept

3

Semicond. Sci. Technol. 26 (2011) 085012 T T Trinh et al

440 445 450 455

Zn 2p1/2

In 3d5/2

In 3d As deposited Annealed at 200oC Annealed at 350oC

Inte

nsit

y (a

.u.)

Binding energy (eV)

(a)

1110 1120 1130 1140 1150

(b)

As deposited Annealed at 200oC

Annealed at 350oC

Ga 2p1/2

Ga 2p3/2

Ga 2p

Inte

nsit

y (a

.u.)

Binding energy (eV)

1020 1030 1040 1050

(c)

Zn 2p1/2

Zn 2p3/2

Zn 2p As deposited Annealed at 200oC

Annealed at 350oC

Inte

nsit

y (a

.u.)

Binding energy (eV)526 528 530 532 534 536

(d )

O 1sO 1s As deposited

Annealed at 200oC Annealed at 350oC

Inte

nsit

y (a

.u.)

Binding energy (eV)

526 528 530 532 534 536

(e)

Sample annealed at 350oC

O3

O2

O1

O 1sO 1s

Inte

nsit

y (a

.u.)

Binding energy (eV)526 528 530 532 534 536

( f )

O2

O1O 1s As deposited

Annealed at 200oC Annealed at 350oC

Inte

nsit

y (a

.u.)

Binding energy (eV)

Figure 4. XPS spectra of IGZO thin films: (a) in 3d (b) Ga 2p (c) Zn 2p (d) O 1s at different annealing temperature and (e) O 1s core-levelXPS spectra of IGZO films annealed at 350 ◦C. (f ) The O1 and O2 fitting spectra extracted from the O 1s of samples annealed at differentthermal treatment conditions (as-deposited, 200, 350 ◦C). O 1s XPS spectra show an increase in the intensity with increasing the treatmenttemperature.

from −5 to 20 V, with the drain voltage (VDS) fixed at1 V. It is clearly found that the best electrical characteristicis obtained corresponding to the device annealed at 350 ◦Cwith the smallest off current and highest on current. Theas-deposited device expresses the opposite aspects with thehighest on current and the highest off current. The annealedsamples at 200 ◦C achieve a result at the average of the twoprevious devices.

Table 1 lists the key parameters of TFTs. VTH wasestimated by linearly fitting the IDS versus VGS curve in thelinear region. Under these conditions, the field-effect mobility(μFE) was calculated using the following equation (2) [27]:

μFE = L

W

gm

CoVDS, (2)

Table 1. TFT characteristics of IGZO-based device with differentannealing temperatures.

TFT parameters As-deposited 200 ◦C 350 ◦C

μFE (cm2 V−1 s−1) 8.55 6.1 7.48VTH (V) 4.63 9.34 7.9SS (V dec−1) 2.64 1.28 0.41�Dit (cm−2 eV−1) 0 −2 × 1012 −3.1 × 1012

VON (V) – −0.31 2.44ION/IOFF 3.7 × 104 2.6 × 106 1.1 × 107

where Co denotes the insulator capacitance, W/L denotes theaspect ratio of the device, and gm denotes the transconductance(gm = ∂IDS/∂VGS). From table 1, the largest ION/IOFF

indicated by 350 ◦C – treated TFT is about 4.2 times and

4

Semicond. Sci. Technol. 26 (2011) 085012 T T Trinh et al

20151050-510-12

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

As deposited Annealed at 200oC

Annealed at 350oC

Dra

in c

urre

nt (

A)

Gate voltage (V)

VD = 1V

Figure 5. Transfer characteristics logID-VG at VD = 1 V ofIGZO-TFTs with different annealing temperatures.

3 × 102 times as high as 200 ◦C annealed and as-depositeddevices, respectively. Other TFT parameters, such as SS andVTH, also prove the predominance of the high-temperature-annealed process. The VTH increases from 4.63 to 9.34 Vcompared to the as-deposited and 200 ◦C annealed sample.A higher annealing temperature leads to a slight reduction inVTH, as we can see from the 350 ◦C sample with VTH = 7.9 V.The SS is reduced linearly, whereas VON increased with anincrease in the annealing temperature. The best SS value of0.41 V dec−1 was obtained for the sample annealed in 350 ◦C.This was related to the reduction in the interface trap density atthe interface between the active layer and insulator. We haveknown that all TFT parameters depend strongly on the defectdensity at the insulator/semiconductor interface and inside thegate insulator. As discussed above, the passivation effect ofa sample annealed at 350 ◦C greatly improves the electricalcharacteristics of TFT. The TFT characteristics are not as goodas those achieved at a higher temperature for the device onlyusing the 200 ◦C treatment process.

The improvement in the electrical properties of the sampleannealed at 350 ◦C can be explained based on the changein both the carrier concentration of IGZO active layers andinterface trap density that exists between the active layer andinsulator. First, the as-deposited sample shows the highest onand off currents related to the high conductivity of the channellayer, leading to a high flow of electrons to pass throughthe source and drain. It is known that the off current is afunction of the conductivity of the channel layer, according tothe following equation [28]:

IDS,off = σW

LtCHVDS (3)

where σ denotes the electrical conductivity of the channellayer, tCH represents the thickness of the active layer, W and Lare the width and the length of the channel layer, respectively.It is apparent from equation (3) that the channel resistance

100 101 102 103 1040.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

Stress time (s)

Subt

hres

hold

sw

ing

(V.d

ec-1

)

As deposited

Annealed at 200oC Annealed at 350oC

100 101 102 103 104

0

2

4

6

8

10

As deposited Annealed at 200oC Annealed at 350oC

Δ VT

H (

V)

Stress time (s)

(a)

(b)

Figure 6. Threshold voltage shift and subthreshold swing ofsamples with different annealing temperatures.

plays a major role in increasing the off current. The sampleannealed at 350 ◦C with the highest resistivity (as shown infigure 3) shows the lowest off current of 3.7 × 10−12 A andvice versa.

Besides the improvement in ION/IOFF, the sampleannealed at 350 ◦C also showed the best in SS (as presentedin table 1) compared to other samples that implied an evidentreduction in interface trap density. The changes in interfacetrap density values, �Dit, presented in table 1 for all samples,were calculated as [29]

�Dit = Cox

ln(10)qkT(SSafter − SSbefore). (4)

The results show that the 350 ◦C annealed sample achievedthe highest �Dit. This meant that the interface trap densitycould be reduced the most compared to the other samples. Thismay be due to the diffusion effects between the insulator layerand the active layer that occur during the thermal process. Thishelps to decrease the number of dangling bonds at the interfacebetween the insulator layer and the active layer. More studiesare needed to confirm this conclusion.

Gate voltage stress measurements were performed toinvestigate the stability properties of TFT devices at differentannealing conditions. Figure 6 shows the SS and �VTH

compared to three devices at different stress times undercondition of VG = +20 V. As shown in figure 6(a), the SS valuesof samples annealed at 200 and 350 ◦C are almost unchanged,

5

Semicond. Sci. Technol. 26 (2011) 085012 T T Trinh et al

while the as-deposited sample shows a large increase with thestress time. The SS of the as-deposited sample was initiallyabout 2.64 and rose rapidly to 3.35 V dec−1 at a stress timeof 103 s. When the stress time increased to 104 s, the SS wasobserved to shrink. Besides, �VTH tends to decrease withincreasing annealing temperatures, as shown in figure 6(b).The sample at 350 ◦C treatment also achieves the lowestvalue. The �VTH values obtained at 104 s for as-deposited,200 and 350 ◦C annealed samples were 8.97, 4.98 and 1.11 V,respectively.

While the parallel shift in VTH without a significantchange in the SS value during the stress time is attributedto simple charge trapping in the gate insulator and/or atthe channel/insulator interface, the positive shift in VTH

accompanying the change in SS is due to both charge trappingand creation of defects within the oxide semiconductor channelmaterial [30]. Change in the as-deposited device at both highSS and �VTH with the stress time implied high defect creationand charge trapping inside the IGZO active channel. Duringbias stress at 103 s the SS increased significantly. This denotesthe braking of the bonding at the interface between IGZO andSiNx such as Si–N created in the interface trap. These defectsformed the traps to disrupt the flow of electrons, and theyare able to collect the electrons. In contrast, the sample with350 ◦C treatment shows both low SS and VTH shift, comparedto other samples, insinuating the reduction in defects inside theIGZO active layer. By using thermal treatment, these bondingat the interface can be reinforced. This results in the decreasein both SS value and the change in SS with the bias stresstime. The samples annealed at 350 ◦C denote the stabilitywith almost no change in the SS value.

The shift in VTH with the bias stress refers to theeffect of the deep trap of insulators on the electrical transfercharacteristic of TFT devices. The deep trap source in our TFTdevices is the interface trap at the SiNx/SiO2 interface. Thedecrease in the VTH shift with increasing treatment temperaturemay be attributed to the improvement of Si–N or Si–O bondinginside the double-layer insulators and inside the IGZO activelayer. Thus, the deep trap in the insulators is significantlyreduced under treatment at 350 ◦C.

Figure 7 presents the hysteresis characteristic of thesamples annealed at 200 and 350 ◦C. Both samples show thatVTH shifted to a more positive voltage for the hysteresis loopduring the return sweep. The positive VTH shift suggests thatnegative charge carriers were trapped at the channel/dielectricinterface or injected into the dielectric from the a-IGZOchannel layer. As clearly shown in the figure, the VTH shiftof the sample annealed at 350 ◦C was very small compared tothe 200 ◦C annealed sample. The �VTH of samples annealedat 200 and 350 ◦C are 1.14 and 0.48 V, respectively.

For forward sweeping, the interface states discharge theinitially trapped carriers and then begin to trap the carriers,while the gate bias sweeps into the subthreshold region [31].Hence, an inferior SS of 1.28 V dec−1 is obtained for the 200 ◦Csample, as shown in figure 7(a). These unfilled interfacestates will also degrade the effective mobility. Conversely, forreverse sweeping, the interface states were filled with carriersand become non-influential in the subthreshold region [31],

-5 0 5 10 15 20 25

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

Reverse

Forward

Dra

in c

urre

nt (

A)

Gate voltage (V)

Annealed at 200oC

ΔV TH =1.14 V

-5 0 5 10 15 20 25

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

R everse

Dra

in c

urre

nt (

A)

Gate voltage (V)

Forw ard

A nnea led at 350oC

Δ V T H =0.48 V

(a)

Figure 7. Transfer characteristics ID-VG at VD = 1 V for IGZOTFTs with annealing at (a) 200 ◦C and (b) 350 ◦C for both in theforward and reverse VG sweeps.

so SS increased to 1.32 V dec−1. Moreover, the carriertrapping/de-trapping will cause the hysteresis phenomenon.Compared to the devices treated at 200 ◦C, the devices treatedat 350 ◦C a-IGZO TFTs exhibit superior electrical properties,such as slight �VTH = 0.48 V, and lower SS (from 0.42 to0.41 V dec−1, for forward sweep). These are shown infigure 7(b). TFTs annealed at 200 ◦C have a relatively largeclockwise hysteresis in the transfer characteristics �VTH =1.14 V, which is explained by trap filling by the accumulatedelectrons. These indicate that the electron traps are reducedby thermal annealing. The improvement in the transfercharacteristic indicates the termination of defects at the a-IGZO/dielectric interface and in the a-IGZO bulk. This can be

6

Semicond. Sci. Technol. 26 (2011) 085012 T T Trinh et al

4

8

12

16

3

6

9

12

0

5

10

15

-5

0

5

102

104

106

108

Fie

ld e

ffec

t m

obili

ty

(cm

2 V-1

s-1)

Thr

esho

ld v

olta

ge (

V)

350oC200oC

Subt

hres

hold

sw

ing

(V.d

ec-1

)

Annealing conditionAs deposited

Tur

n-on

vol

tage

(V

)

350oC200oC

I on/I

off

Annealing conditionAs deposited

Figure 8. TFT performances of IGZO-TFT at different treatment conditions in statically analysis.

ascribed to the reduction in oxygen vacancy by air annealing.The best SS of 0.41 V dec−1 reveals that only a few interfacestates remained.

In summary, the electrical parameters of the four devicesrepresentative of each annealing treatment were determinedfor statistical analysis. Figure 8 shows the statistical analysisresults. It is clear from the figure that the thermal treatmentprocess at different temperatures can easily improve IGZO-TFT performance. VON of devices annealed at 200 and350 ◦C have almost the same value ranges, while VTH ofsamples treated at 350 ◦C significantly decrease, resulting inthe improvement of SS. The most significant influence of theannealing condition is to increase the ION/IOFF and μFE. Notethat the samples annealed at 350 ◦C with high resistivity stillhave the same μFE value compared to the as-deposited samples,implying the upgrading in the TFT structure after annealingand the contact between IGZO and Ag contact. More studiesshould be done to draw a conclusion.

4. Conclusions

In this study, the influence of thermal treatment on electricalproperties of IGZO thin films has been carried out. The oxygenvacancies in the bulk, compensated during the annealing

process, raise the resistivity. The electrical characteristicsof two types of TFT, with and without thermal treatments,are compared by plotting the transfer characteristics. Thepost-annealed TFT is found to be more suitable to be usedfor switching devices, and has better performance, such asthe higher μFE, larger current, and ION/IOFF, as well as lowerVTH, than others do. The interface trap density is controlledto achieve the optimum value of TFT transfer and outputcharacteristics. The mechanism to reduce the interface trapdensity by thermal treatment is explained by the decrease incarrier concentration due to the decrease in oxygen vacanciesin the IGZO films. Consequently, the annealing effect on a-IGZO TFT’s electrical characteristics has been presented. Thiswork is expected to be useful to further advance oxide-basedTFT technology for future devices.

Acknowledgments

This research was supported by the WCU (World ClassUniversity) programme through the National ResearchFoundation of Korea funded by the Ministry of Education,Science and Technology (R31-2008-000-10029-0).

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Semicond. Sci. Technol. 26 (2011) 085012 T T Trinh et al

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