Wideband and multiband CMOS LNAs: State-of-the-art and future prospects

Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎

Contents lists available at SciVerse ScienceDirect

Microelectronics Journal

0026-26http://d

n CorrE-m

Pleas(2013

journal homepage: www.elsevier.com/locate/mejo

Wideband and multiband CMOS LNAs: State-of-the-art andfuture prospects

S. Arshad, F. Zafar n, R. Ramzan, Q. WahabNED University of Engineering & Technology, Electronic Engineering, University Road, Karachi, Sindh 75270, Pakistan

a r t i c l e i n f o

Article history:Received 2 May 2012Received in revised form22 April 2013Accepted 25 April 2013

Keywords:CMOS distributed LNADual-band LNAInductorless LNAMultiband LNATunable LNAWideband LNA

92/$ - see front matter & 2013 Elsevier Ltd. Ax.doi.org/10.1016/j.mejo.2013.04.011

esponding author. Tel.: +92 2199261203.ail address: [email protected] (F. Zafar

e cite this article as: S. Arshad, et al.,), http://dx.doi.org/10.1016/j.mejo.20

a b s t r a c t

The realization of Software Defined Radio (SDR) requires flexible RF front-end to accommodate multiplestandards in different frequency bands. In this review paper, we survey the literature over the period1995–2011 and discuss the state-of-the-art multiband and wideband LNAs in context of different receiverarchitectures suitable for SDR. Wideband and multiband LNA designs reported in open literature arecategorized on the basis of their circuit architecture. Measured results of the sample LNA designs fromeach category are tabulated and discussed with emphasis on power consumption, NF, gain, linearity, andimpedance matching tradeoffs. We have also discussed our own three wideband inductorless LNA designprototypes which are manufactured in 0.13 mm and 90 nm CMOS. This review infers that future LNAssuitable for SDR must be highly linear and scalable with future technology nodes.

& 2013 Elsevier Ltd. All rights reserved.

1. Introduction

HE demand of wireless transceiver RFICs is exp expandingrapidly because of its huge market ranging from pagers, cordlessphones, cell phones, WLAN terminals, nodes for sensor networksand GPS to recently introduced DAB/DVB enabled PDAs [1]. Thesediverse range of mobile terminals have their own standard andrequire separate RF front-end and digital resources for basebandprocessing. As, Today, mobile terminals are no more a standaloneproduct rather they are a small part of consumer electronics e.g.WLAN and Bluetooth in Laptops and GSM, 3G, GPS and Bluetoothterminals in PDAs etc. This demands the mobile terminals to beflexible in nature with low power and low cost.

Therefore, the designer is urged to integrate all radio blocks ona single chip along with hardware reuse/sharing which not onlyresults in cost reduction due to reduced silicon area but allowsexclusion of separate RF packaged chips at the same time. On-chipintegration and placing a lower limit on the power consumption ofperformance centric analog circuits helps to reduce the powerconsumption [2]. In case of single chip radio receiver, only the LNAinput interface needs to be matched to 50 Ω antenna. Since allother RF blocks are on the same chip with interconnect lengthmuch smaller as compared to wavelength of interest, no reflectionoccurs. Therefore, power matching is not required and signal is

ll rights reserved.

).

Wideband and multiband C13.04.011i

transferred using voltage divider rule (low output impedanceconnected with high input impedance) as in low frequency circuit.This results in much smaller power dissipation.

A modern wireless terminal should support multiple standards(mobile: GSM, UMTS, WiMAX, LTE etc.; LAN:

IEEE 802.11a/b/g etc.; PAN: ZigBee, Bluetooth etc.) receivemultiple frequency bands (0.4–6 GHz), and allow any modulationscheme [3]. This mobile terminal is termed as commercial Soft-ware Defined Radio (SDR), as proposed by Mitiola [4].

SDR is still not a reality because of design challenges indomains of antenna, RF Front-end, A/D & D/A conversion andbaseband processing. A paradigm shift in radio design strategy andsome technological breakthroughs are mandatory to overcomethese challenges. Recently, the integration of MEMS in RF circuitshas increased the possibility of developing wideband smartantennas and on-chip high Q filter design [5]. Metamaterials havebrought a new possibility for multiband high efficiency smartantennas [6,7]. Similarly, the Rapid Single Flux Quantum (RSFQ)technology opens gateway to high performance ADCs/DACs [5].

Larson predicted in 1998 [1] that CMOS has the potential tomeet the future demands in comparison with SiGe based HBTs,GaAs based HEMTs and BJTs. With its ability of highest level ofintegration, low cost for bulk fabrication and low power consump-tion, CMOS has become the technology of choice for RFICs inconsumer electronic products [8]. Moreover, due to CMOS scalingthe unity gain frequencies are in hundreds of GHz (e.g. for 65 nmfT¼200 GHz [9]) allowing the design of RF circuits operating atfrequencies near and above 60 GHz [10].

MOS LNAs: State-of-the-art and future prospects, Microelectron. J

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mailto:[email protected]





LNA

Tunable Filteror

Set of Filters

Tunable or Multiband or

Wideband

Frequency Conversion

@ RFf

ADCDigital BBProcessor

Dig

ital B

BPr

oces

sor

Fig. 1. (a) Ideal SDR Receiver (b) practical SDR receiver.

S. Arshad et al. / Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎2

The SDR receiver proposed by Mitiola (Fig. 1 (a)) puts verytough requirements on the dynamic range, speed, noise perfor-mance and linearity of A/D converter. An LNA relaxes the noiseperformance and dynamic range requirements while the fre-quency translation block reduces the speed requirements of theA/D converter (Fig. 1(b)). That is why, all multistandard, multibandreceiver designs reported to date incorporate some sort of lownoise amplifier.

In this paper, we focus on CMOS LNA architectures which havethe potential to be suitable candidates for practical SDR receiver(Fig. 1(b)). In Section II we begin with the review of receiverarchitectures. The emphasis is on LNA, the key component of anywireless receiver. Therefore, Multiband and Wideband LNAs areelaborated in context of SDRs. Challenges in multiband and wide-band LNA designs are discussed in Section 3. A detailed survey andcritical analysis of the state-of-art Multiband and Wideband LNAsare presented in Sections 4 and 5 respectively. Section 6 encom-passes our contribution and approaches to the SDR compatiblewideband LNAs. The paper concludes with summary and futureprospects.

2. Review of receiver architecture

Almost all narrowband receivers use Super Heterodyne Archi-tecture proposed by Armstrong in 1918. Several variants of thisarchitecture are commercially available today [11–13]. This archi-tecture provides high sensitivity and high selectivity simulta-neously [14]. It converts the received RF signal to a fixedintermediate frequency (IF). This requires a high quality off-chipImage Reject SAW filter. Hence, this architecture does not easilylend itself to monolithic integration. Brute force implementationof high Q on-chip filters will result in power consumptionproportional to the square of quality factor of the filter [13]. Thisundermines the concept of on-chip integration to attain lowpower design. In future, cost effective MEMS integrated in CMOSmay resolve this issue [15].

The removal of IF stage and quadrature down conversion of thereceived signal to baseband in Direct Conversion (Zero IF) Archi-tecture allows on-chip implementation by replacing high Q imagerejection filters with low pass filters [12,14]. As proposed by BritishScientists in 1932 [16], this baseband signal is then digitized andreconstructed using complex signal processing techniques whichcancels the image frequency [17,18]. On the downside, Zero IFconversion results in constant and time varying (due to LOleakage) DC offsets and elevated 1/f noise. IQ mismatches andsecond order harmonics are also present in this architecture. These

Please cite this article as: S. Arshad, et al., Wideband and multiband C(2013), http://dx.doi.org/10.1016/j.mejo.2013.04.011i

effects corrupt the signal and may lead to saturation or desensi-tization of the following stages [17,19]. Several techniques includ-ing the injection of dynamic DC offset to resolve this issue arediscussed in literature [20,21]. Most of the modern single chipreceivers can support more than one frequency band and use ZeroIF architecture [17,22–26].

The Low IF Architecture is a blend of both Super Heterodyne andZero IF architectures and is thus susceptible to IQ mismatch andImage problem. Hartley and Weaver quadrature down conversiontechniques can be employed for image rejection. However, IQmismatches can be corrected in digital domain. The dc offset, 1/fnoise and LO leakage are relaxed due to non-zero IF frequency. Anin-depth analysis of such architectures is presented in [27–30].

Despite the drawbacks associated with both Zero and Low IFarchitectures they are highly amenable to monolithic integration[28,31].

3. Challenges in LNA design

In [32], the gain, NF and linearity requirements of a single LNAaccommodating GSM, UMTS and WLAN are specified as 23 dB,3 dB and 0 dBm respectively. Addition of new standards likeWiMAX and LTE will make the LNA specifications even morechallenging. Moreover, multiple filters are used at the LNA input toremove blockers. The linearity parameters of the LNA will becomemore stringent if these filter specifications are relaxed. This clearlyshows that the implementation of a receiver chain without an LNAis practically impossible. Absence of LNA imposes strict require-ments on the ADC such as dynamic range ≥110 dB, noisefloor≤−120 dBm and bandwidth of ≥10 MHz. The inability todesign such an ADC with adequate power consumption in today'stechnology is the main reason that the LNA cannot be skippedaltogether from the receiver architecture as discussed in [3,4].

In a receiver, the first amplifying block is LNA. Its noiseperformance defines the NF of complete receiver [33,34]. Aclassical narrowband LNA should have high gain, low NF, goodlinearity, low power, 50 Ω matching and stability at the frequencyof interest. In comparison, the design specifications for state-of-the-art wideband LNAs include:

i.

MOS

Minimum signal reflection by achieving good (50 Ω) inputmatching (S11≤−15 dB) for all frequencies [35].

ii.
NF≤3.5 dB over the entire bandwidth [36]. iii. Higher linearity (IIP3≥0 dBm) [32]. iv. Flat gain across the entire bandwidth [37]. v. High IIP2≥40 dBm in case of Zero IF architecture [38]. vi. Reverse isolation≥50 dB to reduce self-mixing in Zero IF
architecture [17].
vii. Unconditional stability over entire frequency range.
For multiband LNAs these specifications must be satisfied foreach supported band. However, these requirements must befulfilled without any compromise on silicon area and powerconsumption compared to narrowband LNAs, making them sui-table for portable and hand-held applications [39].

Flexibility in LNA operation can be obtained in three possibleways: (i) using a narrowband LNA for each standard which resultsin high power consumption as well as higher cost due to large Siarea [40–46], (ii) using a reconfigurable/band switching/multibandLNA. This allows more compactness and power saving but stilloccupies large area because of tuning inductors [47–53], (iii) usingwideband LNAs which allows simultaneous multiband operationwith low cost and small area [54–60].

Multiband operation in LNAs is usually achieved in two ways:(i) by tuning of components and (ii) by switching between the

LNAs: State-of-the-art and future prospects, Microelectron. J




Resonant Output Matching Network

RFinRFin

RFoutRFout

1, 2 ... .

LC tank with resonance

at ω ω

M1M1

M2M2

Tunable matching networkInput network to

provide matchingat ω1 ,ω 2 ......

Vbias

Fig. 2. (a) Concurrent LNA and (b) non-concurrent CS inductively degenerated LNAwith tunable matching network.

S. Arshad et al. / Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎ 3

components; each creating resonance with other components atdifferent frequencies. In both cases, LNAs utilize inductors in oneform or another. Inductors cover extremely large silicon area andunfortunately, they do not scale as the CMOS technology does. Onereason is that in a downscaled inductor, amount of energy storedcannot be high compared to energy dissipated per cycle within asmall chip area. Moreover, downsizing of inductor increases itsinductance and decreases its series resistance. As a result, qualityfactor reduces 100 times with only 10 times reduction in inductorsize [61]. A multiband LNA supporting more than two differentfrequency bands results in an unwillingly large chip area. Asproposed by Razavi, large covered area of inductors can be reducedby using either stacked or nested inductors in layout [62]. Anotherchallenge is that the baseband processors are usually designed innew process nodes to achieve better area, power and costmatrices. These new nm technology nodes do not offer preciseon-chip inductors in their latest versions. Hence, the designers areleft with no choice but to use inductorless wideband LNAs in suchsituations.

In wideband LNAs, the need of a large bandwidth imposesignificant challenges compared to narrowband or multibandLNAs. The CMOS transistors used in LNA design have parasiticcapacitances associated with them. In narrowband LNAs, theseparasitic capacitances are tuned out using inductors. Such techni-ques cannot be employed in every wideband LNA design. Thedistributed amplifiers, a wideband topology, which absorb theparasitics into their traditional design, suffer from low gain, highpower consumption and large NF [63–65]. At high frequency, thegain of a wideband LNA is limited by capacitive loading of theoutput stage. To overcome this limitation some approaches mergeLNA and mixer to achieve high gain across the entire bandwidth[66–68]. This merger also reduces the number of components inthe signal path and, thus, improves power consumption andlinearity. The significance of wideband LNA comes into play forapplications like Digital Video Broadcasting for Satellite(950–2150 MHz) and Terrestrial (450–850 MHz) or Analog Cable(50–850 MHz) since they function at lower frequency band (below1 GHz) [106]. At these frequencies, the use of multiband LNAsrenders either bulky integrated coils or improper performanceover the bandwidth. In such cases, a wideband inductorless LNAsaves area and improves performance by replacing several LCtuned multiband LNAs [43,69–73] in multimode operations [39].On the downside, wideband LNA has inherently high NF and alsoamplifies interfering signals with the main signal. These short-comings impose severe implication on high sensitivity receiverdesign [34].

Linearity is also a big issue because of the in-band interferencesand cross/inter-modulation of blockers [74,75] in RF receivers. Thepower of these blockers can be as high as 30 dBm in VHF or Tetraband range [76]. This imposes stringent linearity requirement forLNAs and requires ADCs with unacceptably high power consump-tion. Since Wideband LNAs amplifies the interferers with the mainsignal therefore, their design needs further attention in this regard.

Another important challenge lies in comparison among thevarious LNA designs reported in current literature. Different LNAdesigns have different gain, NF, linearity, and power consumption.To compare such designs, typically the multitude of LNA specifica-tions are mapped into a single scalar called Figure of Merit (FoM)and its large value indicates a more efficient design. FoM servestwo basic purposes in LNA design: (i) to determine the technologydirection and pace of advancement as the technology scales and(ii) to compare the LNAs designed in different technology nodesfor global optimization in design space, independent of thetechnology used. To accommodate the above two conflictingrequirements we have proposed two FoMs: (i) FoMT (FoM fortechnology) and (ii) FoMC (FoM for circuit optimization) each for


narrowband, wideband and multiband LNAs [77]. FoMT incorpo-rates the improvement in LNA matrices both, due to technologyscaling and circuit innovation and optimization while FoMCrepresents the picture of circuit novelty and optimization inde-pendent of technology. In this paper we have used our proposedFOMs [77] for comparing various multiband and wideband LNAs.

Furthermore, LNAs using differential configuration offer robust-ness, common mode noise rejection, smaller variation of bondwire inductance and high noise immunity from supply/substratenoise compared to single ended counterparts [78–80]. Insertion ofbalun, however, increases the receiver loss and decreases LNAsensitivity [81].

4. Multiband LNAs

Multiband LNA switches to the band of interest either by usingcircuits resonating at multiple frequencies simultaneously (con-current) or by switching in or varying a circuit component in thesignal path (non-concurrent) [48–53,82]. It enhances immunityfrom out of band interferers and preserves frequency bandselectivity [47].

4.1. Concurrent LNAs

Concurrent LNAs are capable of simultaneous operation atdifferent frequency bands as shown in Fig. 2(a). Both power andchip area are saved through concurrency since a single platformcovers multiple frequencies. Besides their low noise characteristic,these LNA's achieve high gain with good input matching in multi-ple bands. On the downside, these LNAs suffer from linearityproblem as the spurs in one band can corrupt signals in theother band.

In [50], a concurrent dual-band low noise amplifier (0.35 mmCMOS) is presented. Here, series and parallel LC networks areutilized to achieve narrowband gain of 14 dB and 15.5 dB at 2.45and 5.25 GHz respectively with just 10 mW power consumption.The NF for 2.45 GHz band is acceptable (�2.3 dB) but is quite highfor 5.25 GHz band (�4.5 dB). One major drawback of this design isthat its gain, NF and linearity cannot be further improved becausethe single input matching network cannot be optimized forboth bands.

In [49], CMOS based dual-band (2.4–2.6 GHz and 5–6 GHz) LNA(0.25μm BiCMOS) works at multiple frequencies simultaneouslythrough tuning of the passive and active devices. The simulated NFfor both the bands is≤3.8 dB while gain is 27 dB and 20 dBrespectively. However, the power consumption is 21 mW whichis twice than that of [50]. LNA (0.25 mm CMOS) in [82] is afully-integrated 2.45/5.25 GHz dual-band design. It has high line-arity (IIP3¼7 dBm and 17 dBm respectively) but very poor NF, gainand power consumption (NF¼4.7 and 5.7 dB, Gain¼5.78 and3.24 dB and PDC¼42.5 mW) in both bands.





RFin

RFout

Off-chip matching network

M2

M1

M3

V ctrl

Vbias

Fig. 3. Pseudo-concurrent LNA presented in [96].


In [84], a 1.8/2.4 GHz dual-band concurrent LNA (0.18 mmCMOS) is presented. In this paper, a particle swarm basedoptimization technique (PSO) is employed for the selection andoptimization of output matching network while switched capaci-tors are used for input matching. The simulation results show agood NF (≤2.4 dB), extremely low gain (≤9 dB) and 18 mW ofpower consumption.

Another multiband LNA (0.18 mm CMOS) utilizing notch filters ispresented in [85]. The three staged LNA achieves concurrent opera-tion over three 0.935–5.825 GHz bands with measured gain of 15–24 dB. However, because of its cascaded structure, its NF, linearityand power consumption are very poor (NF¼4.4–4.78 dB, IIP3¼−13.85 and PDC¼32.4 mW). A differential multiband 1.35–2.9 GHzLNA (0.18 mm CMOS) utilizes a new technique for interferencerejection using a parallel resonator unlike series resonator whichcauses gain reduction at resonant frequency [86]. This LNA achieves asimulated maximum NF, voltage gain and interference rejection of3.32 dB, 26 dB and −20 dB respectively with a minimum IIP3 of−7 dBm. However, the power performance is degraded (27.35 mW)because of the differential nature of design.

In [46], a dual-band concurrent LNA supporting 2.44/5.25 GHzis presented. It is implemented in 0.25 mm BiCMOS SiGe:C (onlyHBT). Here, LC networks match both the input and outputimpedances at two different frequencies. The LNA has NF of 3and 3.5 dB and gain of 19.7 and 14.4 dB at both frequencies with apower consumption of 9 mW. However, its linearity is poor (IIP3¼−13.4 and −7 dBm at 2.44 and 5.25 GHz respectively). Similarly,another BJT based concurrent dual-band LNA (SiGe BiCMOS) for802.11a/g WLAN is designed in [83]. The use of monolithictransformers in the input matching network allows dual-bandmatching. However, insertion loss and coupling coefficient oftransformer are the key factors behind the limitation of this LNA.This LNA provides a simulated gain of 18.3 dB and 15.2 dB at2.45 GHz and 5.5 GHz, simultaneously while NF is 2.26 dB and3.2 dB, respectively with power consumption of 12 mW.

4.2. Non-concurrent LNAs

Non-concurrent LNAs are an extension of classical inductivelydegenerated cascode LNA with tunable matching network (Fig. 2(b)). Here, tunability is commonly achieved by using switches orparameter variations (such as variable capacitor, variable biasingvoltage etc). These LNAs are less prone to spurs as they operate inone band at a time. The drawback of such LNAs is the use of severalinductors which consume a large chip area. The area overhead isaggravated when a tunable varactor bank for frequency tuning isalso deployed [87].

In [88], a BJT based LNA (0.35 mm SiGe BiCMOS) is presentedwhere a variable shunt–shunt feedback capacitance is used. Thevariation of this capacitance is achieved through the use of a MOSswitch or by toggling between the different bias currents.A 2.7-3.1 GHz LNA (0.35 mm BiCMOS) employs MEMS varactorsto achieve frequency reconfigurability for multiband operation[89]. It achieves an S21, NF and IIP3 of 7.7 dB, 4.2 dB and −0.5 dBmrespectively at 2.7 GHz, consuming very small power of 2.5 mW.

In [48], a fully integrated 2.4/5.2 GHz LNA (0.18 mm CMOS)achieves input matching by switching the finger number and thebias voltage of the input transistor, while the output matching isachieved by capacitor switching network. The implemented circuitexhibits gains of 10.1 and 10.9 dB, and NF of 2.9 and 3.7 dB at thetwo frequency bands, respectively. In this design, the NMOS basedswitches exhibit non-ideal characteristics at both on and off states;therefore, the circuit performance is severely degraded. This canbe minimized by increasing the fingers of the switching MOStransistor. However, the excess parasitic capacitance associatedwith the MOS switches imposes a limitation on the transistor


sizes. LNA (0.18 mm CMOS) in [53] operates at 2.4 and 5.15 GHzbands. Input impedance matching is achieved through sharing ofdegenerated inductors between two CS transistors whereasswitching between the bands is accomplished through the use oftwo resonated gate inductors. Moreover, similar to [48], the loadinductors are tuned out through switches which degrade Q of theload tank. Another dual-band LNA design (0.18 mmCMOS) achievesnon-concurrent operation by inserting MOS transistor as a switchbetween the gate and source of the input common sourcetransistor [90]. Its simulation shows a low NF (�2.3 dB), goodvoltage gain (�15–17 dB), good linearity (IIP3 of 0.5–3 dBm) andpower consumption of 7.2–14.4 mW. This design reports multi-band operation with high levels of integration and small chip area.

In [91], a low voltage CMOS based 2.45/5.25 GHz LNA (0.18 mmSiGe BiCMOS) is presented. Dual band operation is possible bytuning two series LC loads each at the band of interest. This designprovides two separate outputs for each desired band. However, itcompromises Si area because of the use of the six inductors. A 2.4–5.4 GHz LNA (0.13 mm CMOS), performs continuous frequencytuning by combination of switched inductors and varactors [92].This LNA supports Bluetooth, WiMAX, UWB mode-1, 802.11b/g andpart of 802.11a and achieves a gain of 25 dB, NF of 2.2 dB and IIP3of −1 dBm with power consumption of≤5 mW. On the downside,the largest and smallest inductance values of the PMOS basedinductor are limited due to their significant parasitic capacitance.The LNA (0.35 mm SiGe BiCMOS) achieves triple band operation byswitching an additional transistor [93]. However, the NF isdegraded due to switches at the input. This problem is mitigated,through the reuse of inductors in a multiband LNA (0.13 mm CMOS)[94]. The design saves area by sharing the input matching inductorin two operating modes. While switching from one mode to other,it changes its input matching configuration from narrowbandcommon source to wideband (1 GHz) common gate. NF isacceptable (�3.5 dB) but linearity is poor for both configurations,especially in 2.4 GHz band.

5. Pseudo-concurrent LNAs

A pseudo-concurrent architecture is presented in Fig. 3 [95].The LNA (0.18 mm CMOS) has a multi bandpass filter at the loadwhich allows it to operate in three bands (0.8 GHz, 1.8 GHz and2 GHz). The 0.8 GHz band is received simultaneously with one ofthe other two bands. Frequency selection is done by a simplePMOS switch which changes the capacitance of an output LC filter.It has a simulated NF�1.6 dB, gain�15 dB and IIP3�−5.5 dBm inall bands. The main drawback of this design is the use of manyinductors which consumes a large chip area. In [96], a quad band(0.9/l.8 GHz and 0.9/2.4 GHz) single ended LNA (0.13 mm CMOS),employs a two bit mode RF CMOS switch for band selection. Such





Table

1CO

MPA

RISON

OFVARIO

USPU

BLISH

EDMULT

IBAND

LNAS.

Source

CMOS(mm)

Freq

(GHz)

S21(dB)

S11(dB)

NF(dB)

IIP3

(dBm)

Power

Con

sumption(m

W)

Topolog

yFo

MT

FoMC

ICEC

S’10[98

]0.09

0.85

/0.9/1.8/1.9

33.4/32.8/27

/26c

−10

1.46

/1.37/1.88

/1.78c

−15.8/−1

5.2/−9

.6/−10

.3c

12.18

Non

−con

curren

t0.39

0.19

ICEC

S’10[99

]0.18

1.9/2.4/3.5/5.2

13−1

7−1

41.6/2.8/2.7/3.1

−6.2/−18

.3/−7.1/−1

9.6

3/3.4/3.4/5.3

Non

−con

curren

t0.56

0.38

MTT

S‘09[10

0]0.13

1.9−

2.4

14−1

0a−1

33.2−

3.7

−6.7

(@2GHz)

17Non

−con

curren

t(con

tinuou

stuning)

0.07

0.04

ESSC

IRC‘07[10

1]0.13

2.45

/5.25

22/20.5a

−10

2.1

−17/−1

4.5

3.8

Non

−con

curren

t0.37

0.20

RFIC‘05[91

]0.18

b2.45

/5.25

13.9/8.7

−14/−1

24.98

/6.58

þ2.87

/3.83

2.5

Non

−con

curren

t2.68

N/A

RFIC‘02[97

]0.18

8.0/9.0

13.7/12

−5.8/−5.4

3.2/3.7

~−3

.2/1.3

e22

.4/19.6

Non

−con

curren

t0.41

0.61

ISCAS‘07[85

]0.18

0.9/2.4/

5.25

18/24/23

−35~

−74.6/4.4/

4.4

−12.8/−1

5.3/−1

4.7

32.4

Con

curren

t0.06

0.04

EuMC‘06[46

]0.25

b2.44/5.25

19.7/4.4

−9.4/−9.1

3/3.75

−13.4/−7

9.0

Con

curren

t0.14

N/A

EuMC‘03[49

]0.25

b2.4/5.4

27.3/21

−10/−1

82.1/3.4

0.0e

21.0

Con

curren

t4.29

N/A

VLS

ISy

mp.‘01

[50]

0.35

2.4/5.2

14/15.5a

−25/−1

52.3/4.5

0.0/

5.6

10Con

curren

t5.99

5.99

MTT

−S'03[95

]0.18

0.8/1.8/2.1

19.3/14.5/14

.1o

−25

0.6/1.0/1.4

−5.4/−3.8/−3

.115

.3Pseu

do−

concu

rren

t3.28

2.20

dLo

wGainMod

eaVoltage

gain

bSiGeBiCMOS

cHighga

inmod

e



switch renders reduced insertion loss and good isolation betweenthe selected frequency bands. Simulation results indicate NFo4 dBand gain 414 dB in all bands while power consumption is 12 mW.On the downside, the parasitic effect of switches exhibit non-idealcharacteristics in both on and off states. Table 1 shows the measuredresults of all three types of published multiband LNAs.

6. Wideband LNAs

Wideband LNAs provide continuous flat gain and impedancematching over their entire bandwidth. They employ variousmethods to achieve wideband operation. Wideband LNAs reportedin open literature can be categorized as: (a) common source withresistive termination, (b) feedback, (c) common gate, (d) inputfilter and (e) distributed. The basic circuit diagram of thesetopologies is presented in Fig. 4. The sub categorization of theseconfigurations is also presented in later sections.

6.1. Common source with resistive termination

One brute force approach to achieve wideband impedancematching is by adding a 50 Ω shunt resistor at the input ofcommon source LNA as shown in Fig. 4(a) [11]. This topologyresults in severe tradeoff between NF optimization and inputimpedance matching. The placement of shunt resistor before thetransistor not only attenuates the signal but also adds its ownthermal noise. As a consequence, the NF is unacceptably high.Hence, this approach is no longer in use. The lower bound on thehigh NF of this approach is [11]:

F ≥ 2þ 4 ðγ =αÞð1=gmRÞ ð1Þwhere γ is a noise parameter and α is the ratio of transistor’stransconductance (gm) to drain-source conductance (gds) atzero bias.

A 700–900 MHz RF amplifier (2 mm CMOS) makes use ofresistive termination at the input terminals of amplifying transis-tors to achieve 50 Ω impedance matching [102]. It has a gain of14 dB and consumes 7 mW of power. As expected, this designsuffers from poor NF (6 dB).

6.2. Feedback LNA

The tradeoff between NF and input impedance matching inprevious topology can be broken through the use of globalnegative feedback (Fig. 4(b)). Theoretically, lossless transformerfeedback offers best performance [103]. Practically, a widebandtransformer in CMOS is lossy and occupies extremely large area.Therefore, a lossy feedback including a resistor, resistor–capacitor,reactive element or transistor is a more efficient solution to breakthis tradeoff. Feedback renders wideband input impedance match-ing without reducing the signal with a noisy attenuator before

RFinRFin

RFin

RFoutRFout RFout

RFout

RFin

Zd M1 M2 MN

Feedback

Zg

VG

VS

FilterNetwork

RFin

RFout

Fig. 4. Common wideband LNA topologies (a) common source with resistivetermination (b) feedback (c) common gate (d) filter LNA (e) distributed.





RFin

RFout

RFoutL22

L11

RFout

RFin RFin

RFout

RFin

Fig. 5. (a) R feedback (b) series RC feedback (c) parallel RC feedback (d) transformerfeedback.


amplification. Hence, its NF is much better than that of commonsource with resistive termination.

6.2.1. Resistive feedbackLNAs using resistive feedback (Fig. 5(a)) topology render broad-

band operation with superior input matching and gain character-istics [104–113]. In [104] (0.18 mm), a blend of resistive feedbackand conventional narrowband CS degenerated topologies achievewideband input impedance matching. The placement of feedbackresistor brings the curve of S11 near the central real axis of Smithchart (Fig. 3 of reference [104]). The gain remains flat throughoutthe bandwidth with smaller degradation of NF compared to CSwith resistive termination [104]. This paper clearly discusses theeffect of feedback resistance, Rf, on the NF of the LNA. Thesimplified NF of this topology as reported in [2] is:

F¼ 1þ γαRS=gm ð2Þ

where Rs is the source impedance.Generally for a cascode configuration feedback LNA, S11 is

obtained as [105]:

S11¼ 1þ gmZo

Rf þ Zoþ ωCdg

B1þ 2Cds

Cgs

� �1þ Zo

Rds

� �ð3Þ

where Zo is the characteristic impedance (50 Ω), Rf is the feedbackresistor and B is fT/f. For low NF, large feedback resistor is requiredbut it places stringent tradeoff between gain and linearity and alsohampers flat gain performance. In [106,107], the LNA (0.25 mmCMOS) is designed with a current reuse PMOS/NMOS pair withshunt feedback that achieves wideband operation (0.02–1.6 GHz).This design employs noise cancelation to reduce NF (≤2.4 dB)without degrading input impedance matching and achieves goodlinearity (IIP3 of 0 dBm). However, the auxiliary amplifier, man-datory for feedforward noise cancellation, increases power con-sumption (35 mW). A similar resistive feedback architecture as[106,107], is used in [108–110] to achieve wideband operation.Noise canceling and combination with other topology is used forbetter performance. A 0.1-14 GHz LNA (0.13 mm CMOS) achieveswideband impedance matching through feedback resistor and asource follower which acts as a buffer [111]. It has NF of 2.7–3.7 dB,IIP3 of 3.8 dBm, gain of 12.4 dB with a power consumption of14.4 mW. Another wideband LNA (90 nm CMOS) with remarkablylow NF (NFmin¼1.43 dB) is reported in [112,113]. It employsresistive feedback with NMOS/PMOS pair in a cross coupledfashion for noise canceling. The drawback of this design is thatincreasing the input transistor size for improving NF increasesparasitic capacitance at its gate which forms a low pass filter at theinput, thereby, degrading the response at high frequencies. Thisdesign achieves high gain of 20 dB, power consumption of 18 mW,linearity of −1.5 dBm with severely reduced bandwidth of 1 GHz.Some clever circuit techniques can be used to extend the smallbandwidth of this design.

In a nut shell, the parasitic capacitances degrade the perfor-mance in resistive feedback topology at higher frequencies.


However, some designers use reactive feedback to improve theperformance at the cost of large Si area.

6.2.2. Reactive feedbackReactive feedback can be achieved by using an RC pair either in

series [114–116] or parallel [117–119] or through series RLC con-figuration [120]. The LNA (0.13 mm CMOS) shown in Fig. 5(b) combines series RC feedback with inductive series and shuntpeaking to achieve large bandwidth (�3.1–10.6 GHz) [114]. Thisdesign attains good NF (2.5 dB at 10.5 GHz) and flat gain (�8 dB).However, the linearity is relatively poor (−4 dBm IIP3).

The LNA (0.18 mm CMOS) shown in Fig. 5(c) uses parallel RCfeedback to achieve broadband operation (3.1–10.6 GHz) andimproved NF of 2.5–4.7 dB [117].The increase in NF at highfrequencies is suppressed through LC network at the drain. Thisdesign also suffers from poor linearity (IIP3 of −8.5 dBm). In[118,119], a 0.4–1 GHz LNA (90 nm LP CMOS) utilizes parallel RCfeedback from output to input for wideband operation. It has NF of�3.5 dB, power consumption of 16.8 mW while gain at 1 GHz is16 dB. On the downside, it shows a poor linearity (IIP3 of −17 dBm)because of the use of MOS decoupling capacitors.

The 3.1–10.6 GHz LNA (0.18 mm CMOS) employs series RLCfeedback to achieve an ultra-wideband noise and power matchingwith minimum components [120]. It exploits positive-negativefeedback for flat gain and miller effect for simultaneous noise andpower matching. This LNA has simulated gain of 8 dB, NFmin of3.5 dB, P1dB of −2.48 dBm. However, the power consumption is18.54 mW.

Reactive feedback can also be achieved through transformers asshown in Fig. 5(d) [121–123]. The LNA (0.13 mm CMOS) employstransformer feedback and achieves low NF (2.570.43 dB) andstable gain in 3.1–10.6 GHz band [121]. The chip area is large butcurrent reuse renders reasonable power consumption of 9 mW. Onthe downside, the low power consumption renders poor linearityof −8.5 dBm.

6.3. Common gate (CG)

The CG provides perfect input impedance matching to 50 Ωthrough the resistance looking into its source [34] i.e.:

Zin ¼ 1=ðgm þ gmbÞ ð4Þwhere gm and gmb refer to the transconductance of the transistor.This topology has the inherent potential to achieve widebandinput matching but the major drawbacks are its higher NF, smallgain and high power consumption [63,124]. The NF of a CGtransistor is [63]:

NF ¼ 10 logð 1þ γ=αRSgmÞ ð5ÞWhere γ and α have their usual meanings. The parameter γ in Eq.

(5) is process dependent and not in the designer's hand, therefore, NFcan only be improved by increasing the transconductance whichtrades off with input matching and power consumption. In [125], acomplete receiver design is presented using three pseudo differentiallow noise transconductance amplifiers (65 nm CMOS) instead of aconventional LNA. In each amplifier, wideband operation andimproved IIP3 is achieved through parallel connection of CG transis-tor with the input inverter which results in non-linearity cancella-tion. Simulation results of combined LNAs show good linearity (IIP3of 15 dBm), NFo3 dB and bandwidth 47 GHz. However, the gain isextremely poor (−1 dB).

Generally feedback techniques are incorporated with CG topol-ogy to improve gain and reduce NF as shown in Fig. 6 [47,126,127].In the multiband LNA, the shunt–shunt positive feedback shown in(Fig. 6(a)), relaxes the constraints in selection of gm for theimpedance matching device. However, increasing loop gain in this





RFinRFin

RFout RFout

Output Matching Network

Input MatchingNetwork

Vbias

Vbias

Vbias

Fig. 7. Wideband LNA with filter network in (a) [64] and (b) [140].

RFinRFin RFin -ve feedback

-ve feedback

+ve feedback

+ve feedback

Fig. 6. Conventional CG LNA and low noise techniques employing feedback.


approach reduces the overdrive voltage which degrades thelinearity and NF [47]. In [126], a gm boosting technique utilizingcapacitive cross coupling in a negative feedback fashion is pre-sented (Fig. 6(b)). The technique deliberately uses an invertingamplification in the feedback path to boost effective transconduc-tance. This method reduces NF by the gain of the feedback elementand also improves power consumption. This approach deterioratesthe input and output feed-through and stability of the design.Shown in Fig. 6(c), is a gm boosted wideband design with positive–negative feedback [127]. This approach improves gain and NFwithout sacrificing bandwidth and linearity. It requires half thepower compared to [47] for providing the same power gain. NF inCG topology can also be reduced through dual negative feedbackused in [128] and noise cancellation as used in [59]. Dual negativefeedback approach in [128] optimizes gain, bandwidth, linearityimpedance matching and NF simultaneously. However, the prac-tical implementation of this concept in 0.18 mm CMOS yields abandwidth of 1.05–3.05 GHz only with a small area (0.073 mm2),acceptable gain (16.9 dB) and linearity (–0.7 dBm). The tradeoffbetween noise of the CG amplifier and input impedance matchingis decoupled through the use of parallel CS amplifier in [81,129–133]. LNAs (0.18 mm CMOS) in [81,133] use similar method withinductive series and shunt peaking. This approach offers noisecanceling over a wide bandwidth (3.1–10.6 GHz) while compro-mising power consumption (20 mW), gain (9.7 dB) and linearity(IIP3 of −6.1 dBm). The 0.8–6 GHz CG LNA (90 nm CMOS) achieves18–20 dB of gain with NF of 3–3.5 dB [129]. In [129], (65 nmCMOS), a CS stage accompanies input CG stage in form of noisecanceling circuit. This design achieves total frontend gain and NFof 20.6 dB and �3.4 dB respectively. A (0.2–5.2 GHz) inductorlessLNA (65 nm CMOS) uses similar idea with admittance scaling of CSstage to achieve low NF (o3.5 dB) [131,132]. It features 13–15.6 dBgain and good linearity (IIP340 dBm) but scaling the CS transistorwidth increases power consumption (21 mW).

In references[59,60,69,74,134] different distortion cancellationtechniques are employed to improve the linearity in common gatetopology. In [59], (0.13 mm CMOS) LNA, cancellation of third ordernon-linearity is accomplished through main architecture (whichalso cancels noise) and by removal of second order distortioncomponents from CG stage which contributes to third order nonlinearity. Improved NF of≤2.6 dB and IIP3 of 16 dBm are achievedwhile compromising gain (14.5 dB) and power consumption(17.4 mW). In [74], the LNA (0.13 mm CMOS) uses a non-linearMOS resistor to replicate the non-linear drain current of the mainamplifier which, in turn, partially cancels the second and thirdorder distortion. This approach also cancels some part of linearterms which results in NF degradation. It attains good linearity(IIP3 of 14.1 dBm) with small power consumption (2.62 mW).However, the lower gain (8.6 dB) is also responsible for higherIIP3. The 0.1-1 GHz LNA (90 nm CMOS), feedbacks common modeoutput of two amplifiers (having similar gain but inverted phase)to the input which cancels 2nd order distortion [60]. However, NFdegrades (5 dB). The measured IIP2 is 35 dBm and IIP3 is −1 dBmwhile gain is 10 dB.


In general, CG-LNA topology depicts appreciable widebandbehavior and has a tradeoff between transconductance (gain), NFand power consumption. It has lower linearity and parasitic effectsdegrade input matching at high frequencies [135]. Feedback, noiseand distortion canceling techniques are available in literature forovercoming these limitations.

6.4. Filter LNA

The filter-based topology shown in Fig. 7 embeds the inputimpedance of amplifier in a multi-section reactive network (whichis the filter) and allows it to resonate over the entire bandwidth[104,136,137]. This topology shows good performance while dis-sipating less DC power. LC filter [138], three-section band passChebyshev filter [65], dual RLC filter [139], Miller effect inputmatching filter [140], highpass filter [141], a π-matching LC filter[142] and transformer based input matching network [143] areexamples of such LNAs. The use of LC network is demonstrated in[138] to achieve 6–10 GHz bandwidth with constant gain andgroup delay. This paper does not list further LNA specifications andaims to evaluate the effect of substrate coupling on LCmatched LNAs.

Generally, this topology is implemented with CS with inductivedegeneration stage, it exhibits superior NF and power character-istics besides high gain and good input matching across wholebandwidth [65,144–147]. In the 3.2–4.8 GHz LNA (0.25 mm CMOS),NF (�3.2 dB) is made independent of the transistor width byproperly choosing the source degeneration inductor [145]. Par-tially off-chip LC networks are used at the input and output toachieve wideband impedance matching. This design depicts goodlinearity (IIP3 of 4 dBm) at the cost of gain (7 dB) and powerconsumption (20 mW) [145]. In [144], the LNA (0.18 mm CMOS)offers wideband operation (3.1–10.6 GHz) with low power con-sumption (9.4 mW) using stacked CS stages for current reuse.However, the low consumption is achieved at the cost of linearity(IIP3 of −13 dBm).

In [65], two 3.1–10.6 GHz LNA designs (0.18 μm CMOS) arepresented which require many additional reactive elements asshown in Fig. 7(a). Larger area and higher NF thus results.Contrarily, a 3–5 GHz LNA (0.18 mm CMOS), presented in [140],uses only one inductor at the gate besides a source degenerationinductor as shown in Fig. 7(b). Here, wideband matching isachieved through the exploitation of Miller effect. This approachimproves NF (≤2.3 dB) and reduces the chip area. On the down-side, it is S11≤−10.5 dB for the entire BW and P1dB is −23 dBm.

Another 2.6–10.2 GHz LNA (90 nm CMOS), achieves widebandoperation through deliberate resonance at two different frequen-cies inside the band of interest. This is done through differentcombinations of gate and source inductances, their proper sizingand gate to source capacitances of the input transistor. This novelapproach has NF of 3–7 dB, power consumption of 9 mW and gainof 2.5 dB only [148].





Vbias5

OUT+RBias2

R1

IN+

M3

M1

M2

M4

M5

CC1

RD RBias5

Vbias2

CC2

Vbias3

Vbias4

Fig. 8. Half circuit of differential inductorless wideband LNA [158].


6.5. Distributed low noise amplifier (DA)

The basic structure of a distributed LNA is depicted in Fig. 4(e).Several parallel transistors with transmission lines or inductors areused to achieve extremely wide input matching [124]. Thisarchitecture renders small additive gain and large Si area withhigh power consumption [55,64,124]. The DAs generally offerrelatively flat gain, high IIP3 and inherently poor NF [64,65,149].

The high power consumption in DAs can be reduced byemploying conventional low voltage or current reuse techniquesin DA stages [150,151]. Some other approaches are presented in[64,152]. In [64], a programmable gain (−10 to 8 dB) DA (0.18 mmCMOS) with 9 mW power consumption and IIP3 of 3 dBm isreported. This design compromises bandwidth for low poweroperation. Whereas in [152], a low power DA (90 nm CMOS)employs two distributed amplifiers in a matrix configuration withtapered transmission lines and moderate inversion biasing toreduce the power consumption to only 12.5 mW. This DA achievesmultiplicative gain (15.4 dB), 21 GHz bandwidth but offers poorlinearity (IIP3 of −6 dBm).

The high NF in DAs can be mitigated by incorporating NFimprovement techniques as discussed in [149,153–155]. DA(0.13 mm CMOS) in [149] replaces resistive termination withresistive-inductive network to reduce the noise generated by theterminating resistor, thus achieving an NF of 3.3 dB. The drawbackof this circuit is the use of dual power supply, high powerconsumption (30 mW) and degraded input matching (S11o−7 dB). Another DA (0.18 mm SiGe BiCMOS) employs an additionalinductor in each cascode. This improves bandwidth and decreasesNF to 2.9 dB but linearity reduces to −3.55 dBm [153]. A similaridea is implemented with transmission lines instead of inductorsin [155]. The use of transmission lines severely degrades the noiseperformance (NF of 5.7 dB). In the weighted DA (0.13 mm CMOS),proper selection of transconductance for each stage results inreduced NF (≤4.5 dB), gain of 15 dB and IIP3 of �−3 dBm [154].

Several distributed amplifiers are presented in [55–58].The DA (0.6 mm CMOS) in [55] takes advantage of Metropolisalgorithm to handle the large order interdependent designvariables to achieve optimum performance compared to otherCMOS DA designs. The gain is 5 dB which degrades at higherfrequencies due to the source degenerative feedback. This designhas a large area and its NF seems very high and is not reported.A miniature DA (0.18 mm CMOS) is presented in [156]. It has asimilar gain as in [55] but utilizes multilayered inductors for areasaving (0.08 mm2).

In general, the additive nature of the gain, the need for high Qinductors or transmission lines and high power consumption makeDAs less attractive for compact wideband and portable receivers.Due to their wideband nature, they have vast applications inmedical imaging and high frequency instrumentation [152,157].

VBias2VBias4

M4

M2 IF-R2

7. Our design approach and measured results

The basic concept and motivation of our design approach canbe summarized as:

M6 LO-LO+C1

1.

IN+

M3

M1

M5R1

C2Second Stage ofMerged

Wideband LNA

VBias3

P(2

Inductorless design: As discussed in Section I, the innovation andhigh MIPS requirement in digital processing are driving theCMOS scaling. RFIC designers are forced to use the latesttechnology node for single chip integration and low cost. Recenttechnology nodes do not provide precise resistors and thick layerinductors. Therefore, future LNAs must avoid inductors.

CBW
2.
Fig. 9. Single ended schematic of merged wideband LNA and Mixer [159].

Wideband design: Multiband LNAs use inductors in some formor other. Therefore, wideband LNAs are a better choice forfuture if can be designed without inductors.

lease cite this article as: S. Arshad, et al., Wideband and multiband C013), http://dx.doi.org/10.1016/j.mejo.2013.04.011i

3.
Linearity: In wideband design, the interferers propagated fromantenna terminal get attenuated at the LNA input because of afront-end filter. As a wideband LNA does not have any inbuiltfiltering and requires a flat gain, linearity becomes the mostchallenging issue in its design.
In our first prototype (0.13 mm CMOS), we have designed adifferential wideband inductorless LNA [158]. We break the severetradeoff between input impedance; gain and NF present in con-ventional common gate and resistive shunt series feedback topol-ogies by employing AC-coupled common drain stage (M2 and R1)in feedback as shown in Fig. 8.

This feedback provides wideband input matching and performspartial noise cancellation of correlated noises of all components in itsloop. In the forward path, the common source stage (M1 and M4)and coupling of input signal to the gate of M5 (through CC2) providegain. The reusing of current of M1 and M4 in M5 renders low powerconsumption. This LNA has a power consumption of 25 mW, gain of17 dB, BW of 7 GHz and NF of 2.4 dB at 3 GHz. It is the first reportedLNA with a very small area (0.019 mm2) and comparable perfor-mance with its counterparts using inductors. The downside of thisdesign is relatively poor IIP3 of −4.1 dBm [158].

In second and third prototypes we have proposed a receiverdesign approach that requires a low gain and highly linear LNA toaccommodate strong blockers and maintain high sensitivity at thesame time. In narrowband designs, out of band blockers aresuppressed by passive RF filters. In wideband designs theseblockers reach the LNA and mixer, thus requiring them to managefull blocker power. This requirement can be met using low gainfront-end with high dynamic range ADC.

Cascading wideband LNA with wideband mixer poses a sig-nificant challenge due to parasitic effects and reduces the overallbandwidth. To overcome this drawback we have merged thewideband LNA and Gilbert mixer in second prototype (90 nm






CMOS) as shown in Fig. 9 [159]. The LNA's inverter-like (M1-M4)gain stage also behaves as mixer transconductance stage. Thereuse of bias current of the mixer switching pair (M5–M6) andPMOS transistor (M4) in M1, results in smaller power consump-tion. The 50 Ω wideband input impedance is provided by thefeedback path (M2 and R1). The 3 dB bandwidth of this mergedLNA and mixer is about 5.5 GHz. The measured NF is 7 dB at LOfrequency of 1.5 GHz and IF of 30 MHz. Similarly, measured gain,IIP3 and IIP2 are 5 dB (at 6 GHz), 2.5 dBm and 40 dBm (at 1 GHz)respectively. The power consumption of front-end is 23 mW withsilicon area of only 0.048 mm2 excluding buffers [159].

Vbias

Vbias

C1

C2

M2

M1

L1

L2

Cc1

Cc1

Cc

Mixer

RF+

RF+

Fig. 10. Single ended schematic of wideband common gate LNA and passive mixerfront-end [160].

Table 2Comparison with state−of−the−art published wideband LNAs.

Source CMOS (mm) BW (GHz) S21 (dB) NF (dB) IIP3

TCAS−II 2010[117] 0.18 3.1–10.6 13.9i 2.5−4.7 −8.5JSSC 2007[121] 0.13 3.1�10.6 15.171.4 2.570.43 −8.5JSSC 2005[104] 0.18 2�4.6 9.8 2.3d −7e

JSSC 2004[106] 0.25 0.002−1.6 13.7b �2.4 0MTT−S 2010[128] 0.18 1.05−3.05 16.9b 2.57−2.86i −0.7ISSCC 2009[127] 0.18 0.3−0.92 21b 2c −3.2JSSC 2008[59] 0.13 0.8−2 14.5 o2.6 16

JSSC 2007[81] 0.18 1.2−11.9h 9.7 4.7i −6.2MTT−S 2010[142] 0.09 3.1�10.6 10.4870.2 3.170.16 4MTT−S 2010[139] 0.18 3.1�10.6 11.272.3 3.61�4.68 −12Microelectronics Journal 2008[161]

0.18 5–6 20.5 1.8−2.6 −6.2

JSSE 2006[144] 0.18 3.1−10.6 9.5 5−5.6 −13ISSCC 2006[140] 0.18 3–5c o16 2.2(NFmax) −9

ICACTe 2005[141] 0.18 2.7–9.3 10a 3.3d −0.3JSSC 2004[65] 0.18 2.3–9.2 9.3a 4d −6.7

@6RFIC 2010[152] 0.09 21 15.4i 4.4−6 −6.6

@5ISSCC 2009[154] 0.13 3.1–10.6 15 o4.5 −1.2JSSC 2007[153] 0.18 SiGe 0.1–11 8 2.9 −3.5

JSSC 2006[64] 0.18 0.04–7 8.6i 4.2d +3Design 1 ISSCC 2007[158] 0.13 1−7 17b 2.4 −4.1

f@ 2–6 GHz,a Gmax,b Voltage gain,c 1 dB BW,d NFmin,e @ IF 10 MHz and RF 3 GHz,g IIP3avg not reported (avg. values are read from graph),h 3 dB BW,i average.


In third prototype (Fig. 10), we use the common gate (CG)topology which is inherently wideband and has better noiseperformance when ωo/ωT ratio (ωo is the transistor's operatingfrequency and ωT is transit time frequency) is high [160]. Thecomplementary characteristics of the inverter-like (M1–M2) struc-ture cancel the first and second order derivative of gm in widerange of input voltage, thus, achieving a highly linear operation.The input CG stage is followed by passive ring mixer for highlinearity. L1 and L2 are large off-chip inductors. The measurementresults show SSB NF of 6.25 dB at an LO frequency of 3 GHz and anIF of 10 MHz. The gain is 4.5 dB at 1 GHz with 3 dB bandwidth ofmore than 6 GHz. The +1.5 dBm measured input referred P1dB ofLNA-Mixer pair indicates that this design can tolerate 0 dBmblocker. The IIP3 is +11.73 dBm at an LO frequency of 2 GHz. Itconsumes only 6.2 mW from a 1.1 V supply with an active chiparea of only 0.0856 mm2.

Table 2 shows a comparison of our LNA designs with variousstate-of-the-art wideband LNA designs.

8. Summary and future direction

In this paper, we have presented a categorized overview ofdifferent types of multiband and wideband LNAs published in openliterature. CMOS is the technology of choice for future commercialRFICs due to its unmatched integration capability and extremelylow cost per transistor. Hence, our main focus is on CMOS LNAs.However, the categorization is based on circuit topology instead ofthe technology node used for manufacturing. The main purpose of

(dBm) Powe consumptio(mW)

Topology FOMT FOMC

14.4 Parallel RC FB 0.21 0.14� −5.1 9 CS+reactive FB 1.17 0.63

12.6 CS+series RC FB 0.09g 0.06g

35 R FB+NMOS/PMOS 0.20g 0.14g

12.6 CG+dual negative FB 1.05 0.703.6 Differential CG+C cross coupling 0.64g 0.43g

17.4 CG+noise and distortioncancellation

5.34g 2.90g

20 CG+noise cancellation 0.12g 0.08g

21.6 CS+π input filter 5.59g 2.75g

10.34 CS+RLC input filter 0.13g 0.09g

2 Cascode+inter-stage LC networks 1.83 1.23

9.4 Cascode+input filter 0.02g 0.01g

7.68 CS+miller effect input matchingfilter

0.28g 0.18g

14 Cascode+input HPF 0.86g 0.57g

GHz9 CS+degeneration and input BPF 0.11g 0.07g

GHz12.5 Distributed CS+tapered TX lines 0.30 0.15

5 26 Weighted distributed cascode 1.04 0.565 21.6 Distributed cascode+BW

enhancement0.38 0.26

9 Distributed cascode 1.59g 1.06g

25 Cascode with CD FB 0.57g 0.31g






this review is to draw a snapshot of current state-of-the-art LNAsand to seek potential circuit topologies suitable for future SDR LNAs.The LNAs are one of the major hurdles and their successfulrealization will pave the way to commercial SDR.

The fundamental radio receiver specifications to meet the most ofMobile, LAN, and PAN standards are worked out in [32] as described inSection III. The distribution of these specifications on different blocksof radio receiver chain depends upon the receiver architecture and thenature of duplexing scheme (TDD or FDD). Since 3G standards(WiMAX and LTE) are wideband, use MIMO techniques to combatfading, achieve higher data rates and support both the FDD and TDDmodes, their inclusion puts even tougher requirements on radioreceivers. Moreover, the user expectations are major drivers todetermine upper bound on power consumption and cost metrics.The new portable wireless products cannot be sold in the market iftheir battery backup time is shorter. The same principle rules the costand budgeting paradigm. Thus, future LNAs should have powerconsumption, gain and NF close to what is offered by state-of-the-art narrowband LNA designs. The bandwidth should be more than6 GHz to cover all the deployed commercial and upcoming 3Gstandards. The design should be scalable with standard digital CMOSand should not use any special enhancement to facilitate on-chipinductors.

A simple link budget spreadsheet of today's majority standardsshows that linearity is the most exigent requirement as posed bythe legacy of GSM standard (0 dBm blocker). Therefore, P1dB ofhigher than 0 dBm has proved to be the toughest requirement onmultistandard LNAs [76]. None of the LNAs reported so far meetthe requirements of NF, gain, impedance matching, power con-sumption and linearity simultaneously. There are several reporteddesigns which come close to achieving these specifications exceptfor linearity (P1dB, IIP2, and IIP3) requirements. If we take a closerlook, we realize that the linearity requirements (P1dB40 dBm)along with gain 410 dB cannot be met in 50 Ω impedancematched circuits implemented in nanometer CMOS. Thislinearity-gain tradeoff becomes more stringent as the powersupply scales down in latest technology nodes. As the P1dB orIIP3 cannot exceed supply voltage, hence better linearity withrecent nodes is a major limitation in existing LNA designs.

A similar problem exists in the design of a mixer and itsfollowing stages in a wideband receiver. Therefore, a paradigmshift in the radio receiver design is needed both at the circuit leveland standard level. At the circuit level, one possibility is the use ofcurrent amplification in the LNAs instead of voltage (third proto-type LNA in Section VI), as the currents do not have uppersaturation limit. At standard level, committees involved in draftingthe specifications of communication standards should more clo-sely reflect state-of-the-art circuit capabilities so that the futuredesigns can be improved accordingly.

Acknowledgment

The authors would like to acknowledge the assistance andcontribution of Prof. Christer Svensson, Prof. Jerzy Dabrowski, Dr.Stefan Andersson, Prof. Atila Alvandpour, and Dr. Naveed Ahsan forthe designs presented in Section VI of the paper. Financial supportfrom Government of Oman to NED University is also highlyacknowledged.

References

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[2] C. Svensson, J.J. Wikner, Power consumption of analog circuits: a tutorial,Analog Integrated Circuits and Signal Processing 65 (2010) 171–184.


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Wideband and multiband CMOS LNAs: State-of-the-art and future prospects

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