To be presented at SPIE’s Photonics Europe, conference 5455 - MEMS, MOEMS, and Micromachining, Strasbourg, France, 26-30 April 2004

Designing Manufacturable MEMS in CMOS Compatible Processes - Methodology and Case Studies

Gerold Schröpfer*1, Mark McNie2, Mark da Silva3, Rhodri Davies2,

Alexandra Rickard2, François-Xavier Musalem1

1Coventor SARL, 3 Avenue du Québec, 91140 Villebon sur Yvette, France,

2QinetiQ Ltd, St Andrews Road, Malvern, Worcs WR14 3PS, UK, 3Coventor Inc, 625 Mt Auburn St., Cambridge, MA 02138, USA

ABSTRACT

Designing manufacturable MEMS devices requires a strong link between design and process engineers. Establishing systematic design principles through a common CAD framework facilitates this. A methodology for MEMS Design for Manufacturing (DFM) is presented that focuses on solid process and design qualification through systematic parametric modeling and testing, from initial development of specifications to volume manufacturing. This strategy has been applied to two MEMS fabrication processes, including CMOS-compatible SOI micromachining and metal-nitride surface micromachining. Case studies of designed, simulated, fabricated and characterized test structures demonstrate the methodology and benefits of the outlined DFM approach - including extraction of material properties and process capabilities enabling a prediction of fabricated device performance distribution. The overall result is a MEMS product design framework that incorporates a top-down design methodology with parametric re-usable libraries of MEMS, IC and relevant system components capable of allowing to design within a specific process (via a process design kit) to enable virtual manufacturing. Keywords: MEMS, Micromachining, Design for Manufacturing, CAD, CMOS-compatible, Process Design Kits, EDA

1. INTRODUCTION To date only few MEMS-based products have crossed the threshold of prototype volumes into large-scale volume production. Examples of these products include piezoresistive pressure sensors form SensoNor or Motorola, inertial sensors from Analog Device’s and Bosch and mirrors from Texas Instruments. Each of these successful product development efforts lasted in average between 4-15 years from concept to final volume production and market insertion. A significant time-consuming factor during MEMS development is the persistence of a “traditional” manufacturing approach [1]. Using a “build and test” approach, inherent in such a “traditional” approach, leads to the fact that engineering of the product for volume manufacturing will take much longer time than anticipated. Other important factors that need to be addressed are the novelty of MEMS technology, the lack of adequate design tools, reliability, and the separate engineering of MEMS device, electronic & packaging. In addition there is a lack of “standard” process flows and a corresponding lack of reliable material properties, insufficient understanding of processing effects on materials, and process variabilities. It is possible that there may never be “standard processes” in the IC sense. However, the methods of characterising a process and it’s associated material properties can be standardized and be a significant part of a Design for Manufacturing (DFM) methodology [2]. The development of a robust MEMS DFM strategy is enabled by three capabilities that allow so called concurrent engineering of MEMS devices:

i) Test structures with corresponding models and measurement setups that allow the extraction of material properties and determine process capabilities

ii) Software capable of incorporating these materials and process specific variables and statistical data into the design and simulation stream

and iii) Stable processes proven for various common classes of MEMS devices supported by test structures that are dedicated to manufacturing analysis and yield improvement.

In the first part of this paper, we suggest and discuss a DFM strategy for MEMS product design that considers these three capabilities and which is grounded in top-down design methodology and concurrent engineering practices. In the second part of this paper, the presented DFM methodology is applied to a set of CMOS compatible MEMS processes.

* gerold.schropfer@coventor.com; phone +33 (0)1 69 29 84 85, fax +33 (0)1 69 29 84 88 ; www.coventor.com

2. MEMS DESIGN FOR MANUFACTURING (DFM) METHODOLOGY 2.1 DFM Overview Design for Manufacturing is an approach that considers manufacturability during the design process [1, 3, 4]. Broadly, DFM includes organisational changes, systematic design principles and a common CAD methodology and framework for evaluating product designs. Readers might refer to [5] for details of organisational changes and generic systematic design principles. In this article, we will concentrate on MEMS design enabled by a common CAD methodology and framework for evaluation of MEMS product designs. The fundamental activities of MEMS development may be broadly divided into “design” and “manufacturing”. However, it is important, to further consider several overlapping phases that flow together as follows:

(i) Technical Specifications Development – necessary starting point of all product development activity (ii) Conceptual Design Phase – Initial design activity (iii) Detailed Design Phase – Virtual Manufacturing and Design Verification. (iv) Manufacturing Phase - Begins almost as early as (ii) if non-standard processes are needed, and lasts through to

volume production. Manufacturability should be imbedded in a MEMS CAD framework to continuously consider manufacturing constraints of phase (iv) during the different design phases (ii, iii). The process of developing a technical specification for the product necessarily begins with a clear determination of the needs of the customer. It is important that the customer requirements document maintain the original intent of the customer and is not overly influenced by perceptions of the engineering teams. The next and perhaps most important step is to convert these requirements into engineering requirements and technical specifications. Once the technical specifications are available the Conceptual Design Phase can begin. 2.2 Conceptual Design Phase It is very important for the success of the product development that many design concepts are developed and evaluated simultaneously so as to offer enough choices for a successful product. The key to developing several viable concepts is the ability to create and evaluate concepts rapidly. In the IC industry this is routinely done [6] through the availability of parameterised component libraries and process design kits that are available for reuse. In the MEMS industry this translates to making available libraries of parameterised component elements that designers can then piece together to create more complex designs. This adheres to a fundamental DFM principle that argues for the use of standard components to save time. Libraries of MEMS components [7-8] based on behavioral models are today available for MEMS designers to do exactly what’s mentioned above. Examples include libraries for simulating the electromechanical, RF, fluidic, magnetic, optical or other physical domains. Each element of the library is essentially an analytical or semi-analytical macro-model that captures the behavior of the element accurately over all possible displacements of the element. All parameters of the element macro-model are available to the designers as variables to be defined and set. So, for example, the non-linear beam element model is the model of an Euler beam, where parameters such as length, thickness, width, as well as material properties such as Young’s modulus, Poisson’s ratio, residual stress and/or stress gradient and damping, are all available variables. MEMS devices can sustain mechanical deformations in 3D space (i.e. 6 degrees of freedom or DOFs: 3 translational – x, y, z; and 3 rotational - rx, ry and rz) and so each component model necessarily has 6DOFs. A schematic model assembled from parameterized library components immediately enables very rapid and accurate characterisation of the behaviour of a specific conceptual design [7-10]. This approach has two significant further advantages. The first, is the ability to be able to set process constraints. A process design kit (re-usable IP component within an organisation) is built into the conceptual design phase through process constraints on certain parameters. For instance, parameters such as layer thickness, Young’s modulus, Poisson’s ratio and stress gradient may be well defined within the tolerances of the specific manufacturing unit. The process design kit would automatically set these design constraints for the designer allowing other parameters to be varied during the evaluation of conceptual designs. This certainly influences the product development process substantially as only those designs that can be manufactured within the process are considered. The second major advantage is the ability to include the system level ASIC and physics design during the evaluation of the conceptual designs. Each conceptual design can be hierarchically contained within a schematic of the entire system that is available to the designer as re-usable blocks in the library. By using available circuit components, such as transistors and passives, it is possible for the product design group to create virtual “test” beds for the product within a single environment. The enormous advantage of this is in providing immediate feedback as to the viability of certain concepts over others. This can literally save years of extra effort by further filtering the set of available design concepts to only those that meet the customer requirement. Besides the IC components, designers may add the relevant physics pertinent to the application, such as RF

transmission lines or electromagnetic (EM) coupling. The conceptual design phase rapidly proceeds to the point where a few concepts are available to the design team for further evaluation during the next detailed design phase. 2.3 Detailed Design Phase During this phase detailed engineering analysis of the selected design concepts is performed. The key steps of this phase involve applying Design of Experiments (DOE) to define the simulation space and then using a variety of analysis methods such as analytical, finite element modelling (FEM), boundary element modelling (BEM) or macro-modeling to perform optimization studies, tolerance design, statistical design as well as incorporating precise process-related design rules and guidelines to create manufacturable designs. The schematic models created earlier are again useful as re-usable models, in this crucial step. The parametric models enable identification of critical parts of a design through sensitivity analysis. The ability to perform these types of analyses rapidly, dramatically cuts down the time it takes to reduce the design space to a few “good” conceptual designs for further verification, using more traditional analysis techniques such as FEM, BEM or coupled methods. Once the design has been “centered”, and critical parameter tolerances “cornered”, with respect to the variables of interest, the design group performs detailed analysis involving more traditional field solvers that simulate the entire (or parts of interest) device to provide additional details of the behavior of the design or to study effects not captured at the schematic level. In the top-down methodology being discussed, it is significant time saved if the design tools are capable of porting the conceptual design schematics directly into a layout tool, since they contain all the information pertinent to the design already. From the 2-D layout (for example, in GDSII format), 3D simulation models can be automatically generated provided that the process information is incorporated into the CAD framework [10]. The availability of various kinds of physics solvers to simulate electrostatics, mechanics, coupled electromechanics, magnetics, electro-thermal effects, fluidic and fluid–structure-coupling effects is a vital part of the CAD framework necessary for successful completion of the detailed design phase. Lastly, a statistical Monte Carlo (MC) analysis (at the schematic level) environment to support "virtual manufacturing" and "virtual diagnostic test" that enables the designer to verify manufacturability in the presence of real-world component variations and to assess tolerance specifications, in order to reduce production costs is essential (example see Figure 1). Since these simulations are typically performed utilising parametric components, the simulation times are rapid enough to prove extremely beneficial. Equivalent analysis performed either at the FEM level or by actually fabricating parts, would take inordinately much longer and would require constant supervision by engineers at critical junctures (i.e. re-meshing of models for certain ranges of parameters) or additional material and resource costs respectively. The ability to gain insight into the sources of manufacturing performance variation without actually fabricating devices is extremely cost effective and efficient and common in the IC industry (where a single fab run is typical). Component tolerances and statistical distributions may be used to randomly vary the MEMS system design (and circuit) parameters and random variables over multiple (repetitive) simulations, which effectively simulates real manufacturing process steps. Obviously, this type of analysis is only valuable when both the design and process engineering groups collaborate and share data applicable to the product, such as process tolerances and design rule violations.

Figure 1: Virtual manufacturing analysisThe histogram shows the statistical distribution of pull-in vol

Voltage / V

Number

Voltage / V

Run

of a MEMS variable capacitor (see also paragraph 3). tage (500 simulation runs) based on some selected material tolerances.

2.4 Manufacturing Phase The design group’s activities should not occur in isolation. The input of various groups is critical to success. Concurrently with the initiation of the design group’s activities, the process group begins to create a Manufacturing Specification. This specification contains three major components:

(i) Develop Process Requirements – identifying critical process characteristics, such as wall verticality or surface roughness

(ii) Identify and Evaluate Existing Processes. There are three choices with increasing risk and cost. a) use a standard process, b) use a standard process with minor modifications, and c) develop a new process.

(iii) Packaging Requirements – it is vital for product success that packaging options available be assessed and preliminary development of the packaging specification be initiated simultaneously with MEMS design.

In a company that has already available well characterised “process flows”, the inclination to use a standard process is quite strong as it is lower cost. However, in some cases, the product design itself might necessitate modifications to the existing process, and in some cases, an entirely new process flow may be necessary e.g. developing an SOI process for optical devices rather than using an established polysilicon process. In either case, the manufacturing group’s efforts focus on the capability of specific process steps and actions are taken to characterise the process capability and the material properties. 2.5 Process Capability Independent of the business model adopted, a manufacturing unit that is involved with fabrication either outside or inside the company, necessarily requires adequate process characterisation. In some cases, this implies that short loop experiments that result in test die are almost immediately initiated. An example of just such a test die is shown in the figure below and the benefits of having such die to identify critical process characteristics (e.g. sacrificial layer thickness and line width) impacts all design activity from initial concept development to virtual manufacturing. Process characterisation test die are beginning to be made available from MEMS foundries, as their prior lack of availability was a serious hindrance to accelerated MEMS development. Significant amounts of valuable manufacturing information/data may be obtained from such test die (through measurement) – film thickness, gaps, line-widths and line spacing capabilities, alignment capabilities, and so on. Additionally, it is possible that such die contain some functional-layer checks, such as fixed capacitors and 4-point probe structures that are essential to obtain certain electrical properties of the process. It is this type of information that is incorporated into Design Kits and re-usable process libraries mentioned earlier.

Misregistration structures

ChevronStructures

Contact ViaChains

Meander

OrthogonalStructures

Step Height

4-point probestructures

Capacitors

Electrical BreakdownStructures

4-point probeStructures

Electrostatic Cantilevers

StictionStructures

BucklingStructures

Figure 2: Process Characterisation Test Die (left) and Material Property Characterisation Test Die (right).

2.6 Material Properties Since MEMS devices are essentially mechanical, their design requires that a manufacturing unit also accurately characterise all relevant material properties. Along with process characterisation structures, material property characterisation structures are placed at specific locations on test wafer lots. Many variables, such as wafer size and test structure characteristics, influence placement of test die and the types of structures within each die. For example, it is known that in general the stress in a film layer varies across a wafer and that the larger the wafer diameter, the larger the magnitude of variation observed. A typical material property test die is shown in Figure 2. The specific purpose of having such die is to identify critical material properties, such as Young’s modulus, stress and stress gradient, fracture strength, electrical conductivity, dielectric permittivity, thermal coefficient of expansion and stiction. A sub-set of these structures is typically used to monitor run-run

variations and obtain statistical process data. Other material properties may be of interest to the design group, depending on the specific product application in mind. Since there are very many different types of test structures, discussion of each type is not possible in this article. Instead, we will describe some selected examples in paragraph 3 and 4 of material property test structures. MEMS relevant material properties can be classified roughly into five groups. Depending on the unit process steps involved in defining material layers, the specific material property of interest may be in fact a composite property or a combination of each group. A summary of relevant geometrical parameters and material properties is provided in Table 1.

Geometry Primary Material Properties Reliability Properties Thickness Undercut Line width / Spacing Sidewall profile Step coverage Radii of curvature Voids Minimum feature sizes Misalignments Surface roughness Others

1. Elastic Properties a. Residual (intrinsic) Stress b. Stress Gradients c. Anisotropic Moduli, incl. Temp. Dependence d. Non-linear Elasticity or Plasticity e. Piezoelectric Coefficients f. Others

2. Electrical Properties a. Dielectric Permittivity b. Electrical Conductivity c. Frequency dependent Properties d. Others

3. Thermal Properties a. Anisotropic Coefficients of Thermal Expansion b. Specific Heats, etc. c. Thermal Conductivity d. Others

4. Loss Mechanisms a. Material and Gas Damping b. Contact between Surfaces c. Cavity Pressure and Hermeticity d. Others

5. Failure Mechanisms a. Yield and Fatigue strength b. Delamination / Bond strength c. Creep d. Others

Table 1: List of Material Property and Process Test Structures [2]

In practice a process design kit would contain detailed material property information that has been previously correlated with simulation models of the test structures. The manufacturing phase is broadly divided into 3 major activities, a) process short loops, b) prototype and demonstrator parts and c) precursor and volume production. In each of these sub-phases continuous improvement and refinement of the process must occur to further reduce variability and cost. Iteration between the process and design groups takes place through continuous enhancement of the re-usable libraries of design kits and models. The availability of more or less complete process design kits has to be made available for incorporation into design models throughout the design phase. The process group needs to further characterise the process by establishing process tolerances and quantifying inconsistencies at each process step. These process tolerances can influence a particular design in a significant way later on. Later in this article, we describe case studies that make use of such process design kits. 2.7 Concurrent Design of MEMS, Electronics and Packaging Until recently, MEMS device design, the corresponding integrated or discrete electronic circuits and packaging development was completed by separate teams. As the complexity of MEMS increases, it is becoming increasingly important to design and optimise the coupling between the micromachined elements, the electronic circuits that control them and the constraints due to packaging. The fabrication sensitivities of either the MEMS device, the circuit or the packaging impact the specification of the other. This means that design trade-offs that are necessary to produce a complete sensor system. In the past, designers reduced the micromachined element to a single DOF lumped macro-model, which was given to IC designers for IC design iterations. Such models do not capture enough performance sensitive information, which might lead to repeated prototyping. Recent advances in the integration of sophisticated fully coupled reduced-order models libraries [8,10] with industry leading IC design and manufacturing tools have begun to provide a single CAD environment for the design of both the MEMS element and the IC circuits [11]. Lastly, as part of a DFM approach, packaging of the MEMS chips needs to be considered also in a systematic way. Typically in an organization, package design is handled by a separate group, which gets involved in the design fairly late in the product development cycle. This is quite feasible because of the availability of standard package form factors, sizes and types of packages, which is very different from the situation in MEMS product development where package design is not as straightforward. In MEMS, packaging has been shown to be a very costly oversight. Initiation of the package design early on is necessary so that any unnecessary re-design of the device may be avoided. If it is possible, standard packages should be used.

3. DFM CASE STUDY #1: SURFACE MICROMACHINED VARIABLE CAPACITOR

3.1 CMOS-compatible Metal-Nitride Surface Micromachining Process A two-level metal-nitride surface micromachining process has been developed at QinetiQ [12-15]. The process is different from most customized surface micromachining processes in that the structural layer is not polysilicon. By moving to a metal-nitride structural layer, a low temperature (< 450°C) process results. The process described here is a stand-alone MEMS process but has been used to realise a fully monolithic MEMS solution by post-processing on standard CMOS / BiCMOS wafers from an IC foundry. Figure 3 is a schematic cross-section of the two-level metal-nitride process. A unique metal-nitride sandwich is used as the structural layer with polyimide as the sacrificial layer. This enables an all-dry release process to be used - avoiding stiction-related yield problems associated with wet release processes. The metal-nitride process has been refined over the last 5 years – developing in that time from providing fully constrained structural layers (e.g. membranes) to providing unconstrained structures (e.g. cantilevers). This has involved significant engineering to deliver a repeatable, low stress PECVD nitride layer [12-13] that acts as the dominant mechanical material and a balanced metallization scheme to minimize bimaterial effects due to differential thermal expansion in the structural layer.

Nitride1Metal1b

Metal1aPIQ1Metal0Oxide

Figure 3: Cross-sectional view showing all layers of the metal-nitride process (left) and emulated variable capacitor (right). Si Sub

3.2 Example of Process and Material characterization for Metal Nitride Process: Stress/Strain Metrology Control and engineering of strain and stress within the mechanical layers is common to all MEMS processes and was special focus when developing this metal nitride process. To determine the stress in a mechanical layer, the measurements should be based on a film that mirrors the full process as far a possible (i.e. same thickness, thermal budgets, microstructure, etc.) or at a stage in the process that directly maps to the final film properties. Wafer curvature measurements provide a convenient method to assess the residual stress/strain within a deposited layer. In-plane stress data is sufficient for constrained MEMS elements (e.g. membranes), however, it does not provide the necessary strain gradient information for unconstrained devices (e.g. cantilevers). Specific strain analysis structures are thus required [5,13]. Fixed-free cantilevers (Figure 4) of varying lengths can be employed for out-of-plane strain gradient. Post-release, small tip deflections, are measured using optical techniques, such as high resolution white light interferometry, which allows the extraction of the strain gradient using the corresponding beam model. Figure 4: Positive strain gradient (left) and zero strain gradient (right) in silicon nitride with corresponding white light interferograms

above and equivalent SEM images below.

Where the strain gradient is low, other structures may be used to determine the in-plane residual strain in the film. The commonest of these is are indicator swing beams or bent beam bridges, often with an integrated Vernier scale for additional resolution, whose tip displaces from its initial position by an amount that depends on whether the strain is tensile or compressive in reference beams on either side of the pivot point and the mechanical advantage in the system [14]. Other common structures include arrays of different length fix-fix bridges for compressive strain and of Guckel rings for tensile strain [14]. Strain is directly measured. In order to determine stress, the Young’s modulus of a material needs to be known. There are several techniques to determine Young’s modulus: nano-indentation, vibrating structures and using an AFM tip to deflect structures. Different techniques may give systematically different values. Vibrating structures with electrical or coupled mechanical (e.g. by mounting on a vibrating piezoelectric disc) drive and optical (laser) detection gives a non-contact technique. An example of such a vibrating test structure is given in section 4. The effective Young’s modulus of the metal-nitride structural layer was determined to be 150GPa, whilst it has a low residual in-plane stress (<105MPa) and out-of-plane stress gradient (<20MPa/µm). More details on the material properties of the individual layers and characterization of the metal nitride process can be found in references [14-15] 3.3 Conceptual Design Phase of Variable Capacitor A schematic-driven top-down design process based on behavioural-level modelling described earlier is used in the conceptual design phase. The first step is to create a device schematic from the library of MEMS-specific parametric components as in Figure 5. For example, one beam component includes the parameters for length and width, cross section, tolerances, top and bottom electrodes, stress, stress gradients etc. Using CoventorWare™, the physical device properties are directly imported from the associated materials properties database and the emulated process flow. The device behaviour can be simulated rapidly and accurately using the underlying behavioural models. The four folded suspension arms are each modelled with four connected beams, while the variable capacitor suspended plate and sensing electrode is represented by a rigid plate and an electrode symbol.

Figure 5: Schematic of a variable capacitor. Each “component” in the schematic model corresponds to a part of the conceptual design (left). Image of the on CMOS fabricated device (right).

The main resonant frequency of interest can be calculated by performing a small signal AC analysis in the range of 1Hz to 100kHz. In the case of this device, the first resonance frequency is driving the middle plate out-of-plane, is significantly lower than other, higher order, modes and is approximately 80kHz for nominal layer properties. The pull-in voltage of a structure is defined as the voltage at which the structure under the action of electrostatic and mechanical forces is pulled into contact with the electrostatic actuation electrode. The result from a pull-in simulation is a displacement graph as a function of applied voltage. Figure 6 shows that for the presented case the predicted pull-in voltage is around 7V. The change of the capacitor gap between fixed and movable electrode as a result of the applied voltage close to pull-in (about 350nm displacement), corresponds to an increase in capacitance of about 43fF from 90fF at zero bias to 133fF.

C )

Figure 6: Pull-in analysis using nominal material values. Displacement (left) and capacita

3.4 Detailed Design and Manufacturing Phase of Variable Capacitor Tolerances of the layer properties such like thickness, stress and stress gradpull-in voltages for a number of devices. Based on the material and process charaanalysis (Monte-Carlo simulation) to calculate the distribution of the pull-in vomaterial and process characteristics. We have fabricated a number of devices and measured their pull-in voltage measurement results for 20 devices are compared to the performed Monte-CaAverage values as well as 3 sigma deviations are presented for both measuremtolerance is a combination of the error in the nominal thickness and the process uniin the nominal thickness would appear systematic and hence account for the dmeasured data compared with the simulated data.

Figure 7: Measured pull-in voltages for 20 suspended plate variable capacitors in c Manufacturing sequences and process steps can be implemented into statautomatically generate a 3D solid model for subsequent FEM simulation, e.g. dam3D visualization of the MEMS structure (see Figure 3, right) supports the visuaGDSII mask and contributes to lower the risk of design errors and design rule viola

Voltage (V)

apacitance (F

Voltage (V)

nce (right) versus applied voltage.

ients will give in practice a range of cterisation we performed a statistical ltage in function of the variation of

to be between 6.8 and 7.8 volts. The rlo analysis are shown in Figure 7. ents and simulations. The thickness formity. Thus in a given batch, a shift ifference in the mean value of the

omparison to simulation results

e of the art MEMS design tools to ping analysis. In addition a detailed l verification before tape-out of the tions.

4. DFM CASE STUDY #2: SOI MICROMACHINED COMB-DRIVE RESONATOR 4.1 DRIE-based SOI Micromachining Process The second process is a SOI micromachining process that uses patterning and deep reactive ion etching (DRIE) of an SOI layer to deliver a single free-standing crystalline silicon layer in bonded SOI wafers [16-19]. Figure 8 is a schematic cross-section of an SOI wafer after release. The structural elements are formed in the silicon device layer. This typically has significantly better uniformity than a deposited layer with a thickness tolerance better than ±2%. This is supported on an insulating buried thermal oxide (BOX) layer on a silicon handle. The layers have been fusion bonded during the SOI manufacture. Thus, the BOX may act as both a mechanical anchor to the handle and as the sacrificial layer. This process has much deeper features and the ability to realise higher aspect ratio structures (< 20:1 depth: width) than a conventional surface micromachining process. The geometry is not constrained by the crystal planes of the device layer as in conventional bulk micromachining. Since its inception at QinetiQ in 1997, the SOI micromachining process has benefited from significant engineering to develop well-characterised DRIE processes [17-18] with vertical sidewalls and controlled notching at the buried oxide interface, in establishing formal design rules and to improve release process yield.

BOX anchor Movable element

Device Silicon

Buried oxide (BOX)

Handle (Silicon)

Metal1

Figure 8: Cross-section showing layers in a SOI wafer after release (not to scale) 4.2 Comb-drive Resonator Test structure for Material and Process Characterisation The fundamental resonant frequency of a comb-drive test structure can be used for assessing process uniformity from chip to chip, wafer to wafer, batch to batch [20, 21]. A drift in processing conditions, mechanical properties, measuring conditions such as ambient pressure and applied voltage levels, and/or device geometry can all affect its resonant frequency and in severe cases, affect the shape of the resonant mode. The resonator is commonly actuated into lateral resonance by an electrostatic drive between one set of the fixed fingers and the resonator itself. This resonant mode is easy to measure, to understand analytically, and to simulate. Although out-of-plane forces can simultaneously drive the comb-drive into either torsional or vertical out-of-plane modes, squeezed-film damping effects often suppress this excitation. Design variations of this test structure can be used for quantifying sidewall angle and lateral mask undercut, that can vary from chip to chip.

The procedure for property extraction is as follows [2, 21]:

(i) The compact model is used to predict the resonant frequency of a design for selected values of the size of the resonator, moduli and density. The design is selected such that the frequency falls in an experimentally measurable range.

(ii) A range of test structure designs of different sizes are implemented in the mask set, typically in one or two test cells. The test cells are typically placed with multiple positions in the wafer layout.

(iii) After fabrication, the resonant frequencies for the structures are measured. The measurement techniques utilised in this case have been used extensively in the past and consists of a circuit (with the resonator), a function generator in series with a DC bias and an optical microscope. An alternative is a fully electrical-in, electrical-out oscillator set-up with the resonator addressed as a one-port or a two-port resonator.

(iv) The model may be adjusted to account for other design variations such as lengths, anchor sizes etc. (v) The measurements and model yield similar curves for the frequency vs. design width. The model predictions

are based on fitted values of the offset and sidewall angle. Of each of these the average value and their variation is determined.

a) b) c) Figure 9: Mask layout of a series of comb-drive resonators (a), generated solid model of on device (b) and corresponding SEM image

of the fabricated resonator (c)

4.3 Conceptual Design Phase of Comb-Drive Resonator As outlined before, the conceptual design phases is mostly based on behavioural-level modelling. The first step is to create a device schematic from the library of MEMS-specific parametric components. Properties are automatically imported from the associated process dependent installed materials properties database and process flow. The device behaviour can be simulated rapidly and accurately using the underlying behavioural models. The four folded suspension arms are each modelled with four connected beams, while the central portion of the resonator is modelled by a rigid plate and the comb drive electrodes are represented by a specific electrostatic comb-drive model (Figure 10).

Beam Element and it’s generic cross-section

Figure 10: Schematic of the resonator example including mechanical resonator structure and comb-drive electrodes. The first resonant frequency drives the beams in-plane (y-direction) and is significantly lower than other, higher order, modes. It can be calculated rapidly by performing a small signal AC analysis; as it can be seen in Figure 11 the resonant frequency is approximately 20kHz for 3.2µm wide suspension beams.

Figure 11 Calculation of resonance frequency spectrum showing the lateral and torsional mode.

4.4 Detailed Design Phase of Comb-Drive Resonator The sensitivity of the resonant frequencies to etched sidewall profiles is exploited to quantify manufactured microscopic variations in sidewall geometry. Main geometric parameters are sidewall angle (see Figure 10) and lateral undercut, also called edge bias or offset. For the resonator in Figure 9, the shifts in resonant frequencies due to example manufacturing variations in sidewall angle and undercut values are shown in Figure 12. Varying the lateral undercut from 0µm to 0.9µm results in a 1st mode frequency shift from 12.2kHz to 26.9kHz. Similarly, varying the sidewall verticality from 90 to 88° results in a shift from 20-23kHz. Design analysis using parameterised behavioural modelling does not only allow the estimation of device performance and manufacturing yield in function of process variation, but also to validate measured data. Moreover, the benefit of correlation between simulated and measured data is primarily for specific property extraction i.e. in the resonator case it is easier to measure resonant frequency that it is to measure Young modulus. Further work in progress has fabricated a variety of these structures in the 50µm SOI and has evaluated a nominal process undercut of 0.35µm ± 0.05µm with a sidewall verticality of 89.5 +/- 1°. These devices are being packaged for resonant tests to enable direct comparison with modelling predictions.

a)

b) c)

Frequency (Hz)

Fig) )

Side Wall Angle (degrees

ure 12: Graphics obtained by simulations showing the sensitivity ofto process variation in sidewall angle (a, b) and lateral underc

Mask undercut (m

the frequency ut (c).

5. CONCLUSIONS A DFM strategy that links the design and process groups by establishing systematic design principles through a common CAD framework has been introduced. For low cost, efficient volume manufacture of MEMS products, both the design and process groups need to adopt a top-design methodology for design with parametric re-usable libraries of MEMS components. It incorporates details of the process through qualified and re-usable design kits containing both process characterisation and material properties. Having good materials properties and process information available is important in enabling effective design and maximising the probability of first pass success - reducing development cost and time. This DFM methodology has been applied to two families of MEMS manufacturing processes (metal-nitride surface and SOI micromachining) available through INTEGRAM, part of the EC foundry access program, EUROPRACTICE. Looking forward, the success of any DFM approach for MEMS will be measured by the ability to select the best design option. This will result in higher yield, and ramp-up to volume production in considerable shorter time scales than traditionally seen in the MEMS industry. One route to achieve this is to explore and exploit the many design possibilities quickly and accurately by leveraging proven electronic design automation (EDA) methodologies.

ACKNOWLEDGEMENT

This work was partly supported by the EC IST EUROPRACTICE programme, INTEGRAM (Web: www.QinetiQ.com/Europractice; www.coventor.com/partners/international/qinetiq_kits; www.europractice.com).

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