Optimized design of a back-to-back NPC converter to be used as interface for renewable energies

1November, 2005 IECON 2005

Optimized design of a back-to-back NPC converter to be used as interface of

renewable energiesEmilio J. Bueno1), Santiago Cobreces2), Francisco J. Rodríguez3),

Álvaro Hernández4), Felipe Espinosa5), Raúl Mateos6), Juan C. García7), Félix López8)

1,2,3,4,5,6,7) Department of Electronics, Alcalá University 8) SEDECAL CONTROL

28871 Alcalá de Henares (Madrid) SPAIN 28110 Algete (Madrid) SPAIN

[email protected] [email protected]

mailto:[email protected]



ContentsContents

1. Introduction.

2. Power Electronics System.

3. Control Electronics System.

4. Practical results.

5. Summary.


Disturbances …

Problems to solve in the connection of Problems to solve in the connection of VSCsVSCs to the grid to the grid (1/2)(1/2)

Distribution line

Motor VSC1 VSC23*L13*L2

3*Co

CDC

P

N

Line impedance

ger

from the converter towards the grid:PWM commutations. Can be reduced using a LCL-filter and a mutilevel converter.Temporal drifts of the filter components.Inductances saturation.

from the grid towards the converter:Unknown line impedance (weak grid).Line voltage harmonics.Permanent unbalanced line voltages. Temporal unbalanced line voltages (dips).


““CONDORCONDOR”” projectproject (1/2) (1/2)

CONDOR: “Double converter based on multilevel inverters designed for recovering energy and minimizing electromagnetic emissions”.Financed by the Spanish Science and Technology Ministry (DPI2002-04555-C04).Duration: December, 2002 – December, 2005.Researching groups: University of Alcalá (Coordinator), University of Carlos III, University of Valencia and Institute for Electrical Technology of Valencia.Collaborating companies: SEDECAL CONTROL.

N

nAC

Motor

VSC1 VSC2

Sa2

Sa1

Sa2

Sa1

Sb2

Sb1

Sb2

Sb1

Sc2

Sc1

Sc2

Sa2

Sa1

Sa2

Sa1

Sb2

Sb1

Sb2

Sb1

Sc2

Sc1

Sc2

Sc1

3*L13*L2

3*Co

CDC2

NP

P

CDC1

Da2

Da1

Db2

Db1

Dc2

Dc1

Da2

Da1

Db2

Db1

Dc2

Dc1

ea

eb

ec

PCC

Sc1


““CONDORCONDOR”” projectproject (2/2)(2/2)

AC motor

VSC1 VSC23*L13*L2

3*Co

CDC2NP

P

N

CDC1

ea

eb

ec

PCC

n

Auxiliar breaker

Mainbreaker

Auxiliar rectifier

Power Electronics System

ADCsMeasurements ofgrid filter variables

ADCsMeasurements of DC-bus

variables

ADCsMeasurements of motor

variables

PWM VSC 1 PWM VSC 2FPGA SPARTAN 2E

DSP TMS6713VSC 1 Control VSC 2 Control

Communication cardInterface card between the CoprocessorModule – Power Electronics System

Coprocessor Module

References

Control Electronics System

References


ObjectivesObjectives

This work presents the construction of the Power Electronics System, the converter limitations to compensate unbalanced dips, and the designs of grid filter components and DC-bus capacitors.

In this work the grid filter is the LCL and the analytical equations for the components are obtained to verify the ICE 61000-3-4 standard.

As for the DC-bus capacitors, the analytical equations for the ripples in uDC due to iDC and iNP are obtained. From these equations, the DC-bus capacitors are calculated.

With respect to the Control Electronics System, the chosen structure and the task distribution between the system processors are presented.


ContentsContents

1. Introduction.




5. Summary.


Power electronics specifications and assemblyPower electronics specifications and assembly

Specifications of the utility grid and the converter


Converter limitations to compensate unbalanced dipsConverter limitations to compensate unbalanced dips

The maximum peak phase current to compensate the unbalanced voltage dips and with zero phase jump can be calculated approximately as:

( )

dqndqp

g

ee

Si rr

−≈ 0

max 32ˆ

The system must be oversized to compensate voltage dips to nominal power. The elements that limit this current are mainly the grid filter inductances and the IGBT’s.

i (A)

NBA (Weber·turn)

0.124891

249.6382

-0.124891

-249.6382

L1

0.053172

212.688

-0.053172

-212.688

L2

II

I

II

II

I

II

NBA (Weber·turn)

i (A)

If the excess energy is not stored or dissipated the DC-bus voltage increases. The elements that determine the DC-bus voltage limitations are the IGBTs (maximum direct collector emitter voltage) and the DC-bus capacitors (nominal voltage).


Grid filter designGrid filter design

Filter limitationsResonance frequency. 210 0

SWbase

ωωω ≤≤

Inductance. The total value of the inductances should not be bigger than 10% of Lbase.

Capacitor. i1 in function of Co is: ( ) ( )222

21

221 gobase eCiiii

rrrrrω+=Δ+≈

0 2 4 6 8 10144.2

144.4

144.6

144.8

145

145.2

% de Cbase

Cur

rent

(A) I1n

I2n

The design expressions are

Co is the 5% of Cbase.

21 2LL =

nbaseo

base

baseobaseo ICU

CCL

34

2

222223332006.0334

3334

3ωωω ⋅

+⎟⎟⎠

⎞⎜⎜⎝

⎛+≥

Chosen values are

L1=0.5mH/175Arms.

L2=0.25mH/150Arms.

Co=100μF/400Vrms.


Calculation of the DCCalculation of the DC--bus capacitorsbus capacitors

uDC

vN = uDC/2 + ΔvN

vP = uDC/2 + ΔvP

iNPR

CP= 2CDC

iP

iN

CN= 2CDC

iNPI NP

Simplified diagram of a back-to-back converter based on two NPC’s

Ripple due to iDC

DCDC

SWSW

DC

DCiDC

iNiP CuSTT

Ciu

vv DC

DCDC 4221

2==

Δ=Δ=Δ

0 10 20 30 40 50 60 70 80 90 1000

100

200

300

400

500

600

700

800

900

1000

u DC

(V)

mf

Main ripple due to iNP

Main ripple due to iDC DC

baseNP

P

baseNP

i

NPiNiP C

TiCTiv

vvNP

NPNP

ˆ

121ˆ

61

2 ππ==

Δ=Δ=Δ

Ripple due to iNP


ContentsContents

1. Introduction.




5. Summary.


Control electronics system (1/3)Control electronics system (1/3)

AC motor

VSC1 3*L1 3*L2

3*Co

CDC2 NP

P

N

PCC

CDC1

uDC meas. NP Voltage Balancing

Controller

uDC

controller

)(kuDC

)(kuDC∗

Current controller

)(kid∗

)(kiq∗

)(* kur Grid

current meas.

Grid voltages meas. SPLL

( ) ( ) ( )tititi cgbgag ,, ( ) ( ) ( )tetete cPCCbPCCaPCC ,,

)(kig

r( )kek g

r),(1θ

Control of VSC connected to the grid Control of VSC connected to the AC machine

iDC1 iDC2 Distribution line

High level controller

References from the grid managing

PWM generator

)(* kur

12 pulses

Machine measurements

( )trω

Current controller

Machine controller

)(ki ∗r

)(kr∗ω)(kd

∗λ

( )kki rθ),(r ( )krω

( ) ( ) ( )tititi cba ,,

Turbine controller

( )kPw

PWM generator

12 pulses



Control Electronics System

ADCsMeasurements of grid filter variables

ADCsMeasurements of DC-

bus variables

ADCsMeasurements of motor variables

PWM VSC 1 PWM VSC 2FPGA SPARTAN 2E

DSP TMS6713VSC 1 Control VSC 2 Control

Communication cardInterface card between the Coprocessor Module – Power

Electronics System Coprocessor Module

References References


ContentsContents

1. Introduction.




5. Summary.


““CONDORCONDOR”” projectproject (2/2) (2/2)


Some converter waveformsSome converter waveforms

VSC1 working as non controlled rectifier and VCS2 driving to induction machine

0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.05-10

-5

0

5

10

i A(A

)

0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.05

-500

0

500

time(s)

v AB(V

)

0 0.01 0.02 0.03 0.04 0.05-1

-0.5

0

0.5

1

time(s)

uDCp (V)

uDCn (V)

0 100 200 300 400 500 600 700

0 .050 .1

0 .150 .2

0 .25

frequency in H z

Har

mon

ic A

mpl

itude

D isc re te trans fo rm o f udcp

Ripple due to iNP Ripple due to iDC


ControllerController programmingprogramming

Areas CodeSize

Count Incl. Total

Incl. Max.

Incl. Min.

Inc. Aver.

main() 184 1 441572 0 0 441572

init_system() 328 1 413848 0 0 413848

c_int(5) 472 55 397135 7310 7112 7220

acquisition_data() 1324 55 121487 2230 2196 2208

reference_PWM() 780 55 40578 754 607 737

spll_pi() 720 55 42517 778 772 773

dsc() 1440 55 50961 983 924 926

currentcontroller() 3648 55 107030 2005 1845 1946

dcbuscontroller() 548 55 13864 256 252 252

c_int(4) 220 1 13937 0 0 13937

system_protection() 144 1 7005 7005 7005 7005

Data acquisition

Startmain() and init_system()

t(k)=k·TS=k·200μsNo

Output controllerreference_PWM()

PI SPLLspll_pi()

DSCdsc()

Current controllercurrentcontroller()

DC_bus controllerdcbuscontroller()

Any fault?

System protectionsystem_protection()

Stop

Any hardware fault?

Yes → c_int(4)Yes

Yes → c_int(5)

No

+

+acquisition_data()

c_int(5) Control algorithm

TMS320C6713 DSP is operating at 225MHz.Cycle clock is 4.44ns.Sampling time is 200μsThe execution average time of the Control algorithm is 32μs.


ContentsContents

1. Introduction.




5. Summary.


SummarySummary

A back-to-back NPC three-level converter of 100KVA has been designed, validated by

simulation and tested in a real converter.

In the “Power Electronics System”:

(1) the converter limitations to compensate voltage dips have been analysed;

(2) a method for designing the grid filter components has been proposed; and

(3) the factors that determine the DC-bus capacitor values have been analysed.

With respect to the “Control Electronics System”, the chosen structure and the task

distribution between the two processors have been presented.


Thank you for your attention!!!

Emilio J. Bueno1), Santiago Cobreces2), Francisco J. Rodríguez3), Álvaro Hernández4), Felipe Espinosa5), Raúl Mateos6),

Juan C. García7), Félix López8)

1,2,3,4,5,6,7) Department of Electronics, Alcalá University 8) SEDECAL CONTROL

28871 Alcalá de Henares (Madrid) SPAIN 28110 Algete (Madrid) SPAIN

[email protected] [email protected]

Acknowledgment:This work has been financed by the Spanish administration (CICYT: DPI2002-04555-C04-04).



Optimized design of a back-to-back NPC converter to be used as interface for renewable energies

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