Superlattices and Microstructures 47 (2010) 779–794

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Superlattices and Microstructures

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Microwave performance enhancement in Double andSingle Gate HEMT with channel thickness variationRitesh Gupta ∗, Servin Rathi, Mridula Gupta, R.S. GuptaSemiconductor Devices Research Laboratory, Department of Electronic Science, University of Delhi, South Campus, New Delhi110021, India

a r t i c l e i n f o

Article history:Received 27 January 2010Received in revised form2 March 2010Accepted 5 March 2010Available online 1 April 2010

Keywords:DGHEMTSGHEMTTransconductanceOutput-conductanceCut-off frequencyMaximum frequency of oscillationUnloaded voltage gainChannel thicknessShort-channel effectsDevice aspect ratio

a b s t r a c t

In Single Gate HEMT (SGHEMT) shortening of gate length (Lg )below 100 nm leads to reduction in Transconductance (gm), whichreduces the unloaded voltage gain (gm/gd) of the device, therebyreducing the maximum frequency of oscillation (fmax). The mainreason for this reduction in gm with Lg in the Single Gate HEMT(SGHEMT) is its inability to maintain the desired channel aspectratio (α). At such a miniaturization level, α not only depends onthe channel depth (d) but also on the channel thickness (dc) ofthe device [5]. Moreover, the variation of dc may switch the devicecharacteristics from quantum regime to classical regime [27,28].The Double Gate HEMT (DGHEMT) [22,23] has emerged as asolution for further reduction in Lg and provides enhancementsover SGHEMT by virtue of its double gate and also for same dc dueto double heterojunctions, which virtually increases the value of α.In the present work, extensive simulation work has been carriedout using ATLAS device simulator [35] in order to study the effectof dc and Lg on DGHEMT and SGHEMT. An analytical model has alsobeen proposed for SGHEMT and DGHEMT to incorporate the effectof variation of dc and Lg .

© 2010 Elsevier Ltd. All rights reserved.

1. Introduction

Increasing demands for MMICs in the fields of satellite communications, high-speed wirelessaccess and intelligent transportation systems require high-speed electronic devices. Of all the devices,High Electron Mobility Transistors (HEMTs) consisting of InAlAs/InGaAs heterostructure, lattice

∗ Corresponding author. Tel.: +91 11 24115580; fax: +91 11 24116606.E-mail addresses: riteshgupta23@yahoo.com (R. Gupta), rsgu@bol.net.in (R.S. Gupta).

0749-6036/$ – see front matter© 2010 Elsevier Ltd. All rights reserved.doi:10.1016/j.spmi.2010.03.003

780 R. Gupta et al. / Superlattices and Microstructures 47 (2010) 779–794

a

b

Fig. 1. (a) Cross-sectional view of T-gate pulsed doped SGHEMT showing variation of potential/carrier concentration. (b) Theequivalent gate-drain and gate-source capacitance model for different T-gate pulsed doped SGHEMT.

matched to InP shows promising characteristics [1,2]. Ever since its development, significant effortshave been made to improve the speed of the device by shortening the gate length (Lg). Althoughshortening of Lg leads to higher cut-off frequency (fT ) but for shorter Lg i.e. below 100 nm, it is foundthat transconductance (gm) degrades with decrease in Lg , thereby reducing the unloaded voltage gain[gm/gd (output-conductance)]. It also results in degradation of maximum frequency of oscillations(fmax) [3,4]. For 25 nm InAlAs/InGaAs pseudomorphic HEMT, the fT is observed to be 562 GHz, whilethe fmax is only 330 GHz [5]. Though, fT is of great interest for digital circuits, enhancement in fmax isalso require for applications in analog and power areas [6] and for which degradation in gm with Lghas to be avoided.The main cause of reduction in gm with Lg is its inability to maintain the desired aspect ratio (α =

Lg/d) [7,8], where d (= di + da + ds) is the distance between the gate electrode and heterointerfaceas shown in Fig. 1, which shows the schematic structure of DGHEMT and SGHEMT. In order tomaintain higher Lg/d, d has to be reduced with Lg , but vertical scaling is restricted by several physicallimitations [9–19] like the emergence of gate tunnel current for reduced schottky layer thickness (di),the loss of mobility with the reduction of the spacer layer (ds), channel depleted by surface charge inrecessed region, the increase of quantum energy levels in the quantum well etc. The critical value ofd so as to avoid all these negative effects is around 8–10 nm [4], which also limits the scaling of gate-length above 80–100 nm thereby maintaining α > 10 [20] to avoid short-channel effects like shift inthreshold voltage, deterioration of the transconductance etc. Although Shinohara et al. [21], have beenable to enhance fmax by implementing amultilayer cap technologywhich results in reduction of sourceand drain parasitic resistance in a 30 nm T-gate InGaAs/InAlAs HEMT. This technique increases fmaxto 400 GHz, with a enhanced fT of 547 GHz. However, the issue of short-channel effects still remainsunaddressed.The approach suggested by Wichmann et al. [22,23] is found to be more promising to reduce Lg

below 100 nm. In this approach, the Double Gate (DG) is implemented using transferred substrate

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technique. Wichmann et al. fabricated the device and perform Monte Carlo simulation on DGHEMTas well as on SGHEMT [4]. They observed that when the device is scaled to short-channel regime,gm is decreased in SGHEMT with reduction in Lg , whereas in DGHEMT it remains approximatelythe same. Moreover, the reduction in gd is also observed due to removal of buffer layer and highercarrier confinement in DGHEMT. This noticeable combined effect of higher gm and lower gd results inextremely high gm/gd, which in turn leads to higher value of fmax. However, they also observed that thedifference in extrinsic performance of DGHEMT and SGHEMT are more prominent than intrinsic one.The decrease in gm is partially compensated by lower values of total trans-capacitance (CT ) and hencelesser deviation in intrinsic performance is seen. But higher gm/gd alongwith lower Rg , Rs and Rd leadsto significantly higher values of extrinsic characteristics. Further for smaller Lg , the gate capacitanceno longer scales with Lg [13,24,25] that further degrades the overall frequency performance. Undersuch circumstances, DGHEMT becomes the unavoidable solution for further scaling the Lg of devicebelow 100 nm to enhance device performance despite of expensive and complicated technology usedin fabricating double gate devices.From the above discussion it is quite clear that the DGHEMT is a promising device over SGHEMT

for futuristic communication system, but the cause of these enhancements proposed by them is onlythe reduction in short-channel effects [4,22,23]. Whereas, the oncoming of short-channel effects intothe device are related to α which is generally defined as Lg/d [20]. However, at such aminiaturizationlevel, d becomes comparable to∆d, where∆d is the distance from the heterointerface and the Two-Dimensional Electron Gas (2-DEG) channel as seen from Fig. 1. Thus, the formula for α modifies toLg/(d+∆d) [26]. Furthermore, by reducing the channel thickness (dc) to an extent where it becomesdifficult to judge the exact location of 2-DEG channel, the whole channel got highly populated [8] andhence, the formula for α is again redefined as Lg/(d + dc) [5]. Thus, in the light of this formula thecomparison performed by N. Wichmann between DGHEMT and SGHEMT, for same dc , seemed to beinappropriate. There is a single channel in SGHEMT whereas the same channel thickness shares twochannels in DGHEMT. As a result of which, in DGHEMT, for same dc as of SGHEMT, channel thicknessavailable per heterostructure is virtually half of the SGHEMT that leads to different values of α andthus provoking different magnitude of short-channel effects.For same dc , two effects comes into picture in DGHEMT, viz. one is the higher value of α and the

other is the better controllability of the double gate and it is difficult to interpretwhich factor is playingthemajor role in the enhancement of DGHEMT over SGHEMT. This issue left a void in the comprehen-sive analysis of the two devices, which leads us to study the comparative analysis of both the devicesfor variable dc . Furthermore, in the case of SGHEMT [27,28], if the value of dc falls in quantum regime,then increase in the dc leads to increase in number of highly confined carriers in the channel and henceresults in improved device performance. However, for larger value of dc the channel remains no longera quantum confined system and in this regime, although carrier concentration increaseswith increasein dc but owing to poor carrier confinement leads to degradation of device performance.In this paper, the intensive simulation work has been carried out to study the effect of dc and Lg

variation for both DGHEMT and SGHEMT in order to analyze the proportional enhancement offeredby DGHEMT. An analytical model has also been proposed for DGHEMT and SGHEMT incorporating theeffect of dc variations in characteristic both in sub-threshold regime and conducting region. Firstly,the comparison between SGHEMT and DGHEMT has been performed for two cases one is with sameeffective α i.e., DGHEMT having half of the dc as that of SGHEMT and next is physical α, where value ofdc is same for both type of devices to purely analyze the effect of double gate in enhancing the deviceperformance for two different gate length viz. 50 nm and 300 nm for same d i.e., 22 nm. The variationof dc has also been studied both for SGHEMT and DGHEMT on device characteristics viz. drain current(Id), gm, gd, CT , fT , gm/gd and fmax.

2. Theoretical consideration

2.1. Model for SGHEMT

Fig. 1(a) shows the cross-sectional view of SGHEMT having InAlAs schottky layer of thickness di,doped layer of thickness da, with a doping concentration Nd, and undoped InAlAs spacer layer of

782 R. Gupta et al. / Superlattices and Microstructures 47 (2010) 779–794

thickness ds, on undoped InGaAs of thickness dc , followed by an InAlAs buffer layer. To have shorterLg , various metal-insulator geometries like T-gate [29] are required and have been considered inthe present analysis. These geometries are the combination of Metal-Semiconductor (MS)/Metal-Air-Semiconductor (MAS) contact. Moreover, field plate technology [30] are also been fabricated thesedays, mainly at the drain end (0-gate) having Metal-Insulator-Semiconductor (MIS) instead of MAScontact to increase the breakdown voltage of the device. To consider the effect of T-gate geometryfor both MIS and MAS contact for SGHEMT, region under the gate has been divided into variousMetal Insulator Semiconductor (MIS) contact regions/Metal Semiconductor (MS) (Fig. 1) Schottkycontact regions having different insulators (εIz) of different thicknesses (tIz) between metal and thesemiconductor. The expression of drain current in different region for SGHEMT is given by [31–33]

Ids|z =WqµoCzB2z

(f [y(V1z)]− f [y(V0z)])(Lz +

µo(V1z−Voz )vsat

) (1)

where

f (y) = A2zy+y2

2+4Az t3/2

3y(Vz) = (βzk2)2 + 4βz (1+ βzk3)

(Vgs − Voff |z − Vz − IdsRs

)in which Voff |z is the threshold voltage, Vz is the voltage at the edges of the region [V1, V2 and Vds –Ids (Rs+Rd)], Rs and Rd are the parasitic resistance at the gate edge of source and drain end,Az = −βzk2,Bz = 2 (1+ βzk3), Cz = −4βz (1+ βzk3) and βz =

εo·εS

q(dT+

εS ·tIzεIz

) . Where εo is the permittivity of freespace, εs is the dielectric constant of the semiconductor, dT (= di + da + ds) is the thickness of theInAlAs region, k1, k2 and k3 are the parameters of the equation Ef = k1+k2 ·n

1/2s +k3.ns, which is fitted

with the solution of Schrödinger equation for InAlAs/InGaAs system to include quantum mechanicaleffects in the analysis. At room temperature, k1 = −0.139547 V, k2 = 2.94189 × 10−9 Vm andk3 = 3.49867 × 10−18 Vm2 were obtained using effective mass of electron (m∗e ) for InAlAs/InGaAssystem [31,32,34].It is found from the simulation results [35] that the effect of dc variation mainly affects the sub-

threshold behavior of the device and beyond this limit the effect of dc variation is negligible. This effectcan be considered in the analysis by introducing an extra parameter ξ with subthreshold factor k1 inthe expression of Voff |z given by [31,32]

Voff |z = φb −∆Ec −q · Nd · d2a2 · εo · εs

(1+

2 · dida

)−q · Nd · tIz · daεo · εIz

+ k1 + ξ (2)

where φb is the barrier height of Schottky gate, ∆Ec is the conduction band discontinuity atheterojunctions, k1 incorporates variation inm∗e , interface effects like latticemismatch, thermal strainetc.The effect of dc has been visualized in both the quantum regime and classical regime depending

on the value of dc . For smaller value of dc , the channel region is quantum confined and increase indc leads to increase in highly confined carriers in the channel that leads to variation in m∗e or k1, k2and k3 and mobility (µe). For larger value of dc the channel remains no longer a quantum confinedsystem and in this regime, carrier concentration although increases with increase in dc but owing topoor carrier confinement. Sub-threshold leakage current [Id (sub)] of the device also increases due topoor carrier confinement. The variation in sub-threshold leakage current can easily be incorporated inthe analysis through fitting parameter ξ , which considers the effect of variation in threshold voltagewith dc variation, arises due to dispersion of free carrier concentration.Using the drain current model, gate-source capacitance is calculated and is given by [32,36,37,33]

Cgs|z =−q2W 2µoI2ds

∂ Ids∂Vgs

∣∣∣∣Vgd

(f1 [y(Vz)]− f1 [y(Vz−1)])− C · f2 [y(Vz)] · dyg(Vz)

+ C · f2 [y(Vz−1)] · dyg(Vz−1) (3)

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where

dyg(V ) = 1−∂V∂Vgs

∣∣∣∣Vgd

− Rs∂ Ids∂Vgs

∣∣∣∣Vgd

f2(y) =qWns|zC

(qWns|zµoIds

−1Ec

)f1(y) =

1CzB4z

(A4zy+

8A3zy3/2

3+ 3A2zy

2+8Azy5/2

5+y3

3

).

Similarly, gate-drain capacitance is given by [32,36,37,33]

Cgd|z =−q2W 2µoI2ds

∂ Ids∂Vgd

∣∣∣∣Vgs

(f1 [y(Vz)]− f1 [y(Vz−1)])− C · f2 [y(Vz)] · dy(dVz)

+ C · f2 [y(Vz−1)] · dy(dVz−1). (4)

where dy(dV ) = −dV − gmRs. The resultant Cgs and Cgd for single channel can be represented asseries and parallel combination of insulator capacitances (CI1, CI2 and CI3) and depletion capacitances(CR1, CR2 and CR3) (Cgd|z and Cgs|z) in various regions as shown in Fig. 1(b) for single gate geometry andis further simplified as

Cgs|T , Cgd|T =CI1CR1CI1 + CR1

+CI2CR2CI2 + CR2

+CI3CR3CI3 + CR3

(5)

in which C = ε0ε1z (Lz+tIz/2)Wt1z

[30], for z = 1 to 3 and CR1, CR2 and CR3 can be easily found by using(1)–(4). fT of the device can be obtained by using the relation given below

fT =gm

2π(Cgs|T + Cgd|T

) (6)

such that gm can be calculated by differentiating (1) with respect to gate voltage at constant drainvoltage and fmax is obtained from the simulated results at which unilateral power gain is 1 dB. Thesub-threshold characteristics, i.e., expression for channel potential and electric field for SGHEMT canbe easily obtained by using our proposed model for SGHEMT [20,32].

2.2. Model for DGHEMT

As shown in Fig. 2(a), DGHEMT consists of two identical T-gate, one at the top and other at thebottom, followed by undoped InAlAs schottky layer thickness of di, doped layer of thickness da, with adoping concentrationNd, to provide necessary 2-DEG sheet charge density and undoped InAlAs spacerlayer of thickness ds, on both side of undoped InGaAs layer of thickness, dc , to form the 2-DEG channel.The drain current and capacitances [Fig. 2 (b)] for individual channels in DGHEMT can be obtainedanalytically using (1) and (5) respectively for two channels and is given by

Id = Id(Ch1)+ Id(Ch2)CT = CT (Ch1)+ CT (Ch2).

In DGHEMT devices, for the same dc , as of SGHEMT, channel is occupied by carriers generated bydouble heterojunctions, which hitherto has been in use by single heterojunction carriers in SGHEMT,thus resulting in sharing of dc or virtually altering the effective thickness available per heterostructurein DGHEMT. This leads to a different value ofα and hence differentmagnitude of short-channel effectsand can be incorporated in the analysis by altering the parameter ξ , which is proposed for dc variationin SGHEMT. The sub-threshold characteristics, i.e., expression for channel potential and electric fieldfor DGHEMT can be easily obtained by using our proposed model for SGHEMT [20,32].

784 R. Gupta et al. / Superlattices and Microstructures 47 (2010) 779–794

a

b

Fig. 2. (a) Cross-sectional view of T-gate pulsed doped DGHEMT showing variation of potential/carrier concentration. (b) Theequivalent gate-drain and gate-source capacitance model for different T-gate pulsed doped DGHEMT.

3. Result and discussion

The results for SGHEMT and DGHEMT have been proposed for various channel thickness varyingfrom 10 nm to 80 nm and for Lg 50 nm and 300 nm. In this paper to consider lithographic limitations,300 nm devices is treated as a normal gate device, whereas, 50 nm device is considered to be aT-gate device, in which, upper portion of T-gate is of same physical length as that of a conventionalgate device of 300 nm Lg . To obtain T-gate geometry, an insulator of finite thickness is consideredinstead of air, in between the upper portion of T-gate and the semiconductor, so as to have adefinite effect of field plate in the device for hot carrier reliability. The insulator thickness (tI)with Lg has not been optimized for hot carrier reliability and tI has been considered as 10 nm tohave a definite effect of upper gate electrode in the device. Furthermore, for analytical simplicitysimulation have been performed considering the source and drain electrode to be vertical, so as to

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Table 1Parameters used for simulation/analytical modeling.

Parameters Value

Gate metal work function 4.69 eVSource and Drain contact OhmicDoping (Nd) 4.5× 1018 cm−3Barrier height (φb) 0.56 eV

InxAl1−xAs

Eg300 1.48 eVPermittivity 12.3Affinity (χ1) 4.2 eVNC300 5.30× 1017 cm−3

NV300 1.09× 1019 cm−3

mun 4100 cm2/V sVsatn 2.1× 107 cm/sx 0.52

InxGa1−xAs

Eg300 0.76 eVPermittivity 13.2Affinity (χ2) 4.72 eVNC300 2.18× 1017cm−3

NV300 8.44× 1018 cm−3

mun 10 000 cm2/V sVsatn 3.2× 107 cm/sx 0.53

∆Ec (=χ2 − χ1) 0.52 eVξ −0.2 V to−0.5 VRs and Rd 3�mm–6�mm

minimize the effect of parasitic resistances. Various models included in simulation are the CONMOB(concentration dependentmobilitymodel) FLDMOB (field dependentmobilitymodel) and QUANTUM(carrier quantization model) model [34]. Simulated (symbols) and analytical results (solid lines) arecompared with each other and are found to be in good agreement thus proving the validity of ouranalyticalmodel. Parameters used in the analysis for analyticalmodeling and simulation are tabulatedin Table 1.In order to analyze different magnitude of short-channel effects in DGHEMT and SGHEMT and to

account for the comparison made by N. Wichmann et al., variation of the Id and gm have been plottedin Fig. 3 with gate voltage for DGHEMT with dc = 20 nm [Device I] and SGHEMT with dc = 20 nm[Device II] and dc = 10 nm [Device III] for Lg = 50 nm and Lg = 300 nm respectively at drainvoltage of 0.5 V with same physical α and same effective α in DGHEMT and SGHEMT. The maximumvalues of gm as seen from Fig. 3(a & b) are tabulated in Table 2 and are found to be 1.72 S/mm atVg = −0.45 V for device I and 0.79 S/mm (×2 = 1.58 S/mm) and 0.76 S/mm (×2 = 1.52 S/mm)at Vg = −0.45 V for device II and III respectively for 50 nm Lg and 1.72 S/mm at Vg = −0.15 V fordevice I and 0.85 S/mm (×2 = 1.7 S/mm) and 0.84 S/mm (×2 = 1.68 S/mm) at Vg = −0.15 Vfor device II and III respectively for 300 nm Lg . As device I and III have same effective α, so, boththese devices have similar effects of Lg scaling as well as dc variation and the enhancement in thedevice characteristics is 8.9% and this is only due to presence of double gate in the device I. If wecompare device I and II, then the enhancement in the performance is 13.1% and this is due to themultiplicity of gate electrodes and increased α of the device I. This effect reduces to 2.4% and 1.2%with increase in Lg from 50 nm to 300 nm, for same physical α and same effective α with SGHEMTrespectively.The main factor responsible for the peak in the gm is the abrupt variation or slope of the Id −

Vg characteristics. The measurement of this abruptness can be defined through ∆Vth (= ξ + k1).Higher the ∆Vth lesser will be the abruptness thereby lowering the peak value of gm. This veryfact is apparent from Fig. 4(a & b) where drain current has been plotted in logarithmic scalewith Vg to observe the sub-threshold behavior of the devices under consideration. From Fig. 4(a),it is clear that the Device II has maximum value of ∆Vth while it decreases in Device III andsubsequently reaches its lowest value inDevice I. As all the devices involve samematerial composition,

786 R. Gupta et al. / Superlattices and Microstructures 47 (2010) 779–794

a

b

Fig. 3. Variation of Drain current and Transconductance with gate voltage for (a) 50 nm (b) 300 nm gate length DGHEMT[dc = 20 nm] and SGHEMT [dc = 20 nm and 10 nm]. (Solid) analytical (symbol) simulated [35].

therefore, k1 is same for all devices and only ξ parameter i.e., DIBL effect and DG effect as shownin figures are responsible for variation in device characteristics. Comparing the results of Fig. 4(a)with Fig. 4(b) shows that increasing the Lg from 50 nm to 300 nm leads to not only decrease inDIBL effects but also decrease in DG effect. This shows that the effect of dc variation in devices isprominent only when α falls below a critical limit where short-channel effect tends to show theirpresence.This can be explained through variation in Id (sub) of the devices. The higher value of

Id (sub) in SGHEMT in comparison to DGHEMT is due to lesser depletion of dispersed carriers by singlegate electrode. This can be explained through Fig. 5(a & b), where channel potential for DGHEMT(dc = 20 nm) and SGHEMT (dc = 10, 20 nm) has been plotted along the channel for Lg = 50 nm andLg = 300 nm at two different drain voltages Vd = 0.0 V and 0.5 V. Fig. 5(a) shows the rise inminimum

R. Gupta et al. / Superlattices and Microstructures 47 (2010) 779–794 787

Table 2Device characteristics for DGHEMT and SGHEMT for various channel thickness and gate length at drain bias of 0.5 V.

Device dc(nm)

Lg (nm) Vg(V)

gm(S/mm)

CT (pF/mm) fT (GHz) gd(S/mm)

gm/gd fmax (GHz)

DGHEMT20 50 −0.45 1.72 1.52 179 0.12 14.3 48240 50 −0.45 1.62 1.51 171 0.17 9.7 45180 50 −0.45 1.52 1.50 162 0.24 6.4 417

SGHEMT

10 50 −0.45 0.79 0.75 167 0.10 7.7 435

20 50 −0.45 0.76 0.75 162 0.12 6.5 42040 50 −0.45 0.73 0.74 156 0.14 5.2 39880 50 −0.45 0.71 0.74 151 0.17 4.1 373

DGHEMT 20 300 −0.15 1.72 2.46 112 0.05 33.4 417

SGHEMT 10 300 −0.15 0.85 1.24 109 0.04 20.1 362

20 300 −0.15 0.84 1.24 108 0.05 17.1 346

channel potential in SGHEMT in comparison to DGHEMT even for zero drain bias, depicts the higherconcentration of dispersed carriers in the channel in SGHEMT, thereby leading to the higher value of Id(sub) in the device for Lg = 50 nm. Increasing Lg to 300 nm leads to reduction in short-channel effectsthus decreasing the dispersed carriers in the channel thereby leading to negligible variation in Id (sub)between these devices. Fig. 5(a) also shows lesser DIBL effects in DGHEMT in comparison to SGHEMTand this is also supported from Fig. 3(a) as DGHEMT have lower threshold voltage in comparison toSGHEMT.The effect of reduced dispersed carriers in the channel can also be verified through Fig. 6(a &

b), where total electric field for DGHEMT (dc = 20 nm) and SGHEMT (dc = 10, 20 nm) has beenplotted along the channel for Lg = 50 nm and Lg = 300 nm at Vd = 0.5 V . Fig. 6(a) clearlyshows that DGHEMT have lesser electric field at the minima of channel potential in comparison toSGHEMT, thereby leading to lesser carrier concentration in the channel. Increasing Lg to 300 nmleads to reduced electric field at the minima of channel potential in both SGHEMT and DGHEMTthus decreasing the dispersed carrier concentration in the channel. Fig. 6(a) also shows that thereis lesser electric field under the gate, while, higher electric field is seen at the source and drain endof the gate in DGHEMT as compared to SGHEMT that reflects the lower hot carrier reliability of thedouble gate device and thus it must be optimized for better performance. Comparing the resultsof Fig. 6(a) with Fig. 6(b) shows that Lg = 300 nm device have higher value of electric field incomparison to Lg = 50 nm device due to implementation of T-gate geometry in 50 nm Lg devicewith finite effect of upper gate electrode that proves the importance of T-gate geometry over normalgate.Fig. 7(a & b) shows the variation of CT and fT with Vg for device I, II and III for Lg = 50 nm and

Lg = 300 nm. Figures shows negligible variation in CT with dc variation in SGHEMT and this value isalmost half of what is obtained in the DGHEMT device (Table 2). However, due to variation in gm, asseen from Fig. 7(a & b), fT shows variation with dc . The variation in fT is such that for DGHEMT withdc = 20 nm shows fT = 179 GHz and 112 GHz, whereas SGHEMT for dc = 10 nm and 20 nm havefT = 167 GHz and 162 GHz respectively for Lg = 50 nm and fT = 109 GHz and 108 GHz respectivelyfor Lg = 300 nm.Further improvement in gd is seen at Vg = −0.45 V at which gm peak occurs from Table 2 in

DGHEMT (0.12 S/mm for dc = 20 nm) in comparison with SGHEMT having value of 0.10 S/mm(×2 = 0.2 S/mm), 0.12 S/mm (×2 = 0.24 S/mm) for dc = 10, 20 nm respectively. Increasing theLg to 300 nm changes these enhancements to 0.05 S/mm for dc = 20 nm for DGHEMT and 0.04 S/mm(×2 = 0.08 S/mm), 0.05 S/mm (×2 = 0.1 S/mm) for dc = 10, 20nmrespectively for SGHEMT. Theseenhancements in device performance is further accompanied by experimentally observed bufferleakage current as encountered in SGHEMT in comparison to DGHEMT [4] that degrades the gd of thedevice, which is not considered in the simulation and analytical work. This very fact leads to increase

788 R. Gupta et al. / Superlattices and Microstructures 47 (2010) 779–794

a

b

Fig. 4. Variation of Sub-threshold current with gate voltage for (a) 50 nm and (b) 300 nm gate length DGHEMT [dc= 20 nm,40 nm, 80 nm] and SGHEMT [dc= 10 nm, 20 nm, 40 nm, 80 nm]. (Solid) analytical (symbol) simulated [35].

in gm/gd ratio i.e., 14.3 in DGHEMT for dc = 20 nm and 7.7 & 6.5 in SGHEMT for dc = 10 nm & 20nm respectively for 50 nm Lg and 33.4 in DGHEMT for dc = 20 nm and 20.1 & 17.1 in SGHEMT fordc = 10 nm & 20 nm respectively for 300 nm Lg . This resulted in higher value of fmax i.e., 482 GHz inDGHEMT for dc = 20 nm and 435 GHz & 420 GHz in SGHEMT for dc = 10 nm& 20 nm respectively for50 nm Lg and 417 GHz in DGHEMT for dc = 20 nm and 362 GHz & 346 GHz in SGHEMT for dc = 10 nm& 20 nm respectively for 300 nm Lg .Apart from the comparison between SGHEMT and DGHEMT, the effect of dcvariation has also been

studied separately for SGHEMT and DGHEMT in order to have a clear perspective of dc variation inthese devices. To analyze these devices Lg is considered to be 50 nm i.e., below sub-100 nm regime soas to study the characteristic in short-channel regime. Fig. 8(a & b) shows the effect of dc variation on

R. Gupta et al. / Superlattices and Microstructures 47 (2010) 779–794 789

a

b

Fig. 5. Variation of channel potential with distance along the channel for (a) 50 nm and (b) 300 nm gate length DGHEMT [dc=20 nm] and SGHEMT [dc= 10 nm and 20 nm]. (Solid) analytical (symbol) simulated [35].

Id and gm with Vg . Increasing dc from 10 nm to 80 nm in SGHEMT leads to decrease in maximum valueof gm (0.79 S/mm, 0.76 S/mm, 0.73 S/mm and 0.71 S/mm for dc = 10 nm, 20 nm, 40 nm and 80 nm atVg = −0.45 V). Fig. 8(b) shows similar variation of dc in DGHEMT as with SGHEMT but enhancementin gm is more in DGHEMT (1.72 S/mm, 1.62 S/mm, and 1.52 S/mm for dc = 20 nm, 40 nm and 80 nm atVg = −0.45 V) due to larger variation in Id (sub) with dc in comparison to SGHEMT. This is due to thefact that higher the value of dc higher will be the dispersed carrier concentration and in DGHEMT, byvirtue of its double gate large number of dispersed carrier got depleted resulting in higher variationof Id (sub) with dc .Fig. 9(a & b) shows the effect of dc variation on CT and fT with Vg in both SGHEMT and DGHEMT.

Figure shows negligible effect of dc variation on CT (Table 2), whereas, the key parameter affecting the

790 R. Gupta et al. / Superlattices and Microstructures 47 (2010) 779–794

a

b

Fig. 6. Variation of Electric Field with distance along the channel for (a) 50 nm and (b) 300 nm gate length DGHEMT [dc= 20nm] and SGHEMT [dc= 10 nm and 20 nm]. (Solid) analytical (symbol) simulated [35].

device performance is gm and as a result of this, fT shows variation with dc i.e., 179 GHz, 171 GHz, 162GHz for dc = 20 nm, 40 nm and 80 nm at Vg = −0.45 V respectively in comparison to 167 GHz, 162GHz, 156 GHz and 151 GHz in SGHEMT for dc = 10 nm, 20 nm, 40 nm and 80 nm at Vg = −0.45 Vrespectively. As far as variation in gd is concerned, it shows trends opposite to that of gm, thus resultingin higher loss of gm/gd ratio. As gm/gd ratio is one of the decisive parameter for fmax so, this loss in gm/gdratio results in lower value of fmax and thus, lower values of dc are favorable for optimum performanceof SGHEMT and DGHEMT devices. Comparing the results of gm/gd ratio for DGHEMT and SGHEMTfrom Table 2, it is found that DGHEMT has higher gm/gd ratio i.e., 14.3, 9.7, 6.4 for dc = 20 nm, 40 nmand 80 nm at Vg = −0.45 V respectively in comparison to 7.7, 6.5, 5.2, 4.1 in SGHEMT for dc = 10 nm,20 nm, 40 nm and 80 nm at Vg = −0.45 V respectively. Thus higher fmax of 482 GHz, 451 GHz, 417GHz in DGHEMT for dc = 20 nm, 40 nm and 80 nm at Vg = −0.45 V respectively is expected then

R. Gupta et al. / Superlattices and Microstructures 47 (2010) 779–794 791

a

b

Fig. 7. Variation of Total Trans-capacitance (Cgs + Cgd) and Cut-off Frequency with gate voltage for (a) 50 nm (b) 300 nm gatelength DGHEMT [dc= 20 nm] and SGHEMT [dc= 20 nm and 10 nm]. (Solid) analytical (symbol) simulated [35].

fmax of 435 GHz, 420 GHz, 398 GHz, 373 GHz in SGHEMT for various dc at Vg = −0.45 V respectivelywhere gm peak occurs.

4. Conclusion

DGHEMT has emerged as a solution for further reduction in Lg . DGHEMT provide enhancementsover SGHEMT by virtue of its double gate and for same dc due to double heterojunctionwhich virtuallyreduces α of the device. In the present work, extensive simulation work has been carried out usingATLASdevice simulator in order to study the effect of dc onDGHEMTand SGHEMT. An analyticalmodelhas also been proposed for SGHEMT and DGHEMT to incorporate the effect of dc . Results so obtained

792 R. Gupta et al. / Superlattices and Microstructures 47 (2010) 779–794

a

b

Fig. 8. Variation of Drain current and Transconductance with gate voltage for 50 nm (a) SGHEMT (b) DGHEMT [dc= 10 nm to80 nm]. (Solid) analytical (symbol) simulated [35].

from the analytical model were found to be in good agreement with simulated results that proves thevalidity of our analytical model. DGHEMT leads to depletion of dispersed carriers that reduces Id (sub)of the device and resulting in higher value of gm. This improved gm not only increases the fT of thedevice but also increases its fmax due to increase in gm/gd ratio. Higher the value of dc higher will bethe dispersed carrier concentration and in DGHEMT large number of dispersed carrier got depletedresulting in higher variation of Id (sub) with dc . This enhances the DGHEMT performance much incomparison to SGHEMT. These effects seem to be prominent for 50 nm Lg resulting in degradation ingm as well as fT due to higher concentration of dispersed carrier in the channel for shorter α, leadingto higher value of Id (sub) and lower value of gm. However, in DGHEMT, it shows lesser degradationin gm for Lg below 100 nm regime resulting in not only the higher value of fT but also fmax due toenhancement in gm/gd ratio.

R. Gupta et al. / Superlattices and Microstructures 47 (2010) 779–794 793

a

b

Fig. 9. Variation of Total Trans-capacitance (Cgs + Cgd) and Cut-off Frequency with gate voltage for 50 nm (a) SGHEMT (b)DGHEMT [dc= 20 nm to 40 nm]. (Solid) analytical (symbol) simulated [35].

Acknowledgements

The authors acknowledge the Department of Science and Technology (D.S.T) and Council ofScientific and Industrial Research (CSIR), Government of India for providing the necessary financialsupport for this work.

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