Memory efficient IFFT design for OFDM-based applications

Memory efficient IFFTdesign for OFDM-basedapplications

In-Gul Jang1, Kyung-Ju Cho2a), Hwan-Yong Kim2,and Jin-Gyun Chung31 Electronics and Telecommunications Research Institute ETRI Daejeon Korea2 Department of Electronic Engineering Wonkwang University Iksan Korea3 Division of Electronic Engineering Chonbuk National University Jeonju Koreaa) kjchowkuackr (Corresponding author)

Abstract: In this paper, we propose a new memory efficient IFFT

design method for OFDM-based applications, based on a signed

integer mapping of three IFFT input signals which are composed of

modulated data, pilot and null signals. The proposed method focuses

on reducing the word size of memory in the first two stages of the

single-path delay feedback (SDF) IFFT architectures since the first

two stages require 75% of the overall memory. By Synopsys

simulation of the first two stages of IFFT, it is shown that the

proposed method achieves about 40% reduction in area and 44%

reduction in power consumption compared with the previous work.

Keywords: IFFT, SDF, feedback memory reduction

Classification: Integrated circuits

References

[1] S. N. Tang, J. W. Tsai and T. Y. Chang: IEEE Trans. Circuits Syst. II,

Exp. Briefs 57 (2010) 451.

[2] S. He and M. Torkelson: IEEE URSI Int. Symp. Signals, Syst., Electron.

(1998) 257.

[3] J. Y. Oh and M. S. Lim: IEICE Trans. Electron. E88-C (2005) 1740.

[4] T. S. Cho and H. H. Lee: IEEE Trans. Very Large Scale Integr. (VLSI)

Syst. 21 (2013) 187.

[5] I. G. Jang, K. J. Cho, Y. E. Kim and J. G. Chung: IEICE Trans. Commun.

E95-B (2012) 2059.

1 Introduction

FFT/IFFT processor is one of the key components in OFDM-basedapplications. FFT/IFFT processor for advanced OFDM systems such as

cognitive wireless regional area network (IEEE 802.22 WRAN) and 60GHz

gigabit WPAN should provide a very high throughput rate [1]. A pipelined

FFT/IFFT architecture is well-suited for high-throughput rate applica-tions. Among the various pipelined FFT architectures, the single-pathfeedback (SDF) approach based on the radix-2r algorithm is frequently

used for its low cost and high efficiency [2, 3, 4]. However, if the large-pointIFFT or high-level modulation is adopted to improve the bandwidth

efficiency, then a longer word size is needed in order to preserve the signal-

IEICE Electronics Express, Vol.10, No.21, 1–6

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© IEICE 2013DOI: 10.1587/elex.10.20130530Received July 08, 2013Accepted July 22, 2013Publicized August 15, 2013Copyedited November 10, 2013

LETTER

to-quantization-noise ratio (SQNR). Thus, the longer word size leads to the

exponential increase of feedback memory size of SDF IFFT architectures.

　 In large-point IFFT designs, the memory size occupies more than 70%

of the chip area. In N -point radix-22 [2], radix-24 [3], and radix-25 [4] SDF

FFT/IFFT design, the necessary number of memory locations for ith stage

is N/2i. Thus, the number of the total required memory locations is N�1.

Note that the first two stages in the FFT/IFFT architecture require 75% of

the total memory cells.

　 In [5], to reduce the memory size of IFFT for OFDM transmitters, the

combined integer mapping which generates mapped data composed of two

signed integers corresponding to modulated data and pilot/null signals was

proposed. The mapping leads to more than 40% reduction in memory size.

In this paper, to further reduce the memory size, we propose a new IFFT

design method which uses a signed integer mapping and simple post-processing for compensation.

2 Backgrounds

In most OFDM transmitters, each subcarrier is modulated using either

BPSK, QPSK, 16-QAM, or 64-QAM modulation schemes, depending on

the requested rate. The encoded and interleaved binary serial input data

streams are divided into groups and each group is mapped into a complex

value representing constellation points depending on the modulation

scheme. To achieve the same average power for all mapping schemes, the

final modulated data d is formed by multiplying the mapped value (I + jQ)

by a normalization factor (KMOD) as

d ¼ I þ jQð Þ �KMOD (1)

where, KMOD is 1, 1� ffiffiffi

2p

, 1� ffiffiffiffiffi

10p

, and 1� ffiffiffiffiffi

42p

, for BPSK, QPSK, 16-QAM

and 64-QAM, respectively, depending on the base modulation mode.

　 In all of OFDM symbols, in order to allow for the coherent detection

and to provide robustness against frequency offsets, pilot signals are placed

in the specified subcarriers. Pilot signals are BPSK modulated by a pseudo

binary sequence. Also, null signals are set to zero in specified subcarriers to

avoid difficulties in DAC and ADC offset and carrier feed-through in the

RF chain.

　 Fig. 1 shows the conventional procedure of subcarrier modulation

mapping and IFFT operation. In Fig. 1, the value d, pilot and null signals

are quantized depending on the required SQNR before the IFFT operation.

　 Fig. 2 shows radix-2r (r � 2) SDF IFFT architecture. The first-in first-out (FIFO) memory in stage i stores N/2i pieces of complex data. Thus, the

total memory size is 2(N�1) words. It is interesting to notice that the first

Fig. 1. Conventional procedure of modulation mapping

and IFFT.


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two stages in the SDF IFFT architecture occupy about 75% of the overall

feedback memory.

3 IFFT input data mapping

If the resultant value (I+jQ) from constellation mapping is multiplied by

the normalization factors before quantization as in (1), the required word

size at stage 1 of IFFT should be increased. However, if the multiplication

of normalization factor and the quantization can be processed after stage 2

as shown in Fig. 3, we can significantly reduce the word size of memory at

stages 1 and 2. However, in this case, the multiplication of normalization

factors becomes complicated since different type signals are added or

subtracted in butterfly (BF) before normalization factors are multiplied

(each signal type needs different normalization factors). To overcome this

problem, the combined integer mapping was proposed in [5].

3.1 Combined integer mapping [5]The combined integer mapping generates a mapped data composed of two

signed integers corresponding to modulated data and pilot/null signal. For

IFFT input signals, the combined integer mapped value can be expressed as

I þ jQð Þ ¼ mre; pnreð Þ þ j mim; pnimð Þ; (2)

where m and pn represent modulated data and pilot/null signal in two’s

complement representation, respectively, and the subscript re and im mean

real and imaginary parts, respectively. In each BF, the data in the first part

are added or subtracted only with those of the first part. The same is also

true for the data in the second part.

　 As an example of 16-QAM modulation scheme, consider the addition of

modulated data d=�3�j and pilot p=1 in stage 1. By combined integer

mapping, the two signals are represented as d=(101,00)+j(111,00) and p=(000,01)+j(000,00). Thus, the addition result with sign extension is

expressed as d+p= (1101,001) +j(1111,000).

　 The actual input signals to stage 3 before the multiplication by TF1 in

Fig. 2 can be computed as

Fig. 2. Radix-2r SDF IFFT architecture.

Fig. 3. Proposed procedure of modulation mapping and

IFFT.


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stg3 in ¼ stg2 outre �KMOD þ pnreð Þ þ j stg2 outim �KMOD þ pnimð Þ (3)

The quantized values of (3) can be obtained using two look-up tables [5].

3.2 Proposed mapping methodIn OFDM applications, pilot signal pattern and pilot allocation for

subcarriers are predefined depending on channel environments. Also, the

pilot signals are located with equidistance spacing in time and frequency.

　 Based on the above facts, we propose a new mapping method to achieve

reduction in word-size of IFFT input data. IFFT inputs corresponding to

pilot signals to stage 1 are mapped into zero and compensation values

(CVs) are added to stage 2 outputs to correct the error due to zero-mapping

of the pilot as shown in Fig. 3. Compared with [5], word-size assignment for

pilot signals is not needed.

　 The compensated input signals to stage 3 are expressed as

stg3 in ¼ stg2 outre �KMOD þ CVreð Þ þ j stg2 outim �KMOD þ CVimð Þ (4)

In the proposed method, the word size Wp is 1þ log2rmd e, where, rm means

the number of levels of the modulation scheme, and xd e means ceiling

operation of x.

　 BF at stage i generates the addition output (aoi) and subtraction

output (soi) which are feed into the next stage and the feedback memory,

respectively. The output signals from BF at stage 2 in Fig. 2 can be

expressed as

a o2 nð Þ ¼ x nð Þ þ x nþN=2ð Þ þ x nþN=4ð Þ þ x nþ 3N=4ð Þs o2 nð Þ ¼ x nð Þ þ x nþN=2ð Þ � x nþN=4ð Þ þ x nþ 3N=4ð Þ½ �a o2 nþN=2ð Þ ¼ x nð Þ � x nþN=2ð Þ � j x nþN=4ð Þ � x nþ 3N=4ð Þ½ �s o2 nþN=2ð Þ ¼ x nð Þ � x nþN=2ð Þ þ j x nþN=4ð Þ � x nþ 3N=4ð Þ½ �for n ¼ 0; 1; � � � N=4� 1ð Þ

(5)

From (5), considering feedback path at stage 2, stage 3 input signals before

the multiplication by twiddle factor (TF1) can be expressed as

stg3 in nð Þ ¼ x nð Þ þ x nþN=2ð Þ þ x nþN=4ð Þ þ x nþ 3N=4ð Þstg3 in nþN=4ð Þ ¼ x nð Þ þ x nþN=2ð Þ � x nþN=4ð Þ þ x nþ 3N=4ð Þ½ �sta3 in nþN=2ð Þ ¼ x nð Þ � x nþN=2ð Þ � j x nþN=4ð Þ � x nþ 3N=4ð Þ½ �stg3 in nþ 3N=4ð Þ ¼ x nð Þ � x nþN=2ð Þ þ j x nþN=4ð Þ � x nþ 3N=4ð Þ½ �for n ¼ 0; 1; � � � N=4� 1ð Þ

(6)

Assuming that an IFFT input signal x(n0) is a pilot signal p0, and n0 is a

number between 0 and N/4�1. From (6), it can be noticed that the signal x

(n0) has effects on the third stage input signals stg3_in(n0), stg3_in(n0+N/

4), stg3_in(n0+N/2) and stg3_in(n0+3N/4). Thus, if zero input is used

instead of the actual pilot signal p0, the p0 should be added to the four stage

3 input signals as a CV.

　 Table I summarizes the compensation values to the third stage input

according to four different pilot signal locations. As an example, if the pilot

signals in the range (N/4�n�N/2�1) are represented as p1, different CVs

are used depending on the order of the third stage input as shown in Table I.


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If Np is the number of pilot signals, the number of the required CVs is

4×Np. In addition, for a pilot signal pi, the intervals between adjacent CVs

are N/4. Thus, we can easily compute the locations which require CVs.

　 In Table I, the number in parentheses is binary representation of input

order at each stage. The two most significant bits (lk�1 lk�2) on the first

column and the two most significant bits (ck�1ck�2) on the third column are

used to generate two control signals as

s1 ¼ �lk�1lk�2 ck�1 � ck�2ð Þ þ lk�1�lk�2ck�1 þ lk�1lk�2ck�2

s2 ¼ lk�2ck�1(7)

where, ⊕ means exclusive-OR operator. In (7), s1 and s2 are used for sign

inversion and trivial multiplication of �j, respectively. The rest of the pilot

location bits, (lk�3…l0), are used as address signals of look-up table (LUT)

which stores pilot signals. The LUT size is 2×Np, since pilot signal can be

either 1 (01) or �1 (11).

　 The compensated values can be obtained as shown in Fig. 4. Stage 3

inputs are used as address signals of the quantized LUT for stg3_in×KMOD.

In Fig. 4, the signal (s3) which controls bypass of the values stored in the

quantized LUT can be obtained using pilot allocation information.

Table I. Compensation values to stage 3 inputs

(k : number of stages).

Fig. 4. Computation of desired stage 3 inputs.


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4 Performance comparisons

To compare the memory efficiency in SDF IFFT design, the feedback

memory size and additional hardware of the conventional method, previous

method [5], and proposed method are listed in Table II. We assume that 64-QAM modulation scheme is used and IFFT processors have fixed-widthproperty of truncating least significant bits of the output signals in each

stage. Notice that in stages 1 and 2, the memory sizes of the proposed

method and the method in [5] do not depend on IFFT input word size (W).

By the method in [5], the modulated signal is represented with 6-bits(modulated signal: 4-bits, pilot/null signal: 2-bits). However, by the

proposed method, the input signals are represented using only 4-bits.Except stages 1 and 2, the three methods are identical.

　 Additionally, a practical application for IFFT in IEEE 802.22 WRAN is

adopted to evaluate the performance of three IFFT design methods. Table

III shows the comparison of area and power consumption of the first two

stages of 2048-point radix-22 SDF IFFT with W=16. Three IFFT ware

synthesized through utilizing Synopsys Tool with Samsung 0.13μm CMOS

standard cell library. It is shown that the proposed method achieves about

78% (92%) reduction in area (power) compared with the conventional

method, and about 40% (44%) reduction in area (power) compared with

the previous work [5].

5 Conclusion

To reduce the memory size of IFFT for OFDM transmitters, a new IFFT

design method was proposed based on mapping and post-processingtechniques. The proposed method focuses on reducing the sizes of the

memory cells in the first two stages of IFFT architectures. The benefits of

the proposed method can be maximized in wireless systems with high-levelmodulation or systems which require long transform length.

Acknowledgments

This paper was supported by Wonkwang University in 2013.

Table II. Comparison of the feedback memory size and

additional H/W.

Table III. Synopsys simulation results.


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Memory efficient IFFT design for OFDM-based applications

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