Abstract— In this paper, we propose low power and robust

6T SRAM cells. The cells are based on the Vt-control of the cross-coupled inverters of the SRAM cell to reduce leakage power when SRAM is in the idle mode. Using the Vt-control method along with the built-in feedback leads to increasing the SNM. In comparison to a previous work, our schemes have a higher static noise margin (SNM) and lower standby power consumption. To assess the efficiency of the approach, HSPICE simulations in 45nm and 32nm FinFET technologies are used. The results show considerable improvements in terms of the standby power as well as the hold and read SNM. This suggests that the Vt-control method may be used for realizing low-standby power and robust SRAM.

Index Terms—SRAM, FinFET, Static Noise Margin, Standby Power, Low-Power Memory, Vt-control method.

I. INTRODUCTION SRAM arrays are a major part of the chip in many of digital systems which are implemented by MOSFET transistors. One of two important challenges of scaling the conventional six-transistor (6-T) SRAM cells are the increased transistor leakage and the parameter variation present in the state of the art standard CMOS technologies. The gate length scaling increases the device leakage exponentially across technology generations. Furthermore, the cell stability will continue to degrade with decreasing the system supply voltage (VDD) and the transistor threshold voltages (Vt) in nanometer technology nodes [1]. The FinFET [2] transistor structure has been introduced as an alternative to the bulk-Si MOSFET structure for improved scalability. The structure has two gates which can be electrically isolated and have two different voltages (back-gate) for an improved operation. In the double-gate (DG) operating mode, the two gates have connected together to switch the FinFET on/off, whereas in the back-gate (BG) operating mode, they are biased independently – with one gate used to switch the FinFET on/off and the other gate used to determine the threshold voltage. The BG operation mode provides us with the ability to tune the dynamic and/or static performance characteristics [3]. This feature

can be utilized to improve the SRAM cell. Large embedded SRAM arrays consume a large fraction

of the overall power of a processor. The power consumption in an SRAM array consists of a short active time and a very long idle time making the standby power consumption as a major issue. Therefore, the leakage reduction in large memory arrays is a vital objective for low-power VLSI applications. The cell leakage is commonly suppressed by using a higher transistor threshold voltage [3]. Utilizing a higher transistor threshold voltage also helps to improve the read margin. It, however, negatively impacts the access time due to a lower driving current [3]. In [4], the underlap in the nanoscale FinFET is optimized to control the threshold voltage for increasing the read SNM in the SRAM cell. Another way to control the threshold voltage of the FinFET is to use the back-gate bias. In [5], the Vt-control method has been studied by simulating various DG structures for a single NMOS device and the advantage of the Vt-control method in comparison with the conventional DG operation of these devices has been discussed. In [6], two independent control voltages, Vcn and Vcp, are applied to the back-gates of the n- and p-type transistors, respectively, to reduce the leakage current when the inverter is in the idle mode. In [1], the effectiveness of independent gate operation on lowering the power consumption and maintaining bitcell read stability is verified.

In this work, a low power and robust FinFET-Based SRAM cells based on the Vt-control method are proposed. The rest of the paper is organized as follows. In Section II, the proposed SRAM cells are given and the structure and the I-V characteristic of the FinFET are discussed. In Sections III, the proposed SRAM cells are compared in terms of the static power dissipation, stability and read access time. Finally, the conclusion of the paper is given in Section VI.

Low Standby Power and Robust FinFET Based SRAM Design

Behzad Ebrahimi, Saeed Zeinolabedinzadeh, and Ali Afzali-Kusha

Nanoelectronics Center of Excellence, School of Electrical and Computer Engineering, University of Tehran

b.ebrahimi@ece.ut.ac.ir, s.zeinolabedinzadeh@ece.ut.ac.ir, afzali@ut.ac.ir

IEEE Computer Society Annual Symposium on VLSI

978-0-7695-3170-0/08 $25.00 © 2008 IEEEDOI 10.1109/ISVLSI.2008.8

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(a) (b) (c)

(d) (e) (f)

(g) (h) Fig. 1. Schematics of 6T SRAM cells (a) conventional (DG) (b) independent gate operation on pull-down and pull-up transistors (DGVt-control) (c) independent gate operation on pull-down and pull-up and access transistors (BGVt-control) (d) independent gate operation on pull-up and access transistors (BGVt-control PMOSOnly) (e) independent gate operation on pull-down and access transistors (BGVt-controlNMOSOnly) (f) independent gate operation on NL transistor with GND-biased back-gate (Scheme 1) [9] (g) independent gate operation on NL with GND-biased back-gate and PL with VDD-biased back-gate (Scheme2) [9] (h) independent gate operation on NL transistor with GND-biased back-gate and use of device sizing (Scheme 3) [9].

Fig. 2. Triple-fin FinFET structure [7].

II. PROPOSED SRAM CELLS BASED ON FINFET

A. SRAM Cells In Fig. 1, different SRAM cells based on the FinFET

technology are shown. Unless stated otherwise, assume that the transistors in this paper have the tied front-gate and back-gate. The cell shown in Fig. 1(a) is the conventional double-gate (DG) SRAM cell. For this cell, in the standby

mode, three of devices have the sub-threshold leakage. For example, in Fig. 1(a) (conventional SRAM cell), when VL (left value) = VDD and VR (right value) = 0, the transistors with the sub-threshold leakage are the right access transistor, left pull-down transistor and right pull-up transistor. One can increase the threshold voltage during the standby such that the sub-threshold leakage can decrease. This can be achieved by using the back-gate of the FinFET. The FinFET SRAM cells, proposed in this work, use the

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back-gate of the FinFET to decrease the standby power consumption and improve the stability (robustness) of the cell. The cells shown in Figs. 1(b)-(e) present the proposed SRAM cells based on the FinFET whose back-gate can be controlled by a voltage other than the front-gate voltage.

For the cell shown in Fig. 1(b), we use the idea of [6] which applies two independent control voltages of Vcn and Vcp to the back-gate of the n-type and p-type transistors of the cross-coupled inverters, respectively. In [6], by altering the value of Vcn between 0 and -VDD and Vcp between VDD and 2VDD, the optimum values which minimize the power-delay product are determined. It was shown that the optimum control voltages approach -VDD and 2VDD for the NMOS and the PMOS, respectively.

Connecting the back-gate of the access transistor to the adjacent bit-cell storage node weakens the access transistor current. This increases the cell stability using a built-in feedback [10]. It does not have a significant effect on the static power because it reduces the threshold voltage of the access transistor with Vds=0 in standby mode. In Fig. 1(c), we propose to use the built-in feedback and the Vt-control method simultaneously. In Figs. 1(d) and (e), we invoke the built-in feedback and we apply Vt-control method either to the PMOS or the NMOS transistors, respectively. In the comparison study, we have included the three schemes proposed in [9]. These schemes, shown in Figs. 1 (f)-(h) are asymmetric SRAM cells of which data should be read from one side (right side in Figs. 1(f)-(h)) to achieve a better read stability.

Fig. 3. Ids vs Vfg at |Vds| =VDD for double-gate (DG) FinFET in 45nm with (1) tied front and back-gate, (2) Vbg=GND, (3) Vbg=-VDD case for NMOS and (4) tied front and back-gate, (5) Vbg=VDD, (6) Vbg=2VDD case for PMOS.

B. FinFET Structure and Characteristics For the HSPICE simulations, we use 45nm and 32nm

gate lengths FinFET technology [8] for the transistors used in the SRAM cells. Symmetrical double gate FinFET is used in simulations. We consider single-fin for the pull-up and the access transistors in the SRAM bit-cell to achieve a compact layout area. We also use triple-fin pull-down transistors (shown in Fig. 2) to have a better SNM. However, as suggested in [9], we have optimized the size of NL (left inverter NMOS) transistor to achieve the maximum read SNM. Since the channel widths of FinFET devices are determined by the number of fins, only discrete sizing is available [11]. The optimum number for 32nm

technology is 1 fin and for 45nm technology is 2 fins. The values of key device parameters used in the HSPICE simulations are summarized in Table I.

TABLE I. DEVICE PARAMETERS USED IN SIMULATIONS [8]. LG (nm) 32 45 Tox (A) 14 15 Tsi (nm) 8.6 8.4 VDD (V) 0.9 1

Channel Doping, NBODY (#/cm-3) 2e16 2e16 Hfin (nm) 40 60

Vt0,nmos (V) 0.29 0.31 Vt0,pmos (V) -0.25 -0.25

The drain current (Ids) characteristics versus the front-

gate voltage (Vfg) of NMOS and PMOS FinFETs in the 45nm technology with different back-gate voltage (Vbg) as the running parameter are plotted in Fig. 3. Since the threshold voltage and the short channel effects are dependent on the Vbg, the characteristics strongly depends this voltage [12]. The figure shows the Ids-Vfg characteristic for (1) tied front- gate and back-gate, (2) Vbg = GND, (3) Vbg = -VDD for the NMOS and (4) tied front-gate and back-gate, (5) Vbg = VDD, (6) Vbg = 2VDD for the PMOS. As shown in Fig. 3, there are three different on-current (Ion) values depending on the Vbg for a given Vfg. The Vfg = Vbg = VDD case for the NMOS has the largest Ion due to the front-gate and back-gate coupling. This scheme has only twice the current of the case of the most negative voltage on the back-gate (when Vfg = VDD, Vbg = -VDD). The transistor leakage current is very small when Vfg = GND and Vbg = -VDD for the NMOS and Vfg = VDD, Vbg = 2VDD in the PMOS case. The characteristics and trends for the 32nm are similar.

In the next sections, we discuss and compare different issues in designing SRAM cells.

III. RESULTS AND DISCUSSION

In this section, we compare the proposed SRAM cells based on the FinFET technology. The comparison includes the static power consumption, static noise margin, and read access time.

A. Static Power Consumption In Fig. 4, the results of the HSPICE simulations for the

standby power are depicted. The figure shows that the standby power in the 32nm gate length is greater than that of the 45nm. The reason is the increases of the gate tunneling current due to the oxide thickness (Tox) scaling and sub-threshold leakage as a result of Vt scaling. The BG Vt-control with Vcn = -VDD and Vcp = 2VDD has the smallest standby power which is 20% of that of the DG case. It has less power in comparison to the three schemes proposed in [9]. If smaller control voltages are used, the standby power increases due to the decrease in the Vt. In the cases that the Vt-control is applied only to one type of the cross-coupled transistors (NMOS or PMOS), because of the higher carrier mobility in NMOS, increasing its threshold voltage results in overall lower standby current leading to a smaller static

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power of the Vt-controlNMOSOnly than Vt-controlPMOSOnly.

Fig. 4. The standby power for different SRAM cells in the 32nm and 45nm technologies.

B. Stability The static noise margin (SNM) is the standard metric to

measure the stability in SRAM bit-cells [13]. The SNM of an SRAM cell represents the minimum DC-voltage disturbance necessary to upset the cell state [13], and can be quantified by the length of the side of the maximum square that can fit inside the butterfly curves formed by the cross-coupled inverters. The SNM is smaller for the 32nm than that for the 45nm. This is due to a smaller VDD.

The read stability can also be quantified by the cell SNM during a read access. During a read operation in Fig. 1 (a) since the right access transistor operates in parallel with the right pull up transistor and keeps VR (right cell value) from ever reaching 0V, the gain in the inverter transfer characteristic will decrease. This decreases the read SNM. For this reason, the cell is considered most vulnerable to the noise during the read access [3].

We used the single-ended read for the schemes proposed in [9] and differential read for the rest of the cells. The operating principle of a single-ended READ SRAM is as follows. In the READ mode, only R/WWL is activated, so that the AR is turned-on and the read is performed at the right side only through the read/write bit-line (R/WBL) [9].

Fig. 5 plots the butterfly curves for the DG, DGVt-control, and BGVt-control SRAM designs (Vcn=-VDD, Vcp=2VDD for Vt-control cases). Based on these results, the BGVt-control (Vcn=-VDD, Vcp=2VDD) SRAM has an improvement of 88% in the read SNM in comparison to its DG counterpart in the 45nm technology. For the 32nm gate length, there is not any SNM for DG design. An acceptable read SNM can be achieved by upsizing the pull-down transistors. This leads to an area penalty. The BGVt-control (Vcn=-VDD,Vcp=2VDD) cell has an acceptable SNM without requiring upsizing.

(a)

(b)

Fig. 5. The read butterfly plot for DG and DGVt-control and BGVt-control SRAM cells (Vcn=-VDD, Vcp=2VDD for Vt-control cases) in (a) 32nm and (b) 45nm technologies.

Fig. 6 shows the read SNM of the SRAM cells. As

observed from the figure, among the schemes proposed in [9], scheme 3 has the maximum read SNM which is equal to its hold SNM. In addition, this figure indicates that the read SNM of the scheme 3 is smaller than that of proposed BG Vt-control (Vcn=-VDD, Vcp=2VDD) in the 45nm technology. In the 32nm, the read SNM of the BGVt-control (Vcn=-VDD, Vcp=2VDD) is 13% smaller than that of the scheme 3.

We also see that smaller control voltages result in smaller SNMs as a result of smaller threshold voltages. Furthermore, the read SNM is still higher than that of the DG cell in this condition. Now consider the BGVt-control cells when the method is applied only to one type of transistor in the cross-coupled inverter. While high threshold PMOS loads decrease the inverter trip point, high threshold NMOS pull-down devices tend to increase it. Since the current driving ability of the NMOS transistor is larger than that of the PMOS, increasing the threshold voltage of the NMOS has a stronger impact on the trip voltage [14] giving rise to a larger read margin. As we see, the BGVt-ControlNMOSOnly has a larger read SNM than that of the BGVt-control due to the stronger impact of the NMOS transistors on the trip voltage.

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Fig. 6. The read SNM for different SRAM cells in the 32nm and 45nm technologies.

Fig. 7 plots the hold (when WL (Word Line) is deactivated.) butterfly curves for DG, DGVt-control and BGVt-control (Vcn=-VDD, Vcp=2VDD for Vt-control cases) designs. Fig. 8 shows the hold SNM for different cells. As observed from this figure, the hold SNM has more or less the features as those of the read margin. The DG and the BG schemes have the same Hold SNM. Among the proposed schemes in [9], scheme 2 has the maximum hold margin which is smaller than our proposed BGVt-control (Vcn=-VDD, Vcp=2VDD) Moreover, we can see from this figure that when we apply the Vt-control method to both NMOS and PMOS transistors, the hold SNM is more than that of the case where we apply the Vt-control only to the NMOS or the PMOS.

(a)

(b) Fig. 7. The hold butterfly plot for a FinFET 6-T SRAM DG, DGVt-control and BGVt-control (Vcn=-VDD, Vcp=2VDD for Vt-control cases) SRAM cells in the (a) 32nm and (b) 45nm technologies.

Fig. 8. The hold SNM plot for different SRAM cells in the 32nm and 45nm technologies.

C. Read Access Time To compare the read access time for different SRAM

schemes, we have performed the transient analysis for the cells. As shown in Fig. 9, a 32K 6-T SRAM can be organized as a 128 column-256 row array. The cell device dimensions are determined based on [3]. The resistance and word-line and bit-line capacitances are derived from predictive technology-model (PTM) interconnect model for 45nm and 32nm technology node [8]. Gate and drain capacitances of access transistors are estimated based on simulations and gate capacitance in BG case is half of DG case. The parameters are shown in Table II. The read access time is defined as the time required to produce a pre-specified voltage difference (0.1 VDD) between the two bit-lines (after that the sense amplifiers become active and the bit-lines reach their final values for the differential read) as shown in Fig. 10. The same definition may not be used for the schemes of [9] where a single-ended read operation is performed. As we see in Fig. 11, the read access time for our proposed BGVtControl (Vcn=-VDD, Vcp=2VDD) is 68% (83%) longer than that of the DG case in the 45nm (32nm) technology. The read access time for our proposed schemes should be smaller than those of the proposed in [9] due to the differential-ended read which is faster than the single-ended one.

Fig. 9. SRAM circuit schematic.

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TABLE II. SRAM ARRAY PARAMETERS.

Value

DG BG

Parameter

32nm 45nm 32nm 45nm Cell dimension: Width (µm)

Height (µm) 0.627 0.304

0.882 0.428

0.627 0.304

0.882 0.428

Word-line: Resistance/cell (Ω) Capacitance/cell Cg,AX(fF) Capacitance/cell, Cwl,int(fF)

3.596 0.107 0.067

2.662 0.299 0.101

3.596 0.053 0.067

2.662 0.150 0.101

Bit-line: Resistance/cell (Ω) Capacitance/cell Cd,AX(fF)

Capacitance/cell, Cbl,int(fF)

1.744 0.027 0.032

1.292 0.075 0.049

1.744 0.027 0.032

1.292 0.075 0.049

(a)

(b)

Fig. 10. Timing diagrams in the read mode for (a) BGVt-control (Vcn=-VDD, Vcp=2VDD) in the 45nm technology (b) BGVt-control NMOSOnly (Vcn=-VDD) in the 32nm technology.

Fig. 11. Read access time for different SRAM cells in the 32nm and 45nm technologies.

IV. SUMMARY AND CONCLUSION In this work, we proposed low-power and robust SRAM

cells based on FinFET. The proposed cells included the applications of the Vt-control method to different transistors along with the use of the built-in feedback in the cell. To

determine the efficiency of the cells, the HSPICE simulations for the 32nm and 45nm technologies were used. The study included the static power, the stability, and the read access time. In the cell that the Vt-control method was applied to the cross-coupled inverters, the results revealed a very low static power. The use of the built-in feedback improved the read SNM. The results for the read access times showed a higher access time for the Vt-control method compared to the DG SRAM cell which had the worse SNM and standby power. Compared to the previous work on FinFET asymmetric SRAM, designed to have better read stability, the proposed schemes had a very low static power and shorter read access time.

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