Lecture Notes in Computer Science 2778Edited by G. Goos, J. Hartmanis, and J. van Leeuwen

3BerlinHeidelbergNew YorkHong KongLondonMilanParisTokyo

Peter Y. K. Cheung George A. ConstantinidesJose T. de Sousa (Eds.)

Field-ProgrammableLogic and Applications

13th International Conference, FPL 2003Lisbon, Portugal, September 1-3, 2003Proceedings

1 3

Series Editors

Gerhard Goos, Karlsruhe University, GermanyJuris Hartmanis, Cornell University, NY, USAJan van Leeuwen, Utrecht University, The Netherlands

Volume Editors

Peter Y. K. CheungGeorge A. ConstantinidesImperial College of Science, Technology, and MedicineDept. of Electrical and Electronic EngineeringExhibition Road, London SW7 2 BT, UKE-mail: p.cheung@ic.ac.uk; george.constantinides@ieee.org

Jose T. de SousaTechnical University of LisbonINESC-ID/ISTR. Alves Redol, 9, Apartido 13069, 1000-029, Lisboa, PortugalE-mail: jts@inesc-id.pt

Cataloging-in-Publication Data applied for

A catalog record for this book is available from the Library of Congress

Bibliographic information published by Die Deutsche BibliothekDie Deutsche Bibliothek lists this publication in the Deutsche Nationalbibliografie;detailed bibliographic data is available in the Internet at <http://dnb.ddb.de>.

CR Subject Classification (1998): B.6-7, C.2, J.6

ISSN 0302-9743ISBN 3-540-40822-3 Springer-Verlag Berlin Heidelberg New York

This work is subject to copyright. All rights are reserved, whether the whole or part of the material isconcerned, specifically the rights of translation, reprinting, re-use of illustrations, recitation, broadcasting,reproduction on microfilms or in any other way, and storage in data banks. Duplication of this publicationor parts thereof is permitted only under the provisions of the German Copyright Law of September 9, 1965,in its current version, and permission for use must always be obtained from Springer-Verlag. Violations areliable for prosecution under the German Copyright Law.

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Preface

This book contains the papers presented at the 13th International Workshopon Field Programmable Logic and Applications (FPL) held on September 1–3,2003. The conference was hosted by the Institute for Systems and ComputerEngineering-Research and Development of Lisbon (INESC-ID) and the Depart-ment of Electrical and Computer Engineering of the IST-Technical Universityof Lisbon, Portugal.

The FPL series of conferences was founded in 1991 at Oxford University(UK), and has been held annually since: in Oxford (3 times), Vienna, Prague,Darmstadt, London, Tallinn, Glasgow, Villach, Belfast and Montpellier. It bringstogether academic researchers, industrial experts, users and newcomers in an in-formal, welcoming atmosphere that encourages productive exchange of ideas andknowledge between delegates.

Exciting advances in field programmable logic show no sign of slowing down.New grounds have been broken in architectures, design techniques, run-time re-configuration, and applications of field programmable devices in several differentareas. Many of these innovations are reported in this volume.

The size of FPL conferences has grown significantly over the years. FPL in2002 saw 214 papers submitted, representing an increase of 83% when comparedto the year before. The interest and support for FPL in the programmable logiccommunity continued this year with 216 papers submitted. The technical pro-gram was assembled from 90 selected regular papers and 56 posters, resultingin this volume of proceedings. The program also included three invited plenarykeynote presentations from LSI Logic, Xilinx and Cadence, and three industrialtutorials from Altera, Mentor Graphics and Dafca.

Due to the inclusive tradition of the conference, FPL continues to attractsubmissions from all over the world. The accepted contributions were submittedby researchers from 32 different countries:

USA 42 Belgium 6 Brazil 2 Estonia 1Spain 33 Netherlands 6 Canada 2 Norway 1UK 29 Mexico 5 Hungary 2 India 1Germany 14 Greece 4 Iran 2 Slovakia 1Japan 13 Poland 4 Korea 2 Slovenia 1Portugal 12 Switzerland 4 Romania 2Italy 9 Australia 3 Singapore 2Czech Rep. 8 Ireland 3 Austria 1France 7 China 2 Egypt 1

VI Preface

We would like to thank all the authors for submitting their first versionsof the papers and the final versions of the accepted papers. We also gratefullyacknowledge the reviewing work done by the Program Committee members andmany additional reviewers who contributed their time and expertise towards thecompilation of this volume. The members of our Program Committee and allother reviewers are listed on the following pages. We are particularly pleasedthat of the 1029 reviews sought, 95% were completed.

We would like to thank QuickSilver Technology for their sponsorship of theMichal Servit Award, Celoxica for sponsoring the official FPL websitewww.fpl.org, Xilinx and Synplicity for their early support of the conference,and Coreworks for help in registration processing. We are indebted to Richardvan de Stadt, the author of CyberChair. This excellent free software made ourtask of managing the submission and reviewing process much easier. We aregrateful for the help and advice received from Wayne Luk and Horacio Neto.In addition, we acknowledge the help of the following research students fromImperial College London in checking the integrity of the manuscripts: ChristosBouganis, Wim Melis, Gareth Morris, Andy Royal, Pete Sedcole, Nalin Sidahao,and Theerayod Wiangtong.

We are grateful to Springer-Verlag, particularly Alfred Hofmann and AnnaKramer, for their work in publishing this book.

June 2003 Peter Y.K. CheungGeorge A. Constantinides

Jose T. de Sousa

Organization

Organizing Committee

Program Chair Peter Y.K. Cheung,Imperial College London, UK

Program Co-chair George A. Constantinides,Imperial College London, UK

General Chair Jose T. de Sousa, INESC-ID/IST,Technical University of Lisbon, Portugal

Publicity Chair Reiner Hartenstein,University of Kaiserslautern, Germany

Local Chair Horacio Neto, INESC-ID/IST,Technical University of Lisbon, Portugal

Finance Chair Fernando Goncalves, INESC-ID/IST,Technical University of Lisbon, Portugal

Exhibition Chair Joao Cardoso, INESC-ID/UA,University of Algarve, Portugal

VIII Organization

Program Committee

Nazeeh Aranki Jet Propulsion Laboratory, USAJeff Arnold Stretch, Inc., USAPeter Athanas Virginia Tech, USANeil Bergmann Queensland University of Technology, AustraliaDinesh Bhatia University of Texas, USAEduardo Boemo University of Madrid, SpainGordon Brebner Xilinx, Inc., USAAndrew Brown University of Southampton, UKKlaus Buchenrieder Infineon Technologies AG, GermanyCharles Chiang Synopsys, Inc., USAPeter Cheung Imperial College London, UKGeorge Constantinides Imperial College London, UKAndre DeHon California Institute of Technology, USAJose T. de Sousa Technical University of Lisbon, PortugalCarl Ebeling University of Washington, USAHossam ElGindy University of New South Wales, AustraliaManfred Glesner Darmstadt University of Technology, GermanyFernando Goncalves Technical University of Lisbon, PortugalSteven Guccione Quicksilver Technology, USAReiner Hartenstein University of Kaiserslautern, GermanyScott Hauck University of Washington, USABrad Hutchings Brigham Young University, USATom Kean Algotronix Consulting, UKAndreas Koch University of Braunschweig, GermanyDominique Lavenier University of Montpellier II, FrancePhilip Leong Chinese University of Hong Kong, ChinaWayne Luk Imperial College London, UKPatrick Lysaght Xilinx, Inc., USABill Mangione-Smith University of California at Los Angeles, USAReinhard Manner University of Mannheim, GermanyOskar Mencer Bell Labs, USAGeorge Milne University of Western AustraliaToshiyaki Miyazaki NTT Network Innovation Labs, JapanFernando Moraes PUCRS, BrazilHoracio Neto Technical University of Lisbon, PortugalSebastien Pillement ENSSAT, FranceDhiraj Pradhan University of Bristol, UKViktor Prasanna University of Southern California, USAMichel Renovell University of Montpellier II, FranceJonathan Rose University of Toronto, CanadaZoran Salcic University of Auckland, New ZealandHartmut Schmeck University of Karlsruhe, GermanyRainer Spallek Dresden University of Technology, Germany

Organization IX

Adrian Stoica Jet Propulsion Laboratory, USAJurgen Teich University of Paderborn, GermanyLothar Thiele ETH Zurich, SwitzerlandLiones Torres University of Montpellier II, FranceStephen Trimberger Xilinx, Inc., USAMilan Vasilko Bournemouth University, UKRanga Vemuri University of Cincinnati, USARoger Woods Queen’s University of Belfast, UK

Steering Committee

Jose T. de Sousa Technical University of Lisbon, PortugalManfred Glesner Darmstadt University of Technology, GermanyJohn Gray Independent Consultant, UKHerbert Grunbacher Carinthia Technical Institute, AustriaReiner Hartenstein University of Kaiserslautern, GermanyAndres Keevallik Tallinn Technical University, EstoniaWayne Luk Imperial College London, UKPatrick Lysaght Xilinx, Inc., USAMichel Renovell University of Montpellier II, FranceRoger Woods Queen’s University of Belfast, UK

Additional Reviewers

Anuradha AgarwalAli AhmadiniaSeong-Yong AhnRui AguiarMiguel A. AguirreBashir Al-HashimiFerhat AlimJose AlvesHideharu AmanoJose Nelson AmaralDavid AntosAntonio Jose AraujoMiguel Arias-EstradaRuben ArteagaArmando AstarloaJose AugustoShailendra AulakhVicente BaenaZachary BakerJonathan BallaghSergio Bampi

Francisco BaratJorge BarreirosMarcus BednaraPeter BellowsMohammed BenaissaAbdSamad BenKridKhaled BenKridPascal BenoitManuel BerenguelDaniel BergPaul BerubeJean-Luc BeuchatRajarshee BharadwajUnai BidarteBob BlakeBrandon BlodgetJose A. BoludaVanderlei BonatoAndrea BoniMarcos R. BoschettiIgnacio Bravo

X Organization

Ney CalazansDanna CaoFrancisco Cardells-TormoJoao CardosoDylan CarlineLuigi CarroNicholas CarterGregorio CappuccinoJoaquin CerdaAbhijeet ChakrabortyFrancois CharotSeonil ChoiBobda ChristopheAlessandro CilardoChristopher ClarkJohn CochranJames CohoonStuart ColsellKatherine ComptonPasquale CorsonelloTom Van CourtOctavian CretDamian DaltonAlan DalyMartin DanekKlaus DanneEric DebesMartin DelvaiDaniel DenningArturo Diaz-PerezPedro DinizPeiliang DongCillian O’DriscollMark E. DunhamAlireza EjlaliTarek El-GhazawiPeeter EllerveeWilfried ElmenreichRolf EnzlerKen EricksonRoberto Esper-Chain FalconBela FeherMichael FergusonMarcio Merino FernandesViktor Fischer

Toshihito FujiwaraRafael Gadea-GironesAltaf Abdul GaffarFederico GarciaAlberto Garcia-OrtizEster M. GarzonManjunath GangadharAntonio GentileRaul Mateos GilRafael Gadea-GironesFederico GarciaJorn GauseFahmi GhozziGuy GogniatRichard Aderbal GoncalvesGokul GovinduGail GrayJong-Ru GuoManish HandaFrank HannigJim HarkinMartin HerbordtAntonin HermanekFabiano HesselTeruo HigashinoRoland HollerRenqiu HuangAshraf HusseinShuichi IchikawaJose Luis ImanaMinoru InamoriPreston JacksonKamakotiParivallal KannanIrwin KennedyTim KerinsJawad KhanSami KhawamDaniel KirschnerTomoyoshi KoboriFatih KocanDirk KochZbigniew KokosinskiAndrzej KrasniewskiRohini Krishnan

Organization XI

Georgi KuzmanovSoonhak KwonDavid LacasaJohn LachJesus LazaroBarry LeeDong-U LeeGareth LeeJirong LiaoValentino LiberaliBossuet LilianFernanda LimaJohn LockwoodAndrea LodiRobert LorenczMichael G. LorenzDavid Rodriguez LozanoShih-Lien LuMartin MaUsama MalikCesar Augusto MarconTheodore MarescauxEduardo MarquesL.J. McDaidPaul McHardyMaire McLooneBingfeng MeiMahmoud MeriboutUwe Meyer-BaeseYosuke MiyajimaSumit MohantyGareth MorrisElena MoscuFrancisco Moya-FernandezMadhubanti MukherjeeTudor MurganCiaron MurphyTakahiro MurookaKouichi NagamiUlrich NageldingerJeff NamkungAngel Grediaga OlivoPilar Martinez OrtigosaSelene Maya-RuedaWim Melis

Allen MichalskiMaria Jose MoureJohn NestorJiri NovotnyJohn OliverEva M. OrtigosaFernando OrtizDamjan OseliJingzhao OuMarcio OyamadaChris PapachristouFernando PardoStavros PaschalakisKolin PaulCong Vinh PhanJuan Manuel Sanchez PerezStefania PerriMihail PetrovThilo PionteckMarco PlatznerJuri PoldreDionisios N. PnevmatikatosKara PoonJuan Antonio Gomez PulidoFederico QuaglioSenthil RajamaniJavier RamirezJuergen ReichardtJavier ResanoFernando RinconFrancisco Rodriguez-HenriquezNuno RomaEduardo RosGael RouvroyAndrew RoyalGiacinto Paolo SaggeseMarcelino SantosGilles SassatelliToshinori SatoSergei SawitzkiPascal ScalartBernd ScheuermannJan SchierClemens SchlachtaKlaus Schleisiek

XII Organization

Herman SchmitDavid SchuehlerRonald ScrofanoPete SedcolePeter-Michael SeidelShay SengSakir SezerNaoki ShibataTsunemichi ShiozawaNalin SidahaoReetinder SidhuValery SklyarovIouliia SkliarovaGerard SmitRaphael SomeIoannis SourdisLionel SousaLudovico de SouzaFrancois-Xavier StandaertHenry StylesQing SuVijay SundaresanNoriyuki TakahashiShigeyuki TakanoKalle TammemaeKonstantinos TatasRaoul TawelJohn Teifel

Yann ThomaTim TodmanJon TombsCesar Torres-HuitzilKuen TsoiMarek TudrujRichard TurnerFabrizio VaccaSudhir VakaEduardo do Valle SimoesJozsef VasarhelyiJoerg VeltenFelip VicedoTanya VladimirovaMarkus WeinhardtTheerayod WiangtongJuan Manuel XicotencatlAndy YanKeiichi YasumotoPavel ZemcikXiaoyang ZengYumin ZhangJihan ZhuLing ZhuoPeter ZipfClaudiu Zissulescu-IanculescuMark Zwolinski

Table of Contents

Technologies and Trends

Reconfigurable Circuits Using Hybrid Hall Effect Devices . . . . . . . . . . . . . . . 1S. Ferrera, N.P. Carter

Gigahertz FPGA by SiGe BiCMOS Technologyfor Low Power, High Speed Computing with 3-D Memory . . . . . . . . . . . . . . . 11

C. You, J.-R. Guo, R.P. Kraft, M. Chu, R. Heikaus, O. Erdogan,P. Curran, B. Goda, K. Zhou, J.F. McDonald

Communications Applications

Implementing an OFDM Receiveron the RaPiD Reconfigurable Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

C. Ebeling, C. Fisher, G. Xing, M. Shen, H. Liu

Symbol Timing Synchronization in FPGA-Based Software Radios:Application to DVB-S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

F. Cardells-Tormo, J. Valls-Coquillat, V. Almenar-Terre

High Level Design Tools 1

An Algorithm Designer’s Workbench for Platform FPGAs . . . . . . . . . . . . . . . 41S. Mohanty, V.K. Prasanna

Prototyping for the Concurrent Developmentof an IEEE 802.11 Wireless LAN Chipset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

L. de Souza, P. Ryan, J. Crawford, K. Wong, G. Zyner, T. McDermott

Reconfigurable Architectures

ADRES: An Architecture with Tightly Coupled VLIW Processorand Coarse-Grained Reconfigurable Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

B. Mei, S. Vernalde, D. Verkest, H. De Man, R. Lauwereins

Inter-processor Connection ReconfigurationBased on Dynamic Look-Ahead Control of Multiple Crossbar Switches . . . . 71

E. Laskowski, M. Tudruj

Arbitrating Instructions in an ρµ-Coded CCM . . . . . . . . . . . . . . . . . . . . . . . . . 81G. Kuzmanov, S. Vassiliadis

XIV Table of Contents

Cryptographic Applications 1

How Secure Are FPGAs in Cryptographic Applications? . . . . . . . . . . . . . . . 91T. Wollinger, C. Paar

FPGA Implementations of the RC6 Block Cipher . . . . . . . . . . . . . . . . . . . . . . 101J.-L. Beuchat

Very High Speed 17 Gbps SHACAL Encryption Architecture . . . . . . . . . . . . 111M. McLoone, J.V. McCanny

Place and Route Tools

Track Placement: Orchestrating Routing Structuresto Maximize Routability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

K. Compton, S. Hauck

Quark Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131S.T. McCulloch, J.P. Cohoon

Global Routing for Lookup-Table Based FPGAsUsing Genetic Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

J. Barreiros, E. Costa

Multi-context FPGAs

Virtualizing Hardware with Multi-context Reconfigurable Arrays . . . . . . . . . 151R. Enzler, C. Plessl, M. Platzner

A Dynamically Adaptive Switching Fabricon a Multicontext Reconfigurable Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

H. Amano, A. Jouraku, K. Anjo

Reducing the Configuration Loading Timeof a Coarse Grain Multicontext Reconfigurable Device . . . . . . . . . . . . . . . . . . 171

T. Kitaoka, H. Amano, K. Anjo

Cryptographic Applications 2

Design Strategies and Modified Descriptionsto Optimize Cipher FPGA Implementations:Fast and Compact Results for DES and Triple-DES . . . . . . . . . . . . . . . . . . . . 181

G. Rouvroy, F.-X. Standaert, J.-J. Quisquater, J.-D. Legat

Using Partial Reconfiguration in Cryptographic Applications:An Implementation of the IDEA Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

I. Gonzalez, S. Lopez-Buedo, F.J. Gomez, J. Martinez

Table of Contents XV

An Implementation Comparison of an IDEA Encryption Cryptosystemon Two General-Purpose Reconfigurable Computers . . . . . . . . . . . . . . . . . . . . 204

A. Michalski, K. Gaj, T. El-Ghazawi

Low-Power Issues 1

Data Processing System with Self-reconfigurable Architecture,for Low Cost, Low Power Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

M.G. Lorenz, L. Mengibar, L. Entrena, R. Sanchez-Reillo

Low Power Coarse-Grained Reconfigurable Instruction Set Processor . . . . . 230F. Barat, M. Jayapala, T.V. Aa, R. Lauwereins, G. Deconinck,H. Corporaal

Encoded-Low Swing Technique for Ultra Low Power Interconnect . . . . . . . . 240R. Krishnan, J. Pineda de Gyvez, H.J.M. Veendrick

Run-Time Configurations

Building Run-Time Reconfigurable Systems from Tiles . . . . . . . . . . . . . . . . . . 252G. Lee, G. Milne

Exploiting Redundancy to Speedup Reconfiguration of an FPGA . . . . . . . . 262I. Kennedy

Run-Time Exchange of Mechatronic ControllersUsing Partial Hardware Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

K. Danne, C. Bobda, H. Kalte

Cryptographic Applications 3

Efficient Modular-Pipelined AES Implementation in Counter Modeon ALTERA FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282

F. Charot, E. Yahya, C. Wagner

An FPGA-Based Performance Analysis of the Unrolling, Tiling,and Pipelining of the AES Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292

G.P. Saggese, A. Mazzeo, N. Mazzocca, A.G.M. Strollo

Two Approaches for a Single-Chip FPGA Implementationof an Encryptor/Decryptor AES Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303

N.A. Saqib, F. Rodrıguez-Henrıquez, A. Dıaz-Perez

XVI Table of Contents

Compilation Tools

Performance and Area Modeling of Complete FPGA Designsin the Presence of Loop Transformations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

K.R.S. Shayee, J. Park, P.C. Diniz

Branch Optimisation Techniques for Hardware Compilation . . . . . . . . . . . . . 324H. Styles, W. Luk

A Model for Hardware Realization of Kernel Loops . . . . . . . . . . . . . . . . . . . . . 334J. Liao, W.-F. Wong, T. Mitra

Asynchronous Techniques

Programmable Asynchronous Pipeline Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . 345J. Teifel, R. Manohar

Globally Asynchronous Locally Synchronous FPGA Architectures . . . . . . . . 355A. Royal, P.Y.K. Cheung

Biology-Related Applications

Case Study of a Functional Genomics Applicationfor an FPGA-Based Coprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365

T. Van Court, M.C. Herbordt, R.J. Barton

A Smith-Waterman Systolic Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375C.W. Yu, K.H. Kwong, K.H. Lee, P.H.W. Leong

Codesign

Software Decelerators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385E. Keller, G. Brebner, P. James-Roxby

A Unified Codesign Run-Time Environmentfor the UltraSONIC Reconfigurable Computer . . . . . . . . . . . . . . . . . . . . . . . . . 396

T. Wiangtong, P.Y.K. Cheung, W. Luk

Reconfigurable Fabrics

Extra-dimensional Island-Style FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406H. Schmit

Using Multiplexers for Control and Data in D-Fabrix . . . . . . . . . . . . . . . . . . . 416T. Stansfield

Table of Contents XVII

Heterogeneous Logic Block Architecturesfor Via-Patterned Programmable Fabrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426

A. Koorapaty, L. Pileggi, H. Schmit

Image Processing Applications

A Real-Time Visualization System for PIV . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437T. Fujiwara, K. Fujimoto, T. Maruyama

A Real-Time Stereo Vision System with FPGA . . . . . . . . . . . . . . . . . . . . . . . . 448Y. Miyajima, T. Maruyama

Synthesizing on a Reconfigurable Chipan Autonomous Robot Image Processing System . . . . . . . . . . . . . . . . . . . . . . . 458

J.A. Boluda, F. Pardo

SAT Techniques

Reconfigurable Hardware SAT Solvers: A Survey of Systems . . . . . . . . . . . . . 468I. Skliarova, A.B. Ferrari

Fault Tolerance Analysis of Distributed Reconfigurable SystemsUsing SAT-Based Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478

R. Feldmann, C. Haubelt, B. Monien, J. Teich

Hardware Implementationsof Real-Time Reconfigurable WSAT Variants . . . . . . . . . . . . . . . . . . . . . . . . . . 488

R.H.C. Yap, S.Z.Q. Wang, M.J. Henz

Application-Specific Architectures

Core-Based Reusable Architecture for Slave Circuitswith Extensive Data Exchange Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . 497

U. Bidarte, A. Astarloa, A. Zuloaga, J. Jimenez, I. Martınez de Alegrıa

Time and Energy Efficient Matrix Factorization Using FPGAs . . . . . . . . . . . 507S. Choi, V.K. Prasanna

Improving DSP Performance with a Small Amountof Field Programmable Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520

J. Oliver, V. Akella

DSP Applications

Fully Parameterized Discrete Wavelet Packet TransformArchitecture Oriented to FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533

G. Paya, M.M. Peiro, F. Ballester, F. Mora

XVIII Table of Contents

An FPGA System for the High Speed Extraction, Normalizationand Classification of Moment Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543

S. Paschalakis, P. Lee, M. Bober

Design and Implementation of a Novel FIR Filter Architecturewith Boundary Handling on Xilinx VIRTEX FPGAs . . . . . . . . . . . . . . . . . . . 553

A. Benkrid, K. Benkrid, D. Crookes

Dynamic Reconfiguration

A Self-reconfiguring Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565B. Blodget, P. James-Roxby, E. Keller, S. McMillan, P. Sundararajan

Heuristics for Online Scheduling Real-Time Tasksto Partially Reconfigurable Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575

C. Steiger, H. Walder, M. Platzner

Run-Time Minimization of Reconfiguration Overheadin Dynamically Reconfigurable Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585

J. Resano, D. Mozos, D. Verkest, S. Vernalde, F. Catthoor

SoC Architectures

Networks on Chip as Hardware Components of an OSfor Reconfigurable Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595

T. Marescaux, J.-Y. Mignolet, A. Bartic, W. Moffat, D. Verkest,S. Vernalde, R. Lauwereins

A Reconfigurable Platformfor Real-Time Embedded Video Image Processing . . . . . . . . . . . . . . . . . . . . . . 606

N.P. Sedcole, P.Y.K. Cheung, G.A. Constantinides, W. Luk

Emulation

Emulation-Based Analysis of Soft Errors in Deep Sub-micron Circuits . . . . 616M.S. Reorda, M. Violante

HW-Driven Emulation with Automatic Interface Generation . . . . . . . . . . . . . 627M. Cakır, E. Grimpe, W. Nebel

Cache Design

Implementation of HW$im –A Real-Time Configurable Cache Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . 638

S.-L. Lu, K. Lai

Table of Contents XIX

The Bank Nth Chance Replacement Policy for FPGA-Based CAMs . . . . . . 648P. Berube, A. Zinyk, J.N. Amaral, M. MacGregor

Arithmetic 1

Variable Precision Multipliersfor FPGA-Based Reconfigurable Computing Systems . . . . . . . . . . . . . . . . . . . 661

P. Corsonello, S. Perri, M.A. Iachino, G. Cocorullo

A New Arithmetic Unit in GF(2m)for Reconfigurable Hardware Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 670

C.H. Kim, S. Kwon, J.J. Kim, C.P. Hong

Biologically Inspired Designs

A Dynamic Routing Algorithmfor a Bio-inspired Reconfigurable Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681

Y. Thoma, E. Sanchez, J.-M.M. Arostegui, G. Tempesti

An FPL Bioinspired Visual Encoding Systemto Stimulate Cortical Neurons in Real-Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 691

L. Sousa, P. Tomas, F. Pelayo, A. Martinez, C.A. Morillas, S. Romero

Low-Power Issues 2

Power Analysis of FPGAs: How Practical is the Attack? . . . . . . . . . . . . . . . . 701F.-X. Standaert, L. van Oldeneel tot Oldenzeel, D. Samyde,J.-J. Quisquater

A Power–Scalable Motion Estimation Architecturefor Energy Constrained Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712

M. Martina, A. Molino, F. Quaglio, F. Vacca

SoC Designs

A Novel Approach for Architectural Models Characterization.An Example through the Systolic Ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722

P. Benoit, G. Sassatelli, L. Torres, M. Robert, G. Cambon, D. Demigny

A Generic Architecture for Integrated Smart Transducers . . . . . . . . . . . . . . . 733M. Delvai, U. Eisenmann, W. Elmenreich

Customisable Core-Based Architecturesfor Real-Time Motion Estimation on FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . 745

N. Roma, T. Dias, L. Sousa

XX Table of Contents

Cellular Applications

A High Speed Computation System for 3D FCHC Lattice Gas Modelwith FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755

T. Kobori, T. Maruyama

Implementation of ReCSiP:A ReConfigurable Cell SImulation Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . 766

Y. Osana, T. Fukushima, H. Amano

On the Implementation of a Margolus Neighborhood Cellular Automataon FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776

J. Cerda, R. Gadea, V. Herrero, A. Sebastia

Arithmetic 2

Fast Modular Division for Application in ECC on Reconfigurable Logic . . . 786A. Daly, W. Marnane, T. Kerins, E. Popovici

Non-uniform Segmentation for Hardware Function Evaluation . . . . . . . . . . . 796D.-U. Lee, W. Luk, J. Villasenor, P.Y.K. Cheung

A Dual-Path Logarithmic Number System Addition/Subtraction Schemefor FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808

B. Lee, N. Burgess

Fault Analysis

A Modular Reconfigurable Architecture for Efficient Fault Simulationin Digital Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818

J.S. Augusto, C.B. Almeida, H.C.C. Neto

Evaluation of Testability of Path Delay Faultsfor User-Configured Programmable Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828

A. Krasniewski

Fault Simulation Using Partially Reconfigurable Hardware . . . . . . . . . . . . . . 839A. Parreira, J.P. Teixeira, A. Pantelimon, M.B. Santos, J.T. de Sousa

Switch Level Fault Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 849S.G. Miremadi, A. Ejlali

Network Applications

An Extensible, System-On-Programmable-Chip,Content-Aware Internet Firewall . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859

J.W. Lockwood, C. Neely, C. Zuver, J. Moscola, S. Dharmapurikar,D. Lim

Table of Contents XXI

IPsec-Protected Transport of HDTV over IP . . . . . . . . . . . . . . . . . . . . . . . . . . 869P. Bellows, J. Flidr, L. Gharai, C. Perkins, P. Chodowiec, K. Gaj

Fast, Large-Scale String Matchfor a 10Gbps FPGA-Based Network Intrusion Detection System . . . . . . . . . 880

I. Sourdis, D. Pnevmatikatos

Irregular Reconfigurable CAM Structures for Firewall Applications . . . . . . . 890T.K. Lee, S. Yusuf, W. Luk, M. Sloman, E. Lupu, N. Dulay

High Level Design Tools 2

Compiling for the Molen Programming Paradigm . . . . . . . . . . . . . . . . . . . . . . 900E.M. Panainte, K. Bertels, S. Vassiliadis

Laura: Leiden Architecture Research and Exploration Tool . . . . . . . . . . . . . . 911C. Zissulescu, T. Stefanov, B. Kienhuis, E. Deprettere

Communication Costs Driven Design Space Explorationfor Reconfigurable Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 921

L. Bossuet, G. Gogniat, J.-L. Philippe

From Algorithm Graph Specification to Automatic Synthesisof FPGA Circuit: A Seamless Flow of Graphs Transformations . . . . . . . . . . 934

L. Kaouane, M. Akil, Y. Sorel, T. Grandpierre

Technologies and Trends (Posters)

Adaptive Real-Time Systems and the FPAA . . . . . . . . . . . . . . . . . . . . . . . . . . . 944S. Colsell, R. Edwards

Challenges and Successes in Space Based Reconfigurable Computing . . . . . . 948M.E. Dunham, M.P. Caffrey, P.S. Graham

Adaptive Processor: A Dynamically Reconfiguration Technologyfor Stream Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 952

S. Takano

Applications (Posters)

Efficient Reconfigurable Logic Circuitsfor Matching Complex Network Intrusion Detection Patterns . . . . . . . . . . . . 956

C.R. Clark, D.E. Schimmel

FPGAs for High Accuracy Clock Synchronizationover Ethernet Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 960

R. Holler

XXII Table of Contents

Project of IPv6 Router with FPGA Hardware Accelerator . . . . . . . . . . . . . . . 964J. Novotny, O. Fucık, D. Antos

A TCP/IP Based Multi-device Programming Circuit . . . . . . . . . . . . . . . . . . . 968D.V. Schuehler, H. Ku, J. Lockwood

Tools (Posters)

Design Flow for Efficient FPGA Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . 972R.H. Turner, R.F. Woods

High-Level Design Tools for FPGA-Based Combinatorial Accelerators . . . . 976V. Sklyarov, I. Skliarova, P. Almeida, M. Almeida

Using System Generatorto Design a Reconfigurable Video Encryption System . . . . . . . . . . . . . . . . . . . 980

D. Denning, N. Harold, M. Devlin, J. Irvine

MATLAB/Simulink Based Methodology for Rapid-FPGA-Prototyping . . . . 984M. Lıcko, J. Schier, M. Tichy, M. Kuhl

FPGA Implementations (Posters)

DIGIMOD: A Tool to Implement FPGA-Based Digital IFand Baseband Modems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 988

J. Marın-Roig, V. Torres, M.J. Canet, A. Perez, T. Sansaloni,F. Cardells, F. Angarita, F. Vicedo, V. Almenar, J. Valls

FPGA Implementation of a Maze Routing Accelerator . . . . . . . . . . . . . . . . . . 992J.A. Nestor

Model Checking Reconfigurable Processor Configurationsfor Safety Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 996

J. Cochran, D. Kapur, D. Stefanovic

A Statistical Analysis Tool for FPLD Architectures . . . . . . . . . . . . . . . . . . . .1000R. Huang, T. Cheung, T. Kok

Video and Image Applications (Posters)

FPGA-Implementation of Signal Processing Algorithmsfor Video Based Industrial Safety Applications . . . . . . . . . . . . . . . . . . . . . . . . .1004

J. Velten, A. Kummert

Configurable Hardware Architecturefor Real-Time Window-Based Image Processing . . . . . . . . . . . . . . . . . . . . . . . .1008

C. Torres-Huitzil, M. Arias-Estrada

Table of Contents XXIII

An FPGA-Based Image Connected Component Labeller . . . . . . . . . . . . . . . .1012K. Benkrid, S. Sukhsawas, D. Crookes, A. Benkrid

FPGA Implementation of Adaptive Non-linear Predictorsfor Video Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1016

R. Gadea-Girones, A. Ramirez-Agundis, J. Cerda-Boluda,R. Colom-Palero

Reconfigurable and Low-Power Systems (Posters)

Reconfigurable Systems in Education . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1020V. Sklyarov, I. Skliarova

Data Dependent Circuit Design: A Case Study . . . . . . . . . . . . . . . . . . . . . . . .1024S. Yamamoto, S. Ichikawa, H. Yamamoto

Design of a Power Conscious, Customizable CDMA Receiver . . . . . . . . . . . .1028M. Martina, A. Molino, M. Nicola, F. Vacca

Power-Efficient Implementations of Multimedia Applicationson Reconfigurable Platforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1032

K. Tatas, K. Siozios, D. Soudris, A. Thanailakis

Design Techniques (Posters)

A VHDL Library to Analyse Fault Tolerant Techniques . . . . . . . . . . . . . . . .1036P.M. Ortigosa, O. Lopez, R. Estrada, I. Garcıa, E.M. Garzon

Hardware Design with a Scripting Language . . . . . . . . . . . . . . . . . . . . . . . . . . .1040P. Haglund, O. Mencer, W. Luk, B. Tai

Testable Clock Routing Architecturefor Field Programmable Gate Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1044

L.K. Kumar, A.J. Mupid, A.S. Ramani, V. Kamakoti

Neural and Biological Applications (Posters)

FPGA Implementation of Multi-layer Perceptronsfor Speech Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1048

E.M. Ortigosa, P.M. Ortigosa, A. Canas, E. Ros, R. Agıs, J. Ortega

FPGA Based High Density Spiking Neural Network Array . . . . . . . . . . . . . .1053J.M. Xicotencatl, M. Arias-Estrada

FPGA-Based Computation of Free-Form Deformations . . . . . . . . . . . . . . . . .1057J. Jiang, W. Luk, D. Rueckert

XXIV Table of Contents

FPGA Implementations of Neural Networks –A Survey of a Decade of Progress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1062

J. Zhu, P. Sutton

Codesign and Embedded Systems (Posters)

FPGA-Based Hardware/Software CoDesign of an Expert System Shell . . . .1067A. Netin, D. Roman, O. Cret, K. Pusztai, L. Vacariu

Cluster-Driven Hardware/Software Partitioning and Scheduling Approachfor a Reconfigurable Computer System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1071

T. Wiangtong, P.Y.K. Cheung, W. Luk

Hardware-Software Codesignin Embedded Asymmetric Cryptography Application – A Case Study . . . . .1075

M. Simka, V. Fischer, M. Drutarovsky

On-chip and Off-chip Real-Time Debuggingfor Remotely-Accessed Embedded Programmable Systems . . . . . . . . . . . . . . .1079

J. Harkin, M. Callaghan, C. Peters, T.M. McGinnity, L. Maguire

Reconfigurable Systems and Architectures (Posters)

Fast Region Labeling on the Reconfigurable Platform ACE-V . . . . . . . . . . . .1083C. Schmidt, A. Koch

Modified Fuzzy C-Means Clustering Algorithmfor Real-Time Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1087

J. Lazaro, J. Arias, J.L. Martın, C. Cuadrado

Reconfigurable Hybrid Architecture for Web Applications . . . . . . . . . . . . . . .1091D. Rodrıguez Lozano, J.M. Sanchez Perez, J.A. Gomez Pulido

DSP Applications (Posters)

FPGA Implementation of the Adaptive Lattice Filter . . . . . . . . . . . . . . . . . . .1095A. Hermanek, Z. Pohl, J. Kadlec

Specifying Control Logic for DSP Applications in FPGAs . . . . . . . . . . . . . . .1099J. Ballagh, J. Hwang, H. Ma, B. Milne, N. Shirazi, V. Singh, J. Stroomer

FPGA Processor for Real-Time Optical Flow Computation . . . . . . . . . . . . . .1103S. Maya-Rueda, M. Arias-Estrada

A Data Acquisition Reconfigurable Coprocessorfor Virtual Instrumentation Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1107

M.D. Valdes, M.J. Moure, C. Quintans, E. Mandado

Table of Contents XXV

Dynamic Reconfiguration (Posters)

Evaluation and Run-Time Optimizationof On-chip Communication Structures in Reconfigurable Architectures . . . .1111

T. Murgan, M. Petrov, A.Garcıa Ortiz, R. Ludewig, P. Zipf, T. Hollstein,M. Glesner, B. Oelkrug, J. Brakensiek

A Controlled Data-Path Allocation Modelfor Dynamic Run-Time Reconfiguration of FPGA Devices . . . . . . . . . . . . . . .1115

D. Carline, P. Coulton

Architecture Template and Design Flow to Support Application Parallelismon Reconfigurable Platforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1119

S. Sawitzki, R.G. Spallek

Efficient Implementation of the Singular Value Decompositionon a Reconfigurable System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1123

C. Bobda, K. Danne, A. Linarth

Arithmetic (Posters)

A New Reconfigurable-Oriented Method for Canonical Basis Multiplicationover a Class of Finite Fields GF(2m) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1127

J.L. Imana, J.M. Sanchez

A Study on the Design of Floating-Point Functions in FPGAs . . . . . . . . . . .1131F.E. Ortiz, J.R. Humphrey, J.P. Durbano, D.W. Prather

Design and Implementation of RNS-Based Adaptive Filters . . . . . . . . . . . . .1135J. Ramırez, U. Meyer-Base, A. Garcıa, A. Lloris

Domain-Specific Reconfigurable Array for Distributed Arithmetic . . . . . . . .1139S. Khawam, T. Arslan, F. Westall

Design and Implementations 1 (Posters)

Design and Implementation of Priority Queuing Mechanism on FPGAUsing Concurrent Periodic EFSMs and Parametric Model Checking . . . . . .1145

T. Kitani, Y. Takamoto, I. Naka, K. Yasumoto, A. Nakata, T. Higashino

Custom Tag Computation Circuit for a 10Gbps SCFQ Scheduler . . . . . . . . .1149B. McAllister, S. Sezer, C. Toal

Exploiting Stateful Inspection of Network Securityin Reconfigurable Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1153

S. Li, J. Tørresen, O. Sørasen

XXVI Table of Contents

Propose of a Hardware Implementation for Fingerprint Systems . . . . . . . . . .1158V. Bonato, R.F. Molz, J.C. Furtado, M.F. Ferrao, F.G. Moraes

Design and Implementations 2 (Posters)

APPLES: A Full Gate-Timing FPGA-Based Hardware Simulator . . . . . . . .1162D. Dalton, V. Bessler, J. Griffiths, A. McCarthy, A. Vadher, R. O’Kane,R. Quigley, D. O’Connor

Designing, Scheduling, and AllocatingFlexible Arithmetic Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1166

V.V. Kumar, J. Lach

UNSHADES-1: An Advanced Toolfor In-System Run-Time Hardware Debugging . . . . . . . . . . . . . . . . . . . . . . . . .1170

M.A. Aguirre, J.N. Tombs, A. Torralba, L.G. Franquelo

Author Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1175