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ITk Interlock SystemToDo list Hardware from FDR

January 05, 2021

what remains from the hardware todo list

• test of T2I card in final crate with final power supplies in order to reproduce noise measurements, to be done in Montreal!

• operation of Mon-FPGA in Montreal and Wuppertal crate

• derogation for non halogen-free power supply

• complete LISSY documentation (A32, A33, A35)

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from previous meetings

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ToDo List from FDR: T2I module

• R-17: The T2I module has an extra one-channel ADC (10 bit) to monitor the value of the T-HI threshold. The T-ERR threshold should be monitored as well.• done

• R-18: It was discussed that according to experience from ID operation the temperature sensors in the SCT usually failed with shorts, while those in Pixels failed open. The present design of the T2I module detects opens but not shorts. Should the design be changed to also detect shorts?• no (after discussion with Peter P.)

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ToDo List from FDR: T2I module

• R-19: The T2I card uses a voltage reference AD680 to bias the on-detector NTCs (and as the ADC reference). The data sheet for this device specifies 100 nF input coupling capacitance which is not shown on the schematic, and should be added.• done

• R-20: For the LISSY crate a specification should be added for T2I module, namely that the power supply Vref listed in figure 2.1 is not a noise source for the detector. This supply is the one exception that was made to floating supplies referenced at the detector, as well as allowing an exception for the cables from PP1 to the NTC to be unshielded because of harnessing complexity at PP1. Of course, the capacitance of the 100 m of cable and the filter caps at PP1 will improve the noise suppression.• first measurements available

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ToDo List from FDR: T2I module

• A-21: The Vref input capacitors specified on the ADC AD7998 data sheet (“0.1 μF and 1 μF capacitors should be placed between REFIN and AGND”) have been omitted because the voltage reference AD680 specifies a maximum capacitive load of 50 nF to avoid disrupting the stability of the reference. The team should check the reproducibility (noise) of NTC measurements in the existing design: whilst the necessary precision has been demonstrated across the operational temperature range (page 10 of "IO modules” presentation) error bars were not shown. Any instability of the voltage reference would be expected to show as irreproducibility of the ADC data. The test results should be shown, perhaps scope measurements also, to demonstrate that the design, which does not conform to the ADC data sheet, will be stable in operation, in both fully loaded (16 NTC) and minimally loaded (1 NTC) configurations.• T2I module with new ADC available, tested in Wuppertal successfully

• 2 modules are sent to Montreal for measurement inside the final crate to confirm the Wuppertal measurements

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ToDo List from FDR: T2I module

• R-22: The AD680 incorporates a built-in PTAT temperature sensor. The sensor is used internally to provide the quoted (excellent) temperature stability of the reference. Perhaps this node could be buffered and monitored to provide temperature monitoring within the crate.• AD780 will be used, temperature sensor can be read out, but more an estimate

than a precision measurement

• R-23: The T2I, OUT and GSS modules all use the same LF33CDT voltage regulator, yet its input coupling capacitance is different on T2I (470 nF) from the other two boards (2.2 μF). The data sheet specifies a minimum of 100 nF, so this is all fine. Nevertheless it should be clarified why different capacitors are used.• historical reason, all the same now, everywhere 2.2 μF

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ToDo List from FDR: OUT module

• A-24: The specification defines a voltage level above 3.0 V as “OK” and a level below 0.45 V as “Interlock”. It cannot remain unspecified what voltage levels of 0.45 V < U < 3.0 V correspond to. Similar ambiguities exist in the specifications of other modules as well.

• U ≧ 3.0 V OK

• 0.45 V < U < 3.0 V undefined, not allowed (will be kicked out during QC)

• U < 0.45 V Interlock

• done

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ToDo List from FDR: Mon-FPGA module

• A-26: Two prototype Mon-FPGA modules have been built, the one at Wuppertal is working, the one at Montreal is not. No Mon-FPGA module was available to be included in the long-term test of the prototype interlock system at Wuppertal. Tests of prototype Mon-FPGA modules shall be completed before finalizing the pre-production design for fabrication.

• On fabrication, delivery expected 18/11/2020, FPGAs & power supply mounted, other components will be mounted in-house

• R-27: The Mon-FPGA module uses an Intel/ALTERA MAX10M16F256-7 FPGA, which has 53% LE resources usage with the current firmware, which appears somewhat marginal. The team should consider to use a pin-compatible FPGA with larger capacity, e.g. the MAX10M25F256-7.

• Prototypes with 2x 10M50, 2x 10M25

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ToDo List from FDR: ILK-FPGA module

• R-28: The ILK-FPGA module uses a Trenz Electronic TE0712 SoM with Xilinx Artix 7 A35T/100T/200T FPGA. The current firmware design has 30% LUT resources usage with A200T FPGA. The panel recommends to stay with the A200T FPGA instead of changing to A100T in order to ensure sufficient capacity for future firmware development.• ok

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ToDo List from FDR: PCB design and electrical testing

• A-29: For the PCBs of all interlock modules halogen-free material must be used, which is widely available today. “Traditional” FR4 typically employs bromine to facilitate flame-resistant properties and is not allowed in CERN’s underground installations. This comprises UX15 as well as USA15 and US15. If the use of problematic materials cannot be avoided, a derogation must be sought and obtained through ATLAS Safety (Laetitia Bardo) who is also available for general help and advice.

• will be added to the tender offer for PCBs

• HSE fire experts will be asked for available solutions, if not possible Laetitia will start derogation process.

• Halogen-free FR4 available

• R-30: The PCBs should be designed and fabricated to IPC class 3 except the FPGA area on Mon-FPGA where IPC class 2 is necessary for routing of traces between vias.

• will be added to the tender offer for PCBs, also for Mon-FPGA!

• R-31: The PCB E-test should be tested to IPC356 netlist generated by layout design software, not tested to Gerber data provided to PCB vendors. This will allow catching mismatch between layout design and Gerber data in rare cases.

• will be added to the tender offer for PCBs

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ToDo List from FDR: Hardware – crates and power supplies

• A-32: Backplane, crate mechanics, and power supply design shall be better documented in AT2-IE-ES-0007, e.g. connections between two backplanes for power and monitoring, power sharing, hot swapping, monitoring signals, alternative vendors, etc. It is understood that the power sharing module has not been prototyped yet; the prototype should be completed and tested soon and before finalizing the design for pre-production.

• Nick is working on the documents, 10 more days needed

• A-33: A summary of all the monitored parameters and status information from the power supply shall be added to the specification document.

• See above

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ToDo List from FDR: Hardware – crates and power supplies

• R-34: In addition to a good/bad status signal it is recommended to monitor the current from each power supply and their temperatures. The Mon-FPGA has spare ADC channels which should be used for this purpose, although they would need to be routed to (and through) the crate backplane. Another option for crate temperature monitoring may be to route an I2C bus to the power sharing module and to digitize power pack voltages, temperatures, and status lines there. In this case, existing backplane lines (e.g. status) could be re-used for the I2C bus.

• Monitoring of voltages with 4 ADCs at the PS and PS temperature

• PGOOD conditions to be defined

• A-35: The QA/QC test plans for each manufactured crate shall be documented.

• See presentation by Nick.

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ToDo List from FDR: Hardware – crates and power supplies

• R-36: The data sheet for the suggested power supply, MSP-100-5, quotes 80 mV p-p ripple. The frequency range is not specified. However, this measurement is subject to the usual caveat: "Ripple and noise are measured at 20 MHz of bandwidth by using a 12” twisted-pair wire terminated with a 0.1 μF and 47 μF parallel capacitor." Whilst the linear regulators on the T2I modules will give good isolation between the NTCs and any noise on the 5 V power supplies, the team should consider to add a 47 μF capacitor on the power switching card to help clean up the low end of the spectrum.

• Capacitors have been added.

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