Interleaving Test Algorithm for Subthreshold Leakage-Current Defects in DRAM Considering the Equal...

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1

Interleaving Test Algorithm for SubthresholdLeakage-Current Defects in DRAM Considering

the Equal Bit Line StressHyoyoung Shin, Youngkyu Park, Gihwa Lee, Jungsik Park, and Sungho Kang, Member, IEEE

Abstract— Since the minimum feature size of dynamic RAMhas been down-scaled, several studies have been carried out todetermine ways to protect cell data from leakage current in manyareas. In the field of testing, more appropriate test algorithmsare required to detect weak cells with leakage-current sources.In this paper, we propose an interleaving test algorithm thattakes into account the equal bit-line stress regardless of the celllocation. The proposed test algorithm allows screening of weakcells that cannot hold cell data due to the subthreshold leakagecurrent. During the stress period, the algorithm can also detectother leakage currents. This paper presents the maximum stressdifferences according to the cell location, and determines theinfluence of the refresh operation on the maximum stress time.Therefore, this paper suggests a correlation between the refreshand read time to give maximum stress time.

Index Terms— Bit-line stress time, maximum stress time,subthreshold leakage-current defect, test algorithm.

I. INTRODUCTION

FOR more than four decades, the simple structure of thedynamic RAM (DRAM) cell and continuous improve-

ment in lithography and dry-etching technology has madeDRAM grow exponentially in a large-scale integration andhas decreased the minimum feature size in memory chips [1].For better performance and lower power consumption, thememory chip has been scaled down every year. The 2010 ITRSroadmap reports that the minimum feature size of DRAMwill be 20 nm in 2017 and 10 nm in 2023 [2]. However,with this down-scaling trend of the minimum feature size andpower, many problems (capacitor/word line/bit-line bridges,coupling noise, P-MOS/N-MOS ratio, leakage current, and soon) need to be considered. Furthermore, due to the demandsof higher density and speed, the leakage-current problem

Manuscript received March 5, 2012; revised January 1, 2013; acceptedMarch 14, 2013. This work was supported by the National ResearchFoundation of Korea Funded by the Korea Government under Grant2012R1A2A1A03006255.

H. Shin is with the Department of Electrical and Electronics Engineer-ing, Yonsei University, Seoul 120-749, Korea, and also with the Manufac-turing Division, Hynix Semiconductor, Inc., Gyounggi-do 467-701, Korea(e-mail: [email protected]).

Y. Park and S. Kang are with the Department of Electrical and Elec-tronics Engineering, Yonsei University, Seoul 120-749, Korea (e-mail:[email protected]; [email protected]).

G. Lee and J. Park are with the Manufacturing Division, HynixSemiconductor, Inc., Ichon-si, Gyounggi-do 467-701, Korea (e-mail:[email protected]; [email protected]).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TVLSI.2013.2255628

has recently become more serious. With the short length ofthe word-line channel, the subthreshold leakage current willincrease more. To prevent this subthreshold leakage-currentproblem, channel doping should be increased in order tomaintain adequate control of short-channel effects. However,junction leakage current due to band-to-band tunneling andgate-induced drain leakage current may increase as a result ofhigh channel doping. The variability of the threshold voltagecan also increase due to defects resulting from manufacturingaberrations [3]–[7].

To detect these complicated defects, it is necessary to ana-lyze the fail mechanism and find appropriate test algorithms.Conventional DRAM testing can be grouped into retentiontesting and functional testing [8]. Retention testing is a testmethod that screens leakage-current defects by operating readand write functions containing a particular delay time. In func-tional testing, March elements that are a finite sequence of reador write operations applied to a cell in memory before pro-ceeding to the next cell are conducted on each memory cell inorder to detect the cell-to-cell bridge and coupling noise. Dueto the flexibility of these March elements, most built-in selftest (BIST) architectures adopt functional test algorithms usingthe conventional March elements [9], [10]; but with the down-scaling of the device, conventional March testing cannot prop-erly detect the leakage-current defects, and these defects haveto be assessed using the time-consuming stress method. Totest for leakage-current defects, several studies have attemptedto implement retention testing using special techniques. Theword-line-pulsing technique has been proposed as a meansof detecting weak cells by coupling nearby neighbor wordlines [11]. This technique results in an adjustable test stressbased on setting the word-line enable time. This method can beused to detect subthreshold leakage-current defects; but whenit is used in DRAM, it has to consider stress equality accordingto the cell location during the stress enable time. Marchcomplex read faults (CRF, which is also suggested in staticRAM) detects faulty cells induced by the leakage current usingthe voltage gap between the bit line and the target cell withopposite data [12]. However, according to our experimentalresults, March CRF has lower screenability than the word-line pulsing technique. X-direction-Extended March C- andY -direction MATS are proposed to screen retention faultsusing self-refresh and time delay in eDRAM [13], but thesestudies mainly deal with detecting retention faults and analyz-ing the relationship between the leakage current and temper-ature. They do not focus on the subthreshold leakage-current

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2 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

defects. A large V DS data retention test is also proposed todetect leakage-current defects in DRAM [14]. However, mostof the previous works have not considered stress differencesamong cells caused by cell locations due to the refreshoperation of DRAM. Therefore, the quality problems canoccur. Thus, a more powerful screening technique is neededto detect subthreshold leakage-current defects.

This paper proposes a new efficient test algorithm for equalbit-line stress in order to screen for subthreshold leakage-current defects. During the stress time, the algorithm candetect other leakage-current defects. First, the leakage-currentsources and scrambling technique are discussed, and then theproposed test algorithm operation is explained. The influenceof the refresh operation is investigated, and the stress time ofthe proposed test algorithm is simulated taking into accountDRAM refresh. In terms of equal bit-line stress, a correlationbetween the refresh and read time is suggested. Finally, thetest results are discussed to demonstrate the performance ofthe new test algorithm.

This paper is organized as follows. Section II introduces thesimplified DRAM architecture, which is an essential guide fordetermining the solution to equal bit-line stress. Sections IIIand IV explain the new test algorithm and the simulationresults. Finally, Section V concludes the paper.

II. BACKGROUND

A. Main Leakage-Current Sources

The gate-oxide thickness needs to be decreased to improvegate controllability and short-channel behavior, and the dopingconcentration needs to be increased to maintain the electricfield; however, the smaller the device becomes, the more easilythe leakage-current defects occur. In order to screen theseleakage-current defects, primary leakage-current sources needto be classified and analyzed. There are several leakage-currentsources that affect the retention time of the cell capacitor [3].The main leakage-current sources of DRAM are shown inFig. 1. The tunneling leakage current into and through thegate oxide occurs in proportion to the reduction of the gate-oxide thickness, and subthreshold leakage current occurs withlow subthreshold voltage due to the low concentration of theminority carrier and the decrease in gate width. P-mos N-mos(P-N) junction leakage current is caused by the high electricfield of the depletion region.

Generally, in order to find defects early and more eas-ily, the worst operation environment must be induced. Forexample, voltage gap, delay time, repeated march operation,temperature, humidity, and other conditions can be applied.In this sense, cells that are weak due to the leakage currentcan be detected by increasing the voltage gap between theleakage-current sources in order to more easily accelerate theflow of leakage current at high temperatures. The tunnelingleakage-current into and through the gate oxide can be detectedby applying a high voltage to the gate while writing a lowvoltage to the cells. Subthreshold leakage-current and P-Njunction-leakage current can also be detected using the highvoltage difference between the drain and the source orbody.

Fig. 1. Main leakage current sources of DRAM.

In addition to the voltage gap, the time delay is usually usedto find weak cells that leak marginally at a certain time. Thistime-delay method lengthens the test time, but is necessaryto guarantee device quality. Therefore, the proper time delayshould be considered according to the customer’s needs forsatisfying the quality.

B. Basic Cell Array

The gates of the DRAM cells are tied to the row decoder,and the bit-line pairs are connected to the sense amplifier, asshown in Fig. 2 [15]. A sense amplifier is composed of a pairof cross-connected inverters between the bit lines. When theaddress and row access signal (RAS) instruction are loaded tothe device, each row of the selected cells is active. In thisoperation, the data stored in the cells of the selected rowaddress are amplified and stored again by the sense amplifiers.This operation of an RAS instruction to read or write is likethe DRAM refresh operation, which is activated periodicallyto store the cell data. When the address and column accesssignal (CAS) instruction are transferred, the selected columncells of the activated row cells are accessed. Through theseoperations, the desired data can be read or written via the Dinor Dout pin.

The bit-line pairs are connected in parallel to the senseamplifier to reduce the bit-line coupling noise. This arrayarchitecture is called the folded bit-line array. This arrayusually has a small feature size of 8F2 (F : feature size),and has proven to be the most reliable design. Another arrayscheme called the open bit-line array [16], [17] has smallerfeature sizes (6F2 or 4F2) than the folded bit line. Thisscheme has high density and cell efficiency, and is also usedwhen reducing the number of word lines to ease the impactof a bit-line interference noise on DRAM scaling. But thereis no difference in operating the DRAM cells between thefolded bit line and open bit-line architecture. Therefore, thefolded bit-line array architecture is used in this paper for betterunderstanding.

C. Scrambling

The logical structure differs from the physical internalstructure of the chip to optimize the memory layout moreefficiently [18]. Therefore, logically adjacent addresses maynot be physically adjacent. This is called address scrambling.


SHIN et al.: TEST ALGORITHM FOR SUBTHRESHOLD LEAKAGE-CURRENT DEFECTS IN DRAM 3

Fig. 2. Simplified DRAM diagram.

Fig. 3. Address and data scrambling.

Likewise, data scrambling means that logically adjacent dataare not physically adjacent. Fig. 3 shows the twisted addressline between the physical and logical addresses and the datastatus when the value of 0 is transferred to the cells withoutusing scrambling scheme. In this case, the logical address ofWL4, 5, 6, and 7 is different from the physical address dueto the efficiency of the memory layout. And in case of thememory cell, which is based on the bit line, the inverted dataare written into the cells connected to the bit bar line.

When a test algorithm is implemented, different types ofdata backgrounds are used and Fig. 4 shows commonly useddata backgrounds (DB), which are listed below.

1) Solid: All cells are filled with “0.”2) 1-Row Bar: Alternating between “0” and “1,” all cells

are written in the row direction.3) 1-Column Bar: Alternating between “0” and “1,” all cells

are written in the column direction.

Fig. 4. Commonly used data background [14].

(a)

WL0

WL1

WL2

WL3

DataData

1

1

SenseAmplifier

Data Data

1

1

0

0

SenseAmplifier

a

0

0

r

WL0

WL1

WL2

WL3

DataDat

0

0

SenseAmplifie

Data Data

0

0

0

0

SenseAmplifier

ta

0

0

er

(b)

Fig. 5. Scrambling enabled scheme. (a) 1-Row Bar data background. (b) Soliddata background.

4) 2-Row Bar: Alternating between a pair of “0” and “1,”all cells are written in the row direction.

It is necessary to write a proper background data fortest algorithms. For example, when data value 0 is writtento the cells, the 1-Row Bar data background is physicallyimplemented, as shown in Fig. 5(a). As mentioned previously,the inverted data are written into the cells connected to thebit bar line and the directed data are written into the cellsconnected to the bit line. But the Solid data background canbe implemented by using the scrambling enabled scheme.When the scrambling enabled scheme is used, the scramblingscheme makes changed the data connected in the bit bar lineto the inverted data, as shown in Fig. 5(b). Therefore by usingthe scrambling-enabled scheme, the intended data of “0” canbe written physically to the cells. In this paper, only datascrambling is considered for better understanding.

III. PROPOSED NEW-TEST ALGORITHM

A. Concept

The concept of the proposed test algorithm is shown inFig. 6. This simplified DRAM array is composed of eightrows and one column, and is implemented using a 2-Row Bardata background with scrambling enabled. Cells of word lines0, 1, 4, and 5 are stored as “0,” and cells of word lines2, 3,6, and 7 are stored as “1.” During the read operation of thefirst word line, the data stored as “0” is transferred to the bit



Fig. 6. Concept of the proposed test algorithm.

line through the gate transistor. The sense amplifier then pullsdown the bit line to “0” and pulls up the bit bar line to “1.”

When the first word line is activated at a specified time, thebit-line cells stored as “1” are stressed during the activatedtime because of the voltage difference between the cell dataand the voltage level of the bit line. The stress of the cellsstored at the same voltage level as the bit line can be ignoredbecause that stress is very small compared with that of cellsstored at a different voltage level. Cells stored as “0” data atthe bit bar line are also stressed by the voltage difference withthe bit bar line. If the first word line is activated more thana certain number of times, then the cells stored as oppositedata with the bit line and bit bar line are stressed during theactivated time. If cells have a defect caused by the thresholdleakage-current, the defect-cell data are easily changed tothe opposite value during the stress time. Furthermore, thesedefects can be detected by setting an appropriate activatedtime of the word line depending on screenability in order tooptimize the test conditions.

B. Statistical Analysis Model

In order to estimate the stressability of memory cells, it isnecessary to calculate the stress intensity using a mathematicalexpression. When a word line is selected, the selected celldata (Dk) is transferred to the sense amplifier through thebit lines or bit bar lines. The sense amplifier then pulls thebit line or bit bar line to the data level of the selected cell.During the activated time of the word line k, the cell i receivesthe stress that causes the subthreshold leakage-current. Thus,the maximum stress time (MSTi ) of cell i can be defined asfollows:

MSTi = Maximum

{i−1∑k=0

Sk Rt ,

N−1∑k=i+1

Sk Rt

}(1)

where Sk indicates the stress effect of each cell k, Rt is theread time when the word line of cell k is activated, and N isthe number of word lines per sense amplifier. If the stored celldata of i differs from the bit line or bit bar line transferredfrom the activated cell data k (Di �= Dk ), then the stress effectis available. Thus, the stress effect of Sk can be expressed as 1.

On the contrary, if Di = Dk , then Sk can be expressedas 0, and Rt can be set depending on the screen conditionof the subthreshold leakage-current. Thus, it is necessaryto determine the appropriate read-time conditions consider-ing the quality level, test time, and screenability. Note thatMSTi of cell i is initialized when the read operation ofcell i is activated because of the recharge operation by thesense amplifier. MSTi is also initialized during the periodicrefresh operation.

Suppose that Di �= Dk in any cell k (k �= i ). When theread operation of the WL0 cell is performed, cell i is stressedduring time Rt . Also, during the next read operation time ofthe WL1 cell, cell i undergoes stress that accumulates to thestress value of WL0. After all, before the read operation ofcell i , the stress time of cell i is the sum of the read operationtime of cell k (0 to i − 1), and when the read operation of thei th (that is k = i ) WL cell is conducted, the cumulative stresstime of cell i is initialized to zero. In the next read operationof cell k(= i+1), cell i is stressed again. After the word-lineactivation of cell i+1, cell i is stressed as much as the sum ofthe read operation time of cell k (i+1 to N − 1). As a result,MSTi is the larger of the two stress times caused by cells 0to i − 1 and i+1 to N − 1{

↑ (wa) ; ↑ (ra (t) ,wa) ; ↑ (ra)}

(2)

where

wa write operation (data “a” to the cell);wa write operation (inverse data “a” to the cell);ra read operation (expected value is “a”);ra read operation (expected value is inverse data “a”);ra(t) read operation during t time (= Rt ).

When the test algorithm in (2) is applied using a solid databackground with data scrambling, the MSTi of cell i can becalculated as follows. As shown in Fig. 7, cell i is on the evenword line and is connected to the bit line. By the operationof (wa), all cells are written as “0.” When the read operationof even cells is performed, the bit line is charged to “0” dueto the activated cell data. Thus, cell i is not stressed becausethe cell data of I are the same as the activated cell data ofk (Di = Dk ) shown in Fig. 7(a). However, if the read operationof odd cells is activated, cell i is stressed because the bit lineis charged to “1” due to the activated odd cell data on the bitbar line shown in Fig. 7(b).

In other words, when the activated cells k (0 ≤ k ≤ N − 1)are on odd word lines (2 j + 1(0 ≤ j ≤ N/2 − 1)), cell i isstressed. And when the activated cells are on even word lines(2 j (0 ≤ j ≤ N/2 − 1)), cell i is not stressed. Thus, the stresseffects of the activated even word lines S2 j and activated oddword lines S2 j+1 are expressed as follows:

S2 j = 0, S2 j+1 = 1. (3)

After all, MSTi of cell i is defined as follows when cell iis connected with even word lines (i is even):

MSTi = Max

⎧⎨⎩

i/2−1∑j=0

(S2 j+1)Rt ,

N/2−1∑j=i/2

(S2 j+1)Rt

⎫⎬⎭ .



(a) (b)

Fig. 7. Read operation is applied by solid data background with datascrambling. (a) When even cells are activated. (b) When odd cells areactivated.

If cell i is connected with odd word lines, it is stressed onlywhen even word lines (2 j ) are activated (so S2 j+1 = 0). Asa result, MSTi is defined as follows (i is odd):

MSTi = Max

⎧⎨⎩

(i−1)/2∑j=0

(S2 j )Rt ,

N/2−1∑j=(i+1)/2

(S2 j )Rt

⎫⎬⎭ .

If the test algorithm is applied by a solid data backgroundwith disabled data scrambling, cell i is not stressed in anycase (Sk = 0). After all, the MSTi of cell i is zero whenusing a specific data background with scrambling. Table Isummarizes the MSTi values of cell i according to algorithms,data background, and data scrambling. This analysis indicatesthat the MSTi of cell i differs according to the cell locationin all cases of data background and scrambling. Note thatcalculation of the summarized MSTi results in Table I canvary as a function of the value of i . Thus, Table I is justexpressed when i is a multiple of 4 to make the values of i/2and i/4 to an integer (for example i = 0, 4, 8, 12, . . .).

The operations of DRAM are reading the data stored in thecells, writing data in the device, and refreshing periodically tomaintain the cell data. DRAM manufacturers typically specifythat the refresh operation must be conducted every 64 ms orless, as defined by the JEDEC. However, in order to guaranteebetter than required refresh time, the refresh test is conductedmore strictly by most manufacturers.

To simulate the MSTi results, we first estimated the stress-ability of memory cells according to the cell location asexplained earlier and derived the mathematical expression inTables I and II considering the data background and scram-bling. Our experiment applies the burst refresh method [19],which is conducted by a simplified DRAM model consistingof 64 rows and 16 sense amplifiers, for a total of 1024 cells.For easy simulation, the read operation time of the cells is setto 1 µs. Based on this analysis, the MSTi of Tables I and IIare applied according to the cell location and the results of

(a)

(bb)

Fig. 8. MSTi simulation results. (a) MSTi difference according to the databackground. (b) MSTi of cell i when refresh time is 112.

several MSTi experiments considering that the refresh timesare shown in Fig. 8. The MSTi result in Fig. 8(b) has ahigh variance compared with the MSTi result in Fig. 8(a)in condition of 1 Row Bar data background with scramblingenabled because of the refresh operation [the refresh cycle ofFig. 8(a) is 48 and that of Fig. 8(b) is 112, and the value ofthe refresh cycle is relative].

As shown in Fig. 8, it can be known that the variation inMSTi differs depending on the data background, scrambling,and refresh conditions.

C. Proposed Interleaving Mode

To overcome the variation in MSTi , a new test algorithmis proposed based on the previous model. In the proposedalgorithm, an interleaving mode that jumps the word line +2is used. The algorithm is as follows:

↑ (wa) ; ↑ (ra (t)2n, wa2n

) ; ↑ (ra) ;↑ (

ra (t)2n+1, wa2n+1) ; ↑ (ra) . (4)

Instead of the read operation of the sequential addressincreasing from word line 0 to the end, each read operationof the even word-line cells is activated. All cells are then



TABLE I

SUMMARIZED RESULTS OF MSTi

Algorithm {↑ (wa) ; ↑ (ra (t) , wa) ; ↑ (ra)}

Data Scrambling Maximum Stress Time of Cell i

SolidOn Max

⎧⎨⎩

i/2−1∑j=0

(S2 j+1)Rt ,

N/2−1∑j=i/2

(S2 j+1)Rt

⎫⎬⎭

Off 0

1-row bar

On 0

Off Max

⎧⎨⎩

i/2−1∑j=0

(S2 j+1)Rt ,

N/2−1∑j=i/2

(S2 j+1)Rt

⎫⎬⎭

2-row barOn Max

⎧⎨⎩

i/4−1∑j=0

(S4 j+1 + S4 j+2)Rt ,

N/4−1∑j=i/4

(S4 j+1 + S4 j+2)Rt

⎫⎬⎭

Off Max

⎧⎨⎩

i/4−1∑j=0

(S4 j+2 + S4 j+3)Rt ,

N/4−1∑j=i/4

(S4 j+2 + S4 j+3)Rt

⎫⎬⎭

Algorithm {↑ (wa) ; ↑ (ra (t) , wa) ; ↑ (ra)}

Data Scrambling Maximum Stress Time of Cell i

SolidOn Max

⎧⎨⎩

i/2−1∑j=0

(S2 j+1)Rt ,

N/2−1∑j=i/2+1

(S2 j )Rt

⎫⎬⎭

Off Max

⎧⎨⎩0,

N/2−1∑j=i/2+1

(S2 j + S2 j+1)Rt

⎫⎬⎭

1-row barOn Max

⎧⎨⎩0,

N/2−1∑j=i/2+1

(S2 j + S2 j+1)Rt

⎫⎬⎭

Off Max

⎧⎨⎩

i/2−1∑j=0

(S2 j+1)Rt ,

N/2−1∑j=i/2+1

(S2 j )Rt

⎫⎬⎭

2-row barOn Max

⎧⎨⎩

i/4−1∑j=0

(S4 j+1 + S4 j+2)Rt ,

N/4−1∑j=i/4

(S4 j + S4 j+3)Rt

⎫⎬⎭

Off Max

⎧⎨⎩

i/4−1∑j=0

(S4 j+2 + S4 j+3)Rt ,

N/4−1∑j=i/4

(S4 j + S4 j+1)Rt

⎫⎬⎭

read to detect the weak cells with the subthreshold leakage-current. Each read operation of the odd word line cells isalso performed in the same way. The MSTi results for theinterleaving mode are listed in Table II. As shown in Fig. 7,cells on the bit line are stressed only when cells on bitbar lines are activated. Thus, regardless of the cell location,cells on the bit line or bit bar line have stress times that arehalf of the word line length.

In Table II, the MSTi of the interleaving mode has fixedvalues that differ according to the data background andscrambling conditions regardless of the location of cell i .These results overcome the variation in stress according tothe cell location. However, if the refresh operation is appliedto the interleaving test results as shown in Table II, stressinitialization is performed due to the refresh operation before

testing the end of the word line cells. Therefore, the MSTi ofthe cells also varies, as shown in Fig. 9.

Despite the interleaving mode, MSTi varies because ofthe refresh conditions. Thus, in order to identify suitablerefresh conditions, we simulate the variance of MSTi andthe mean of the interleaving mode. As shown in Fig. 10,the MSTi varies according to the refresh conditions, but thereis also no variance in MSTi during the specific refresh timeeven though the interleaving mode is applied. The mean ofthe MSTi at that refresh time is higher than at any otherrefresh time. Thus, a suitable refresh condition can be foundto equal the bit-line stress using the interleaving mode asfollows:

refresh ∝ Rt × N/2. (5)



Fig. 9. MSTi of the interleaving mode when the refresh operation is applied.

M

V

V

Mean of the inter

Variance of the se

Variance of the in

rleaving test

equencial test

nterleaving test

Fig. 10. Variance comparison of MSTi according to the refresh time (solid, scramble on).

TABLE II

MSTi RESULTS OF THE INTERLEAVING MODE

Algorithm

{ ↑ (wa) ; ↑ (ra (t)2n , wa2n

) ; ↑ (ra)

; ↑ (ra (t)2n+1, wa2n+1

) ; ↑ (ra)

}Data Scramble Maximum Stress Time of Cell i

SolidOn

N/2−1∑k=0

(S2k+1

)Rt ∼= N

2Rt

Off 0

1-row barOn 0

OffN/2−1∑

k=0

(S2k+1

)Rt ∼= N

2Rt

2-row barOn

N/4−1∑k=0

(S4k+1

)Rt ∼= N

4Rt

OffN/4−1∑

k=0

(S4k+3

)Rt ∼= N

4Rt

As mentioned previously, N is the end of word lines persense amplifier. Since we use the interleaving mode (+2 wordline jump), the equation is divided by 2. This equation meansthat the variance of MSTi is zero if the refresh operations are

Fig. 11. Screen coverage comparison.

conducted immediately after the read operation of the last cellof the column address per sense amplifier.

IV. EXPERIMENTAL RESULT

To verify this analysis, experiments were conducted with2G bit DRAM chips. First, the failed DRAM chips were



Interleaving test

Vds Data Retention

Fig. 12. Coverage comparison depending on the read time.

Vds D

Interleavin

Data Retention

g test

Fig. 13. Test time comparison depending on the screen coverage.

gathered from the mass production test program related tothe data retention and leakage current test, with the exceptionof the contact, DC parameters test, and some of the functiontests such as address decoder and simpleMarch algorithm. 128samples were chosen randomly from the failed chips. Ourexperiment was conducted at a high temperature above 85°C.As shown in Fig. 11, the failed chips were tested using thepreviously published March CRF, W/L pulsing technique, andlarge V DS data retention test algorithms [11], [12], [14]. Theresults of our experiments indicated that the screen coverageof the W/L pulsing technique is more efficient than that of theMarch CRF in our failed chips, but the W/L pulsing techniqueis limited to detecting most of the subthreshold leakage-current defective chips regardless of increasing the word-lineenable time. As the word-line enable time increases, the testtime of the W/L pulsing technique increases rapidly. Theseexperiments did not include X-direction Extended MarchC- and Y -direction MATS [13] as mentioned in Section Ibecause these algorithms use a self-refresh operation and this

special operation is different for the purpose of this experimentto screen the subthreshold leakage-current.

To confirm our analysis, we conducted the experimentswith the same failed DRAM chips. As the bit line stress isanalyzed theoretically in Section III, the bit line stress differsdepending on the scrambling and data background. Amongthe combinations of data background and scramble, the screencoverage was greatest with the combination of a solid databackground and scrambling enabled, as mentioned previouslyin the discussion of the MSTi of cells. Therefore, in ourexperiment, we used a solid data background with scramblingenabled. And the test is carried out by setting the refreshcondition based on the W/L size in order to optimize themaximum stress time.

In Fig. 12, the experiments demonstrated that the screencoverage varies according to the read time, so the screen-ability increases as the read time increases. However, it isnecessary to confirm adequate read time in order to screenthe subthreshold leakage-current defective chips, not the good



chips. The read-time test conditions can be varied accordingto the customer’s needs and the levels of chip quality. Severalsemiconductor companies specify an active to precharge time(tRAS time) of 70 µs on the technical data sheet. Therefore,Fig. 10 demonstrates experimentally that the interleaving testhas higher detection ability than the V DS data retention testwhen the read time is 70 µs. This is due to the bit-linestress difference between the interleaving and sequential testalgorithms as mentioned previously.

It is known that there are marginally defective chips interms of subthreshold leakage-current among the failed chipsaccording to the read time. To screen the marginally defectivechips, the read time is needed more than 70 µs. In Fig. 12,110 µs of the read time is needed to detect the marginallydefective chips with the interleaving test. However, more than130 µs of the read time is needed with the large V DS dataretention test. Therefore, the total test time of the interleavingmode is 15 s less than the V DS data retention in Fig. 13. Thefigure shows that the test time of the interleaving algorithmdiffers from that of the V DS data retention algorithm for thesame coverage. This means that the test time can be reducedby using the interleaving test instead of the large V DS dataretention test.

The yield loss of the good chips did not occur when theread time was 110 µs. This is consistent with the finding thatthe fail rates of the V DS data retention test (which was usedbefore) and the interleaving test are saturated.

V. CONCLUSION

Various screen algorithms have been proposed to detectleakage-current faults. As the length of the gate channel isshortened as down-scaling of the minimum feature size ofDRAM, subthreshold leakage-current faults have become moreserious. Therefore, this paper proposes a new test algorithmto detect subthreshold leakage-current faults.

To confirm variation in the MST according to cell locationand to determine the optimized refresh conditions, simulationsare conducted under various test conditions. An interleavingmode is adopted in the test algorithm in order to overcome thevariation in MST. The screenability and efficiency are exper-imentally compared between the previous test algorithm andthe proposed test algorithm. As a result of the experiment, wefind that the proposed test algorithm has a higher screenabilityof about 6% and reduces test time by about 20% comparedwith the previous test algorithm.

The MST of the cells and optimized test conditions of thetest algorithm can differ depending on the DRAM cell arrayand design, but proper test conditions and flexibility can beachieved by adjusting the read time and refresh cycle. Theproposed test algorithm can be used not only to reduce thetest time, but also to improve device quality.

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Hyoyoung Shin received the B.S. degree in informa-tion and telecommunication engineering from KoreaAerospace University, Gyeonggi-do, Korea, and theM.S. degrees in electrical and electronic engineeringfrom Yonsei University, Seoul, Korea, in 2012.

He has been a Product Engineer with the ProductDevelopment Division, SK Hynix Semiconductor,Inc., Gyeonggi-do, since 2005. His current researchinterests include memory testing, yield enhance-ment, product reliability, and test methodology.

Youngkyu Park received the B.S. degree in elec-tronic engineering from Hoseo University, Asan,Korea, in 2004, and the M.S. and Ph.D. degreesin electrical and electronic engineering from YonseiUniversity, Seoul, Korea, in 2007 and 2013, respec-tively.

He was a Senior Engineer with the Memory Divi-sion, Samsung Electronics Company, Seoul, from2013. His current research interests include VLSIdesign and testing, memory BIST, and design fortestability.



Gihwa Lee received the B.S. degree inelectronics from Chungbuk National University,Chungcheongbuk-do, Korea, in 1993.

He was involved in device engineering of DRAMfrom 1993 to 1998 with LG Semiconductor,Inc. Since 1999, he has been a Test Engineerwith the Package and Test Division, SK HynixSemiconductor, Inc., Gyeonggi-do, Korea. Hiscurrent research interests include memory testing,yield enhancement, product reliability improvement,defect screen ability improvement for mass

production, and low-cost test solutions.

Jungsik Park received the B.S. and M.S. degreesin electrical and electronic engineering from HongikUniversity, Seoul, Korea in 1987.

He was involved in device engineering of DRAMfrom 1990 to 1998 with LG Semiconductor, Inc.Since 1999, he has been a Test Engineer with thePackage and Test Division, SK Hynix Semiconduc-tor, Inc., Gyeonggi-do, Korea. His current researchinterests include low-cost test solutions, product reli-ability improvement, defect screen ability improve-ment for mass production, and test methodology

development in DRAM and Flash.

Sungho Kang (M’91) received the B.S. degree fromSeoul National University, Seoul, Korea, and theM.S. and Ph.D. degrees in electrical and computerengineering from the University of Texas at Austin,Austin, TX, USA, in 1992.

He was a Research Scientist with the Schlum-berger Laboratory for Computer Science, Schlum-berger Inc., and a Senior Staff Engineer withthe Semiconductor Systems Design Technology,Motorola Inc. Since 1994, he has been a Professorwith the Department of Electrical and Electronic

Engineering, Yonsei University, Seoul. His current research interests includeVLSI/SOC design and testing, design for testability, and design for manufac-turing.

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