Design of 1V, 0.18μ Folded Cascode Operational Amplifier for Switch Capacitor Sigma Delta Modulator

International Journal of Electrical and Electronics

Engineering Research (IJEEER)

ISSN 2250-155X

Vol. 3, Issue 4, Oct 2013, 223-232

© TJPRC Pvt. Ltd.

DESIGN OF 1V, 0.18µ FOLDED CASCODE OPERATIONAL AMPLIFIER FOR SWITCH

CAPACITOR SIGMA DELTA MODULATOR

RATNAPRABHA W. JASUTKAR1, P. R. BAJAJ

2 & A. Y. DESHMUKH

3

1Research Scholar, G. H. Raisoni College of Engineering, Nagpur, Maharashtra, India

2Director and Professor, G. H. Raisoni College of Engineering, Nagpur, Maharashtra, India

3Professor, G. H. Raisoni College of Engineering, Nagpur, Maharashtra, India

ABSTRACT

In this paper, the concept of folded topology and design methodology in terms of equations, criteria and

procedures is presented for folded cascode operational amplifier which is to be used in switch capacitor sigma delta

modulator. The design of folded cascode operational amplifier results in high gain and high unity gain bandwidth. The

circuit performance has been simulated with ±10% voltage supply variations. A prototype of an operational amplifier has

been built in 0.18µm CMOS process with 1V supply voltage. Further the results of folded cascode operational amplifier

are compared with simple two stage operational amplifier and two stage cascode operational amplifier.

KEYWORDS: CMOS, Folded Topology, Folded Cascode Amplifier (FCA), Folded Cascode Operational Amplifier

(FCOA), Sigma Delta Modulator, Analog to Digital Converter (ADC)

INTRODUCTION

Operational amplifiers (op amps) are an integral part of many analog and mixed-signal systems. Opamps with

vastly different levels of complexity are used to realize functions ranging from dc bias generation to high-speed

amplification or filtering, analog to digital conversion etc. Here we are likely to use this FCOA in sigma delta modulator as

analog to digital converter (ADC). Sigma delta modulator is an oversampling converter and require high loop gain.

Fully differential output operational amplifiers are widely used because they provide a large output voltage swing

and they are less susceptible to common-mode noise than the single-ended versions. Fully differential amplifiers are used

in a noisy environment when external noise can mask low input signals. Also, the differential operation in switched-

capacitor analogue circuits is a good way to minimize the influence of clock feedthrough and charge injection. A

disadvantage of fully differential operational amplifiers is the fact that they require the use of a common mode feedback

(CMFB) circuit to control the common-mode output voltage.

This paper deals with the analysis and design of CMOS op amps. Following a review of performance parameters,

the simple folded cascode amplifier and then folded cascode operational amplifier topologies are described. Next, we

studied two-stage and gain-boosting configurations and the problem of common-mode feedback. Also the complete biasing

and buffering for FCOA is also described in detail. Finally, we have introduced the concept of slew rate and analyze the

effect of supply rejection and noise in op amps. In order to achieve fast settling time and high dc gain, the folded-cascode

operational amplifier is used in many analog circuit designs. The cascode configurations can be used to design high voltage

gain of CMOS transistor amplifier. The stage gain of the folded-cascode amplifier can be increased to increase the voltage

gain output volts a range, current sourcing/sinking capability.

224 Ratnaprabha W. Jasutkar, P. R. Bajaj & A. Y. Deshmukh

CONCEPT OF CASCODE TOPOLOGY

The cascade of a common source stage and common gate stage is called a “Cascode” topology, providing many

properties. The idea behind the cascode structure is to convert the input voltage to a current and apply the result to a

common gate stage. The different types cascode amplifiers include.

Simple Cascode Amplifier

Multi – level cascode Amplifier

Gain boosted Cascode Amplifier

Folded Cascode Amplifier

Folded Cascode Amplifier

Folded-cascode amplifier circuit with proper biasing with the source terminal of M1 at VDD and at a suitable bias

voltage at VB is shown in figure 1. Folded cascode amplifier offer more freedom to choose the DC input voltage at Vin

(such as figure 1(a)), higher voltage swing, convenience in shorting the input and the output in feedback configurations.

In Figure 1, I1 is the current flowing through M3 and is equal to the sum of ID1 and ID2, VTH1 = VTH. When

Vin >VDD-IVT1I, M1 is off and M2 carries all of I1 yielding Vout =VDD-I1RD.For Vin < VDD-IVT1I, M1 turns on in saturation.

As Vin drops, ID2 decreases future, falling to zero if ID1=I1(Vin =Vin1). If Vin < Vin1, M1 enters triode region.

Figure 1: Folded Cascode Amplifier

Figure 2: Large Signal Characteristics of Folded Cascode Amplifier

Design of 1V, 0.18µ Folded Cascode Operational Amplifier for Switch Capacitor Sigma Delta Modulator 225

FOLDED ASCODE OPERATIONAL AMPLIFIER

The operational amplifier (op-amp) is a fundamental building block in analog integrated circuit design. Figure 3

Shows the architecture of an opamp called folded cascode opamp. This opamp uses cascoding in the output stage combined

with an unusual implementation of differential amplifier to achieve good input common mode range. Thus the folded

cascode opamp exhibits self compensation, good input common mode range and gain of two stage opamp.

Figure 3: Folded Cascode Operational Amplifier

Figure 3 presents a basic fully differential folded cascode operational amplifier [8]. It is a two stage amplifier. The

input stage is a differential output differential folded cascode amplifier with the transistors M1-M2. The high gain of this

stage is a result of the cascode current mirrors M5-M8 and M9-M12. The nMOS devices M1 and M2 are chosen as the

input differential pair because of larger transconductance compared to pMOS devices.

The output stage is a common source amplifier with the transistors M13-M16. It is designed to drive resistive

loads. Special attention is dedicated to the design of the output transistors in order to obtain a high voltage swing. The

frequency compensation network consists of the compensation capacitors Ccp and Ccm and zero-nulling resistors Rcp and

Rcm.

The common mode feedback (CMFB) circuit is used in a fully differential operational amplifier to keep the

operational amplifier outputs balanced around a known voltage VCM. The common mode feedback (CMFB) amplifier is

shown in Figure 4. The common mode output voltage is detected by the resistive divider R1 and R2. One side of the large

and equal resistors R1 and R2 is connected at the gate of MC1, where the common voltage is detected, while the other side

of the resistors is connected to the basic FDFC amplifier output nodes vOUTP and vOUTM (Figure 3), respectively. The

resistors R1 and R2 have to be large to prevent the gain loss of the output stage of the basic FDFC amplifier. On the other

hand, the large resistances R1 an R2 and the parasitic gate-source capacitance of MC1 form the RC network that slows

down the common mode detection.

From the stability consideration, the common mode detection must be fast enough in order to ensure the stability

of the whole amplifier. To ensure that the balance is maintained at high speed, two equal capacitors C1 and C2 are added in

parallel with the resistors R1 and R2. At high frequencies the impedance of the capacitors becomes dominant, lowering

down the total impedance. The value of the resistors is a trade-off between the fast common voltage detection and the gain


of the output stage. The CMFB amplifier must have enough gain to ensure good tracking between the common voltage

VCM and the detected common voltage at the outputs, which is equal to (vOUTP + vOUTM)/2.

Figure 4: Common Mode Feedback Circuit

High gain is achieved by cascade connected active loads. The CMFB amplifier output is VCMFB. This common

mode voltage regulation is applied to the gates of the transistors M7 and M8 of the FCOA amplifier in Figure 3. This is the

best point for the regulation with respect to the stability of the circuit.

The biasing circuit is shown in Figure 5. The voltages VBIASP2, VBIASP1, VBIASN1 and VBIASN2 determine all biasing

currents for the FCOA operational amplifier in Figure 3 and the CMFB amplifier in Figure 4. The biasing current is

controlled by the current source IBIAS. The transistors MB9-MB11 with transistors MB14 and MB15 form a low voltage

wide-swing current source [7-8]. This type of source, that mirrors currents in input stage of basic amplifier, is necessary

because of the stack of the transistors M3, M4 and M9-M12 in Figure 3. The series connection of the transistors MB9-

MB11 is used instead of a single nMOS transistor with longer channel. The usage of the series connection is also applied to

the transistors MB16-MB18.

Figure 5: Biasing Circuit of Folded Cascode Opamp

Design of Folded Cascode Operational Amplifier

Design of the op-amp consists of determining the specifications, selecting device sizes and biasing conditions,

compensating the op-amp for stability, simulating and characterizing the op-amp AOL (open-loop gain), CMR (common-

mode range on the input), CMRR (common-mode rejection ratio) and PSRR (power supply rejection ratio).


Table 1: Design Specifications

Parameters Values

Voltage Gain 50dB

Unity Gain Bandwidth 140MHz

CMRR 60dB

Slew Rate 15 V/usec

Voltage Supply ± 1V

Figure 6: AC Equivalent Circuit of FCOA

Design Equations for the Folded Cascode Opamp

The folded cascode opamp does not required perfect balance of current in the differential amplifier because excess

dc current can flow into the current mirror. The biasing current I11, I5, I6 of folded cascode opamp should be designed so

that the dc current in cascode mirror never goes to zero. If the current go to zero its requires a delay in turning the mirror

back on because of the parasitic capacitance that must be charged.

Selection of bias current I11

SR = (1)

I11 = SR.CL

Selection of bias currents in the output cascodes I5 = I6 are selected such that there should not zero current in the

output cascades

I5 = I6 = 1 .2 I11 to 1.5 I11 (2)

Maximum output voltage Vout(max)

52'

66

8

SDpVK

IS (3)

42'

44

8

SDpVK

IS (4)

Let S5 = S6 and S3 = S4

VSD6 (Sat) = VSD4 (Sat) = 2

V- V (min)out DD (5)

Minimum output voltage Vout (min)

I11

CL


102'

1010

8

SDpVK

IS (6)

82'

88

8

SDpVK

IS (7)

Let S9 = S10 and S7 = S8

VDS8 (Sat) = VDS11 (Sat) = 2

V (min)out SSV (8)

Determination of Gain bandwidth (GB)

L

m

C

gGB 1 (9)

11

'

22

11

'

2

121

IK

CGB

IK

gSS

N

L

N

m (10)

Minmum input at common mode\

21(min)

'

1111

1'

11

2

TSK

I

SSinN VVVK

IS

N

(11)

Maximum input at common mode

1(max)

'

565

2

TinDDp VVVK

ISS

(12)

S5 and S6 must meet or exceed the requirement of step 3.

Differential voltage gain

IImm

in

outV R

K

gg

V

VA

)1(22

21

IImV RgK

KA 1

22

2

(13)

where

44

528 )(

dsm

dsds

rg

ggRK

62441188 dsdsdsmdsdsmII rrrgrrgR

Power dissipation

1091112 IIIIVVP SSDDdiss (14)


SIMULATION RESULTS

Differential Voltage Gain(Avd)

The differential voltage gain of an opamp is defined as

id

odvd

V

VA

This is also the small signal ac. Voltage gain decreases with increasing frequency after the system encounters its

first pole. Thereafter, this gain decreases at 20 dB/decade until it reaches another pole after which the drop rate becomes 40

dB/ decade and so on.

Differential Gain Bandwidth Product GBW

The differential gain bandwidth product (GBW) is equal to the unity gain frequency (W) since out system is a

dominant pole system. The gain bandwidth product should ideally be equal at any frequency. In other words, it indicates

that with the increase in the gain of system bandwidth suffers and vice versa.

Phase Margin

Figure 7: Transient Response of FCOA

For a system to be stable it is very important to maintain a certain phase margin A system having phase margin

less than 45 degrees is considered unstable. Similarly a large phase margin like 100 degrees, though acceptable makes the

system response slow

Figure 8: AC Response of FCOA


Common Mode Rejection Ratio (CMRR)

Common Mode Rejection Ratio is a measure of the op amp which tells how good the op amp is at rejecting

common mode signal at it two inputs. The CMRR of an ideal op amp is infinity. For all practical op amps, this value

should be as high as possible.

The CMRR is given by

cm

dm

A

ACMRR Where Adm is Differential Mode Gain, Acm is Common Mode Gain.

Slew Rate (SR)

Slew Rate is the measure of an op-amps speed to respond to pulse edges at its inputs. For sharp rising edges at its

inputs, the output of the op amp rises/ falls with a finite delay. We want this delay to be as low as possible. In other words,

the output should have a slope as high as possible.

The slew rate is approximately given by dt

dVSR out Volts /usec.

Figure 9: Response of FCOA to Square Signal

Table 2: Comparison between Different Types of Opamps

Parameters Two-Stage Opamp Cascode Opamp Folded Cascode Opamp

Max. gain 16.62db 6.10db 31.59db

UGB 7.19KHz 77.43MHz 125.60MHz

Phase margin 88.370 91.66

0 -96.59

0

Figure 10: Frequency Response of Different Operational Amplifiers


CONCLUSIONS

Folded Cascode Operational amplifier is designed and implemented for given specification and then results are

compared with simple two stage opamp and two stage cascode opamp . Folded cascode Opamp Amplifier (FCOA) provide

amplification to the input voltage in the range of 100mV to 1.0V with maximum differential gain of 34.15db .It offer large

unity gain bandwidth of 125.60MHz which is nearly double the bandwidth of simple cascode Opamp.

It provide good common mode rejection capability with CMRR of 62.68db .Also the output response time of

FCOA is less with the slew rate of 13.33V/usec. Folded cascode Opamp gives highest unity gain bandwidth which is

nearly double the simple cascode Opamp and 10,000 times the two stage of Opamp. FCOA provide the highest differential

gain with good circuit stability.

AS FCOA provides high differential gain ,high unity gain bandwidth and CMRR, it can be used in electronic

circuits of wide frequency range from very low like biomedical signals to radio frequencies.

REFERENCES

1. K. Bult and G. Geelen, "A fast-settling CMOS op amp for SC circuits with 90-dB DC gain," IEEE J. Solid-state

Circuits, VOL. 25, NO. 6, Dec. 1990,pp. 1379-1384.

2. J. Lloyed and H.-S. Lee, " A CMOS op amp with fullydifferential gain-enhancement,'' IEEE Trans. On Circuits

and Systems 11: Analog and Digital signal processing, Vol. 41, No.

3. P. C. Yu, H.-S. Lee, "A 2.5-V, 12-b, 5-MSample/s pipelined CMOS ADC," IEEE Journal of Solid-state circuits,

Vol. 31, No. 12, December 1996, pp. 1854-1861.

4. S. H. Lewis, H. S. Fetterman, G. F. Gross, Jr., R. Ramachandran, and T. R. Viswanathan, "A 10-b 20-Msample/s

analog-to digital converter," IEEE J. Solid-State Circuits, vol. 27, pp.

5. K. Y. Kim, N. Kusayanagi, and A. A. Abidi, "A lO-b, 100-MS/s CMOS AID converter," IEEE J. Solid-state

Circuits, vol. 32

6. E. Opris, L. D. Lewicki and B. C. Wong, "A single-ended 12-bit 20Msample/s self-calibrating pipeline A/D

converter" , IEEE Journal of Solid-state circuits, vol. 33, No. 12, December 1998

7. D. Fu, K. Dyer, S . Lewis, and P. Hurst, "Digital background calibration of a 10-b 40 MSls parallel pipelined

ADC," in Proc. Int. Solid-state Circuits Conf., Feb. 1998, pp. 140-141.

8. K. Dyer, D. Fu, S. Lewis, and P. Hurst, "Analog background calibration of a 10-b 40 MSls parallel pipelined

ADC," in Proc. Int. Solid-state Circuits Conf., Feb. 1998, pp. 142-143

9. Benjamin J. Blalock, Phillip E. Allen “Designing 1V Opamp using standard Digital CMOS Technology” , IEEE

and Gabriel A. Rincon-Mora.

10. Xin Jiang, Sanghyun Seo and Yumin Lu “A CMOS single stage fully differential Opamp with 120db DC gain” ,

EECs Dept. University of Muchigan at Ann Arbor, MI.

11. Kimmolasanen, Elvi Raisansen-Ruotsalaisen, Juha Kostamovaara “A 1V-5uw CMOS opamp with bulk driven

input transistors”, University of Oulu, Finland.

12. P. E. Allen and D. R. Holberg, “CMOS Analog Circuit Design”, 2nd edition, Oxford University Press, 2002.


13. Randall L. Geciger, Phillip E. Allen and Noel R. Strades, “VISI Design Techniques for analog and digital circuit“

14. R. Jacob Backer, harry W. Li, David E. Boyce, “CMOS circuit Design, Layout and Simulation”.

Design of 1V, 0.18μ Folded Cascode Operational Amplifier for Switch Capacitor Sigma Delta Modulator

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