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Data Manipulation

How Computers Work

Outline

• Circuitry for Arithmetic Operations and Data Transfer/Storage• Machine Architecture• Machine Instructions• Instruction Cycle• Pipelining and Multiprocessors

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Circuitry for Arithmetic Operations - Adder

= xy + (x y) z

Circuitry for Data Transfer/Storage – Memory

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Machine Architecture (Simplified)

• A CPU consists of an arithmetic/logic unit and a control unit.• A program (or its parts) is loaded on the main memory, and fetched instructions

one by one into the instruction register.• Data must be loaded onto registers to be subject to manipulation by a CPU.• A bus is a collection wire for data transfer between a CPU and a main memory.

General purpose registers

Special purpose registers

Machine Instructions

• A collection of instructions recognizable and executable by CPUs• Categories

– Data transfer (actually copy or clone)• LOAD: transfer data from memory to registers• STORE: transfer data from registers to memory• Input/output• Operand: source, destination

– Arithmetic/logic• AND, OR, XOR, NOT• SHIFT, ROTATE• ADD (integers or floating point numbers)

– Control• JUMP (conditional or unconditional)

• RISC vs. CISC– RISC (Reduced Instruction Set Computer): tens of simple instructions– CISC (Complex Instruction Set Computer): hundreds of powerful

instructions

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Encoding of Machine Instructions

0011 0101 1010 0111

3 5 A 7

STORE R-5 Mem(A7)R-5 => Mem(A7)

0111 0000 1100 0101

7 0 C 5

OR R-0 R-C R-5R-0 <= R-C R-5

Example Algorithm: Addition of Two Numbers

Step 1. LOAD a register with a value from memory

Step 2. LOAD another register with another value from memory

Step 3. ADD the values in the above two registers

Step 4. STORE the result in memory

Step 5. STOP

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Loaded Program

LOAD 5, 6C

LOAD 6, 6D

ADD 0, 5, 6

STORE 0, 6E

STOP

Instruction Cycle

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Program Ready for Execution

Fetch Step

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Decoding and Execution Steps

• Mapping of each machine instruction to the corresponding set of micro instructions

LOADMAR <= IR(addr)R0 < = &MARPC <= PC + 2

STOREMAR <= IR(addr)&MAR <= R0PC <= PC + 2

ADDMAR <= IR(addr)R0 <= R0 + &MARPC <= PC + 2

Each bit segment is input to the circuitryaccording to the

system clock pulses

User Program vs. Machine Language

GET AGET BC = A + BPRINT C

LOAD 100STORE 1000LOAD 100STORE 1004LOAD 1000ADD 1004STORE 1006LOAD 1006STORE 104

MAR <= IR(addr)R0 < = &MARPC <= PC + 1

Compile Mapping

User Program Machine Language Microcode

cf. assembly language

MAR <= IR(addr)&MAR <= R0PC <= PC + 1

…

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Example Set of Machine Instructions (1/2)

Cited from J. Brookshear, Computer Science, Pearson

Example Set of Machine Instructions (2/2)

Cited from J. Brookshear, Computer Science, Pearson

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Benchmark

• What determines the CPU speed?– System clock?– An 1 GHz RISC is faster than a 900 MHz CISC CPU?– Different CPU designs may perform different amounts of work in one

clock cycle– Very complex formula might be required to compare CPU speed. Even

impossible.

• Benchmarking (cf. Clinical test)– Preparation of representative applications along with relevant test

data sets.– Test-run CPUs with those applications, and evaluate results– Some CPUs are good at some types of applications, while others are

good at other applications.

I/O Controllers

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I/O and Data Communication

• I/O instructions vs. Memory-mapped I/O– I/O instructions:

• Send (Port_Number, Source)• Receive (Port_Number, Destination)

– Memory-mapped I/O• Designated address spaces are for I/O

– e.g. 0x1200: printer, 0x1201: scanner, etc• Memory read and write operations become I/O operations

• Serial vs. Parallel communication– bps: bits per second– bandwidth: maximum communication speed– parallel: higher bandwidth but requires more wires– serial: lower bandwidth but less wires => becoming faster

• RS232C, modem, DSL, USB, IEEE1394, …

Pipelining

• Throughput: how many tasks have been completed in a unit time interval

• Turnaround: how long it takes to complete a given task• Response: how long it takes to get the first answer

• Pipelining

Fetch Decode Execution

Fetch Decode Execution

Fetch Decode Execution

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Multiprocessors

• SMP (Share Memory Processors)

• MPP (Massively Parallel Processors)

Memory

CPU CPU CPU CPU

CPUMemory CPU Memory

CPUMemory CPU Memory

CPUMemory CPU Memory

CPUMemory CPU Memory