17

Congestion-Aware Layout Design for High-ThroughputDigital Microfluidic Biochips

SUDIP ROY, Indian Institute of Technology, KharagpurDEBASIS MITRA, National Institute of Technology, DurgapurBHARGAB B. BHATTACHARYA, Indian Statistical Institute, KolkataKRISHNENDU CHAKRABARTY, Duke University

Potential applications of digital microfluidic (DMF) biochips now include several areas of real-life applicationslike environmental monitoring, water and air pollutant detection, and food processing to name a few. In orderto achieve sufficiently high throughput for these applications, several instances of the same bioassay maybe required to be executed concurrently on different samples. As a straightforward implementation, severalidentical biochips can be integrated on a single substrate as a multichip to execute the assay for varioussamples concurrently. Controlling individual electrodes of such a chip by independent pins may not beacceptable since it increases the cost of fabrication. Thus, in order to keep the overall pin-count within anacceptable bound, all the respective electrodes of these individual pieces are connected internally underneaththe chip so that they can be controlled with a single external control pin. In this article, we present anorientation strategy for layout of a multichip that reduces routing congestion and consequently facilitateswire routing for the electrode array. The electrode structure of the individual pieces of the multichip maybe either direct-addressable or pin-constrained. The method also supports a hierarchical approach to wirerouting that ensures scalability. In this scheme, the size of the biochip in terms of the total number ofelectrodes may be increased by a factor of four by increasing the number of routing layers by only one. Ingeneral, for a multichip with 4n identical blocks, (n + 1) layers are sufficient for wire routing.

Categories and Subject Descriptors: B.7.2 [Integrated Circuits]: Design Aids - Layout; J.3 [Life andMedical Sciences]: Biology and genetics, Health

General Terms: Algorithms, Design, Performance, Theory

Additional Key Words and Phrases: Bioassays, design, high-throughput, biochips, design automation, digitalmicrofluidics, pin-constrained design, wire routing

ACM Reference Format:Roy, S., Mitra, D., Bhattacharya, B. B., and Chakrabarty, K. 2012. Congestion-aware layout design for high-throughput digital microfluidic biochips. ACM J. Emerg. Technol. Comput. Syst. 8, 3, Article 17 (August2012), 23 pages.DOI = 10.1145/2287696.2287700 http://doi.acm.org/10.1145/2287696.2287700

1. INTRODUCTION

In recent years, interdisciplinary enrichment across microelectronics, nano-engineering, and medical sciences has led to new technologies for addressing several

This article is an extended and revised version of Roy et al. [2010] published in Proceedings of the IEEEInternational Symposium on Electronic System Design (ISED’10).The work of S. Roy was supported in part by the Indian Statistical Institute, Kolkata, Indian Institute ofTechnology Kharagpur (MHRD Ph.D. Scholarship), and by Microsoft India Research Ph.D. Fellowship. Thework of K. Chakrabarty was supported in part by the National Science Foundation under grant CCF-0914895and grant OISE-1041708.Authors’ addresses: S. Roy (corresponding author), Indian Institute of Technology, Kharagpur, India;email: sudipr@cse.iitkgp.ernet.in; D. Mitra, National Institute of Technology, Durgapur, India; B. B. Bhat-tacharya, Indian Statistical Institute, Kolkata, India; K. Chakrabarty, Duke University, Durham, NC 27705.Permission to make digital or hard copies of part or all of this work for personal or classroom use is grantedwithout fee provided that copies are not made or distributed for profit or commercial advantage and thatcopies show this notice on the first page or initial screen of a display along with the full citation. Copyrights forcomponents of this work owned by others than ACM must be honored. Abstracting with credit is permitted.To copy otherwise, to republish, to post on servers, to redistribute to lists, or to use any component of thiswork in other works requires prior specific permission and/or a fee. Permissions may be requested fromPublications Dept., ACM, Inc., 2 Penn Plaza, Suite 701, New York, NY 10121-0701 USA, fax +1 (212)869-0481, or permissions@acm.org.c© 2012 ACM 1550-4832/2012/08-ART17 $15.00

DOI 10.1145/2287696.2287700 http://doi.acm.org/10.1145/2287696.2287700

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17:2 S. Roy et al.

SampleDroplet

ReagentDroplet

DropletMixed

Electrode

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ctri

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ht (

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Fig. 1. (a) Top view of a digital microfluidic biochip and (b) cross-sectional view of a cell at a detectionsite [Chakrabarty and Xu 2010].

challenges of low-cost health-care management. This has fueled the emergence ofmicrofluidic “lab-on-a-chip”, which has potential for on-chip diagnosis of various car-diovascular diseases, cancer, diabetes, HIV/AIDS and others. These chips are minia-turized, highly integrated, and mimic automated biomedical laboratory systems. Com-pared to traditional laboratory bench-top bioprotocols, microfluidic biochips offer theadvantages of low sample/reagent consumption, less likelihood of error due to minimalhuman intervention, high-throughput and high sensitivity [Chakrabarty and Xu 2010].

Digital microfluidic (DMF) biochips [Chakrabarty and Xu 2010; Fair 2007], thatimplement biochemical laboratory protocols (i.e., bioassays) on a single chip ofa few square centimeters in size, have now emerged as a more versatile optioncompared to the other microfluidic counterparts. A typical DMF biochip consists ofa two-dimensional patterned electrode array, on which discrete droplets of nanolitervolume biochemical fluids are manipulated using electrical actuation [Xu et al. 2007;Abdelgawad and Wheeler 2009; Pollack et al. 2000]. Basic fluidic operations such asdroplet dispensing, transportation, mixing and splitting are performed typically byapplying voltages to the electrodes. A schematic diagrams of the top view of a DMFbiochip is shown in Figure 1(a) and the cross-sectional view of a basic cell at a detectionsite of a DMF biochip is shown in Figure 1(b). Detailed descriptions of DMF biochipscan be found in several research articles [Chakrabarty and Xu 2010; Fair 2007; Xu etal. 2007; Fouillet et al. 2008]. These chips offer the additional advantage of reconfigura-bility as a droplet on any electrode can be controlled individually. Several bioassays,for example, multiplexed assays (for the detection of glucose, lactate in the humanphysiological fluids based on colorimetric analysis), Polymerase Chain Reaction (PCR),protein dilution, protein crystallization, can be automated efficiently on such a biochip.

Droplet routing and operation scheduling are implemented using a preprogrammedmicro-controller that drives actuation voltages to the electrode array through the con-trol pins. In the direct-addressing scheme, each electrode in the array can be accesseddirectly and independently via a dedicated control pin. This method is suitable forsmall/medium-scale microfluidic electrode arrays. However, the number of such con-trol pins may turn out to be unacceptably high for a large array because of boundarylimitations and interconnection complexity. Thus, in order to reduce fabrication cost,several pin-constrained design methods have been developed that use fewer controlpins than the number of electrodes.

In some applications, the same bioassay may need to be executed concurrently onseveral samples to detect the presence of a particular substance in those samples. Forexample, it may be necessary to ascertain the presence of some kind of toxicity in

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Congestion-Aware Layout Design for High-Throughput Digital Microfluidic Biochips 17:3

different food samples or to detect pollutant/smoke in air samples collected from differ-ent parts of a building [Jang et al. 2011; Lim et al. 2006; Kim et al. 2008; Gardeniersand van denBerg 2004]. Design of microfluidic biochips for environmental monitoringapplications has also become important [Sciencedaily 2010; PCR-Blog 2011; NASA2011]. For such applications, several identical biochips can be integrated on a sin-gle substrate as a multichip to execute the assay for various samples concurrently.However, with the increasing dimension of the array, the number of external controlpins connected to the electrodes may increase significantly. Several pin-constrainedbiochip design techniques have been proposed for controlling the electrodes througha small number of pins, a review of which is presented in this article. An importantdesign problem in such a chip is wire routing that is required for interconnecting theidentically controlled electrodes. We analyze several biochip architectures, study theproblem of wiring congestion, and propose a new scheme of layered wire routing thatreduces congestion. A hierarchical scheme is proposed that preserves the simplicity ofwire routing as well as the scalability of layout. We also demonstrate parallel loadingof sample droplets from a dispenser to the corresponding boundary electrodes of all theblocks and unloading of waste droplets from each of the blocks to an external wastereservoir of the multichip.

The organization of the remainder of the article is as follows. Section 2 provides areview of prior works on pin-constrained design techniques of DMF biochips. Section 3describes the motivation of our work presented in this article and Section 4 presentsa new scheme of wire routing for a multichip with four blocks of a DMF biochip forhigh-throughput applications. In Section 5, the loading scheme of droplets from thereservoirs in a multichip architecture has been demonstrated with an example. Finally,conclusions are drawn in Section 6.

2. PRIOR ART: PIN-CONSTRAINED DMF BIOCHIPS

The number of independent control pins is an important cost factor from the viewpointof fabrication. While a direct-addressing scheme provides maximum freedom for dropletmanipulation, it requires a control pin for each electrode. Wire routing for connectingall the electrodes to the control pins adds to the product cost because of increase incongestion and subsequent increase in the required number of routing layers. Gongand Kim [2008] demonstrated a DMF biochip on Printed Circuit Board (PCB), in whichmultilayer electrical connections from the electrodes to their independent control pinswere designed using the PCB technology. However, multilayer electrical connectionstructures and wire routing solutions become complicated for larger arrays, therebyleading to higher production cost. In order to facilitate manufacturing of low-cost anddisposable biochips, design with reduced pin-count, termed as pin-constrained design,has received attention. Several techniques have been introduced for automated designof pin-constrained biochips.

2.1. Droplet-Trace-Based Array Partitioning Method

Xu et al. [2007] proposed a pin-constrained biochip design known as the droplet-trace-based array partitioning method. Given the schedule of the target bioassay, by tracingthe routes of individual droplets, an N × M microfluidic array is partitioned in sucha way that at most one droplet is enclosed in each partition. Electrodes in each ofthese partitions are addressed by a set of five pins. The pin assignment is done using a“Connect-5 algorithm”. The partitions having no overlapping time spans are merged toreduce the total number of partitions. The set of electrodes constituting multidropletoperation modules, for example, mixers, does not belong to any partition and hence theyare addressed directly. This technique requires a constant number of pins. However, itrequires detailed information about operation scheduling of the bioassay, microfluidic

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module placement, and droplet routes, and hence it is specific to a target bio-fluidicapplication.

2.2. Cross-Referencing-Based Method

An alternative method of cross-reference driving has been presented for a special kindof DMF biochip layouts. In such chips, the electrode rows are patterned on both thetop and bottom plates, and placed orthogonally. Hence, a single cell or electrode can beaccessed with the help of a row and a column pair. In order to drive a droplet along the X-direction, electrode rows on the bottom plate serve as driving electrodes, while electroderows on the top serve as reference ground electrodes. When the droplet is to be drivenin the Y -direction, top electrodes are the driving electrodes and the bottom electrodesbecome the reference grounds. Thus, in this type of “cross-referencing” chip, an N × Melectrode array can be driven with only N + M control pins. An efficient droplet ma-nipulation method was proposed to achieve high-throughput on such cross-referencingchips [Xu and Chakrabarty 2008a]. Xiao and Young [2010] proposed another methodfor droplet routing on such chips. However, since the cross-referencing-based methodrequires a special electrode structure (i.e., both the plates contain electrode rows), it re-sults in increased manufacturing cost for disposable DMF biochips. Moreover, becauseof electrode interference, this design cannot handle the concurrent transportation ofmore than two droplets, and thus is not suitable for high-throughput assays.

2.3. N-Phase or Bus-Phase Addressing

A simple pin-constrained design known as bus-phase or N-phase addressing was intro-duced by Srinivasan et al. [2004]. In the bus-phase addressing scheme, each electrodeis not individually addressable, instead, a set of electrodes is controlled by the samesignal. For a droplet transport bus, the number of control pins is reduced to a smallnumber N (typically N = 4) irrespective of the total number of electrodes, since everyNth electrode in an N-phase bus is electrically connected. Though this hardware designsimplifies chip fabrication, it increases the complexity of routing droplets. A schedul-ing and droplet routing algorithm was proposed for coordinating droplet movement inbatch mode operations on ring layouts with bus-phase addressing [Gupta and Akella2007]. Although this technique can reduce the number of control pins to a great extent,it is only applicable to a one-dimensional (linear) DMF electrode array and so it canonly handle a limited set of bioassays.

2.4. Broadcast Electrode-Addressing

Xu and Chakrabarty [2008c] proposed an assay-specific scheme known as the broadcastelectrode-addressing method. It reduces the number of control pins by identifying the“compatible” actuation sequences. A single control pin is used to address a group of elec-trodes with mutually compatible activation sequences, thereby leading to a significantreduction in the number of control pins. Like the direct addressing scheme, it providesmaximum freedom of droplet movement. This scheme provides high-throughput forbioassays and is useful for multifunctional biochip designed to execute a set of multi-plexed bioassays. The degree of reduction in pin-count depends highly on the actuationsequence characteristics of the bioassay on the chip layout. It may not always guaranteesignificant reduction in pin-count, if the set of electrodes having compatible actuationsequences for a bioassay is too small. This problem was overcome in an ILP (integer lin-ear programming)-based droplet routing algorithm proposed by Huang and Ho [2010]with simultaneous consideration of both the droplet routing and broadcast addressing.The scheme simultaneously minimizes the number of control pins, the number of usedcells, and the latest arrival time.

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2.5. ILP-Based Pin-Count-Aware Design Method

Most of the earlier works considered the module placement and droplet routing solu-tions for postprocessing. Hence, the quality of such solutions is inevitably limited bythe placement and routing solutions. A comprehensive pin-constrained biochip designflow that addresses the pin-count-issue at all design stages was considered by Linand Chang [2009]. First, a pin-count aware stage assignment is performed to partitionthe bioassay operations into execution stages. Then, module assignment is done todetermine the specific microfluidic module used for each operation. Finally, the guidedmodule placement, droplet routing, and pin assignment are performed to achieve re-duction in assay completion time and pin count. Exact ILP formulations and effectivesolution-space reduction schemes are proposed to minimize these two parameters.

3. MOTIVATION OF THE WORK

As discussed earlier, in order to reduce the turn-around time of typical health-careassays, several instances of the same assay may be run concurrently with differentsamples. For example, a biochemical laboratory protocol for detecting a particularpathogen may require to be performed for different samples. There are severalbiochemical applications [Cases and de Castro 1988; Thermo Scientific 2006; Moravecet al. Promega 2011; Thermo Scientific 2007; Millipore 2011], where concurrentexecution of the same protocol for detecting a substance in different samples can beimplemented with a multichip. If a single biochip is used to execute one instance ata time for one sample, then it is required to wash the chip by routing wash dropletsfor contamination removal after completing the bioassay for one sample and beforestarting it for another sample. Hence, a significant amount of time is wasted forsequential processing of the assay on various samples. On the other hand, if the samebioassay is performed for different samples, using different biochips, it would be costineffective. To maintain the throughput, more resources like additional system setupare necessary for multiple executions of the same biochip.

In this article, we address an architectural issue for pin-constrained biochip designto concurrently execute multiple instances of the same bioassay for more than onesamples. The idea is to get a more compact design; multiple replicas of the samebiochip layout can be grouped and fabricated on a single chip (called a multichip) thatcan be controlled concurrently with the same set of control pins. In this case, we calleach instance of the minimum size electrode array that can host the target bioassay asa block. Hence, the design of a biochip with a number of blocks, each capable of hostingan instance of the same bioassay with different samples, helps in concurrent executionof the bioassay. The proposed technique reduces the total assay completion time formultiple concurrent executions of the same bioassay. Hence, it increases the overallthroughput of the system. A block can be of any dimension, say N × M, N and M areintegers. An example square block of size 5 × 5 that can be controlled by 25 individualcontrol pins is shown in Figure 2(a). Again, a block with reduced pin-count can beobtained by applying some pin-constrained design technique. Such an example blockof size 5 × 5 that can be controlled by only five pins is shown in Figure 2(b). Dependingon the number of instances of the same bioassay that are to be executed concurrently,we can construct the actual biochip layout by appropriately placing the blocks of samesize within the minimum possible chip area.

3.1. Design Issue for Pin Assignment of a Multichip

For estimation of certain type of contaminants in water collected in various parts ofa region, or for concurrent execution of a bioassay for different food samples, multi-ple blocks can be fabricated on a single big two-dimensional array of electrodes. The

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21 22 23 24 25

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(a)

1 3 5 24

3 5 2 4 1

2 4 1 3 5

1 3 5 2 4

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(b)

Fig. 2. A block of 5×5 electrode array. (a) Direct-addressing scheme and (b) a pin-constrained design scheme.

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Fig. 3. Interconnection in a 4-block multichip, where blocks are placed side-by-side (each block with 5 × 5electrode array).

identically addressed electrodes of each block are to be interconnected so that they arecontrolled by the same control pin. This can be thought of as a pin-constrained biochipdesign and the wire routing for these interconnections is to be done at the backplane ofthe biochip. Thus, like any other pin-constrained biochip design, the underlying wirerouting of the electrodes in different identical blocks also poses a challenging problem.An arbitrary orientation of individual blocks may cause a large number of crossoversin a routing plane, that is, crossings of interconnection wires for differently addressedelectrodes. Hence, the wire routing complexity as well as the number of required layersis highly dependent on the relative positions and orientations of these blocks. Thus itmay not be possible to route all the interconnection wires with a given number of layersunderneath a pin-constrained biochip.

To demonstrate this problem, let us consider a 5 × 5 electrode array block and letfour such blocks be placed side-by-side according to the orientation shown in Figure 3.In this figure, a “blue” colored tiny square on each electrode represents the via thatconnects it with the wiring in the layer beneath that electrode (similar to a VLSI chip).

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Congestion-Aware Layout Design for High-Throughput Digital Microfluidic Biochips 17:7

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Fig. 4. Label-symmetric orientation of a 4-block multichip (each block with 5 × 5 electrode array).

Three-quarter rectilinear dotted “black” lines are used to indicate the wire routing ofcorresponding electrodes in the four blocks. The wired connections of each of the 25identically addressed electrodes in the chip to the respective external control pins areshown in the figure by “green” lines. As there is no intersection between two “green”lines, they can be routed on a single layer. For the example orientation of four blocks,a crossing point of two nets is shown by a small “red” cross on it. From the figure, itappears that the interconnection wires among the electrodes of the four blocks (shownby dotted “black” lines) have a large number of crossing points (shown by small “red”crosses). Hence, for such orientations, four blocks would require more than one layerand a large number of vias.

4. PROPOSED SCHEME OF WIRE ROUTING FOR MULTICHIPS

4.1. Circular Wire Routing of an N × N Multichip

We propose a scheme for placement or orientation of four blocks such that interconnec-tion wire routing can be done on a single layer. To ensure this, we place the blocks so thatthe electrodes labeled as “1” are mutually adjacent to each other and are equi-distantfrom the center (“O”) of the multichip as shown in Figure 4. For such an orientation(called label-symmetric orientation), all the identically addressed electrodes will beat the same distance from “O”. For the simplicity of drawing, the interconnections ofidentically addressed electrodes is shown in the figure with “red” dotted concentriccircular wires. In a practical situation, these circular wires may be implemented asthree-quarter rectilinear interconnection wires. As evident from the figure, these inter-connection wires do not cross each other and therefore can be routed on a single layer.Another layer is required to route the interconnection wires from the electrodes to the

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Via

PinWire 2

Layer 2

Layer 1Wire 1

Electrode

Fig. 5. Three-dimensional view of circular wire routing under an electrode.

external control pins as shown in Figure 4 by “green” lines. Thus, a simple two-layerwire routing scheme with a linear number of vias can solve the interconnection problemin a pin-constrained design for four identical blocks. A three-dimensional view of wirerouting beneath an electrode is depicted in Figure 5.

4.1.1. Congestion of Interconnection Wires for an N×N Multichip. If K is the length of the sideof an individual 25-electrode block (square), then the distance of the farthest electrode(“25”) from the center “O” is roughly K

√2. From Figure 4, we may observe that within

this diagonal distance of K√

2 all the 25 interconnection circular wires will have tobe routed. The electrodes have fixed dimension of each, and let a be the length of theside of a square-shaped electrode (called electrode pitch). The number of circular wirespassing through a band of width a

√2 varies in accordance to a certain sequence as the

distance from the center increases. By counting the number of wires passing throughevery a

√2 interval along the central diagonal, the congestion pattern can be obtained

for different block sizes.The congestion of interconnection routing wires along the diagonal can be computed

as follows. We partition the rectangular N × N box into N annular regions by con-structing N concentric circles (C1, C2, . . . , CN), each centered at “O”. The circle C1 hasa radius of v

√2, where a via is assumed to be a square of size v × v, taking into account

of some additional clearance needed between the center “O” and the top-left cornerof the via. These concentric circles are shown in “black” color (Figure 4). Thus, theconcentric circle i has a radius of di as [(i − 1).a + v]

√2, where i ∈ [1, N]. The distance

between two consecutive concentric circles is a√

2 along the diagonal.The actual wire routing for the electrodes is shown as “red” circles in Figure 4. Let,

f (i) be the number of electrode vias within the distance di from the center “O”; thenthe electrodes whose vias fall within the circular region between the two consecutive“black” circles can be computed as f (i + 1) − f (i), for all i ∈ [1, N]. Some values ofwiring congestion for a four square-block (N × N) multichip with varying block sizesare shown in Table I, in which the first column shows the block size as N × N, thesecond column indicates the total number of electrodes (i.e., N2), the third columnshows the ordered sequence of electrodes with increasing distance from the center “O”and the last column presents the congestion values at consecutive intervals of lengtha√

2 across the diagonal from the center “O” to a block corner. The congestion patternmay be represented as a “congestion vector, for example,” for a 5×5 array, the congestionvector is 〈1, 3, 5, 11, 5〉 (Table I).

The average congestion is clearly N, where N ∗ N is the total number of electrodesin each block. However, the maximum congestion value turns out to be 11, 11, 13, and15 for a multichip with 5 × 5, 6 × 6, 7 × 7, and 8 × 8 blocks, respectively. Thus, asthe block size increases, the maximum congestion of wires increases and it demandsprogressively denser wire-routing through a fixed-size annular corridor, and thereforean efficient routing solution is needed. One way to resolve it is to equally distribute

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Congestion-Aware Layout Design for High-Throughput Digital Microfluidic Biochips 17:9

Table I. Wire Routing Congestions for Different Block Sizes (assuming full-circular wires; inpractice three-quarter circular wires can be used to interconnect four blocks)

N × N N2 Sequence of electrodes Congestion vector{{1},{6,2,7},{11,3,12,8,13},

5 × 5 25 {16,4,17,9,18,14,21,5,22,10,19}, 〈1, 3, 5, 11, 5〉{23,15,24,20,25}}

{{1},{7,2,8},{13,3,14,9,15},6 × 6 36 {19,4,20,10,21,16,25,5,26,11,22}, 〈1, 3, 5, 11, 11, 5〉

{27,17,31,28,23,6,32,12,33,18,29},{34,24,35,30,36}}

{{1},{8,2,9},{15,3,16,10,17},{22,4,23,11,24,18,29,5,30,12,25},

7 × 7 49 {31,19,36,32,26,6,37,13,38,20,33}, 〈1, 3, 5, 11, 11, 13, 5〉{39,27,43,7,44,14,45,21,40,34,46,28,41},

{47,35,48,42,49}}{{1},{9,2,10},{17,3,18,11,19},

{25,4,26,12,27,20,33,5,34,13,28},8 × 8 64 {35,21,41,36,29,6,42,14,43,22,37}, 〈1, 3, 5, 11, 11, 15, 13, 5〉

{44,30,49,7,50,15,51,23,45,38,52,31,57,8,58},{46,16,53,39,59,24,60,32,54,47,61,40,55},

{62,48,63,56,64}}

Wire

ElectrodeVia

d

va

a√

2

Fig. 6. Geometrical specification of wire routing for a multichip (4 square blocks) with the proposed scheme.

all the N2 wires over a distance of K√

2 by using multiple wiring layers. Interestingly,consideration of certain geometric characteristics of the electrode locations leads toan elegant routing solution of a large-size multichip, which we present in the nextsubsection.

4.1.2. An Estimate of Number of Layers Required on a PCB - A Detailed Geometrical Study of WireRouting for a Multichip. We consider certain simple geometric properties while allocatingthe wiring layers required for complete routing of all the N2 wires in a multichip offour N × N blocks. As shown in Figure 6, let a be the electrode pitch, v be the via side-length, and d be the thickness of the wire used for interconnection of electrodes. Hence,N interconnection wires can be routed through the vias of N diagonal electrodes. Theinterconnections for the remaining electrodes should be made through the annularregions between two consecutive circular wires corresponding to the two electrodesalong the diagonal (as shown the figure). Effectively, there are (N − 1) such circularregions, each of width (a − v)

√2, through which a fixed number of wires can be laid on

a single layer. Thus, multiple layers are required with the increasing block size, thatis, with the increasing values of N.

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Fig. 7. Illustration of wire routing limit on a PCB [Xu et al. 2008].

Let WL=1 denote the number of interconnecting circular wires that can be accommo-dated in a single layer beneath the electrodes. Thus,

WL=1 = N +⌊

(N − 1)(a − v)√

2d

⌋(1)

assuming that the required spacings between two adjacent electrodes, between twoadjacent vias, and between two adjacent circular wires are included within a, v and d,respectively. Now, let L(N, N, a, v, d) be the number of layers required to accommodateN2 circular wires, while one single layer can accommodate WL=1 circular wires. Hence,

L(N, N, a, v, d) =⌈

N2

WL=1

⌉. (2)

It may be noted that several fabrication technologies are now available to manu-facture a digital microfluidic biochip. Commercial PCBs can accommodate up to 30separate wiring layers, which are electrically accessed through drilled vias that haveCu-electroplated inner walls [Gong and Kim 2008]. For its maturity and low cost, PCBtechnology has widely been used in microfluidic systems. Table II shows some details offabrication technologies commonly used to develop DMF biochips by several researchgroups. In PCB technology, the diameter of a via hole is usually comparable to the elec-trode pitch size [Xu et al. 2008]. Therefore, there is only a limited number of controllines that can be routed on one layer of a PCB. For example, the via hole diameter maybe 40% of the electrode pitch. Hence, only four control pins can be wired in any row(Figure 7).

For a particular fabrication technology, the values of a, v, and d may be assumed asconstants, and thus the value of L(N, N, a, v, d) will depend on the block size N. How-ever, the electrode pitch size and the via size may vary from one fabrication technologyto another (see Table II). In summary, we consider different values of a as 0.5, 0.6, 0.7,0.75, 0.9, 1.0, 1.125, 1.4, and 1.5 (in millimeters).

Let us assume that Nmax be the maximum block size of a multichip that can befabricated using only one layer of interconnection wires on a PCB. To show the variationof the maximum block size (Nmax), we have plotted Nmax versus a, v, and/or d. The valuesof a are assumed to be 0.5, 0.6, 0.7, 0.75, 0.9, 1.0, 1.125, 1.4, and 1.5 (in millimeters).We show the plot of the computed values of Nmax for different values of electrode pitch(shown in Figure 8(a)). Here, we have considered the via sizes (v) to be 0.15 and 0.2mm and the wire width to be 0.125 mm.

In another plot (Figure 8(b)), we have shown the variation of the computed valuesof Nmax against via sizes for a particular electrode pitch size (1.5 mm). The via sizes(v) have been considered to be 25%, 30%, 35%, 40%, and 45% of the correspondingelectrode pitch, and the wire width is assumed as 0.125 mm.

It may be noted that the value of d is determined by the minimum width of theconnecting wire as used in a particular fabrication process. In the last plot shown in

ACM Journal on Emerging Technologies in Computing Systems, Vol. 8, No. 3, Article 17, Pub. date: August 2012.

Congestion-Aware Layout Design for High-Throughput Digital Microfluidic Biochips 17:11

Tabl

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ACM Journal on Emerging Technologies in Computing Systems, Vol. 8, No. 3, Article 17, Pub. date: August 2012.

17:12 S. Roy et al.

2

4

6

8

10

12

14

16

18

0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6

Nm

ax

Electrode Pitch (a) in mm

v=0.15mmv=0.20mm

(a)

2

4

6

8

10

12

14

0.1 0.2 0.3 0.4 0.5 0.6 0.7

Nm

ax

Via Size (v) in mm

a=1.5mma=1.0mma=0.5mm

(b)

2 4 6 8

10 12 14 16 18 20 22 24 26

0.05 0.075 0.1 0.125 0.15 0.175 0.2

Nm

ax

Wire Width (d) in mm

v=0.15mmv=0.20mm

(c)

Fig. 8. Scaling effects on wire routing. (a) Nmax versus electrode pitch, a [wire width, d = 0.125 mm];(b) Nmax versus via size, v [wire width, d = 0.125 mm]; and (c) Nmax versus of wire width, d [electrode pitch,a = 1.5 mm].

Figure 8(c), we have varied the wire width (d) keeping the electrode pitch at a fixedvalue as 1.5 mm and the via size as 0.15 mm and 0.2 mm. The different values of dconsidered are 0.175, 0.15, 0.125, 0.1, and 0.075 (all in mm).

The relation between the maximum block size (Nmax) that can be interconnected on asingle layer for a multichip design and the geometric parameters (a, v and d) of a DMFbiochip has been studied and simulations are performed by varying the electrode pitchsize {a (0.5 mm to 1.5 mm) where v and d are constants}, by changing the via size {v(25% to 45%) where a and d are constants}, and for different wires {d (0.075 mm to0.175 mm) where a and v are constants}. The maximum block size is plotted against a,v, and d in Figures 8(a), 8(b), and 8(c), respectively. From the simulation results it maybe observed that the maximum block size (Nmax) increases with increasing electrodepitch size for a particular via size and wire width; it decreases with the increasing viasize for a fixed electrode pitch size and wire width, and decreases with the increasingwire width for a particular electrode pitch and via size.

4.1.3. Rectilinear Interconnection Wires for an N × N Multichip. In the previous subsection,the interconnection scheme was abstracted by assuming circular wiring. However, thelayout of actual interconnection may be rectilinear in a routing layer. In Figure 9, sucha rectilinear wire routing is shown for a multichip (4 square blocks) with the proposedorientation.

ACM Journal on Emerging Technologies in Computing Systems, Vol. 8, No. 3, Article 17, Pub. date: August 2012.

Congestion-Aware Layout Design for High-Throughput Digital Microfluidic Biochips 17:13

(a) (b)

Fig. 9. Rectilinear wire routing for a multichip (4 square blocks) with the proposed orientation. (a) Layer-1and (b) Layer-2.

Layer 1

Layer 2

Wire 1

Wire 2

Via1Via2

Doglegging Wire

E1E2

DogleggingLayer

Fig. 10. Use of doglegging layer for multilayer rectilinear wire routing of a multichip (one-via and two-viarouting solutions).

Depending on the values of a, v, and d, the layout may require two layers to intercon-nect all the electrodes of a multichip with four 3×3 electrode arrays. One routing layer(Layer-1) is shown in Figure 9(a) with “blue” colored vias, and the second layer (Layer-2)is shown in Figure 9(b) with vias colored “green”. It is clear that in this scheme, one morelayer (called “doglegging layer”) is required for interconnecting the vias on differentlayers, when needed. An example is shown in Figure 10 for two electrodes E1 and E2.

4.2. Circular Wire Routing for an N × M Multichip

For a rectangular biochip block N × M, wire routing can be made in a similar fashionas that of a square block. Figure 11 shows the wire routing for a multichip with fourrectangular blocks, each of size 4 × 7. As before, the interconnection wires do notcross each other and thus routing can be completed on a single layer. Another layeris required for connecting each net to the respective external control pin (shown inFigure 11 by “green” lines). Hence, in general, determining a two-layer wire routingsolution is straightforward for such a multichip.

For a rectangular block (N × M), the number of concentric “black” circles is the max-imum of N and M, that is, max(N, M). Here, some of the concentric “black” circles areassumed to pass through some virtually located electrode vias as shown in Figure 12.For example, V ′

1 and V ′2 are two such vias on two virtually located diagonal electrodes

E′1 and E′

2, and W ′5 and W ′

6 are two such circular wires passing through those vias,

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17:14 S. Roy et al.

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V1 E1

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W5W5W4W3W2W1

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Congestion-Aware Layout Design for High-Throughput Digital Microfluidic Biochips 17:15

respectively. The actual concentric “black” circle W5 may be placed close to W ′5. The

total number of circular wires that can be accommodated on a single layer can becomputed assuming the number of concentric “black” circles as max(N, M).

Let us assume that WL=1 be the number of interconnecting circular wires that can beaccommodated in a single layer beneath the N ∗ M electrodes. Hence, for a multichipwith four rectangular blocks,

WL=1 = max(N, M) +⌊

(max(N, M) − 1)(a − v)√

2d

⌋(3)

with the earlier assumptions concerning the required spacings. If L(N, M, a, v, d) de-notes the number of layers required to accommodate N ∗ M circular wires, and if WL=1circular wires can be laid on one layer, then

L(N, M, a, v, d) =⌈

N ∗ MWL=1

⌉. (4)

4.3. Circular Wire Routing for Hierarchical Placement of 16 Blocks in a Multichip

We now analyze the scalability issues of the proposed scheme for wire routing of apin-constrained biochip with a large number of blocks. These blocks can be placedhierarchically with similar orientation strategy such that the interconnection can beaccomplished hierarchically in the same way as discussed earlier for a multichip withfour blocks. A hierarchical arrangement of 16 blocks (partitioned into four groups,each with four blocks) is shown in Figure 13. In this case, two layers are requiredfor interconnection of the identical electrodes in 16 blocks. The circular wire routingfor interconnection within the individual groups can be made in one routing layer(Layer-1) as shown in Figure 13, whereas that for interconnecting the four groups canbe performed in another routing layer (Layer-2) as shown in Figure 14.

In Figure 13, wire routing for each of the four groups (A, B, C, and D) can be achievedlocally on a single layer as shown by “red” dotted circular lines in the figure. Anotherlayer is required to interconnect the corresponding electrodes of the four central blocks{A3, B4, C1, D2}, as they are placed around the center with the label-symmetric ori-entation. Finally, one more layer is required to connect the external control pins tothe respective nets as shown by “green” lines in the figure. Hence, three layers will besufficient for wire routing in such a multichip with 16 blocks, each one being directlyaddressable. It is worth noting that for the second level of hierarchy, only one extrarouting layer is required. For the aforesaid multichip with 16 blocks, the congestionvector in each of the two layers is 〈1, 3, 5, 11, 5〉. In other words, the maximum conges-tion of wire routing for the 16-block multichip remains only 11, which is same as thatof the basic 5 × 5 block.

In the hierarchical scheme of a multichip, addition of one level increases the numberof routing layers by only one, whereas the size of the biochip in terms of the total numberof electrodes may increase by a factor of 4. Table III summarizes the advantage ofhierarchical placement of blocks in a multichip environment, where we have assumedthat the wire routing including the pin-assignment for 4 identical blocks of 25 electrodes(5 × 5) can be done in two layers as described in Section 4.1. In general, for a multichipwith 4n identical blocks, (n + 1) layers are sufficient for wire routing.

4.4. Circular Wire Routing for a Multichip with Four Pin-Constrainedor Application-Specific Blocks

So far we have assumed that all the electrodes of each individual block are directlyaddressable. The routing solution becomes less complex for a pin-constrained block,

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17:16 S. Roy et al.

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3

B2

Fig. 13. Hierarchical wire routing scheme for a multichip with 16 blocks (each having 5 × 5 array ofelectrodes) - Layer-1.

as the number of independently controlled electrodes becomes fewer. In Figure 15, weshow the interconnection for a multichip with four pin-constrained blocks, where each(5 × 5)-electrode block is controlled by only five pins, as shown in Figure 3 [Xu et al.2008]. Thus, the same label-symmetric orientation strategy holds for pin-constrainedblocks and so does hierarchical routing. The congestion vector of the preceding pin-constrained multichip (shown in Figure 15) is 〈3, 2, 0, 0, 0〉, in contrast to that of directlyaddressable 5 × 5 electrode array, which is 〈1, 3, 5, 11, 5〉 (Table I).

4.4.1. Example DMF Biochips with Pin-Constrained Blocks. In this subsection, we considersome examples of pin-constrained DMF biochips developed for some specific applica-tions. Figure 16(a) shows a layout of electrodes obtained by a pin-count minimizationtechnique known as broadcast electrode addressing scheme [Xu and Chakrabarty2008b]. This biochip can execute all the three assays (multiplexed assay, PCR, and

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Congestion-Aware Layout Design for High-Throughput Digital Microfluidic Biochips 17:17

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Fig. 14. Hierarchical wire routing scheme for a multichip with 16 blocks (each having 5 × 5 array ofelectrodes) - Layer-2.

Table III. Maximum Number of Electrodes that Can Be Accommodated on a Given Number of Routing Layersfor Hierarchical Placement

Maximum # of electrodes that can be accommodated# of routing layers Flat (No hierarchy) 2-level hierarchy 3-level hierarchy 4-level hierarchy1 100 - - -2 200 400 - -3 300 800 1600 -4 400 1200 3200 6400

protein dilution) using only 81 electrodes on the 15 × 15 array. Another exampleof a pin-constrained biochip is shown in Figure 16(b), that has been obtained byapplying the technique called “Connect-5 algorithm” (Bagua repetition) [Xu et al.2008]. This chip can be used as a 4-well-plate protein crystallization platform, where

ACM Journal on Emerging Technologies in Computing Systems, Vol. 8, No. 3, Article 17, Pub. date: August 2012.

17:18 S. Roy et al.

35

24

1

24

13

5

13

52

4

52

51

3

41

35

2

35241

24135

13524

52513

41352

35

24

1

24

13

5

13

52

4

52

51

3

41

35

2

3

1

2

4

5

3 5 2 4 1

2 4 1 3 5

1 3 5 2 4

5 2 5 1 3

4 1 3 5 2

Fig. 15. Two-layer interconnection for four blocks (each with 5 × 5 electrode array controlled by five pins).

Fig. 16. Pin-assignments to the layouts for (a) a multifunctional chip [Xu and Chakrabarty 2008c], and (b) a4-well-plate protein crystallization biochip [Xu et al. 2008].

a unit well size is 6 × 6 and an 11 × 11 array of electrodes is controlled by only5 pins.

4.4.2. Layouts of Application-Specific DMF Biochips. There are several DMF biochips de-veloped/fabricated by several research groups for some particular biochemical applica-tions, and we refer them as Application-Specific Bio-Chips (ASBCs), a few examplesof which can be found in the literature [Srinivasan et al. 2004; Fair 2007; Fair et al.2007; Xu et al. 2008; Sista et al. 2008; Xu and Esko 2009; Malic et al. 2009; Jebrail andWheeler 2009]. An ASBC layout for a golgi-on-a-chip having 10 reservoirs for storingdifferent fluids and with a very sparse electrode array has been fabricated [Xu andEsko 2009]. Another sparse electrode layout of DMF biochip for protein precipitationapplication has been reported with five reservoirs [Jebrail and Wheeler 2009]. In gen-eral, a typical ASBC consists of fewer electrodes compared to a full two-dimensionalarray, and the proposed hierarchical routing strategy works well. Hence, both for a pin-constrained biochip or for an ASBC, the maximum congestion as well as wire routingcomplexity reduces significantly compared to those in a directly addressable array ofelectrodes.

ACM Journal on Emerging Technologies in Computing Systems, Vol. 8, No. 3, Article 17, Pub. date: August 2012.

Congestion-Aware Layout Design for High-Throughput Digital Microfluidic Biochips 17:19

V1 V2 V3 V4 V5

H5

H4

H3

H2

H1

V5 V4 V3 V2 V1

V1

V2

V3

V4

V5

H5 H4 H3 H2 H1

H1 H2 H3 H4 H5

V5

V4

V3

V2

V1

H5

H4

H3

H2

H1

(a)V1 V2 V3 V4 V5

H5

H4

H3

H2

H1

V5 V4 V3 V2 V1

V1

V2

V3

V4

V5

H5 H4 H3 H2 H1

H1 H2 H3 H4 H5

H4

H3

H2

H1

H5

V1

V2

V3

V4

V5

(b)

Fig. 17. Interconnection for (a) horizontal plates and (b) vertical plates of four blocks (each with 5 × 5electrodes controlled by 10 cross-referencing (five horizontal and five vertical) plates) (the “black” smallsquares on each plate indicate vias and the “brown” small circles denote the external control pins).

4.4.3. Multichip with Cross-Referencing Blocks. The cross-referencing technique is alsoused for pin-constrained DMF biochips, in which N × M number of electrodes arecontrolled by only (N + M) external control pins (please see Section 2.2). In a multichipwith four blocks of cross-referenced electrode arrays, one layer is required for intercon-necting the respective horizontal plates from each block and another layer is neededfor the respective vertical plates from each block. Hence, two layers are sufficient tointerconnect the multichip layout (see Figure 17).

5. A COMPLETE MULTICHIP WITH RESERVOIRS AND I/O PATHWAYS

An important issue in the design of a multichip is to plan the transportation of dropletsfrom the reservoirs at the boundary of the multichip to each of the individual blocksexecuting a target bioassay (i.e., input pathways) and also to manage the transportationof waste droplets (i.e., output pathways) to the waste reservoirs. We present an exampleof a four-block, pin-constrained multichip with four reservoirs at the boundary as shownin Figure 18. The common corridor formed by the electrodes (“orange” colored) can beused as input or output pathways of droplets for each of the four blocks.

For concurrent execution of a bioassay in all the basic blocks of a multichip, inputdroplets from a dispenser should be loaded to the corresponding boundary electrodesof all the four blocks. Similarly, waste droplets from each of the basic blocks are tobe drained to an external waste reservoir. Therefore, sequential loading/unloading ofsample/waste droplets in a large multichip will require a significant amount of time. Tospeed up the process, parallel loading(unloading) of sample (waste) droplets in pipelinemay be adopted while satisfying fluidic constraints to prevent any accidental mix/splitwhile transporting multiple droplets concurrently [Chakrabarty and Xu 2010].

We assume a four-block multichip, and for each of the four electrodes (with the samelabel) we observe its shortest Manhattan distance from the dispenser. We then rank theelectrodes with the nonincreasing distance values. The droplet targeting the farthestdestination is dispensed first and that for the nearest one is dispensed last. However,the shortest paths for two droplets may overlap, and hence, to avoid any violation offluidic constraints, two idle time slots are kept between dispensing of two consecutivedroplets, where a time slot represents the amount of time taken by a droplet to movefrom one electrode to any one of its neighbors. The droplets can be moved in a pipelineto reach their respective destination electrodes, which are adjacent to the I/O pathways.

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17:20 S. Roy et al.

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Fig. 18. Layout of a multichip (shown in Figure 4) with four external reservoirs and I/O droplet pathways(A and B are fluid reservoirs, W1 and W2 are waste reservoirs).

P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 1P1

P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15P1 1

P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12P1 P17 1

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P2 P3 P4 P5 P6 P7 P8 P9 P10 P11P1 P12 1

Fig. 19. Timing diagram for concurrent loading of sample droplets in pipeline from a boundary dispenserto all the 4 blocks of a multichip.

Figure 19 shows the locations of four droplets moving towards the electrode labeled“1” on each of the four blocks (NE, NW, SE, SW) at consecutive time slots. It is apparentthat the time taken for loading is 22 time slots, whereas the sequential loading time ofthe four droplets for the same destinations turns out to be 60.

Table IV shows a comparative study of the time taken for loading sample dropletsfrom the dispenser A to the corresponding locations on each of the four blocks of themultichip shown in Figure 18. The loading of electrodes labeled “25” requires themaximum time (27 slots). The mechanism of unloading from each of the four blockswill be similar to the strategy described earlier for loading.

6. CONCLUSIONS

In this article, we have presented a brief review on various classes of pin-constrainedDMF biochips. Several wire routing issues have been discussed for a pin-constrained

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Congestion-Aware Layout Design for High-Throughput Digital Microfluidic Biochips 17:21

Table IV. Time Taken to Load a Droplet from A to the Corresponding Positions of All the 4 Blocks of a Multichip

Boundary electrode 1 2 3 4 5 6 10 11 15 16 20 21 22 23 24 25# to be loadedSequential loading 60 62 62 62 62 62 62 62 62 62 62 60 64 64 64 64(time slots)Pipelined loading 22 21 21 22 23 22 24 21 25 22 26 23 24 25 26 27(time slots)

multichip that can concurrently execute multiple instances of the same bioassay fordifferent samples. An orientation scheme has been proposed to reduce the number oflayers required for wire routing underneath the biochip. Finally, we have discussed howthis scheme can be used hierarchically that maintains the scalability of the scheme forlarger-size biochips. It may be noted that the power requirement for electrode actuationmay become high as a bioassay is concurrently executed on the proposed hierarchicalpin-constrained architecture. The effects of this phenomenon on droplet transportationand consequently on assay performance may be studied further.

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Received June 2011; accepted June 2011

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