Appendix A: 8051 Microcontroller Instructions Set

Appendix A: 8051 MicrocontrollerInstructions Set

Data transfer operations

Instruction Byte Cycles Code Symbolic representation

Movement within the microcontroller (no flag is affected)The content of the second register/memory is copied to the content of the first register/memoryMOV A,Rn 1 1 1110 1rrr (PC) (PC) + 1

(A) (Rn)The program counter isadded by one unit, andthe content of the Rnregister is copied to thecontent of theaccumulator(A) register. No flag isaffected

MOV A,direct

2 1 1110 0101directaddress

(PC) (PC) + 2(A) (direct)

The program counter isadded by two units,and the content of theposition of the internalRAM whose address isdirect is copied to thecontent of theaccumulator(A) register

MOV A,@Ri

1 1 1110 011I (PC) (PC) + 1(A) ((Ri))

The program counter isadded by one unit, andthe content of thememory locationwhose address is givenby the content of the Riregister is copied to thecontent of theaccumulator(A) register

MOV A,#data

2 1 0111 0100immediatedata

(PC) (PC) + 2(A) #data

The program counter isadded by two units,and the date value iscopied to the content ofthe accumulator(A) register

(continued)# Springer International Publishing AG, part of Springer Nature 2019S. P. Gimenez, 8051 Microcontrollers,https://doi.org/10.1007/978-3-319-76439-9

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https://doi.org/10.1007/978-3-319-76439-9



MOV Rn,A 1 1 1111 1rrr (PC) (PC) + 1(Rn) (A)

The program counter isadded by one unit, andthe content of theaccumulator(A) register is copied tothe content of the Rnregister

MOV Rn,direct

2 2 1010 1rrrdirectaddress

(PC) (PC) + 2(Rn) (direct)

The program counter isadded by two units,and the content of theinternal RAM locationwhose address is directis copied to the contentof the Rn register

MOV Rn,#data

2 1 0111 1rrrimmediatedata

(PC) (PC) + 2(Rn) #data

The program counter isadded by two units,and the date value iscopied to the content ofRn register

MOV direct,A


(PC) (PC) + 2(direct) (A)

The program counter isadded by two units,and the content of theaccumulator(A) register is copied tothe content of theinternal RAM locationwhose address is direct

MOV direct,Rn

2 2 1000 1rrrdirectaddress

(PC) (PC) + 2(direct) (Rn)

The program counter isadded by two units,and the content of theRn register is copied tothe content of theinternal RAM memorylocation whose addressis direct

MOV direct,direct

3 2 1000 0101dir.adr.srcdir.adr.dest

(PC) (PC) + 3(direct) (direct)

The program counter isadded by three units,and the content of theposition of the internalRAM whose address isdirect is copied to thecontent of the internalRAMmemory locationwhose address is direct

MOV direct,@Ri

2 2 1000 011idirectaddress

(PC) (PC) + 2(direct) ((Ri))

The program counter isadded by two units,and the content of theinternal RAM positionwhose address is given

(continued)

294 Appendix A: 8051 Microcontroller Instructions Set



by the content of the Riregister is copied to thecontent of the internalRAMmemory locationwhose address is direct

MOV direct,#data

3 2 0111 0101dir. adr.immed.data

(PC) (PC) + 3(direct) #data

The program counter isadded by three units,and the date value iscopied to the content ofthe internal RAMlocation whose addressis direct

MOV @Ri,A

1 1 1111 011i (PC) (PC) + 1((Ri)) (A)

The program counter isadded by one unit, andthe content of theaccumulator(A) register is copied tothe content of theinternal RAM positionwhose address is givenby the content of the Riregister

MOV @Ri,direct

2 2 1010 011idirectaddress

(PC) (PC) + 2((Ri)) (direct)

The program counter isadded by two units,and the content of theinternal RAM locationwhose address is directis copied to the contentof the internal RAMposition whose addressis given by the contentof the Ri register

MOV @Ri,#data

2 1 0111 011iimmediatedata

(PC) (PC) + 2((Ri)) #data

The program counter isadded by two units,and the content of theinternal RAM positionwhose address is givenby the content of the Riregister is initializedwith the date value

MOVDPTR,#data16

3 2 1001 0000imme.data15,8imme.data7,0

(PC) (PC) + 3(DPH) #data15,8(DPL) #data7,0

The program counter isadded by three units,and the value data16 iscopied to the content ofthe 16-bit DPTRregister

(continued)

Appendix A: 8051 Microcontroller Instructions Set 295



Moving the content from the programmemory to the content of the accumulator (A) register(no flag is affected)MOVC A,@A + DPTR

1 2 1001 0011 (PC) (PC) + 1(A) ((A) + (DPTR))

The program counter isadded by one unit, andthe content of theprogram memoryposition addressed bythe sum of the contentsof the accumulator(A) and DPTRregisters is copied tothe content of theaccumulator(A) register

MOVC A,@A + PC

1 2 1000 0011 (PC) (PC) + 1(A) ((A) + (PC))

The program counter isadded by one unit, andthe content of theprogram memoryposition addressed bythe sum of the contentsof the accumulator(A) and PC registers iscopied to the content ofthe accumulator(A) register

Moving the content from the external data memory to the content of the accumulator(A) register and vice versa (no flag is affected)MOVX A,@Ri

1 2 1110 001i (PC) (PC) + 1(A) ((Ri))

The program counter isadded by one unit, andthe content of thememory location of theexternal RAM whoseaddress is given by thecontent of the Riregister is copied to thecontent of theaccumulator(A) register

MOVX A,@DPTR

1 2 1110 0000 (PC) (PC) + 1(A) ((DPTR))

The program counter isadded by one unit, andthe content of thememory location of theexternal RAM whoseaddress is given by thecontent of the DPTRregister is copied to thecontent of theaccumulator(A) register

(continued)




MOVX@Ri,A

1 2 1111 000i (PC) (PC) + 1((Ri)) (A)

The program counter isadded by one unit, andthe content of theaccumulator(A) register is copied tothe content of thememory location of theexternal RAM whoseaddress is given by thecontent of the Riregister

MOVX@DPTR,A

1 2 1111 0000 (PC) (PC) + 1((DPTR)) (A)

The program counter isadded by one unit, andthe accumulator(A) register is copied tothe content of thememory location of theexternal RAM whoseaddress is given by thecontent of the DPTRregister

Storing data with direct addressing in the stack (no flag is affected)PUSH direct 2 2 1100 0000

directaddress

(PC) (PC) + 2(SP) (SP) + 1((SP)) (direct)

The program counter isadded by two units, thecontent of the stackpointer (SP) register isadded by one unit(it points to the nextmemory location), andthe content of theregister/memorylocation < src > iscopied to the content ofthe memory locationwhose address is givenby the contents of theSP register

Reading data from the stack to the content of data memory with direct addressing (no flag isaffected)POP direct 2 2 1101 0000

directaddress

(PC) (PC) + 2(direct) ((SP))(SP) (SP) – 1

The program counter isadded by two units, thecontent of the memorylocation whose addressis given by the contentof the SP register iscopied to the content ofthe register/memorylocation <dest>, andthe content of the stackpointer (SP) register is

(continued)




decremented by oneunit (it points to thememory position of thepreviously stored datain the stack)

Data exchange (no flag is affected)XCH A,Rn 1 1 1100 1rrr (PC) (PC) + 1

(A)$ (Rn)The program counter isadded by one unit andexchanges the contentof the accumulator(A) register with thecontent of the Rnregister

XCH A,direct


(PC) (PC) + 2(A)$ (direct)

The program counter isadded by two units andexchanges the contentof the accumulator(A) register with thecontent of the positionof internal RAMwhose address is direct

XCH A,@Ri 1 1 1100 011i (PC) (PC) + 1(A)$ ((Rn))

The program counter isadded by one unit andexchanges the contentof the accumulator(A) register with thecontent of the internalRAM position whoseaddress is given by thecontent of the Riregister

XCHD A,@Ri

1 1 1101 011i (PC) (PC) + 1(A3–0)$ ((Rn3–0))

The program counter isadded by one unit andexchanges the contentof the least significant4 bits of theaccumulator(A) register with thecontent of the leastsignificant 4 bits of thecontent of the internalRAM position whoseaddress is given by thecontents of the Riregister

Arithmetic operationsAddition (all flags are affected)ADD A,Rn 1 1 0010 1rrr (PC) (PC) + 1

(A) (A) + (Rn)The program counter isadded by one unit, and

(continued)




the result of theaddition operationbetween the contentsof the accumulator(A) register and Rnregister is stored in thecontent of theaccumulator(A) register

ADD A,direct


(PC) (PC) + 2(A) (A) + (direct)

The program counter isadded by two units,and the result of theaddition operationbetween the contentsof the accumulator(A) register and theposition of the internalRAM whose address isdirect is stored in thecontent of theaccumulator(A) register

ADD A,@Ri 1 1 0010 011I (PC) (PC) + 1(A) (A) + ((Ri))

The program counter isadded by one unit, andthe result of theaddition operationbetween the contentsof the accumulator(A) register and theposition of the internalRAM whose address isgiven by the content ofthe Ri register is storedin the content of theaccumulator(A) register

ADD A,#data


(PC) (PC) + 2(A) (A) + #data

The program counter isadded by two units,and the result of theaddition operationbetween the contentsof the accumulator(A) register and thedate value is stored inthe content of theaccumulator (A)

(continued)




Addition with carry-bit (all flags are affected)ADDC A,Rn 1 1 0011 1rrr (PC) (PC) + 1

(A) (A) + (C) + (Rn)

The program counter isadded by one unit, andthe result of theaddition operationamong the contents ofthe accumulator, thecarry-bit, and the Rnregister is stored in thecontent of theaccumulator(A) register

ADDC A,direct


(PC) (PC) + 2(A) (A) + (C) + (direct)

The program counter isadded by two units,and the result of theaddition operationamong the contents ofthe accumulator, thecarry-bit flag, and theposition of the internalRAM whose address isdirect is stored in thecontent of theaccumulator(A) register

ADDC A,@Ri

1 1 0011 011I (PC) (PC) + 1(A) (A) + (C) + ((Ri))

The program counter isadded by one unit, andthe result of theaddition operationamong the contents ofthe accumulator, thecarry-bit flag, and theposition of the internalRAM whose address isgiven by the content ofthe Ri recorder isstored in the content ofthe accumulator(A) register

ADDC A,#data


(PC) (PC) + 2(A) (A) + (C) + #data

The program counter isadded by two units,and the result of theaddition operationamong the contents ofthe accumulator, carry-bit flag, and date valueis stored in the contentof the accumulator(A) register

(continued)




Subtraction with carry-bit (all flags are affected)SUBB A,Rn 1 1 1001 1rrr (PC) (PC) + 1

(A) (A)-(C)-(Rn)

The program counter isadded by one unit, andthe result of thesubtraction operationamong the contents ofthe accumulator, carry-bit flag, and Rn registeris stored in the contentof the accumulator(A) register

SUBB A,direct


(PC) (PC) + 2(A) (A)-(C)-(direct)

The program counter isadded by two units,and the result of thesubtraction operationamong the contents ofthe accumulator, carry-bit flag, and position ofinternal RAM whoseaddress is direct isstored in the content ofthe accumulator(A) register

SUBB A,@Ri

1 1 1001 010i (PC) (PC) + 1(A) (A)-(C)-((Ri))

The program counter isadded by one unit, andthe result of thesubtraction operationamong the contents ofthe accumulator, thecarry-bit flag, and theposition of internalRAM whose address isgiven by the content ofthe Ri recorder isstored in the content ofthe accumulator(A) register

SUBB A,#data


(PC) (PC) + 2(A) (A)-(C)-#data

The program counter isadded by two units,and the result of thesubtraction operationamong the contents ofthe accumulator, thecarry-bit flag, and thedate value is stored inthe contents of theaccumulator(A) register

(continued)




Adding one unit (increment) [the (C), (AC), and (OV) are not affected]INC A 1 1 0000 0100 (PC) (PC) + 1

(A) (A) + 1The program counter isadded by one unit, andthe content of theaccumulator(A) register isincremented by oneunit

INC Rn 1 1 0000 1rrr (PC) (PC) + 1(Rn) (Rn) + 1

The program counter isadded by one unit, andthe content of the Rnregister is incrementedby one unit

INC direct 2 1 0000 0101directaddress

(PC) (PC) + 2(direct) (ditect) + 1

The program counter isadded by two units,and the content of theinternal RAM positionwhose address is directis incremented by oneunit

INC @Ri 1 1 0000 011i (PC) (PC) + 1((Ri)) ((Ri)) + 1

The program counter isadded by one unit, andthe content of theinternal RAM position,whose address is givenby the content of the Riregister, is incrementedby one unit

INC DPTR 1 2 1010 0011 (PC) (PC) + 1(DPTR) (DPTR) + 1

The program counter isadded by one unit, andthe content of theDPTR register isincremented by oneunit

Subtraction of a unit (decrement) [the (C), (AC), and (OV) are not affected]DEC A 1 1 0001 0010 (PC) (PC) + 1

(A) (A)-1The program counter isadded by one unit, andthe content of theaccumulator(A) register isdecremented by oneunit

DEC Rn 1 1 0001 1rrr (PC) (PC) + 1(Rn) (Rn)-1

The program counter isadded by one unit, andthe content of the Rnregister is decrementedby one unit

(continued)




DEC direct 2 1 0001 0101directaddress

(PC) (PC) + 2(direct) (ditect)-1

The program counter isadded by two units,and the content of theinternal RAM location,whose address isdirect, is decrementedby one unit

DEC @Ri 1 1 0001 011i (PC) (PC) + 1((Ri)) ((Ri))-1

The program counter isadded by one unit, andthe content of theinternal RAM position,whose address is givenby the content of the Riregister, isdecremented by oneunit

Multiplication [all flags are affected, except the auxiliary carry-bit (AC)]MUL AB 1 4 1010 0100 (PC) (PC) + 1

result15–0(A) result7–0(B) result15–8

The program counter isadded by one unit, itmultiplies the contentsof the (A) and(B) registers, and itproduces a resultrepresented by 16 bits.The least significant8 bits of the result arestored in the content ofthe accumulator(A) register, and themost significant 8 bitsare stored in thecontent of the(B) register

Division [all flags are affected, except the auxiliary carry-bit (AC)]DIV AB 1 4 1000 0100 (PC) (PC) + 1

(A) quotient ofthe (A)/(B)(B) rest of the(A)/(B)

The program counter isadded by one unit anddivides the content ofthe (A) register by thecontent of the(B) register. Thedivision quotient isstored in the content ofthe accumulator(A) register, and theremainder is stored inthe content of the(B) register

(continued)




Decimal adjustment (conversion from binary/hexadecimal to BCD code) [carry-bit (C), zero(Z), and parity (P) flags are affected]DA A 1 1 1101 0100 (PC) (PC) + 1

1�) IF {[(A3–0) > 9]OR (AC) ¼ 1} then(A3–0) (A3–

0) + 6;2�) IF {[(A7–4) > 9]OR (C) ¼ 1} then(A7–4) (A7–

4) + 6;

The program counter isadded by one unit andadds the value 6 to theleast significant 4 bitsif (AC) ¼ 1 or theinferior nibble does notbelong to the decimaldigits. It adds the value6 to the mostsignificant 4 bits if(C) ¼ 1 or the superiornibble does not belongto the decimal digits

Logical operations [only the zero flag (Z) is affected and P if (A) is changed]ANDANL A,Rn 1 1 0101 1rrr (PC) (PC) + 1

(A) (A) and (Rn)The program counter isadded by one unit, andthe result of the logicalAND operationbetween the contentsof the accumulator(A) register and Rnregister is stored in thecontent of theaccumulator(A) register

ANL A,direct


(PC) (PC) + 2(A) (A) and(direct)

The program counter isadded by two units,and the result of thelogical AND operationbetween the contentsof the accumulator(A) register and theposition of internalRAM whose address isdirect is stored in thecontent of theaccumulator(A) register

ANL A, @Ri 1 1 0101 011I (PC) (PC) + 1(A) (A) and((Ri))

The program counter isadded by one unit, andthe result of the logicalAND operationbetween the contentsof the accumulator andposition of the internalRAM whose address is

(continued)




given by the content ofthe Ri register is storedin the content of theaccumulator(A) register

ANL A,#data


(PC) (PC) + 2(A) (A) and#data

The program counter isadded by two units,and the result of thelogical AND operationbetween the contentsof the accumulator(A) register and thedate value is stored inthe content of theaccumulator(A) register

ANL direct,A


(PC) (PC) + 2(direc) (direc)and (A)

The program counter isadded by two units,and the result of thelogical AND operationbetween the contentsof the internal RAMlocation, whoseaddress is direct, andthe accumulator(A) register is stored inthe content of theinternal RAM location,whose address is direct

ANL direct,#data

3 2 0101 0011directaddressimmed.data

(PC) (PC) + 3(direc) (direc)and #data

The program counter isadded by three units,and the result of thelogical AND operationbetween the contentsof the position ofinternal RAM, whoseaddress is direct, andthe date value is storedin the content of theinternal RAM memorylocation, whoseaddress is direct

ORORL A,Rn 1 1 0100 1rrr (PC) (PC) + 1

(A) (A) or (Rn)The program counter isadded by one unit, andthe result of the logicaloperation OR betweenthe contents of theaccumulator

(continued)




(A) register and the Rnregister is stored in thecontent of theaccumulator(A) register

ORL A,direct


(PC) (PC) + 2(A) (A) or(direct)

The program counter isadded by two units,and the result of thelogical operation ORbetween the contentsof the accumulator andthe position of internalRAM, whose addressis direct, is stored inthe content of theaccumulator(A) register

ORL A, @Ri 1 1 0100 011I (PC) (PC) + 1(A) (A) or ((Ri))

The program counter isadded by one unit, andthe result of the logicaloperation OR betweenthe contents of theaccumulator(A) register and theposition of the internalRAM, whose addressis given by the contentof the Ri register, isstored in the content ofthe accumulator(A) register

ORL A,#data


(PC) (PC) + 2(A) (A) or #data

The program counter isadded by two units,and the result of thelogical operation ORbetween the contentsof the accumulator(A) register and thedate value is stored inthe content of theaccumulator(A) register

ORL direct,A


(PC) (PC) + 2(direc) (direc) or(A)

The program counter isadded by two units,and the result of thelogical operation ORbetween the contentsof the internal RAMlocation, whoseaddress is direct, and

(continued)




the accumulator(A) register is stored inthe content of theinternal RAM location,whose address is direct

ORL direct,#data


(PC) (PC) + 3(direc) (direc) or#data

The program counter isadded by three units,and the result of thelogical OR operationbetween the contentsof the internal RAMlocation, whoseaddress is direct, andthe date value is storedin the content of theinternal RAM location,whose address is direct

Exclusive-ORXRL A,Rn 1 1 0110 1rrr (PC) (PC) + 1

(A) (A) or-ex(Rn)

The program counter isadded by one unit, andthe result of theOR-EX logic operationbetween the contentsof the accumulator(A) register and the Rnregister is stored in thecontent of theaccumulator(A) register

XRL A,direct


(PC) (PC) + 2(A) (A) or-ex(direct)

The program counter isadded by two units,and the result of theOR-EX logicaloperation between thecontents of theaccumulator(A) register and theposition of internalRAM, whose addressis direct, is stored inthe content of theaccumulator(A) register

XRL A, @Ri 1 1 0110 011i (PC) (PC) + 1(A) (A) or-ex((Ri))

The program counter isadded by one unit, andthe result of theOR-EX logicaloperation between thecontents of the

(continued)




accumulator(A) register and theposition of the internalRAM, whose addressis given by the contentof the Ri register, isstored in the content ofthe accumulator(A) register

XRL A,#data


(PC) (PC) + 2(A) (A) or-ex#data

The program counter isadded by two units,and the result of theOR-EX logicaloperation between thecontents of theaccumulator(A) register and thedate value is stored inthe content of theaccumulator(A) register

XRL direct,A


(PC) (PC) + 2(direc) (direc)or-ex (A)

The program counter isadded by two units,and the result of theOR-EX logicaloperation between thecontents of the internalRAM location, whoseaddress is direct, andthe accumulator(A) register is stored inthe content of theinternal RAM location,whose address is direct

XRL direct,#data


(PC) (PC) + 3(direc) (direc)or-ex #data

The PC is added bythree units, and theresult of the OR logicaloperation between thecontents of the internalRAM location, whoseaddress is direct, andthe date value is storedin the content offinternal RAM position,whose address is direct

Reset [zero flag (Z) only]CLR A 1 1 1110 0100 (PC) (PC) + 1

(A) 00 hThe program counter isadded by one unit, andthe content of theaccumulator(A) register is reset

(continued)




Complementary (all flags are affected)CPL A 1 1 1111 0100 (PC) (PC) + 1

(A) not (A)The program counter isadded by one unit, andthe content of theaccumulator(A) register is storedwith its complement ofone

Rotation [the carry-bit (C) and zero (Z) flags are affected]RL A 1 1 0010 0011 (PC) (PC) + 1

(An + 1) (An) forn ¼ 0 a 6(A0) ¼ (C) (A7)

The program counter isadded by one unit, andthe content of theaccumulator(A) register is rotated1 bit to the left(An + 1) (An) forn ¼ 0 to 6 and(A0) ¼ (C) (A7),where n is the bitindex. Ex: An for n¼ 0corresponds to the 0 bitof the accumulator(A0), An for n ¼ 1corresponds to the 1 bitof the accumulator(A1), and so on

RLC A 1 1 0011 0011 (PC) (PC) + 1(An + 1) (An) for n ¼ 0 a 6(A0) (C) e (C) (A7)

The program counter isadded by one unit, andthe content of theaccumulator(A) register is rotated1 bit to the left(An + 1) (An) forn ¼ 0 to 6 and (C) (A7) and (A0) (C),where n is the bit index

RR A 1 1 0000 0011 (PC) (PC) + 1(An) (An + 1)for n ¼ 0 a 6(A7) ¼ (C) (A0)

The program counter isadded by one unit, andthe content of theaccumulator(A) register is rotatedfrom 1 bit to the right(An) (An + 1) forn ¼ 0 to 6(A0) ¼ (C) (A7),where n is the bit index

(continued)




RRC A 1 1 0001 0011 (PC) (PC) + 1(An) (An + 1)for n ¼ 0 a 6(A7) (C) e (C) (A0)

The program counter isadded by one unit, andthe content of theaccumulator(A) register is rotatedfrom 1 bit to the right(An) (An + 1) forn ¼ 0 to 6 and (C) (A0) ) and (A7) (C),where n is the bit index

Change of the least significant 4 bits with the most significant 4 bits [zero flag (Z) only andparity flag (P)]SWAP A 1 1 1100 0100 (PC) (PC) + 1

(A3–0)$ (A7–4)The program counter isadded by one unit, andthe content of the leastsignificant 4 bits (A3,0)is exchanged with thecontents of the mostsignificant 4 bits (A7,4)of the content of theaccumulator(A) register

Manipulation of Boolean variablesReset (clear)CLR C 1 1 1100 0011 (PC) (PC) + 1

(C) #02The program counter isadded by one unit, andthe carry-bit content isreset [only the carry-bitflag (C)]

CLR bit 2 1 1100 0010bit address

(PC) (PC) + 2(bit) #02

The program counter isadded by two units,and the content of thebit is reset (no flag isaffected)

SetSETB C 1 1 1101 0011 (PC) (PC) + 1

(C) #12The program counter isadded by one unit, andthe content of thecarry-bit (C) flag isstored with the unitvalue [only the carry-bit (C) flag]

SETB bit 2 1 1101 0011bit address

(PC) (PC) + 2(bit) #12

The program counter isadded by two units,and the bit content isstored with the unitvalue (no flag isaffected)

(continued)




ComplementCPL C 1 1 1011 0011 (PC) (PC) + 1

(C) not (C)The program counter isadded by one unit, andthe content of thecarry-bit flag (C) isstored with itscomplement of one[carry-bit (C) flagonly]

CPL bit 2 1 1011 0010 (PC) (PC) + 2(bit) not (bit)

The program counter isadded by two units,and the content of thebit is stored with itscomplement of one(no flag is affected)

ANDANL C,bit 2 2 1000 0010

bit address(PC) (PC) + 2(C) (C) and (bit)

The program counter isadded by two units,and the AND operationresult between thecarry-bit flag and bitcontents is stored in thecontent of the carry-bitflag (C) [only thecarry-bit (C) flag]

ANL C,/bit 2 2 1000 0000bit address

(PC) (PC) + 2(C) (C) and (not(bit))

The program counter isadded by two units,and the result of theAND operationbetween the contentsof the carry-bit flag(C) and thecomplement of one ofthe bit is stored in thecontent of the carry-bitflag (C) (no flag isaffected)

ORORL C,bit 2 2 0111 0010

bit address(PC) (PC) + 2(C) (C) or (bit)

The program counter isadded by two units,and the result of theOR operation betweenthe contents of thecarry-bit flag (C) andthe bit is stored in thecontent of the carry-bitflag (C) [only thecarry-bit (C) flag]

(continued)




ORL C,/bit 2 2 1010 0000bit address

(PC) (PC) + 2(C) (C) or (not(bit))

The program counter isadded by two units,and the result of theOR operation betweenthe contents of thecarry-bit flag (C) andthe complement of oneof the bits is stored inthe content of thecarry-bit flag(C) (no flag is affected)

MoveMOV C,bit 2 1 1010 0010

bit address(PC) (PC) + 2(C) (bit)

The program counter isadded by two units,and the content of thebit is copied to thecontent of the carry-bitflag (C) [only thecarry-bit (C) flag]

MOV bit, C 2 2 1001 0010bit address

(PC) (PC) + 2(bit) (C)

The program counter isadded by two units,and the content of thecarry-bit flag (C) iscopied to the content ofthe bit (no flag isaffected)

Conditional jump (no flag is affected)JC address 2 2 0100 0000

rel address(PC) (PC) + 2If (C) ¼ 1, then(PC) address

The program counter isadded by two units,and if (C) ¼ 1 then(PC) address(it jumps to the addressof the programmemory defined by theaddress); otherwise,the program executesthe next instruction

JNC address 2 2 0101 0000rel address

(PC) (PC) + 2If (C) ¼ 0, then(PC) address

The program counter isadded by two units,and if (C) ¼ 0, then(PC) address(it jumps to the addressof the programmemory defined by theaddress); otherwise,the program executesthe next instruction

(continued)




JB bit,address

3 2 0010 0000bit addressrel address

(PC) (PC) + 3If (bit) ¼ 1, then(PC) address

The program counter isadded by three units,and if (bit) ¼ 1, then(PC) address(it jumps to the addressof the programmemory defined by theaddress); otherwise,the program executesthe next instruction

JNB bit,address


(PC) (PC) + 3If (bit) ¼ 0, then(PC) address

The program counter isadded by three units,and if (bit) ¼ 0, then(PC) address(it jumps to the addressof the programmemory defined by theaddress); otherwise,the program executesthe next instruction

JBC bit,address


(PC) (PC) + 3If (bit) ¼ 1, then(bit) 0(PC) address

The program counter isadded by three units,and if (bit) ¼ 1, then(PC) address(it jumps to the addressof the programmemory defined by theaddress) and zeroes thebit; otherwise, theprogram executes thenext instruction

JZ address 2 2 0110 0000rel address

(PC) (PC) + 2If (A) ¼ 0, then(PC) address

The program counter isadded by two units,and if (A) ¼ 0 [zeroflag (Z) ¼ 1], then(PC) address(it jumps to the addressof the programmemory defined by theaddress); otherwise,the program executesthe next instruction

JNZ address 2 2 0111 0000rel address

(PC) (PC) + 2If (A) 6¼ 0, then(PC) address

The program counter isadded by two units,and if (A) 6¼0 [zero flag(Z) ¼ 0], then (PC) address (it jumps to theaddress of the programmemory defined by theaddress); otherwise,the program executesthe next instruction

(continued)




Call the subroutine (no flag is affected)ACALLaddr11

2 2 a10 a9 a8 10001a7a6a5a4a3a2a1a0

(PC) (PC) + 2(SP) (SP) + 1((SP)) (PC7–0)(SP (SP) + 1((SP)) (PC15–8)(PC) addr11

It calls the subroutinelocated at the programmemory address:The program counter isadded by two units(it calculates the returnaddress); it incrementsthe content of the SPregister (it points to thenext stack address) byone unit; it stores theleast significant byte ofthe content of the PCregister in the contentof the internal memory(stack), whose addressis given by the contentof the SP register; itincrements the contentof the SP register(it points to the nextstack address) by oneunit again; and it storesthe most significantbyte of the content ofthe PC register in thecontent of the positionof internal RAM(stack), whose addressis given by the contentof the SP register

LCALLaddr16

3 2 0001 0010addr15–8 addr7–0

(PC) (PC) + 3(SP) (SP) + 1((SP)) (PC7–0)(SP (SP) + 1((SP)) (PC15–8)(PC) addr16

It calls the subroutinelocated at the programmemory address:The program counter isadded by three units(it calculates returnaddress); it incrementsthe contents of the SPregister (it points to thenext stack address) byone unit; it stores theleast significant byte ofthe content of the PCregister in the contentof the internal memory(stack), whose addressis given by the contentsof the SP register; it

(continued)




increments the contentof the SP register(it points to the nextstack address) by oneunit; and it stores themost significant byte ofthe content of the PCregister in the contentof the position ofinternal RAM (stack),whose address is givenby the contents of theSP register

Return of subroutines (no flag is affected)RET 1 2 0010 0010 (PC) (PC) + 1

(PC15–8) ((SP))(SP) (SP) – 1(PC7–0) ((SP))(SP (SP) – 1

It returns from thesubroutine: it reads theaddress from thecontent of the stackand stores it in thecontent of the PC; theprogram counter isadded by a unit; thecontent of the internalRAM (stack) position,whose address is givenby the contents of theSP register, is copied tothe content of the mostsignificant byte of theprogram counter(PC) register; thecontent of the SPregister (it points to theprevious address of thestack) is decreased byone unit; the content ofthe internal RAM(stack) position, whoseaddress is given by thecontents of the SPregister, is copied tothe content of the leastsignificant byte of theprogram counter(PC) register; and itdecrements the contentof the SP register byone unit (it points tothe previous address ofthe stack)

(continued)




RETI 1 2 0011 0010 (PC) (PC) + 1(PC15–8) ((SP))(SP) (SP) – 1(PC7–0) ((SP))(SP (SP) – 1

It returns from theservice subroutine ofan interruption source:it reads an addressfrom the content of thestack and stores it inthe contents of the PC;the program counter isadded by a unit; thecontent of the internalRAM (stack) position,whose address is givenby the contents of theSP register, is copied tothe content of the mostsignificant byte of theprogram counter(PC) register; itdecreases by one unitthe content of the SPregister (it points to theprevious address of thestack); the content ofthe internal RAM(stack) position, whoseaddress is given by thecontent of the SPregister, is copied tothe content of the leastsignificant byte of theprogram counter(PC) register; and itdecrements thecontents of the SPregister by one unit(it points to theprevious address of thestack)

Unconditional jump (no flag is affected)AJMP addr11 2 2 a10 a9 a8

0 0001 a7... a0

(PC) (PC) + 2(PC10–0) addr11

The program counter isadded by two units,and the value addr11 iscopied to the PCregister

LJMP addr16 3 2 0000 0010addr15–0 addr7–0

(PC) (PC) + 3(PC) addr15–0

The program counter isadded by three units,and the value addr11 iscopied to the PCregister

(continued)




SJMPaddress

2 2 1000000 reladdress

(PC) (PC) + 2(PC) address

The program counter isadded by two units,and the address valueis copied to the PCregister

JMP@A + DPTR

1 2 0111 0011 (PC) (PC) + 2(PC) ((A) + (DPTR))

The program counter isadded by two units,and the content of theinternal RAM position,whose address is givenby the sum of thecontents of the A andDPTR registers, iscopied to the PCregister

Conditioned subroutine call [the carry-bit (C) and zero (Z) flags are affected]CJNE A,direct,address

3 2 1011 0101directaddress reladdress

(PC) (PC) + 3If (A) 6¼ (direct),then it calls thesubroutine whoseaddress is addressIf (A) < (direct),then (C) #12;otherwise, (C) #02

The program counter isadded by three units,and if (A) 6¼(direct),then it calls thesubroutine whoseaddress is [(PC) address], and it storesthe return address ofthe subroutine in thestack (memory addressof the instructionprogram following theinstruction “CJNE A,direct, address,” and itperforms theoperations described inthe LCALL addressinstruction); otherwise,the program executesthe next instructionsubsequent to thatinstruction. Inaddition, if (A) is lessthan the content of theinternal RAM locationwhose address isdirect, the carry-bit flag(C) is set; otherwise, itis reset

CJNE A,#data,address

3 2 1011 0100immed.address reladdress

(PC) (PC) + 3If (A) 6¼ #data, thenit calls thesubroutine whoseaddress is address

The program counter isadded by three units,and if (A) 6¼date value,then it calls thesubroutine whose

(continued)




If (A) < #data, then(C) 1;otherwise, (C) 0

address is [(PC) address], and it storesthe return address ofthe subroutine in thestack (address programmemory of theinstruction followingthe instruction “CJNEA,#data, address,” andit performs theoperations described inthe LCALL addressinstruction); otherwise,the program executesthe next instructionsubsequent to thatinstruction. Inaddition, if (A) is lessthan data value, thecarry-bit flag (C) is set;otherwise it is reset

CJNE Rn,#data,address

3 2 1011 1rrrimmed.address reladdress

(PC) (PC) + 3If (Rn) 6¼ #data,then it calls thesubroutine whoseaddress is addressIf (Rn) < #data ,then (C) 1;otherwise, (C) 0

The program counter isadded by three units,and if (Rn) 6¼datevalue, it calls thesubroutine whoseaddress is [(PC) address], and it storesthe return address ofthe subroutine in thestack (address programmemory of theinstruction followingthe instruction “CJNERn,#data, address,”and it performs theoperations described inthe LCALL addressinstruction); otherwise,the program executesthe next instructionsubsequent to thatinstruction. Inaddition, if (Rn) is lessthan the data value, thecarry-bit flag (C) is set;otherwise, it is reset

(continued)




CJNE @Ri,#data,address

3 2 1011 011iimmed.address reladdress

(PC) (PC) + 3If ((Ri)) 6¼ #data,then it calls thesubroutine whoseaddress is addressIf ((Ri)) < #data,then (C) 1;otherwise, (C) 0

The program counter isadded with three units,and if ((Rn)) 6¼datevalue, then it calls thesubroutine whoseaddress is address[(PC) address], and itstores the returnaddress of thesubroutine in the stack(address programmemory of theinstruction followingthe instruction “CJNE@Ri,#data, address,”and it performs theoperations described inthe LCALL addressinstruction); otherwise,the program executesthe next instructionsubsequent to thatinstruction. Inaddition, if ((Rn)) isless than data value,the carry-bit flag (C) isset; otherwise, it isreset

Decrements a unit and jumps if nonzero [only zero flag (Z) is affected]DJNZ Rn,address

2 2 1101 1rrrrel address

(PC) (PC) + 2(Rn) (Rn)-1IF (Rn) 6¼ 0 then(PC) address

The program counter isadded by two units, thecontent of the Rnregister is decrementedby one unit, and if thecontent of the Rnregister is differentfrom zero, the programjumps to the address[(PC) address]

(continued)




DJNZ direct,adress

3 2 1101010 directaddress reladdress

(PC) (PC) + 3(direct) (direct)-1If (direct) 6¼ 0, then(PC) address

The program counter isadded by three units;the content of theposition of internalRAM, whose addressis given by direct, isdecreased by one unit;and if the content of theposition of the internalRAM, whose addressis given by direct, isdifferent from zero, theprogram jumps to theaddress [(PC) address]

Não executa nada (nenhum flag é afetado)NOP 1 1 0000 0000 (PC) (PC) + 1 O contador de

programa é somado deuma unidade


Index

AAddresses of service subroutines, 235Addressing by register, 102–103Addressing modes, 74, 75, 102–106Assembly programming, 131–165Asynchronous, 272, 273Auxiliary carry-bit flag (AC), 96–98, 100

BBaud rate, 273–280, 283, 285, 286, 288, 290Bounce, 207–213, 216–219, 221–223

CCalling a subroutine, 167, 172–180Carry-bit flag (C), 95–97, 100, 102, 109, 112,

113, 117, 120, 122, 125, 126Clock, 65–69, 75, 88–90Combined or mixed addressing, 102, 105–106Computer systems, 1–59

DData memory, 61, 64–67, 69, 72–89, 92, 93Direct addressing, 103

EExternal interruptions, 229–230, 233–236, 239

FFirmware, 42, 44, 45, 57, 59Flip-flop, 3, 11, 12, 19, 20, 43Flowchart, 9, 10, 46–51, 53, 59, 131–165Full duplex, 273

HHardware, 19, 24, 31, 33, 42, 44, 45, 49,

53–55, 57

IImmediate addressing, 104Indirect by base registers, 102, 104Indirect or indexed by register, 102–106Input port, 191–223Instructions, 95–117, 119–121, 126, 127Instruction set, 95–129Internal architecture, 61–64Internal Oscillator (Clock), 21–22Interruption enable (IE), 226, 233, 235Interruption priority, 233, 234Interruption sources, 225–236, 239

MMachine cycle, 68, 69, 87–89MCS-51, 61, 62, 64, 70, 71, 74, 78, 88, 89,

92, 93Memory, 1, 11–21, 26, 34, 35, 41–51, 53,

55–58Memory organization, 64–80Microcomputer, 21, 41–45, 57, 58Microcontroller, 21–23, 29–34, 37, 38, 45–46,

48, 54–57, 59Microprocessor, 1, 21, 22, 41–49, 51, 54–59Mode 0, 242, 245, 247–249, 251, 267,

275–276, 279–281, 283Mode 1, 243, 245, 249, 251, 258, 267, 268,

274–280, 283, 285, 286, 288, 290Mode 2, 243, 246, 249, 258, 267, 268,

276–280, 285, 288, 290Mode 3, 244, 246, 250–251, 278–280, 290

# Springer International Publishing AG, part of Springer Nature 2019S. P. Gimenez, 8051 Microcontrollers,https://doi.org/10.1007/978-3-319-76439-9

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https://doi.org/10.1007/978-3-319-76439-9

NNumeral systems, 1–7, 58

OOperation modes, 242–245, 247–251Output port, 191–223Overflow-bit flag (OV), 98–99

PParity bit, 273–275, 277, 278Pin description, 64Program memory, 61, 64–73, 80–82, 88, 89,

92, 93Programming, 13, 15, 17, 18, 42, 44,

47–54, 59Program status word (PSW), 95–102, 114,

117–128Pulse width modulation (PWM), 36–38

QQueue, 167–168

RRegister, 3, 4, 7, 19, 41–44, 54–58Registers’ banks, 74–76Reset, 22–23, 57, 58Reset (initialization) signal, 68, 71, 72, 75,

87–88, 90, 91, 93, 94Returning of a subroutine, 167, 172–180

SSBUF, see Serial buffer (SBUF)SCON, see Serial control (SCON)Sequential software, 132, 136–139, 144Serial buffer (SBUF), 274–278, 280, 281, 283,

285, 286, 289Serial communication interface, 271–319Serial control (SCON), 274–281, 283, 285, 288SFRs, see Special function registers (SFRs)Software with loop, 140–143Special function registers (SFRs), 65, 67, 68,

73, 74, 78–80, 87, 88, 91, 92, 94Stack, 167–180, 182, 187Stack pointer (SP), 168–180Start bit, 273, 274, 276–278, 280Stop bit, 273–279Subroutine, 167–188

TTimer control (TCON), 246Timer mode (TMOD), 245, 250, 251Timers/counters, 226, 229–235, 241–269Timing routines, 204–206TMOD, see Timer mode (TMOD)

VVariable management, 225–229

ZZero-bit flag (Z), 101–102

322 Index

Appendix A: 8051 Microcontroller Instructions Set

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