Analysis of Ultra Wide Band Four stage Distributed Low Noise Amplifier in TSMC 0.18μm Process

International Journal of Research in Computer Engineering and Electronics. Page # 1 ISSN 2319-376X VOL :2 ISSUE :6 (Dec’ 2013)

Analysis of Ultra Wide Band Four stage

Distributed Low Noise Amplifier in TSMC 0.18μm

Process

Habib Muhammad Nazir Ahmad [1]

, Mohammad Shafquatul Islam[2]

, Arman Riaz Ochi [3]

Abstract—

In communication circuitry detection of ultra weak signals at reception end is delicate. In order to have preci-

sion performance and acceptable gain in ultra wide band frequency range the noise performance and power

consumption for low noise amplifier is significant. Among different techniques, this paper presents the simu-

lated result for a distributed low noise amplifier with four stage amplification to ensure minimum noise figure

as well as low power consumption. The simulation work is based on TSMC 0.18μm process parameter.

Index terms- Ultra Wide Band (UWB), Distributed circuit theory, Low Noise Amplifier (LNA), Distributed Low Noise Amplifier

(DLNA), Noise Figure (NF), Transmission Line (TL).

—————————— ——————————

I INTRODUCTION

In Ultra Wide Band (UWB) receiver's front end Low

Noise Amplifier (LNA) must retain good performance

(i.e., low noise figure, high gain, wide bandwidth,

proper input-output isolation etc ). In UWB band (3.1-

10.6 GHz), LNA receives small signals and when ampli-

fies tend to maintain good signal to noise (SNR) ratio.

Recent manuscripts have reported to achieve stable gain

and low noise LNAs , several techniques have been pro-

posed to accomplish required wide band matching at the

input of LNA. There are four types of input matching

circuits available which includes resistive, 1/gm method

using common gate configuration, shunt feedback and

wideband band pass termination method.

Though the resistive feedback architecture has accept-able wide band , they suffer from poor NF and gain [1] Common-gate low-noise amplifier (CG-LNA) [2] and CMOS resistive feedback amplifiers, designed for the UWB lower frequency band (i.e., 3–6GHz), exhibit poor performance in the UWB upper band due to the device’s parasitic capacitances. The inductance of Ls in CG-LNA extends the bandwidth of the input match-ing. However, the Noise Figure of the CG LNA is con-siderably larger than that of the CMOS common-source or cascode LNAs. Previously employed in common-source LNAs in [3] and [4], the gm-boosting technique was proposed by [5] to improve the NF per-formance of a UWB CG LNA. References [6] and [7] independently designed the first lumped LNA circuits for the UWB radio using a cascode circuit and high-order wideband band pass filters (BPF)’s to provide wideband input matching. But an important point regarding NF's reported in [6] and [7] were that it's not flat across the 7.5 GHz bandwidth. And in band NF of LNA [6] mismatch related with frequency dependent resistance (50 Ω) found from the gate terminal of transistor.

________________________________

[1] Habib Muhammad Nazir Ahmad is an Assistant Professor, Ameri

can International University – Bangladesh.

[2] Mohammad Shafquatul Islam is Lecturer at American Intenaional

University – Bangladesh.

[3] Arman Riaz Ochi is Lecturer at American Internaional University

– Bangladesh.


A distributed method with multiple gain stages along actual or artificial transmission lines (TLs) can show wideband characteristics. In distributed circuits the source impedance is matched to the termination im-pedance. In the process the input and output capaci-tances of gain stages will be absorbed to the input and output TLs.

2. DISTRIBUTED CIRCUITS THEORY

The following block diagram (figure-1) shows a Dis-

tributed Amplifier consisting of TLs and gain stages

where gain stages can be a common source amplifier

stage. TLs can be realized as cascaded LC circuits. The

circuit Bandwidth can be determined by the cut off

frequency of TLs as in frequency domain the parasitic

capacitance of transistor's are absorbed into the con

Fig. 1: Capacitance estimation

stants of TLs [8]. Though distributed circuits consume

more power than conventional lumped circuits, the

architecture is highly manageable in terms of technol-

ogy scaling.

For Distributed circuit with N stages the power con-

sumption will be N times that of a single stage am-

plifier. In distributed circuits the source impedance is

matched to the termination impedance. Considering

the gm stage with resistive matching shown in Fig. 2

(a). The lower bound noise factor F of the gm stage

with bias current of I is

F = = 1 + + (1)

Zin

Zin

Zin Zin

RF RL

RS

RG

LS

LSL2

L1 C1

C2

LG

(a) (b)

(c) (d)

Fig. 2: Different approach to calculate input imped-

ance

If the gm stage consumes N.I just to match the current

consumption of an N stage distributed amplifier, then

gm increases proportional to √N, hence the device

noise contribution is reduced by factor of 1/√N. Al-

though the noise contribution from the RG remains

unchanged, no matter how much power is burned in

the gm stage. Now considering an N stage distributed

amplifier comprising N identical gm stages, where

these stages are distributed along the input/output

TLs. The input matching network is again resistive

realized by the resistive termination of the TLs. How-

ever, in distributed circuits the input/output matching

is intrinsically provided by the use of transmission

lines.

The noise from RS travels toward the output from each

path and reaches coherently to the output just similar

to the main desired signal. Therefore, the total output

noise power due to the source resistance is:

Total Output Noise due to Source Resistance =

But the noise from the resistive matching termination

reaches at the output form N paths with different de-

lays. As a result, they all become uncorrelated at the

V in

V out

Z 0

Z 0

C 0 C

0

C i C

i

A A

V 1

AV 1

C i : Input Parasitic Capacitance of gain stage plus external capacitances

:


output. One can thus easily calculate the total output

noise power due to the resistive termination, which is

the sum of the noise powers contributed by each path.

i.e.,

Total Output Noise due to Gate Resistance =

Thermal noise sources from all gm stages will add up

at the output portion and can be calculated by the fol-

lowing:

Total Output Noise due to gm = NkT gd0

Therefore at lower bound the Noise Factor of an N

stage distributed amplifier can be calculated

FN = = 1 + ( +

For Distributed circuit, increasing number of stages

lead to more power consumption but it will reduce

the noise contribution of the active device as well as

noise contribution of the matching resistance hence

improve the total noise factor. In fact under the same

amount of power consumption, Distributed Amplifier

exhibits lower noise factor than lumped amplifiers.

The conventional DA is potentially unstable. In addi-

tion, any voltage/current variation in either gate or

drain TL’s terminations will be coupled to the other TL

through CGD of the common-source transistor. A DA

with cascode cell can mitigate these deleterious effects

[8,9,10]. However, common-gate transistors of each

cascode cell begin to contribute significant noise to the

output at high frequencies, thereby degrading the cir-

cuit’s NF.

Indicated in Fig. 3 is the schematic of the proposed N-

stage UWB DLNA comprising uniform gate and drain

artificial LC TLs and identical cascode cells. Each cell

employs a cascode configuration to guarantee stability

across the entire bandwidth by providing isolation

between the cell’s input and output terminals. The

inter stage inductors of the gate (drain) TL along with

gate (drain) parasitic capacitances of transistors Mak1

(Mak2), 1 ≤ k ≤ N, constitute cascaded LC ladder cir-

cuits with characteristic impedance of

where Ci,cs is the

input capacitance of the common-source stage and

Co,cg is the output capacitance of the common-gate

stage within each cascode cell. Both ZG and ZG stay

constant over a wide range of frequencies. In this de-

sign, both ZG and ZD are chosen to match the 50Ω

source/load resistances.

The gate and drain TLs boost the BW by absorbing the

input and output parasitic capacitances of each cell.

These TLs do not, however, affect the frequency roll-

off due to large parasitic capacitance seen at the inter-

nal node of a conventional cascode cell, where the

drain of the common-source transistor is short-

circuited to the gate of the common-gate transistor.

The proposed DLNA topology is based on a uniform

distributed architecture, therefore,

LCk = LCr = LC, for all k r.

In the absence of LC, the circuit bandwidth is primari-

ly limited by the pole associated to the internal node

of the cascode cells whose value is -1 where Co,cs is the

output capacitance of the common-source transistor,

Ci,cg is the input capacitance of the common-gate

transistor, and gm,cg is the transconductance of the

common-gate transistor in each cascode cell.

Fig. 3: Schematic of 4 stage DLNA


Figures 4 (a) and (b) show the AC equivalent and

high-frequency small-signal model of the k-th cascode

cell with BW-enhancing inductor LC, seen from the

internal node of the cascode cell. The high-frequency

model of Fig. 1 is used to obtain the transfer function

Vdk (s)/Vgk (s)

Fig. 4: (a) AC equivalent of BW-enhanced cascode cell

and (b) small signal model

LC makes the equivalent impedance Zo,cs , seen look-

ing up from Vdk and expressed as

Zo,cs(s) = (LCCi,cgs2+gm,cg LCs+1)/(gm,cg+Ci,cgs), be-

have inductively at high frequencies. This impedance

effectively determines the series resonant frequency

ωn,z = (LCCi,cg)−1/2 of the transfer function Vdk (s)/Vgk

(s) of the k-th cell, and is in parallel with the output

impedance of common-source transistor Mak1 which

is capacitive. Using the circuit model of Fig. 4 (b), the

transfer function Vdk (s)/Vgk (s) of the k-th cell is readi-

ly obtained as:

for 1 N

The parallel resonant frequency can be found as:

To increase the bandwidth while avoiding large fre-

quency peaking, the transfer function Vdk (s)/Vgk (s)

should hold specific characteristics including:

1. The numerator should be in the form of a maximal-

ly flat polynomial, implying that the damping factor

z is 1/√2

2. The denominator should exhibit small peaking in

frequency domain, which leads to additional BW in-

crease. A damping factor of 1/2 (i.e., p = 0.5) results in

a peaking of 1.25dB. Additionally, the parallel reso-

nant frequency ωn,p becomes equal to the 0-dB fre-

quency, where the magnitude response of the transfer

function crosses the 0dB axis after experiencing 1.25

dB peaking

By choosing ωn,p = ωn,z , the 0-dB cutoff frequency of

the transfer function Vdk (s)/Vgk (s) is boosted to ωn,p.

Moreover, it results in a frequency peaking of less

than 10%, This criterion along with the above design

guidelines 1 and 2 provide sufficient information to

calculate the inductance LC and the new 3-dB band-

width as follows:

The bias for cascode transistors in all constituent cells

is provided by a single current mirror, as shown in

Fig. 3 The artificial LC gate line provides the wide-

band input impedance matching, thereby obviating

the need for inductive degeneration for each cascade

cell of the DLNA circuit.

TL inductors are designed such that the same charac-

teristic impedance of 50Ω is obtained at each tap-point

of the gate and drain lines so as to maximize the pow-

er transfer toward the load termination. The gate line’s

inductor LG is larger than the drain line’s inductor LD,

because the input capacitance is larger than the output

capacitance of each cell.


3.NOISE ANALYSIS

The dominant intrinsic noise sources in the DLNA are:

(1) thermal noise from the input source impedance

(RS = ZG; ZG is the gate line’s characteristic imped-

ance defined earlier), (2) thermal noise from the gate

and drain terminations, and (3) dominant noise

sources associated with each MOS transistor including

the channel thermal noise, gate-induced noise, and

flicker noise.

The noise analysis of partially correlated channel

thermal noise Id,k and gate-induced noise Ig,k of the

kth stage, the gate-induced noise is first decomposed

into its correlated and uncorrelated components [8, 11,

12]; i.e.,

, where kB is the Boltzmann’s constant (1.38065×10−23

Joule/◦K), T is the absolute temperature, gg,k =

𝜉ω2C2GS,k/gm,k for 1 ≤ k ≤ N, is a technology-

dependent constant, and c is the correlation coefficient

[defined as whose value for

long-channel devices is approximately j0.395 [8, 11].

Moreover, gm,k = gm,csk for 1 ≤ k ≤ N

The noise contribution of MOSFETs of the k-th stage to

the output is calculated by accounting for both for-

ward and backward propagations of these noise

sources. In calculating the noise contribution of MOS-

FETs, the TLs are assumed to have identical propaga-

tion constants. The DLNA’s power gain with the same

input and output matching impedances will be max-

imized if the LC TLs have identical propagation con-

stants

Fig. 5: Forward Propagation of dominant device noise

sources

Fig. 6: Backward Propagation of dominant MOSFET

noise sources

Simple calculations reveal that the noise contributions

of the source impedance Rs = ZG, the gate-line termi-

nation ZG, and the drain-line termination ZD to the

output are calculated as follows (see [13]):

Source impedance =


Gate termination =

Drain termination =

Noise contributions of various noise sources to the

output noise power of the DLNA were calculated the

definition of the spot NF yields

NFtot = NFHF +

, where

NFHF = 1 +

And NFHF denotes the high-frequency NF and ZT =

ZG = ZD. The flicker noise corner frequency, fcorner , is

simply determined by equating the mid-range fre-

quency value of NFHF with the low-frequency value

of NFtot , resulting in

, where K1/ f is the process dependent flicker noise

constant with typical values less than 10−26V2F [14]

Differentiating the circuit NF with respect to N yields

As an approximation, the noise contribution of the

flicker noise can be neglected, which simplifies

The design optimization procedure utilizes the GBW

expression obtained from [23] in terms of the −3dB

bandwidth, i.e.

where

A0 = DC gain

ω-3dB = -3dB cutoff frequency of the amplifier (rad/sec)

ωmax = MOSFET's maximum frequency of oscillation

(rad/sec)

a = N

b = N

X-3dB = ω-3dB ω-3dB

where Ro,cg denotes the output resistance of the com-

mon gate stage in each cascode cell.

1. For a flat magnitude response across the UWB

band, set f−3dB = 13GHz. TheTLs’ cutoff frequency, fc,

defined as: fc = 2/[ ] = 2/[ ] is calcu-

lated so as to ensure that Nβ l , l ∈ Z. To achieve

maximum gain for frequencies up to the UWB upper

corner frequency, we set a = 0.70 and b = 0.30. Moreo-

ver, N = Nopt, and Nopt is obtained for minimum NF.

2. The maximum bias current for which the MOS tran-

sistors of each cell remain in saturation is calculated

for the bias circuit used This current is readily calcu-

lated as ID,max = VT HN/Nopt ZT .

3. We calculate the maximum DC gain, A0.

4. Equation in [15] gives the DC gain of a conventional

distributed amplifier as

This equation holds for the DLNA of Fig. 4 with iden-

tically matched transistors Mak2 and Mak1 for the

each cascode cell. All the parameters are expressed

with respect to gate aspect-ratio of transistors, W/L.


Fig. 7: Gain of 4 stage DLNA

gate line’s inductance is chosen to be 912 pH and the

gate input capacitance is 270 fF resulting in a line cut-

off frequency of 20.28 GHz VDD = 1.8V and the over-

all current consumption of 15.45 mA So the total Pow-

er consumption 27.81 mW.

5. Using step 4, calculate the W/L. This W/L results in

minimum NF and maximum gain.

6. Obtain minimum NF.

4.SIMULATION RESULTS

TSMC 0.18 RF CMOS technology was used to design

the DLNA. Optimum W/L ratio is used as 215 m /

0.18 m . The values of parameters 𝜉 = 5 ,

Fig. 8: Noise Figure of 4-stage DLNA

5.CONCLUSION

The Stage can be increased to lower the noise figure and

more tweaking in inductance and capacitance can

ovide possible improvement at gain and decrement of

power dissipation.

Reference BW

(GHz)

S21 (dB) NF

(dB)

Power

(mW)

[8] 0.1-23 14.5 0.9 5 54

[16] 1-25 7.8 1.3 4.8-7 54

[17] 0.5-14 10.6 3.5-5.7 52

[18] 0-11 10 3.2-6 100

This De-

sign

3-11 12.5 0.5 2.7-4.1 27.81 mW

Table I : Performance Comparison of LNA circuits:


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Analysis of Ultra Wide Band Four stage Distributed Low Noise Amplifier in TSMC 0.18μm Process

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