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Laboratory for Manufacturing andSustainabilityUC Berkeley

Peer Reviewed

Title:A Hybrid Life Cycle Inventory of Nano-Scale Semiconductor Manufacturing

Author:Krishnan, NikhilBoyd, Sarah, UC BerkeleySomani, Ajay, Massachusetts Institute of TechnologyDornfeld, David, UC Berkeley

Publication Date:03-19-2008

Series:Green Manufacturing and Sustainable Manufacturing Partnership

Publication Info:Green Manufacturing and Sustainable Manufacturing Partnership, Laboratory for Manufacturingand Sustainability, UC Berkeley

Permalink:http://escholarship.org/uc/item/7931209f

Abstract:The manufacturing of modern semiconductor devices involves a complex set of nanoscalefabrication processes that are energy and resource intensive, and generate significant waste.It is important to understand and reduce the environmental impacts of semiconductormanufacturing because these devices are ubiquitous components in electronics. Furthermore,the fabrication processes used in the semiconductor industry are finding increasing applicationin other products, such as microelectromechanical systems (MEMS), flat panel displays,and photovoltaics. In this work we develop a library of typical gate-to-gate materials andenergy requirements, as well as emissions associated with a complete set of fabricationprocessmodelsusedinmanufacturingamodernmicroprocessor. In addition, we evaluate upstreamenergy requirements associated with chemicals and materials using both existing process lifecycle assessment (LCA) databases and an economic input-output (EIO) model. The result isa comprehensive data set and methodology that may be used to estimate and improve theenvironmental performance of a broad range of electronics and other emerging applications thatinvolve nano and micro fabrication.

A Hybrid Life Cycle Inventory ofNano-Scale SemiconductorManufacturingN I K H I L K R I S H N A N , * , † S A R A H B O Y D , ‡

A J A Y S O M A N I , § S E B A S T I E N R A O U X , |

D A N I E L C L A R K , ⊥ A N D D A V I D D O R N F E L D ‡

Columbia University, New York, NY, University of California,Berkeley, CA, Massachusetts Institute of Technology,Cambridge, MA, Transcarbon International, San FranciscoCA, and Applied Materials Inc., Santa Clara, CA

Received May 18, 2007. Revised manuscript receivedJanuary 25, 2008. Accepted January 29, 2008.

The manufacturing of modern semiconductor devices involvesa complex set of nanoscale fabrication processes that areenergy and resource intensive, and generate significant waste.It is important to understand and reduce the environmentalimpacts of semiconductor manufacturing because these devicesare ubiquitous components in electronics. Furthermore, thefabrication processes used in the semiconductor industry arefinding increasing application in other products, such asmicroelectromechanical systems (MEMS), flat panel displays,and photovoltaics. In this work we develop a library oftypical gate-to-gate materials and energy requirements, aswell as emissions associated with a complete set of fabricationprocessmodelsusedinmanufacturingamodernmicroprocessor.In addition, we evaluate upstream energy requirementsassociated with chemicals and materials using both existingprocess life cycle assessment (LCA) databases and an economicinput-output (EIO) model. The result is a comprehensive dataset and methodology that may be used to estimate and improvethe environmental performance of a broad range of electronicsand other emerging applications that involve nano andmicro fabrication.

1. IntroductionSemiconductor devices are ubiquitous components of mod-ern electronics. Device fabrication is complex, involvingnumerous process steps that use a broad set of specializedequipment in a tightly controlled environment. Over the pastfew years, life cycle assessment (LCA) has been increasinglyused to assess the environmental implications of semicon-ductor fabrication. A 2002 study highlighted the importanceof assessing manufacturing and upstream environmentalimpacts associated with semiconductor devices (1). Otherstudies have worked toward developing within-facility (gate-to-gate) semiconductor manufacturing inventory data (2–7).Some of these studies present data from the fab as a black-box (2, 3), whereas Smati and collaborators present a“bottom-up” gate-to-gate inventory analysis with a focus on

gaseous emissions (4) and Murphy and collaborators developa methodology to parametrize semiconductor gate-to-gateinventories with a focus on material and electricity inputs(5).

However, there are three key gaps in previous work thatthis analysis addresses: (i) Given rapid rates of technologicalchange and an emerging set of nanofabrication applicationsthere is a need for an analysis methodology and a library ofmanufacturing data that is transparent and structured toallow for modifications; (ii) Previous work has typicallyfocused on fabrication process-related material and energyinputs. There is a need to both quantify unit process emissionsand the impacts of auxiliary equipment at the facility scale;(iii) There is a need for streamlined methodologies to assessupstream impacts of manufacturing chemicals, materials andequipment infrastructure.

In this work, we first develop a bottom-up, within-fab lifecycle inventory (LCI) for semiconductor fabrication (Figure1). We follow an approach similar to Murphy (5), but alsobase our analysis on equipment sets (7) in order to estimateconfigurations and materials/energy flows related to auxiliaryequipment (pumps, chillers, heat exchangers, abatementsystems, etc.) required in the subfab (typically below thecleanroom floor), or at the facilities scale. Additionally, wesignificantly add to Murphy’s work by developing andpresenting a detailed library of material and energy processmodels (both input and emissions) for a complete set ofmanufacturing processes. The primary contribution of ourwork is a detailed and transparent bottom-up analysis ofwithin-fab inventories (both inputs and emissions) of a broadset of fabrication processes used to manufacture a modernmicroprocessor.

Second, we utilize a hybrid approach, an emergingmethodology in LCA, to perform a streamlined evaluation ofthe impacts of upstream chemicals and equipment (Figure1). Hybrid approaches combine conventional process-basedLCA (8) with input-output (IO) LCA strategies (9) (Figure 1).A conventional process-model based life cycle study ofupstream chemical/material impacts is problematic becauseof the significant data gaps associated with specialty chemi-cals. Our work represents the first attempt to apply a hybridapproach to a complete set of semiconductor manufacturingprocesses. Such an approach combines the strengths ofprocess LCA (assessment of impacts associated with specificproducts and technologies) and IO LCA (representation ofthe complete supply chain), providing a more inclusive modelof upstream impacts (10). At this point we restrict our analysisof upstream environmental impacts to primary energyrequirements.

2. Methodology and Scope

The manufacturing of a modern semiconductor device mayinvolve hundreds of different process steps. We focus hereon high performance complementary metal-oxide semicon-ductor (CMOS) logic devices (microprocessors), althoughmany fabrication steps are similar for different device typesor in different applications that use nano or microfabricationprocesses. Integrated circuits are manufactured on high-purity silicon substrates (wafers), using ultrapure chemicalsand materials in clean-rooms. Each finished wafer is com-prised of hundreds of individual devices called “dies”. Oncethe wafer is diced, the dies are packaged into chips.

In its most basic form, semiconductor manufacturinginvolves variations on the following three methods. First,thin films of materials are deposited on the wafer using

* Corresponding author phone: 1-212-854-9366; fax: 1-212-854-7081; e-mail: nk2162@columbia.edu.

† Columbia University.‡ University of California.§ Massachusetts Institute of Technology.| Transcarbon International.⊥ Applied Materials Inc.

Environ. Sci. Technol. 2008, 42, 3069–3075

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Published on Web 03/19/2008

physical or chemical processes. This is followed by lithog-raphy, the coating the wafer with sacrificial photosensitivematerials to transfer a pattern through a mask. Finally, thethin films are etched, resulting in the transfer of the patternto the films. Other processes are related to the introductionand control of dopants required for transistor active regions(ion implant), planarize films, clean substrates, etc. Detailson fabrication processes appear in the Supporting Informa-tion.

In this work we use a case example of a modernsemiconductor microprocessor at the 130 nm technology“node” (defined by the smallest feature size fabricated in arepeated array). Devices are fabricated on silicon wafersubstrates that are 300 mm in diameter, and we choose thiswafer as a functional unit. The microprocessor described inthis work is equivalent to a Pentium 4. Each 300 mm wafercan produce 442 such functioning Pentium 4 equivalentprocessors (the wafer can be diced into 491 processors, witha mature die yield of approximately 90%).

Fabrication of the microprocessor is modeled based ona process flow consisting of 195 sequential steps, 53 of whichrepresent unique steps that are repeated with some modi-fications. The entire inventory and process flow are includedin the Supporting Information, Tables S2–S17 . While theexisting process flow is most readily adapted to model otherintegrated circuits (including logic devices, memory andanalog devices), our models cover a wide range of typicalnanofabrication technologies (different processing tech-niques and materials), and are linked to the thickness offilms deposited, etched or grown. The underlying data setcan therefore be adapted by LCA practitioners to model otherproducts such as flat panel displays, photovoltaics andmicroelectromechanical systems (MEMS). The data set maybe adapted by (i) adjusting the process flow; (ii) scaling unitprocesses inventories based on different film thicknesses;(iii) scaling the inventory based on changes in substrate area,and (iv) modifying or adding specific processes or materials.

We primarily use process emissions, abatement efficiency,and energy consumption data (from 2002 to 2006) that werecollected as part of a long-running and ongoing measurementprogram at Applied Materials Inc. For the purposes of thiswork, the process flow is organized into four key manufac-turing modules: silicon on insulator (SOI), shallow trench

isolation (STI), gate stack, and interconnect. Each moduleconsists of numerous individual unit process steps performedon different equipment sets. To perform an inventoryanalysis, we organize facility mass/flow data according toprocess and equipment sets to construct a library ofenvironmental process models. For each process step, ahierarchy of three data components is required:

(i) Unit process inputs/outputs: This includes informationon identity of and mass of chemicals and other resourcesused as well as emissions.

(ii) Point-of-use (POU) infrastructure requirements: Eachprocess tool is supported by infrastructure equipment locatedin the subfab, such as pumps, chillers, heat exchanger, POUabatement equipment, and gas panels.

(iii) Facility infrastructure: Emissions from equipment mayrequire additional treatment at the facility scale (end of pipe),prior to discharge. Also, resources used by equipment mayrequire facilities support. We include mass and energy dataassociated with systems such as fluoride waste treatment,house scrubbers, heating ventilation, and air conditioning(HVAC), etc.

A description of key fabrication processes, POU infra-structure modules and facility infrastructure modules appearin the Supporting Information.

A hybrid approach is used to evaluate upstream energyrequirements. We combine the use of detailed process-basedLCA databases for some chemicals and materials with aneconomic input-output LCA (EIO-LCA) model developedat Carnegie Mellon (11) for all other upstream inputs(Figure 1).

In this work our focus is on materials and energy use insemiconductor manufacturing and nanofabrication pro-cesses. We, therefore, close the boundaries of the analysis atthe point at which wafer processing is complete (Figure 1).We exclude steps related to the dicing of wafers into dies andthe packaging of dies in ceramic materials, the mountingand assembly of packaged chips onto circuit boards, andsubsequent end of life impacts associated with the devices.We briefly touch upon use-phase electricity consumption inthe discussion section.

FIGURE 1. Scope and boundary of analysis.

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3. Manufacturing-Stage Life Cycle Material InventoryResults

Details on selected material and energy flows are presentedbelow. Additional information and detailed inventory tablesare included in the Supporting Information, Tables S3–S17.The electrical demands in the fab are illustrated in Figure 2.Process electricity accounts for approximately two-thirds ofthe total electrical demands inside the facility. Depositionand etch processes are seen to drive process electricityconsumption. Electricity consumption at the facility scale isdriven by clean-room air cooling and airflow (which includespurification), followed by process cooling water (PCW)pumping and cooling, and ultrapure water (UPW) purificationsystems.

Manufacturing processes often involve the use andemission of perfluorocarbons (PFCs) that have high globalwarming potentials. POU abatement based on combustionor plasma technologies can be located downstream of processchambers and used to break down emissions (Figure 3).Considering all processes, POU abatement reduces globalwarming impact of chamber emissions from 61 kg carbonequivalent (kgCE)/wafer to 13 kgCE/wafer, which is close toan 80% reduction. Conventional facility abatement systemsuse water scrubbers and provide no abatement of GHGs.

All deposition processes use a plasma to clean residuesfrom chamber walls in between deposition steps. In ourinventory, we consider chamber cleaning technologies thatuse NF3 remote plasma formation (plasma is formed externalto the process chamber). This technology is increasinglyfinding adoption, because it helps reduce both GHG emis-sions and clean times (12). Despite this improvement, PE-CVD (a deposition process) still remains the largest con-tributor to GHG emissions (Figure 4). Etch processes are thesecond largest contributors primarily due to emissions ofN2O, which is not abated as efficiently as other GHGs.

Volatile organics are a growing concern for fabs, and areused in parts cleaning, lithographic processes, and to a lesserextent, in deposition. Only deposition steps have POUabatement of VOCs, in which trimethyl-silane (TMS) is abatedwith a typical efficiency of >98% (Figure 5). Other processVOCs may be abated at the facility level through oxidation,at efficiencies between 95 and 99%. Liquid organic wastesof propylene glycol monomethyl ether (PGME), p-cresol,m-cresol and formaldehyde are collected through solventdrains and hauled away for further treatment.

4. Upstream Energy RequirementsWe use a hybrid formulation (10) to estimate upstream energyrequirements (eq 1), where E refers to life cycle primary energy

FIGURE 2. Fab electricity consumption: process vs facility.

FIGURE 3. Greenhouse gas (GHG) emissions: postprocess, post-point of use (POU) abatement, and postfacility abatement to air.

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requirements and the subscripts i and j refer to inputs thatare modeled using process-based LCA and IO LCA respec-tively.

ELife_Cycle )∑i

EProcessSum,i +∑j

EIO,j (1)

Such a formulation expands the number of inputs that wecan include in the analysis. While we explicitly includeupstream inputs related to chemicals, silicon wafer produc-tion, and equipment, such an approach may still leave outother upstream processes that may be important. RunningEIO-LCA for the semiconductor sector offers a rough estimateof processes that may be important and that are not included.In terms of primary energy demand, there are eight sectorsin the top 25 (that together contribute to approximately 11%of total primary energy) that may have been excluded in ouranalysissrelated to transportation, wholesale trade, ware-housing, and storage, paper manufacturing, couriers, andmanagement of companies. Given that the top 25 mostimportant sectors account for close to 90% of total primaryenergy requirements, we estimate that our hybrid LCAformulation may undercount primary energy by at least 12%.

Chemical Manufacturing. As described before, modernsemiconductor manufacturing involves the use of hundreds ofspecialty chemicals and materials, most of which are of highpurity. For a modern microprocessor this means that somechemicals have allowable metallic contamination levels of 0.1-1ppb (13). LCI data on high purity or specialty chemicals areextremely scarce in the literature (13, 14), and chemicalmanufacturers are reluctant to share process information owingto proprietary concerns. To make this analysis tractable, wetherefore leave out purification energy requirements from anyprocess LCI data used with the understanding that this mayresult in a degree of undercounting of energy. We identify anexamination of purification energy requirements, along withdetailed gate-to-gate LCI for semiconductor chemicals, alongthe lines of previous work on bulk chemicals (15, 16), as animportant topic of future work.

Given these limitations, when upstream life cycle chemicalmanufacturing energy data exist (even if for industrial grades),we use these numbers. For our process flow, total energy usefrom process LCI amounts to 580 MJ/wafer. For the remainingchemicals, we use EIO-LCA. The price per unit mass ofspecialty chemicals can be up to 2–3 orders of magnitude

FIGURE 4. Global warming potential of post POU abatement emissions by process (% kgCE/wafer).

FIGURE 5. Organic compounds: postprocess, post-point of use (POU) abatement, postfacility abatement to air, and liquid haul away.

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greater than bulk chemicals (10–100 $/kg as opposed to 1$/kg for bulk chemicals). It is, therefore, not reasonable touse specialty chemical prices in combination with EIO-LCAsupply chain energy intensities (Esc) for bulk chemical sectors.Bulk chemical sectors represent a high energy consumptionfor a low $ value. We therefore adopt an approach describedby Williams (17) and utilize the sector, photographic film,paper plate and chemical manufacturing, that has an Esc of7.5 MJ/$ (Esc,photo_films), that is similar to the silicon supplychain (Esc,Si ) 5 MJ/$). Upstream energy requirements forthe remaining chemicals (Erem_chem) are obtained by multi-plying this Esc figure with the sum of the producer prices forall corresponding input chemicals, Cj (124 $/wafer in 1997$) resulting in 930 MJ/wafer (eq 2). Estimates for producerprices are obtained from semiconductor industry sources.

Erem_chem ) (Esc,photo_filmsMJ$ ) · (∑

j

C$

wafer)) (7.5) · (124)

MJwafer

) 930MJ

wafer(2)

Silicon Wafer Production. We estimate energy require-ments related to silicon using data from the literature. Toform 1 kg of crystalline silicon wafer, 2,127 kWh of electricityis required (1), which translates to 2,900 MJ/wafer for astandard 300 mm wafer. This energy figure accounts for:processing of mined quartz into metallurgical grade Si,purification of metallurgical Si into an ingot and processingof the ingot into wafers.

Equipment Manufacturing. We use an IO approach toestimate the embedded energy of semiconductor capitalequipment. Esc for the sector, semiconductor machinerymanufacturing (Esc, semi_equipment) is 7.09 MJ/$. A typical fabproducing microprocessors on 300 mm wafers invests roughly$ 1.1 billion (in 1997 $) in equipment, Cequipment (18) andproduces 6000 wafer starts per week (NWspw). Althoughsemiconductor manufacturing processes change rapidly(with time cycles of 18 months), equipment lasts much longerand often has a lifetime of 10 years (t ) 520 weeks). Processchambers may be upgraded or modified, but the coreequipment platform remains. Also, older equipment are oftenused to run less critical processes. As a first-order estimate,we leave out the embedded energy related to chamberupgrades and maintenance (parts, supplies) and estimateequipment embedded primary energy as below (eq 3).

FIGURE 6. Life cycle primary energy requirements.

FIGURE 7. Specific processing energy (MJ/mm3) vs process rate (mm3/s).

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EEquipment ) (Esc,semi_equipmentMJ$ ) · (Cequipment$

NWspw · t )) (7.09) ×

( 1.1 · 109

6, 000 · 520)) 2, 500MJ

wafer(3)

5. Uncertainty

Of the various components of the hybrid LCI modelpresented, the material and energy inventory related tosemiconductor manufacturing is the most up to date andaccurate. Material flows are primarily based on processrecipes, and an emissions measurement program at AppliedMaterials. Stoichiometric balances are used to check massflows, and most unit process mass balances are closed within10%. Care must be taken, however, in translating the datapresented to any specific logic or memory product. Variationsin recipes, overall process flow (number and type of steps),and presence of different types of abatement equipment willinfluence the inventory. For example, fabs that do not havePOU abatement equipment for GHGs may have a factor of4–5 more GHG emissions as compared with fabs that do(Figure 3). Additionally, technological change occurs rapidlyin the semiconductor industry. While the addition of newprocesses or process modifications with new technologynodes will require that the underlying data set be modified,we have attempted to streamline the process of updatingthis analysis by presenting detailed and disaggregatedinventory tables (at the unit process level).

We expect there is greater uncertainty in the models usedfor estimation of upstream energy requirements. In additionto known issues with EIO and process LCAsowing to errorsin economic data, errors in sector aggregation, and potentialboundary errors with process LCA (8–10)sthere are two keysources of uncertainty. First, as described before, the hybridmodel we have used requires an explicit definition ofupstream inputs (we have included chemicals, equipmentand silicon) and may exclude some important processes.Second, we have somewhat excluded chemical purificationenergy. The process LCI data we have used are associatedwith industrial grades (90–99% purity range) (19–22). Puri-fication energies associated with industrial chemical gradescould be several MJ/kg; by comparison, semiconductor gradesilicon requires processing energies of 10–100 MJ/kg (1). Itis doubtful, however, that such large purification energieswould be required for all semiconductor grade chemicals.Data on the production of H2O2 indicates that industrial graderequirements are 6.7 MJ/kg. Processing to super large scaleintegration (SLSI) specifications that emerged in the mid1990s (<1 ppb of impurity metals) requires an additional 1.3MJ/kg and to extra large scale integration (XLSI) specificationsthat emerged in the late 1990s (<100 ppt of impurity metals)requires an additional 0.2 MJ/kg (13). The EIO-LCA modelwe use may account for purification energy to a certain extent,because we use the energy intensity (MJ/$) value of thephotographic film sector. If a purified specialty chemicalsector existed, it may have a lower energy intensity thanphotographic films (specialty semiconductor chemicals havehigher specific energy but are also significantly moreexpensive). For both these reasons (exclusion of upstreamprocesses and partial exclusion of purification energy), ouranalysis should be viewed as a lower bound on total life cycleenergy.

6. DiscussionEnergy Consumption. We estimate the total primary energyrequirement associated with upstream (chemicals andinfrastructure) and device manufacturing at 14 100 MJ/wafer,with about half of this going to device fabrication itself (7100MJ/wafer for a 6-layer microprocessor), followed by siliconwafer production (2900 MJ/wafer) (Figure 6). It is interesting

to note that equipment infrastructure, at 2500 MJ/wafer andchemical manufacturing (1510 MJ/wafer) represent a non-negligible fraction of the overall amount. While our estimatefor chemical energy is slightly higher than that by Williams(1020 MJ/wafer) (1), it may still be an underestimate, sincewe only approximately account for purification energyrequirements.

Our estimate for fabrication energy consumption relatedto process equipment alone is 4700 MJ/wafer, which is lowerthan Murphy’s figure of 8000 MJ/wafer (5) (wafer size, whichvaries among these studies, is normalized to 300 mm forcomparison). Our overall result for semiconductor fabricationenergy (combining process and facility infrastructure) is 7100MJ/wafer, which is lower than that cited by both Williams(11 900 MJ/wafer) (1) and Yao (16 600 MJ/wafer) (6). Dif-ferences between these studies may be driven by technologyevolution. Our analysis is based on more recent fabricationtechniques and involves larger, 300 mm wafers that tend tocost more and are less energy efficient per unit area ofproduction (23). Furthermore, both Williams and Yao use a”top-down” type of approach to estimate energy/wafer so itis reasonable to find that these studies are more inclusiveand have energy estimates higher than those found in ourwork. In particular, our estimate for facility infrastructureenergy use may be low.

Use phase energy consumption for a logic device designedon the 130 nm node and produced on 300 mm wafers is anIntel Pentium 4 processor, which uses 6–8 W of power inoperation (6). The lifetime of a desktop computer is takento be three years (17) and we assume a home use at a dutycycle of 3 h/day, with no standby (24). Such a processor willconsume 20–26 kWh of electrical energy over a lifetime ofuse, which translates to 211–281 MJ/die of primary energyfor 10.7 MJ of primary energy per kWhr (1). Given that 442Pentium 4 Northwood processors are produced per wafer,we determine use phase energy to be 93–124 GJ/wafer. Thisquantity is almost a factor of 8 larger than our total upstreamproduction chain energy estimate. This result is consistentwith analysis performed by Yao et al. (6) in which gate-to-gate manufacturing energy for a Pentium 4 (3.5 kWhr/die)is an order of magnitude lower than use-phase energy number(25–45 kWhr/die). The result is, however, contrary to thatpresented by Williams (1), in which an analysis of a 32 MBDRAM device indicates that fabrication energy (27 MJ/die)exceeds use-phase energy (15 MJ/die). The primary reasonfor this discrepancy is the significantly lower power require-ments of the DRAM device (0.3 W) when compared with alogic device (6–8 W). In order to reduce overall energyconsumption of logic devices, use phase power reductionand effective power management are the most importantareas requiring improvement. For memory and passivedevices, semiconductor fabrication energy consumption isrelatively more important.

Energy Consumption in Nanofabrication. Researchershave conjectured that manufacturing processes used tomanipulate materials at smaller (“nano”) length scales mayhave disproportionately high energy demands (1, 25). Gu-towski and collaborators have examined the specific manu-facturing energy (the energy per unit volume materialaddition or removal, MJ/mm3) for a range of manufacturingprocesses (25). They observe that specific manufacturingenergy increases dramatically with increasing precision, andthat an inverse trend is observed between specific manu-facturing energy and rate of material removal.

Based on our data sets, we develop an equivalent processenergy map for several key fabrication processes used insemiconductor manufacturing (Figure 7). Our results alsoindicate an upward trend in specific manufacturing energyas a function of decreasing processing rate (increasingprecision). Given trends toward increasing precision and

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nanoscale fabrication in semiconductor and other applica-tions (smaller features, thinner films), the results indicatethat it may be important to examine energy consumptionrelated to nanofabrication processes in more detail. Theprocesses with highest specific energy consumption are forma-tion of the gate oxide (thermal oxidation) and CVD of thin films(TiN CVD and LPCVD of silicon nitride). The analysis presentedonly considers the specific processing energy within themanufacturing facility. As mentioned before, additional workis also required to quantify energy requirements related toultrapure materials used in nanofabrication.

The semiconductor industry has made significant progressin improving its environmental performance, and continuesto develop a proactive environmental roadmap (6, 26).However, it is important for the semiconductor industry,and other industries using nanofabrication processes, tocontinue to optimize fabrication processes, and to reducethe use and emissions of toxic and hazardous materials. Ourlife cycle inventory model provides a methodology and dataset to quantify the environmental implications of a broad setof nanofabrication processes. It is our hope that manyapplications and tools will emerge from this work.

AcknowledgmentsWe thank Mehran Moalem of Applied Materials Inc. forhelpful comments. The manuscript reviewers also providedinvaluable feedback.

Supporting Information AvailableSection A: Acronym guide; Section B: Semiconductor manu-facturing overview; Section C: Manufacturing process flow;Section D: Supplemental results; Section E: Detailed inventorytables; Figures S1–S8; Tables S1–S17. This material is availablefree of charge via the Internet at http://pubs.acs.org.

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