TSV Cu Plating and Implications for CMP

TSV Cu Plating and Implications for CMP

A. Radisica, H. G. G. Philipsena, M. Honorea, Y. S. Wanga, N. Heylena, Z. El-Mekkia, S. Arminia, K. Vandersmissena, S. Rodeta, A. Van Ammela, H. Bendera, C. Drijboomsa,

K. Vanstreelsa, and W. Ruythoorena

aimec, Kapeldreef 75, 3001 Leuven, Belgium

In the work presented here, we focused on fabrication of Cu nails for 3D Stacked-Integrated-Circuits (3D-SIC) applications using electrochemical deposition from the bath with model (‘open source’) additives. We have studied the effects of bath composition on the Cu fill profile and overburden, and have also examined the correlations between phenomena observed during post-plating-processing and bath composition. Based on these results, we explored different approaches to improving Cu removal rate during Chemical Mechanical Polishing (CMP).

Introduction In the past, we have explored the possibility of void-free Cu fill of vias with aspect ratios ranging from 2 to 8 (height/diameter) (1-5), on both coupon- and wafer-level, using in-house made chemistry with model additives. These additives are also sometimes referred to as ‘open source’, or ‘public domain’ additives. We chose to work with the model additives for several reasons, such as the direct control over the bath composition, and the abundance of scientific literature detailing their properties and role in Cu plating (6-11). The most important reason for choosing these additives is that they can provide super-conformal fill of TSV-s (1-5), which is crucial for fabrication of void-free structures. However, Cu electroplating, should provide not only a void-free TSV fill, but also short plating time, and enable cost-effective post-plating processing.

In the work presented here, we focused on wafer-level Cu plating of vias 5 μm in diameter and having aspect ratios (AR) ranging from 5 to 10. Our goal was to fabricate void-free Cu nails for 3D-SIC applications, or establish the limitations of 3-component model chemistry, and improve the understanding of the effects of chemistry and electrochemical deposition parameters on the Cu fill profile. We have also explored Cu plating phenomena specific to TSV applications, and optimized plating parameters and processes in such a way that their impact on post-processing steps was minimal. For example, Cu plating of a TSV is several orders of magnitude longer than plating of a damascene structure, and consumption of additives during former might be quite severe. Therefore, we established bath monitoring techniques during TSV plating (roughly 1 hour/wafer), and replenishment procedures so that the additives’ concentration was kept within allowed limits. Also, we examined the correlations between phenomena observed during post-plating-processing, such as annealing/sintering or CMP and bath composition, and tested different approaches to improving Cu removal rate during CMP.

ECS Transactions, 33 (36) 11-21 (2011)10.1149/1.3575437 © The Electrochemical Society

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Experimental The plating bath was made up of virgin make-up solution (VMS = aqueous, acidic, Cu-sulfate solution with Cl-), and organic additives such as poly-ethylene glycol (PEG), bis(3-sulfopropyl) disulfide (SPS), and Janus Green B (JGB). VMS contained 0.8 M CuSO4 · 5H2O, 38 ml/L M H2SO4, and 60 ppm Cl- (inorganic additive).

Physical vapor deposition (PVD) technique was used to deposit Ta/Cu barrier/seed, and although highly non-conformal, they were continuous throughout the 5 μm (diameter) × 40 μm (height/depth) and 5 μm × 50 μm vias. The true area of the wafer, including the area of TSV sidewalls, was 1.1–1.3 times larger than the apparent area, depending on the via density. Nevertheless, deposition current densities reported in this paper were calculated using the apparent wafer area.

Three-hundred millimeter wafer-level experiments were performed on Stratus 300 (NEXX Systems) and SlimCell (Applied Materials) plating tools. In a typical 300 mm wafer-level experiment, four wafers were plated in a sequence. Cu bath samples were collected before, during, and after plating of each wafer for composition analysis. Accelerator (SPS) and suppressor (PEG) organic additives were monitored using adapted Cyclic Voltammetry Stripping (CVS) procedures. Measurements were done manually (and off-line) on a CVS ECI QUALILAB ql-10 system (PEG: dilution titration; SPS: MLAT). The concentration of leveler (JGB) was determined using UV–VIS technique (between 340 and 700 nm). Cu concentration was determined by titration with Na-thiosulphate. The additive replenishment procedures, established for sequential plating of four wafers, kept the SPS and PEG additive concentration within 10% of the set values.

Coupon-level experiments were performed using three-electrode rotating disk electrode (RDE) setup and computer controlled Autolab/Metrohm PGSTAT30 potentiostat. Working electrode (WE) was the coupon with TSV-s or a blanket sample with Cu seed. The sample area (i.e. the apparent area of the WE) was 1.5 cm2. A Pt mesh was used as a counter electrode (CE), and was separated from the WE by diaphragm, which prevents anodic additive breakdown products from affecting the deposition process. Ag/AgCl was used as a reference electrode (RE). Volume of the electrolyte in the plating cell was between 100 and 300 ml. The same bath was used for plating of two coupons, and then replaced by a fresh Cu bath. The additive consumption was not monitored in coupon-level experiments.

Scanning electron microscopy (SEM) and focused ion beam (FIB) analysis were used to characterize Cu filled vias. SEM and FIB images were obtained using NOVA 600i (FEI) or Strata 400 STEM DualBeam (FEI).

Results and Discussion Figure 1a shows a cross-section FIB image of a 5 μm × 40 μm via filled with Cu using in-house made bath with model additives. The FIB image reveals that deposition was close to conformal and not void-free. Narrow seems are visible at the bottom and at the top of the via. Cu grains are quite small down to the depth of about 25 μm, after which they become larger (on the order of a micron). Figure 1b shows the Cu nail after anneal, which preceded the CMP step. This was done to avoid defects in post CMP processing, and the anneal step was defined based on the post-processing parameters (such as the highest temperature the stack would see post-CMP). Upon anneal/sinter at 430°C for 20 minutes in N2/H2 atmosphere (Figure 1b), grains became uniformly large. After closer

ECS Transactions, 33 (36) 11-21 (2011)


inspection, small voids could be seen not only along the z-axis, which is probably caused by conformal Cu deposition, but also at grain boundaries away from the z-axis. Small voids are even seen at the grain boundaries in the Cu plated on the field of the wafer.

Figure 1. Cu fill of 5 μm × 40 μm vias using Model chemistry (a) before, and (b) after anneal at 430°C for 20 minutes in N2/H2. Voids in the Cu fill are highlighted. The insert on the right is a zoomed-in top of the via shown in Figure 1b. And although the Cu fill seen in Figure 1 was not ideal, it was good enough to serve as the test material for the following step: CMP. The main requirements for the TSV Cu CMP were small number of defects and high removal rate (RR). For electrodeposition closer to conformal than super-conformal type, the overburden thickness would exceed the size of the radius of the via, and for 5 μm diameter via it was typically around 3.5 μm. For such a thick overburden, it was desirable that RR ≥ 1000 nm/min (≥ 1 μm/min). In order to achieve these goals we tested two experimental Cu slurries, both advertised as high RR slurries (RR ≥ 1 μm/min). One of the slurries was abrasive-free, while the other contained abrasives. Figure 2 shows of a 5 μm × 40 μm via filled with Cu using in-house made bath with model additives, annealed at 430°C for 20 minutes in N2/H2, and then CMP-ed using abrasive-free experimental slurry. FIB images revealed that the top surface was smooth, and wafers were ready for further processing. However, the removal rate was quite low, RR < 200 nm/min, which was not acceptable for practical applications.

Figure 2. FIB cross-section images of Cu fill of 5 μm × 40 μm vias after anneal/sintering step and CMP using abrasive-free experimental slurry. Images were obtained at different magnifications.



Such a large discrepancy between advertised and measured RR was surprising. To understand the cause of this, we designed experiments in which the RR was measured on blanket Cu wafers deposited from two different electrolytes, one of them being model bath. The other electrolyte was a commercial damascene bath that was used in-house for a number of years, and for which we had significant experience in post-plating processing. After plating to a Cu thickness > 3 µm, the wafers MODEL (plated using Model bath) and DAMASCENE (plated using commercial Cu damascene bath) were annealed at 250°C for 20 minutes, in N2 atmosphere. After anneal, they were CMP-ed using experimental abrasive-free slurry and their respective removal rates were determined to be: RRDAMASCENE = 675 nm/min and RRMODEL = 195 nm/min. The removal rate was a factor 3.5 lower for MODEL wafer! This result showed that our model bath and/or plating parameters were the reason for low RR of the Cu overburden. Top-down FIB images of MODEL and DAMASCENE wafers (Figure 3) after plating, anneal, and CMP using abrasive-free slurry, revealed more differences between the two samples. The change in Cu grain size was quite dramatic in the case of a DAMASCENE sample, and the grains were much larger than those of the MODEL sample. As expected, nano-indentation measurements showed that MODEL sample had higher hardness. Cross-section FIB images (not shown) also revealed voids/spaces between Cu grains in MODEL sample after anneal step. Please, note that these were blanket films!

Figure 3. Top-down FIB images of blanket wafers plated using commercial ‘damascene’ Cu bath (DAMASCENE sample), and Model chemistry (MODEL sample). All the images are obtained at the same magnification. Completely opposite results were obtained with experimental abrasive slurry. 5 μm × 40 μm vias were filled with Cu using in-house-made bath with model additives, annealed at 430°C for 20 minutes in N2/H2, but then CMP-ed using abrasive experimental slurry (Figure 4). High removal rate was achieved with experimental-abrasive slurry (RR ≈ 1000 nm/min). However, crater-like defects appeared on the top of 5 × 40 µm Cu nails (Figure 4b and 4c). This was not acceptable, since no structures could be stacked on the



top of the via. Since we had high Cu removal rate with abrasive slurry, we varied the model bath composition, i.e. the concentration of leveler additive JGB, to find out if this could reduce the number defects observed after CMP.

Figure 4. Cu filled 5 µm × 40 µm vias plated using Model chemistry, annealed, and CMP-ed using abrasive-experimental slurry. (a) and (b) are cross-section FIB images, while (c) is a tilted SEM image of the top of Cu nail. Figure 5 shows top-down and cross-section FIB images of 300 mm blanket wafers plated using Model chemistry with different concentration of JGB. The wafers were annealed at 430°C for 20 minutes in H2/N2 atmosphere, and CMP-ed with experimental-abrasive slurry. FIB analysis showed that the number and size of the defects on the wafer surface increased with the increase in JGB concentration. JGB is incorporated into the Cu film (12) during plating, and this could be a reason for the differences observed between model and commercial chemistries. The same argument could be used to explain the differences between Cu films deposited using model bath with different JGB concentrations (Figure 5). Therefore, an optimized model bath composition should provide void-free fill, reduced overburden, and contain as little JGB as possible.

Figure 5. Top-down (top) and/or cross-section (bottom) FIB images of blanket wafers plated using Model chemistry with different amount of leveler additive JGB. However, this might be a challenge. As could be seen from Figure 6, Cu fill of 5 µm × 40 μm vias improved with the increase in JGB concentration. This was a general trend



we have seen during Cu plating from the three-component model chemistry with SPS, PEG, and JGB. The same trend is expected for 5 µm × 50 µm and deeper vias.

Figure 6. Cross-section FIB images of 5 µm × 40 µm vias plated using Model chemistry with different amount of leveler additive JGB. [JGB](a) < [JGB](b) < [JGB](c). These contradicting requirements forced us to take a hard look into our options, if we were to continue working with model additives. For example, we could use increased concentration of JGB, have void-free fill of vias, and leave it to the CMP team to find a workaround, i.e. select a slurry, or develop a process that would provide high removal rates and low number of defects on the surface. However, this would change nothing about the voiding inside the vias observed in Figure 4, and we had no way of saying how that would impact post-CMP processing and final-product reliability. The second option was to replace JGB with some other ‘public domain’ leveler. One of the possible replacements for JGB was Diethyl Safranine (DSF). Li and co-workers (13) have filled vias using the Cu bath containing DSF and found it to be a better additive than JGB in their case study. We found this work quite interesting due to the fact that DSF was a by-product of JGB reduction (13 and references cited therein). This meant that DSF was already present in our plating tool, and we had fewer logistics issues to worry about. Also, both JGB and DSF could be monitored using UV-VIS spectroscopy. Therefore, the effect of DSF replacement of JGB on our system could be checked relatively quickly and easily. The other by-product of JGB reduction, N, N’ Dimethyl-1,4 Phenylenediamine (DPD) was claimed not to have any effect on Cu plating (13), and also could not be monitored using UV-VIS. Figure 7 shows UV-VIS spectra of the test solutions containing VMS and mixture of JGB and DSF. The spectra obtained for different mixtures, i.e. different molar ratios of JGB and DSF, differed significantly around peaks at wavelengths of about 560 nm and 620 nm. For example, we saw a peak at 560 nm, and no peak at 620 nm in the solution containing 1 mol DSF and 0 mol JGB (0% JGB). On the other hand, the solution with no DSF and 1 mol JGB (100% JGB) showed a strong peak at 620 nm, and a shoulder at 560 nm. Quantitative analysis of the UV-VIS spectra, and determination of the [JGB] and [DSF] was not straightforward and exceeded the scope of this paper. We plan to present details in a future publication. In the meantime, we used UV-VIS spectra of the actual plating bath with JGB as a leveler, taken from the plating tool (Figure 8) in designated intervals, to discuss compositional changes in qualitative manner only.



Figure 7. UV-VIS spectra of the test mixtures of JGB and DSF. The percentage gives the molar parts. For example, 75% JGB means that there is 0.75 M JGB and 0.25 M DSF in the solution. The relative intensity of the peaks at 560 nm and 620 nm changed after less than 10 hours of plating (Figure 8a) in the 300 mm plating tool. The trend stayed the same even after the tool was at ‘idle’, i.e. the plating was stopped (Figure 8b), and the bath was only circulated. From Figure 8b one could conclude that after 24h from the first measurements, there was significant amount of DSF in the plating bath. After 15 days at ‘idle’, UV-VIS spectra showed there was hardly any JGB left in the bath.

Figure 8. UV-VIS spectra of the Model bath samples recorded during plating in the tool (a), and during ‘idle tool’ time (b). Plating tests using model bath with DSF did not show improvements over Cu nails fabricated under identical conditions, but with JGB as a leveler. Cross-section FIB image (Figure 9) shows many voids along the z-axis of the via.

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Figure 9. Cross-section FIB image of the Cu nail fabricated using Model bath in which JGB was replaced by DSF. Figure 10 shows the morphology of the Cu films plated on blanket coupons with Cu seed, using model bath with different levelers, JGB, DSF, and DPD. Deposition was performed galvanostatically, at -5 mA/cm2 and 80 rpm in the three-electrode RDE setup. Top-down SEM images of these samples reveled the difference in size of Cu grains between the samples plated with JGB as a leveler versus samples plated using model bath with DSF or DPD as levelers. The same experiment was later repeated using the same plating parameters, and different rotation rates. Here we were not interested in the surface morphology of the deposited Cu film, but rather potential-time (U-t) responses during plating. This technique was developed as a pre-screening method for baths/bath compositions that could potentially promote super-conformal growth, and is well described in the literature (14, 15).

Figure 10. Top-down SEM images of Cu plated on a blanket coupons with Cu seed using Model bath with (a) JGB, (b) DSF, and (c) DPD, as la leveler additive, at i = const. = -5 mA/cm2, and 80 rpm. The difference in potentials obtained for different rotation rates contains the information on whether Cu could be plated preferentially on the top or inside/bottom of the TSV. The influence of forced convection diminishes with via depth (16), and lower rotation rate (lower rpm) corresponds to the conditions deeper inside the via. Also, the more negative the potential is, the more difficult it is to plate at the same current density. Therefore, based on this method, Cu deposition was inhibited on the top, and promoted inside the via, if the potential difference (ΔU) was ΔU = U10 – U600 > 0. Here, U10 is the potential measured at 10 rpm, and U600 is the potential measured at 600 rpm. The rotation rates of 10 rpm and 600 rpm were chosen based on the practical limitations of our RDE setup. As it can be seen from Figure 11, ΔU(JGB) > 0, and ΔU(DSF) ≈ 0, suggesting that JGB is more likely to promote differential-inhibition and super-conformal Cu growth, while DSF is likely to promote conformal Cu profile, under given deposition parameters. To



summarize, all of our experimental data suggested that DSF was not a preferred leveler over JGB for our system. In fact, the breakdown of JGB into DSF and DPD during TSV plating might be one of the reasons for problems we were facing in post-plating processing, and the leveler with long-term stability would be highly desirable. We are planning to test more ’public domain’ levelers in the future, but are also looking into alternative approaches. One of them is to use microcontact printing of octadecane thiol (ODT), or thin PVD Ta-flash to inhibit Cu plating on the field of the wafer (1-3, 17, 18). These inhibiting layers would effectively take the role of the leveler additive, and could enable void-free fill from the model bath without JGB. Also, by stopping deposition when via-fill is complete one would need to CMP PVD Cu seed only, and could reduce CMP-related costs.

Figure 11. Potential-time (U-t) responses for Model bath with JGB or DSF leveler at 10 rpm and 600 rpm. As an example of the approach with Ta capped vias, we show partial fill of 5 × 25 µm vias with Ta flash on top/field ≤ 1 nm (Figure 12). Deposition was performed on a 200 mm wafer using commercial Cu chemistry due to practical constraints on the 300 mm tool, at that time. This was continuation of the work described in Reference (18), which demonstrated that super- conformal, void-free fill, was possible on 200 mm wafers with optimized Ta flash. This approach resulted in 60% shorter Cu CMP processing time when compared to standard non-Ta capped wafers with 5 × 25 µm vias.

Figure 12. Cross-section SEM (a) and FIB (b) image of Cu nails fabricated in 5 × 25 µm Ta-capped vias (200 mm wafers).

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Figure 13 shows two examples of the Cu fill of Ta-capped of 5 × 40 µm vias on a 300 mm wafer using Model chemistry without leveler. These were performed in April 2010, and at that time we have not achieved the void-free fill of 5 µm × 40 µm vias without leveler additive. Further optimization of both plating parameters and bath composition was required, and results were to be reported in the future.

Figure 13. Cross-section FIB images/examples of Cu nails fabricated in 5 × 40 µm Ta-capped vias (300 mm wafers) using different Model bath compositions.

Summary We have explored the possibility of using model bath with SPS, PEG, and JGB additives in fabrication of Cu TSVs for 3D-SIC applications. We found that bath composition had strong effect on post-plating processes, and JGB, a leveler additive, was found to cause problems in CMP. DSF, its reduction by-product, was tested as a possible replacement for JGB. However, our results suggested that DSF was not a better option for our system, under given plating conditions. While planning to examine other ‘public domain’ levelers as the replacement for JGB, we have also explored alternative approaches. In one of them, a layer blocking deposition of Cu on top/field, such as thin PVD Ta-flash layer, could be used to effectively replace leveler additive, enable deposition from the leveler-free Cu baths, and reduce the time needed to CMP the wafers.

Acknowledgments

The authors are grateful to all the imec 3D Program members for their contributions and support for this work.



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TSV Cu Plating and Implications for CMP

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