DISCRETE APPLIED

ELSEVIER Discrete Applied Mathematics 90 (1999) 89-l 14 MATHEMATICS

Transistor chaining in static CMOS functional cells of arbitrary planar topology *

Bradley S. Carlsona,*, C.Y. Roger Chenb, Dikran S. Meliksetian b

a The Advanced IC Design and Simulation Laboratory and The Department of Electrical Engineering,

State University of New York at Stony Brook, Stony Brook, NY 11794-2350, USA

b Department of Electrical and Computer Engineering, Syracuse University, Syracuse,

NY 13244-1240, USA

Received 30 May 1995; received in revised form 1 February 1997; accepted 1 August 1997

Abstract

A technique for chaining the transistors in the layouts of static CMOS leaf cells is presented and analyzed. This new method is superior to existing techniques, since it can operate on a more general class of circuits and is very efficient. It is shown that the layout width of a CMOS leaf cell can be significantly reduced (nearly 40% in the average case) by transistor chaining. Moreover, more than half of the switching functions of four variables have optimal CMOS circuit implementations with non-series/parallel topologies. Therefore, the use of non- series/parallel circuits can have a positive global impact on layout area and performance. The transistor chaining technique presented in this paper produces the optimal solution for 82.5% of the circuits tested, and has linear time complexity. 0 1999 Published by Elsevier Science B.V. All rights reserved.

1. Introduction

Since the early 1980s Complementary-Metal-Oxide-Silicon (CMOS) technology has

been the dominant technology for the implementation of digital integrated circuits.

CMOS has gained its dominance from its simplicity and robustness. The integrated

circuits of modem desktop computers are fabricated exclusively in CMOS technology.

The semiconductor device implemented in a CMOS technology is the MOS-FET

(Metal-Oxide-Silicon Field-Effect Transistor). In a CMOS process two MOSFETs are

available (n-type and p-type). These two devices have identical structure and com-

plementary characteristics due to complementary pn (semiconductor) junctions. The

cross section, layout and circuit symbol of an n-type MOSFET device are shown in

*This research was supported in part by the National Science Foundation under grant number MIP- 8909792.

* Corresponding author. Fax: (516)632-8494; E-mail: bcarlson@sbee.sunysb.edu.

0166-218X/99/$ ~ see front matter 0 1999 Published by Elsevier Science B.V. All rights reserved.

PII: SO1 66-2 18X( 98)00086-9

90 B.S. Carlson et al. I Discrete Applied Muthematics 90 11999) 89-114

source gate drain

~d~~u~io” -

substrate

gate (polysilicon)

drain

gate

cross section layout symbol

Fig. 1. Cross section, layout and symbol of an n-type MOSFET device

Fig. 1. The source and drain regions of an n-type MOSFET are formed by diffusing

(or implanting) into the silicon free electrons. For this reason the source and drain re-

gions are known as diffusion regions. The n-type MOSFET is constructed on a substrate

of p-type silicon. The source and drain regions of a p-type MOSFET are formed by

diffusing free holes into the silicon, and the p-type device is constructed on a substrate

of n-type silicon. Thus, the p-n junctions of the two devices are complementary. The

source and drain terminals of a MOSFET are interchangeable; i.e., it is a physically

symmetric device in the lateral direction. The gate terminal of the device is a conduc-

tor (usually polysilicon) separated from the substrate by an insulator (usually silicon

dioxide). During the early years of this technology the gate terminal was constructed

with metal; thus, the origin of the first part of the name of the device: metal-oxide-

silicon. The circuit symbol of a p-type MOSFET is similar to the n-type MOSFET

except a circle is drawn at the gate terminal (Fig. 2). The substrate terminal of the

MOSFET is not illustrated in its symbol, since for a digital circuit the substrate of

the n-type (respectively, p-type) device is always connected to ground (respectively,

power supply).

The conduction of current from drain to source in this device is controlled by the

vertical electric field induced by the application of a potential between the gate and

source. This is the origin of the latter half of the device name: field-effect transistor.

The device can be operated as an electrical switch by controlling the potential applied

to the gate terminal. To construct logic (functional) cells in CMOS technology the

source and drain terminals of p-type devices are connected between the cell output

and supply voltage, and the source and drain terminals of n-type devices are connected

between the cell output and ground (Fig. 2(a)). Switching on any group of n-type

(respectively, p-type) devices that lead from the cell output to ground (respectively,

power supply) results in the output of the cell being a low (respectively, high) voltage.

The functional cells are the basis of all digital switching circuits in CMOS technology.

Two transistors whose source and drain are electrically connected in the circuit can

be fabricated such that they share a diffusion region. For example, in the layout shown

in Fig. 2(b) none of the transistors share diffusion regions. However, in Figs. 2(c)

and (d) many transistors share diffusion regions. A set of adjacent transistors in the

layout of a circuit are said to form a transistor chain if each one shares a diffusion

B.S. Curlson et al. I Discrete Applied Mathernutics 90 (1999) 89-114 91

output

vddG

TTT-T T a C

(a)

El diffusion polysilicon

D GND

metal

0 contact

ffS.nSlStOrS wtth separation between diffusion regions

Vdd

output

GND

Fig. 2. (a) An example circuit, and (b) an arbitrary layout of the circuit

region with its neighbors. The transistor chaining problem is the problem of finding

the longest possible (and fewest number) of transistor chains for a given circuit.

The transistor chaining problem was first addressed by Uehara and vancleemput

[ 141 in 198 1, and soon became an important problem in CAD for VLSI circuit design

[I, 4, 5, 7-l 1, 13, 161. Uehara and vancleemput showed that the layout area required

by a CMOS functional cell can be significantly decreased by chaining the transistors

in the cell. For example, the circuit shown in Fig. 2(a) can be laid out as shown in

Fig. 2(b) or (c). The layout of Fig. 2(b) does not use transistor chaining, and the layout

of Fig. 2(c) does. The reduction in layout area due to transistor chaining is significant.

Furthermore, the sequence of the polysilicon gates in the layout can be adjusted to give

a minimum width layout. A minimum width layout for the circuit shown in Fig. 2(a) is

shown in Fig. 2(d). The problem of determining a minimum width layout of a CMOS

leaf cell is known as the transistor chaining problem, and is defined as follows. Given

a CMOS complex gate, determine a sequence for the polysilicon gates of its transistors

such that its corresponding layout has minimum width. The height of the layout is not

a concern, since the cells are typically used in a cell-based layout system and the height

92 B.S. Carlson et al. I Discrete Applied Mathematics 90 (1999) 89-114

transistors with shared diffusion regions

a b c//a f d

diffusion ibutments

n

dxsion gaps

d f e

“dd

output

GND

“dd

output

GND

(4

Fig. 2 (Continued). (c) A layout using transistor chaining and (d) a layout optimized using the method

described in this paper.

of a row of cells is dominated by a single cell (i.e., it is assumed that all cells have

the same height) and dictated by the desired drive strength of the cell. The transistor

chaining problem is the fundamental problem which must be solved in the generation

of CMOS functional cells [ 141.

Many variations of the transistor chaining problem have been addressed in re-

cent years [l, 4, 5, 7- 11, 13, 14, 161 and most of the solutions are restricted to cir-

cuits which are constructed using only series and parallel connections of transistors.

Results tabulated by Moore in [6] indicate that a significant reduction in the number

of transistors, and hence layout area, can be achieved by implementing functions with

non-series/parallel circuits. Of the optimal transistor network implementations of all

four variable switching functions, 51% are known to have non-series/parallel topolo-

gies. (Only 33% are known to have series/parallel topologies). Very few methods have

been proposed which are suitable for chaining transistors in non-series/parallel circuits

[ 1, 12, 161. Methods for series/parallel circuits are often not extensible to non-series/

B.S. Curlson et al. I Discrete Applied Mathematics 90 (1999) 89-114 93

parallel circuits due to their use of the inherent hierarchy in series/parallel circuits. That

is, a series/parallel circuit can be decomposed in a natural way and represented by a

composition tree [4, 91 and this representation is often exploited to obtain an efficient

solution to the problem [4, 9, 11, 141. In contrast to series/parallel circuits, very little

is understood about the nature of non-series/parallel circuits, and this paper helps to

fill a significant part of this void.

There are a few methods presented in the literature for solving the transistor chaining

problem for non-series/parallel circuits [I, 12, 161. The algorithm presented in [16]

applies heuristics in an attempt to minimize the number of diffusion gaps by assuming

a different problem formulation where intracell routing is performed between the NMOS

and PMOS parts of the circuits. The algorithm in [lo] utilizes the branch-and-bound

technique to find an optimal solution in terms of the number of diffusion gaps. In

[12] an exhaustive algorithm is presented which determines an optimal solution in

reasonable time for non-series/parallel circuits with stack height’ four or less.

In this paper we present a new algorithm that is heuristic in nature (and therefore

efficient), and produces optimal results for a very large set of practical examples. The

algorithm is based on a transformation of the problem to a representation that permits

the identification of a good heuristic. The new algorithm produces optimal solutions for

82.5% of the circuit implementations of most of the four variable switching functions

(55 124 of them).

This paper is organized as follows. The layout problem is formulated in the next

section and the circuit representation and the corresponding graph theoretic problem

are given in Section 3. The transistor chaining algorithm is presented in Section 4, and

the experimental results are given in Section 5. Finally, Section 6 concludes the paper.

2. Problem formulation

The functional cell generation problem was initially formulated by Uehara and

vancleemput [14] and most of the succeeding work on this problem utilized a sim-

ilar formulation. According to [14] the functional cells are constructed as follows.

The diffusion is placed in two parallel horizontal rows, one row is made of n-type dif-

fusion and the other is made of p-type diffusion. These rows may or may not be contin-

uous. The polysilicon is placed vertically across both rows of diffusion to form both the

n-type and p-type transistors. The necessary interconnections between diffusion ports

are made on the first level metal layer in the horizontal direction. This construction is

very similar to the way in which cells are constructed for a standard cell layout system.

Two ways in which a functional cell generation tool may be used in conjunction with a

standard cell design system are to generate the cells when required thereby eliminating

’ The stack height of a CMOS circuit is the maximum number of transistors between the output and the

power or ground terminals.

94 B.S. Carlson et al. I Di.wete Applied Mathematics 90 (1999) 89-l 14

the need for a cell library, or when a cell library is desired to relieve the designer of

the manual layout of library cells.

Consider the CMOS circuit shown in Fig. 2(a). A layout of this circuit which fol-

lows the construction guidelines given previously is shown in Fig. 2(c). The width

of the layout may be minimized by replacing some of the diffusion gaps with diffu-

sion abutments as shown in Fig. 2(d). The problem is to determine a sequence for

the vertical polysilicon lines such that the number of diffusion abutments is maximum.

That is, a transistor gate sequence must be determined such that the transistors can be

“chained” together. As will be seen in the next section, the concept of an Euler path

in an undirected multigraph will assist in the determination of a gate sequence which

allows the maximum number of diffusion abutments.

A slightly different problem formulation has been used by some researchers

[ 1, 8, 10, 161. In their approaches the transistors driven by a common gate signal are

not necessarily aligned in the same column, and intracell routing is performed between

the NMOS and PMOS parts of a circuit. This freedom allows the potential for a bet-

ter result in terms of total layout area; however, the solution space is expanded and

the complexity of the problem is increased. The potential improvement due to this

additional freedom is small, and does not justify the increase in complexity.

In a standard cell system the boundaries of a row of standard cells are forced to

be uniform, and the widths of the transistors in cells with small height are increased

so all the cells have height equal to the cell with the largest height. Since the height

is dictated by the largest cell, the size of the overall layout is not affected by op-

timizing the heights of most cells. Therefore, it is the objective of this research to

minimize the width of the functional cells. This objective has been used by most of

the previous researchers (e.g., [4, 5, 7, 9, 12-141). Algorithms have been designed to

optimize functional cells in width and height [ 1, 8, 10, 161; however, the increase in

problem complexity does not justify the slight global improvement which can be made

by optimizing height as well as width. Moreover, the minor improvement made on

the height by slightly increasing the width may not actually help in a standard cell

environment.

3. Circuit representation

Similar to previous works [5, 8, 9, 12-141 the MOS transistor network is represented

by a plane connected undirected multigraph r( V, E), where V is the set of vertices and

E is the set of edges. The transistors of the circuit correspond to edges of r and the

source/drain connections of transistors correspond to the vertices of r. Each edge of r

is labeled with the name of the gate signal of its corresponding transistor. In addition,

a pseudo-edge is placed between the vertices corresponding to the power and output

terminals of the MOS transistor network. The power terminal of an NMOS network

is ground, and that of a PMOS network is the power supply. Let us label the pseudo-

edge with an X. A network and its graph representation are shown in Figs. 3(a) and

B.S. Carlson et al. I Discrete Applied Mathematics 90 (1999) 89-114 95

(b), respectively. It is assumed that the circuit has no floating nodes and there exists

no transistor whose source and drain terminals are connected together. Hence, the

graph representation of a circuit contains neither isthmuses nor loops. A path p in an

undirected graph r is a sequence of alternating vertices and edges vieiv2 . . ok-_lek__l uk

such that ei is incident on vi and vi+, (1 <id k - 1) and ei # ej for i fj.

The dual graph Td of a graph r is also a plane connected undirected multigraph

with set Vd of vertices and Ed of edges. Given a plane undirected multigraph r, the

vertex set Vd of the dual of r is obtained by placing a vertex in each face of r and

one vertex in the infinite region (i.e., the space of the plane not surrounded by a set

of edges in r). The edge set of Td is obtained by placing one edge in Td for each

edge in r such that the edge in r d is incident on two vertices in Td and intersects

exactly one edge in r. Two vertices in Td have an edge joining them if and only if

their corresponding faces in r are adjacent (i.e., their borders have a common edge).

An edge in Td is labeled with the name of the edge in r which it intersects in the

embedding. The dual of the graph in Fig. 3(b) is shown in Fig. 3(c).

A dual vertex pair is a pair of vertices (VI, ~2)~ such that VI EV and 74 E Vd for

some r and rd. A dual edge puir is similarly defined. A dual path 6 in a plane

undirected multigraph r and its dual Td is a sequence of alternating dual vertex and

dual edge pairs

such that vie~v2..~vk_iek_iUk is a path in r and uleiu2~~~24-~ek-~Uk is a path in

rd. A dual path is a dual circuit if the dual vertex pairs which begin and end the

sequence coincide (i.e., vi = vk and ui = uk). A set of dual paths A = {61,&,. . . , (Sk} is

a dual puth covering set of r and Td if Ye EE \{X} and e cEd \{X}, 36i such that

(e, e)d E &, and ‘di #j 6i and 6j do not share a dual edge pair (i.e., they are dual edge

pair disjoint). That is, a dual edge pair appears in one and only one di E A. Denote the

cardinality of a set S by IS]. A graph and its dual which admit a A such that IAl = 1

is said to be dual Eulerian and the dual path is called a dual Euler path [ 131. When

a dual path is said to be in r, its existence in Td is implicit. Consider the example

shown in Fig. 3.

(vl~~s>d~s,s>d~v2,~s~d~~~~~d~~~,~~~d~~,~~d~~~~~~~d~~,~~d~~~,~l~d

is a dual path in r, and a dual path covering set containing this dual path is

{(vl,Us)d(s~s>d(v2,U~)d(~,~)d(v~~~~)d(~,c)d(v~,~~)d(~,~)d(v~,~l)d,

The edge X is not covered since it does not correspond to a real transistor. The edge X

is included so the graph representations of the transistor networks are graph theoretic

duals.

96 B.S. Car1.m et al. I Discrete Applird Mathematics 90 (1999) 89-114

(cl

Fig. 3

Dual edge pairs which are adjacent in a dual path 6 correspond to polysilicon gates in

which the diffusion regions in the layout may be abutted if they are placed adjacent to

one another. A dual path S, in the dual path covering set A of the graph representation

of a circuit corresponds to a gate sequence for the subset of inputs corresponding to

the edges in 6i for which thts part of the circuit can be constructed with zero diffusion

gaps. A circuit which has a graph representation that is dual Eulerian can be constructed

with zero diffusion gaps.

B.S. Carlson et al. IDiscrete Applied Mathematic.~ 90 (1999) 89-114 97

4. Transistor chaining algorithm

The objective is to find a dual path covering set which has the smallest cardinal-

ity of all dual path covering sets of the graph representation of the circuit. Such a

dual path covering set corresponds to a gate sequence which allows the circuit to be

constructed with minimum width. This problem has been proven to be NP-hard [15].

The heuristic algorithm described here is shown to produce very good results in linear

time.

The determination of dual paths in a pair of plane connected undirected multigraphs

r and Td requires the traversal of edges in both graphs simultaneously. Assume for

the moment that some sequence of edges has already been traversed and the algorithm

is visiting some dual vertex pair, say 1’ E V and V’ E Vd. The dual path must terminate

unless there is an edge incident on v in r and an edge incident on V’ in Td and

these edges have the same label assigned to them. It is shown in [3] that given a

dual path 6 of length two or more, if 6 can be extended, then there are only two

ways in which it can be done, one way from each end (i.e., the extension of 6 in a

given direction is unique). That is, given a dual path 6 of length two, there exist only

two dual paths of length three which contain 6. This property allows one to uniquely

compute the set of maximum length dual paths. The set of maximal length dual paths

contains information that is sufficient to determine an optimal solution; however, all

known methods for computing an optimal solution have exponential complexity (i.e.,

the problem is NP-hard).

The algorithm begins by reducing the graph without loss of generality. It is proven

in [3] that an even (respectively, odd) number of edges in series can be replaced by

two (respectively, one) edges, and an even (respectively, odd) number of edges in

parallel can be replaced by two (respectively, one) edges in parallel. The graph can

be reduced recursively in this way until it cannot be reduced further. A solution found

for the reduced graph is equivalent to a solution found for the original graph.

The algorithm computes all the dual paths of length two, and determines the maxi-

mum length dual paths from this information. The dual paths of length two are com-

puted by taking the pairwise intersections of the sets of edges incident on vertices in

r with the sets of edges incident on vertices in rd. For example, the pairwise inter-

sections of edges incident on vertices in r and Td of Fig. 4 produce the dual paths

of length two shown in Table 1. The maximum length dual paths are computed by

extending as far as possible the dual paths of length two.

The left and right successors of a dual path

of length two are the edges eo and e3, respectively, in r such that

is a dual path in r. The left and right successors are easily computed from the graph

specification, since they are unique [3]. For example, the left and right successors of

98 B.S. Curlson et al. I Discrete Applied Mathematics 90 (1999) 89-114

Fig. 4. Example graph r and its dual rd.

“4

d l-

Table I Dual paths of length two for the example in Fig. 4

Pair of vertices in r and Td Dual path of length two

UI,U2

m,u2

02, u3

03, u3

03,u4

L’3, u5

L’2,UI

u2.u2

02, u4

04, u4

the dual path

in the graphs of Fig. 4 are d and e, respectively. The left and right successors for

each of the dual paths of length two for the example shown in Fig. 4 are tabulated in

Table 2. If the left or right successor of a dual path of length two is X, then this dual

path cannot be extended in that direction.

The algorithm for computing the maximum length dual paths works as follows.

Choose a dual path of length two, say

B.S. Carlson et al. I Discrete Applied Mathematics 90 (1999) 89-114

Table 2

Successors of the dual paths of length two in the example of Fig. 4

99

Dual path of length two Left successor Right successor

(uz,ul)d(a.a)d(vl,u2)d(b,~)d(~~,~~)d d e

(u,,Us)d(b,b)d(u3,U2)d(~,~)d(u2,u~)d X C

(s,U2)d(f,f)d(u2,a)d(c,c)d(~~.u~)d h e

(uz,U*)d(f,f)d(s,U~)d(c,c)d(~*,~~)d a d

(V2,u~)d(c,c)d(u3.U4)d(e,e)d(u~,u~)d .f x

(u,,u2)d(b,b)d(u~,us)d(e,e)d(u~,~~)d a d

(ul,uz)d(a,a)d(uz,U,)d(d,d)d(~~,~~)d b e

(ol,u,)d(a,a)d(u2,u2)d(~,.~)d(u~,~~)d X C

(u3,U3)d(C,C)d(V2,U4)d(d,d)d(u~,u,)d f X

(~2,~1)~(d,d)~(u4,~4)~(e,e)~(u3,~~)~ a b

not contained in a maximum length dual path which has already been computed. If the

left and right successors of

(vl,~l)~(el,el)~(v2,~~)~(e~,e*)~(u~,~~)~

are eo and es, respectively, then it can be extended to a length of four. This dual path of length four contains the dual paths

(v0,u0>d(e0,e0>d(ul,~~)d(e,,e~)d(~2,~2)d

and

(u2,U2>d(e2,e2>d(v3,~3)d(e3,e3)d(~~,~~)d

which can be extended according to their left and right successors, respectively,

algorithm marks the dual paths

(u0,u0>d(e0,e0)d(vl,~~)d(e,,e,)d(~2,t12>d

and

visited, and uses their successors to further extend the dual path of length four. A

path cannot be extended if a successor is an edge already contained in the dual

currently being computed, or if it is X. For example, the algorithm chooses the

path

The

dual

path

dual

from Table 2 and marks it visited. The dual path (02, ui )d(a, a)d(vi, ZQ)~(~, b)d(v3, u5)d

can be extended to

100 B.S. Carlson et al. I Discrete Applied Mathematics 90 (1999) 89-114

according to its successors. Since all the dual paths of length two are contained in the

table, the dual paths

and

must be in the table. The left successor of (04, UJ)~(CI,~)~(U~, ~1 )d(a,a)d(vr,~2)d (or

the right successor of (01, u~)~(Lz, CZ)~(U~, u1 )d(d, d)d(v4, ~4)~) is used to extend

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

to the left, and the right successor of (~,,~2)~(b,b)~(a3,~5)~(e,e)~(u~,~~)~ (or the left

successor of (04, U4)d(e,e)d(u3,U5)d(b,b)d(ul, ~2)~) is used to extend

(u4,U4)d(d,d)d(V2,UI)d(~,~)d(~,,~2)d(~,~)d(~~,~5)d(e,e)d(u4,~4)d

to the right. The right successor of

is e, so

(u4,U4>d(d,d>d(u2,U~)d(~,~)d(~,,~2)d(~,~)d(u~,z~5)d(e,e)d(~4,~4)d

cannot be extended to the left since e is already contained in it. The right successor

Of

(VI,U2>d(6,b>d(u3,U5)d(e,e)d(u4,~4)d

is d which is also contained in

(~4,~4)~(d,d)~(~2,~1)~(u,u)~(~~,~~)~(~,~)~(u~,~~)~(e,e)~(~4,~4)~.

Therefore,

is a maximum length dual path. Since

is a dual path of length two, the dual path

B.S. Curlson et al. I Discrete Applied A4utlzematics 90 (1999) 89-114 101

contains the dual path

and

must be marked in the table. The next unmarked dual path of length two in the table

is chosen, and the procedure is repeated. The next unmarked dual path of length two

is

CR> UsId (Wd (~3&dd (fAd k2dd.

It cannot be extended to the left since its left successor is X. Its right successor is c,

so

is extended to

The right successor of

is e, so

is extended to

The right successor of

(02,u31d (c,cId (a3,u41d (e,eId (v4,115>~

is X, so

is a maximum length dual path. There is one remaining maximum length dual path for

this example, and it is

(Cl, Ul Id GWd (v2, U21d (f>.nd (u3, dd kC>d (u2, U4jd (Gqd (z’4, Ul Id.

The termination condition for this iterative procedure is that all dual paths of length

two must be marked; i.e., each one must be contained in a maximum length dual path.

102 B.S. Curlson et al. IDiscrete Applied Mathematics 90 (1999) 89-114

The maximum length dual paths contain information that is sufficient to determine

an optimal solution; however, an efficient method which guarantees an optimal solution

is not known. Therefore, an efficient heuristic which is shown to produce very good

results is used to determine the dual path covering set.

The heuristic is based on the degrees of the vertices. It is known that if a path

in a graph reaches a vertex of odd degree and all the edges incident on the vertex

are contained in the path, then the path must terminate. On the other hand, if a path

reaches a vertex of even degree that is not a start vertex, then there must be at least

one untraversed edge incident on it. In other words starting or ending dual paths at

vertices of odd degree is likely to minimize the total number of paths. Therefore, the

dual paths of the dual path covering set are chosen from the maximum length dual

paths by breaking the maximum length dual paths at vertices of odd degree.

A vertex pair (~1, ur )d is said to be an od&odu’ vertex pair if both ur and ut have

an odd degree, it is said to be an odd-even vertex pair if either vt or ur has an odd

degree but not both, and it is said to be an even-even vertex pair if both VI and ur

have an even degree. Note that the edge X does not contribute to the degree of a

vertex. Since the size of the dual path covering set is related to the number of vertices

of odd degree (i.e., a lower bound on its size is the maximum number of vertices of

odd degree in r and Td divided by two) and the minimum dual path covering set

must contain dual paths which begin and end at vertices of odd degree, the heuristic

chooses dual paths which begin and end at odd-odd, odd-even and even-even vertex

pairs in this prioritized order. The details of the heuristic are given in Fig. 5.

Consider the example dual graph pair shown in Fig. 4. The set of maximum length

dual paths of this example is

The algorithm determines the following minimum dual path covering set,

The algorithm is guaranteed to find the optimal solution if the size of the minimum

dual path covering set is one. The final layout for the example of Fig. 4 is shown in

Fig. 6.

Consider the example shown in Fig. 7. The static CMOS circuit is shown in Fig. 7(a),

its graph representation is shown in Fig. 7(b) and a minimum width layout for

the circuit is shown in Fig. 7(c). The set of maximum length dual paths for this

example is

B.S. Carlson et al. I Discrete Applied Mathematics 90 11999) 89-114 103

Cover(r){ compute all dual paths of length two:

compute the set of maximum length dual paths;

while(al1 edges are not covered){

choose t.he longest. dual path 6i in t,he set of maximum length dual paths;

if(6; contains all uncovered edges)

6j = &;

else if(6, cont.ains t,wo or more odd-odd vert,ex pairs)

break 6i int,o the longest, dual path 6, which has t,wo odd-odd t,erminals;

else if(& contains one odd-odd vertex pair and at least. onr odd-even vert.rx pair)

break i$ into the longest dual p&h 63 which has one odd-odd and one

odd-even terminal;

else if(& contains two or more odd-even vertex pairs)

break 6i into the longest pat.h 6, which has two odd-even terminals;

else if(6; contains one odd-even vertex pair)

break 6; into the longest. dual path 63 with one odd-even terminal and one

even-even t.erminal;

&e

6j = 6,; A= AUljj: for(each remaining maximum lengt~h dual pat,h)

remove edges contained in lij ; 1 return(4);

Fig. 5. The algorithm for determining the dual path covering set

During the first iteration of the while loop in algorithm Cover (Fig. 5)

4 = (u4?451d (Wd (u3,U3>d (CJId (~5Wd (GOd (W*)d (CI,COd (u2,%>d (UQd

(~4~~4)~ (e,e)d (05,u31d.

Since (~3, ~3)~ and (~4, ~4)~ are odd-odd vertex pairs,

dj = (U3, u3 Id (C, C)d (“5> Ul Id Cd, d>d ( W21d (CLCI>d(u2,%>d @Ad (04,U4>d.

The set of maximum length dual paths is updated as follows.

{(vl,Ul>d(a,a)d(u3,U5)d(~,~)d(u4,~3)d(e,e)d(~5,~4)d,

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

During the second iteration

& = (UI,W )d @4Qd (U3,U51d (Wd ( v4,~3>~(e,e>~(u5,~4)~(~,~)~(u2,~2)~.

104 B.S. Curlson et al. I Discrete Applied Mathematics 90 11999) 89-114

Vdd

b

a 4

output

a -I

d -1

* GND

El diffusion (a)

polysilicon

metal

q contact

b e d a C f

Vdd

output

GND

(b)

Fig. 6.

Since 6, contains every uncovered edge,

d={(u3,U3)d(C,C)d(U5,Ul)d(d,d)d(t’l,U2)d(g,g)d(U~,Ug)d(h,h)d(Uq,U4)d, (vl,Ul)d(a,u>d(v3,Us)d(~,~)d(~~,~~)d(e,e)d(~~,~~)d(~,~)d(~~,~~)d}.

The layout corresponding to this dual path covering set is shown in Fig. 7(c).

4.1. Complexity

The algorithm in Fig. 5 has time complexity O(lEl), where IEl is the number of

edges in the graph representation of the circuit. In order to compute all of the dual

B.S. Carlson et al. I Discrete Applied Mathematics 90 (1999) 89-114 105

9

El diffusion polysilicon I

metal *

q contact (4

a b e f

“1

“5

lb)

h

paths of length two the algorithm visits each vertex of r once, and at each vertex u

examines each face which u is adjacent to. For example, consider the graphs shown in

Fig. 3(c). When the vertex us in r is visited the faces of I- corresponding to vertices

243,244 and ug in Td must be examined. Let d(v) denote the degree (i.e., the number

of edges incident on) of D. The number of constant time operations performed while

determining the dual paths of length two is

c d(u) = 21EI = O(lEl>. Vl,EV

106 B.S. Carlson et al. I Discrete Applied Mathernutic.s 90 (1999) 89-114

To compute the set of maximum length dual paths the algorithm must visit each

row of the successor table (e.g., Table 2) exactly once, and by clever use of memory

pointers the amount of work done at each row is constant [3]. Since the successor

table has at most 41/Z rows [3], the time required to compute the maximum length

dual paths is O(lEl).

The while loop of the algorithm in Fig. 5 is executed at most k times, where k is

the number of maximum length dual paths. The amount of work done in the body of

the loop is proportional to the size of &. Let e(6i) denote the number of dual edge

pairs in hi. Since

i: e(&) 64/E\ [3], i=l

the time complexity of the while loop is 0( IEI). The for loop of the algorithm has time

complexity O(]E]) due to the memory pointers used in the data structure [3]. Hence,

the time complexity of algorithm Cover is O(lEl).

5. Experimental results

Presented in Table 3 is a topological distribution of the optimal contact network im-

plementations of all four variables switching functions (excluding the two trivial func-

tions). This information has been extracted from [6]. It should be noted that whenever

series/parallel and non-series/parallel implementations exist for the optimal solution,

the series/parallel implementation is chosen [6]. Since the functions are implemented

as contact networks in [6], the optimal implementations given there are minimum for

both contacts and springs. In the design of digital CMOS circuits the transistor is anal-

ogous to the contact, but there is no analog of the spring. Therefore, in a few cases the

series/parallel and non-series/parallel implementations have the same number of con-

tacts, but the non-series/parallel implementation has fewer springs, and hence is chosen

in [6] as the optimal solution. For these cases it is desirable to use the series/parallel

implementation for CMOS design, since the series/parallel implementation is easier to

derive.

Shown in Table 4 is the breakdown of series/parallel and non-series/parallel imple-

mentations for transistor networks. All of the functions which have non-series/parallel

implementations in [6] only because they have fewer springs are counted as series/

parallel implementations in Table 4. Note that 51 .O% of the switching functions of

four variables have optimal CMOS implementations with non-series/parallel topolo-

gies. Therefore, it is important that CMOS leaf cell design algorithms operate on this

class of circuits.

In Table 5 the circuits are classified by the difference between the number of

transistors required for static CMOS implementations of the best series/parallel and non-

series/parallel topologies. It is clear from Table 5 that a significant reduction in transis-

tor count can be achieved by implementing functions using a non-series/parallel circuit

B.S. Carlson et al. IDiscrete Applied A4athematics 90 (1999) 89-114 107

Table 3

Topological distribution of the optimal contact network implementations of all switching functions of four

variables

Topology Circuits

Number Percent

Series/Parallel 56 19.5

Non-series/Parallel 156 54.4

Nonplanar 34 11.8 Unknown 41 14.3

Total 287 100.0

Functrons

Number Percent

II 580 17.7

43 544 66.4

3695 5.7

6712 10.2

65 534 IOO.0

Number of circuits tested

Optimal solutions

Number Percent

56 55 98.2

156 120 76.9

0

0

212 175 82.5

Table 4

Topological distribution of the optimal transistor network implementations of all switching functions of four

variables

Topology Circuits

Number Percent

Functions Number of circuits tested

Optimal solutions

Number Percent Number Percent

Series/parallel 93 32.4 21 676 33.1 93 85 91.4

Non-series/parallel 119 41.5 33 448 51.0 119 90 75.6

Total 212 73.9 55 124 84.1 212 175 82.5

Table 5

Distribution of the reductions in transistor count due to the implementation of circuits in a non-series/parallel

rather than a series/parallel topology

Reduction in the Number of Percent of Number of Percent of

number of transistors circuits circuits functions functions

0 93 32.4 21 676 33.1

2 65 22.6 21680 33.1

4 35 12.2 8832 13.5

6 I5 5.2 2816 4.3

8 4 I .4 120 0.2

Total 212 73.9 55 124 84.1

topology. An algorithm is presented in [ 171 which synthesizes a non-series/parallel

implementation of a switching function.

The transistor chaining algorithm has been implemented on a SUN SPARC-station 2

in the C programming language. It has been executed on all of the planar circuits listed

in [6], and the results are summarized in Table 6.

The circuits are identified by a Harvard serial number which is also used in [6].

The reader is referred to [6] for the circuit topologies. The types of the topologies of

the optimal implementations for contact networks and transistor networks are given in

columns 2 and 3, respectively. For each circuit there is a set of switching functions

108

Table 6

B.S. Carlson et al. IDiscrete Applied Mathematics 90 (1999) 89-114

Summary of experimental results

Harvard opt. Opt. No. of circuit contact xsistor funsd numb& ntwkb ntwkC

32 8

64 6

96 12

64 14

16 16

6

7

8

9 10

192 8

384 12

128 14

128 16

96 18

11

12

13

14

15

192 18

48 4

128 12

384 10

384 14

16

17

18

19

20

21

22

23

24

26

192

384 192

96

384

384 192

384

32

32

27

28

29

30

31

96 20

64 20 24 I6 24 16

384 8

32

33

34

35

36

192 12

128 12

32 16 384 12

192 18

37

38 39

40

41

42

43

44

45 46

47

sP

sP

sP

sP

sP

SP

sP

sP

nsp

sP

nsp

sP

nsp

SP

nsp

nsp

SP

nsp

sP

nsp

nsp

sP

nsp

sP

nsp

nsp

nsp

sP

nsp

sP

sP

nsp

nsp nsp

nsp

nsp

sP SP

nsp SP

nsp nsp

nsp

nsp nsp nsp

sP

sP

sP

sP

sP

sP

sP

sP

nsp

sP

nsp

sP

sP

SP

sP

nsp

sP

sP

sP

nsp

nsp

sP

nsp

SP

nsp

nsp

nsp

sP

nsp

sP

sP

nsp

sP

nsp

SP

nsp

sP

sP

nsp

sP

nsp

nsp

nsp

sP sP

nsp

128 I8

384 12 384 12

768 14

384 16

192 18

384 18 768 18

384 14 384 14 192 18

No. of No. of layout width %improvement xsistorse diff. gaps (A units) in layout widthj

Oursf opts 7tch tc’ -

14

14

16

10

16

16

12

16

12

20

0

0

I

0

0

0

0

1

I

I

0

0 2

I

I

I

0

0

I

0

I

0

0

0

2

2

2

I

2

0

0 2

2

0

3

I

0 0

0

0

1

0

0

I

1 1

0

0

1

0

0

0

0

1

I

1

0

0

1

1

I

1

0

0

1

0

1

0

0

0

I

1

2

1

I

0

0

I I

0

2

1

0

0

0

0

I

0

0

1 1

I

60 36 40

44 28 36

92 60 36

108 60 44

124 68 45

60 36 40

92 52 43 108 68 37 124 76 38 140 84 40

140 76 45

28 20 28

92 68 26

76 52 31 108 68 37

108 68 37 108 60 44

124 68 45

76 52 31 124 68 45

124 76 38 92 52 43

124 68 45 92 52 43

156 100 35

156 100 35

156 100 35 124 76 38 124 84 32

60 36 40

92 52 43 92 68 26

124 84 32 92 52 43

140 100 28

140 84 92 52 92 52

108 60 124 68

140 84 140 16 140 76 108 68 108 68

40

43 43

44

45

40

45

45

37

37 40 140 84

B.S. Carlson et al. I Discrete Applied Mathematics 90 (1999) 89-114 109

Table 6 (Contd),

Harvard opt. opt. No. of No. of No. of layout width %improvement circuit contact xsistor fun& xsistorse diff. gaps (2~ units) in layout widthj number” ntwkb ntwkC

Oursf 0pt.g -tch tc1

48

49

50

51

52

53

54

55

51

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

19

80

81

82

83 84

85

86

87

89

90

91

92

93

94

95

96

sP

sP nsP

nsP

nsp

nsp

nsP

nsp

nsp

sP

sP

nsp

nsp

sP

SP

nsP

nsp

sP

SP

nsP

nsP

nsP

nsp

nsP

nsp

nsp

nsP

nsp

nsp

nsP

SP

nsp

nsp

sP

nsP

nsp

nsp

sP

nsP

nsp

sP

nsp

nsP

nsP

nsp

nsp

nsp

sP

sP

nsp

nsp

nsp

nsP

nsP

nsp

nsp

sP

SP

sP

nsp

sP

sP

sP

sP

sP

sP

nsp

nsp

nsP

nsp

nsp

nsP

nsp

nsp

nsp

nsp

sP

sP

nsp

nsP

SP

nsp

nsp

SP

sP

nsp

sP

sP

nsp

nsp

sP

nsp

nsp

nsp

96 16

384 14

384 16

64 18

192 18

384 20

384 16

64 22

96 20

192 6

192 12

192 12

384 IO

96 12

384 10

768 14

192 16

192 10

96 16

128 18

384 18

192 20 64 16

16 22

384 14

768 14

384 18

192 18

384 18

192 18

32 14

384 16

384

384

384

384

384

192

384

768

192

192

192

96

768

384

192

18

14

18

16

14

16

I8

14

16

22

20

16

18

18

20

0

0

0

1

1

I

I

3

0

0 1

0

2

0

0

0

1

0

I

0 I 2 I

2

0

0 1

I

0

1

0

1

1

0

0 0

0

0

2

0 I

2

I

2

2

2

2

0

0

0

1

1

1

1

2

0

0

I

0

1

0

0

0

I

0

1

0

1

2

1

1

0

0

I

1

0

1

0

I

1

0

0 0

0

0

1

0

1

I

1 I

2

1

2

124 68 45

108 60 44

124 68 40

140 84 40

140 84 40

156 92 41

124 76 38

172 116 32

156 84 46 44 28 36

92 60 34

92 52 43

76 60 21

92 52 43

76 44 42

108 60 44

124 76 38

76 44 42

124 76 38

140 76 45

140 84 40

156 100 35

124 76 38

172 108 37

108 60 44

108 60 44

140 84 40

140 84 40

140 76 45

140 84 40

108 60 44

124 76 38

140 84 40

108 60 44

140 76 45 124 68 45

108 60 44

124 68 45 140 92 34

108 60 44

124 76 38

172 108 37

156 92 41 124 84 32 140 92 34

140 92 34

156 100 35

110 B.S. Carlson et al. IDiscrete Applied Mathmzatics 90 (1999) 89-114

Table 6 (Contd.),

Harvard Opt. opt. No. of No. of No. of layout width %improvement circuit contact xsistor funsd xsistors’ diff. gaps (i units) in layout width’ number” ntwkb ntwk’

Ours’ 0pt.g itch tc1

91

98

99

100

101

102

105

107

108

109

110

III

112

II3

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

135

136

137

138

139

140

141

142

143

144

145 146

148

w sP

nsp

SP

nsp

nsp

nsp

nsp

sP

nsp

SP

nsp

nsp

nsp

nsp

nsp

sP

nsp

nsp

nsp

nsp

sP

nsp

sP

sP

nsp

nsp

sP

nsp

nsp

nsp

nsp

nsp nsp

nsp nsp

nsp

nsp nsp

nsp

nsp

nsp nsp

nsp

nsp

nsp nsp

sP

sP

nsp

sP

nsp

nsp

nsp

nsp

sP

sP

SP

sP

sP

nsp

sP

nsp

sP

nsp

nsp

nsp

nsp

SP

sP

sP

sP

nsp

sP

SP

nsp

nsp

nsp

nsp

nsp

nsp

nsp

nsp

nsp

nsp

nsp

sP

nsp

nsp

nsp

nsp

sP nsp

nsp

192 16

96 12

192 I4

48 I6

64 14

96 18

192 20

I6 24

128 8

384 12

768 10

384 14

192 16

384 14

192 14

384 18

96 8

384 16

96 18

168 12

768 16

192 14

384 I6

768 12

384 I6

384 I8

768 14

192 12

192 20

128 20

192 I6

768 20

384 20

384 16

192 18

384 16

I28 16

768 16

192 20

192 16

768 18

384 16

384 18

128 22

384 20 I28 IX

768 I8

1

0

1

0

0

2

2

2

0

0

0

2

I

0

0

0

0

1

I

0

0

1

0

0

0

3

0

0

0

I

2

1

2

1

1

2

I

I 1

1

0 1

1

1

I 2

1

1

0

1

0

0

1

1

2

0

0

0

1

1

0

0

0

0

1

I

0

0

1

0

0

0

2

0

0

0

1 1

1

2

1

1 1

1

I 1

1

0

1

1

1

1 1

1

124 76 38

92 52 43

108 68 37

124 68 45

108 60 44

140 92 34 156 100 35 188 116 38

60 36 40 92 52 43

76 44 42

108 76 29

124 76 38

108 60 44

108 60 44

140 76

60 36

124 76

140 84

92 52

124 68

108 68

124 68

92 52

124 68

140 100

108 60

92 52

I56 84

45

40

38

40

43

45

37

45

43

45

28

44

43

46

156 92 41

124 84 32 156 92 41

156 100 35 124 76 38

140 84

124 84

124 76

124 76 156 92

124 76

140 76

124 76

140 84

172 100

156 92

140 92 140 84

40

32

38

38 41

38

45

38

40 41

41 34

40

B.S. Curlson et al. I Discrete Applied Mathematics 90 (1999) 89-114 Ill

Table 6 (Contd.),

Harvard opt. opt. No. of No. of No. of layout width %improvement circuit contact xsistor fun& xsistorsr diff. gaps (;. units) in layout width’

number” ntwkh ntwkC

Oursf Opt.” +ch tc’

149

150

152

153

154

155

156

157

I58

159

161

162

164

I65

166

167

I68

169

170

171

172

173

174

175

176

177

I78

179

180

1x2

I83

I84

I85

187

188

IX9

I91

192

193

195

196

197

198 199

200

201

w “sP

sP

nsp

nsp

sP

nsp

nsp

nsp

nsp

nsp

nsp

sP

nsp

nsp

nsp

nsp

nsp

nsp

nsp “SP

nsp

sP

sP

sP

sP

nsp

nsp

nsp

nsp

nsp

nsp

nsp

nsp nsp

sP

sP

nsp

nsp nsp

nsp

nsp

nsp

sP nsp

nsp

nsp

nsp

SP

nsp

nsp

sP

nsp

nsp

nsp nsp

nsp

nsp

sP

nsp

sP

sP

sP

sP

sP

nsp

nsp

V

sP

sP

sP

sP

sP

sP

sP nsp

“SP

nsp nsp

nsp sp

sP

sP

nsp

nsp

nsp

nsp

nsp

sP

sP

nsp

nsp

384 16

384 16

384 14

384 16

192 20

192 I6

384 IX

76X I6

192 22

96 20

192 18

64 I8

8 2

64 IO

192 I4

192 12

64 I6

32 10

192 10

384 14

192 I6

192 I8

96 8

192 12

192 I4

384 I2

384 I6

96 I2

48 16

384 18

192 16

48 16

3x4 I4

192 18

3X4 16 96 14

48 16

96 20

192 16

384 14

3x4 IX

192 I6

384 I6 96 16 96 20

192 I4

2

0

0

0

I

0

I

I

2

2

1 I

0

2

0

0

0

2

2

I

0

2

0

0

I

0

1

0

0

0

I

2

0

2

I

1

0

2

0

1

0

2

1

2 2

2

1

0

0

0

1

0

1

1

2

2

1

I

0

1

0

0

0

1

1

I

0

I

0

0

1

0

I

0

0

0

1

2

0

I

1

I

0

I

0

I

0

2

I I

2 I

124 84 32 124 68 45

108 60 44

124 68 45 156 92 41 124 68 45 140 84 40

124 76 3X 172 108 37 156 100 35 140 84 40 140 84 40

I2 I2 0 16 60 21

108 60 44

92 52 43 124 68 45

76 60 21 76 60 21

I08 68 37 124 68 45

140 92 34 60 36 40 92 52 43

108 68 37

92 52 43

124 76 38 92 52 43

124 68 45

140 76 45 124 76 38

124 84 32 108 60 44 140 92 34 124 16 38 108 68 37

124 68 45 156 100 35 124 68 45 I08 68 31 140 76 45

124 84 32 124 76 38 124 84 32 156 100 35 108 76 29

112 B.S. Carlson et al. I Discrete Applied Mathematics 90 (1999) 89-114

Table 6 (Contd.),

Harvard Opt. Opt. No. of No. of No. of layout width %improvement

circuit contact xsistor fun& xsistor? diff. gaps (i units) in layout width’

numbera ntwkb ntwkC

Oursf 0pt.g ytch tc’

202

203

204

206

210

214

219

222

223

224

225

231

248

264

269

212

211

281

286

301

314

324

349

354

369

384

Total

sP

nsp

sP

nsP

nsP

nsp

nsp

nsp

nsp

nsp

nsp

sP

nsp

nsp

nsp

nsp

nsp

nsp

nsp

nsp

nsp

nsp

nsp

SP

nsp

nsp

sP

sP

SP

nsp

nsp

nsp

nsp

nsp

nsp

nsp

nsp

sP

nsp

nsp

nsp

nsp

nsp

nsp

nsp

sP

sP

nsp

sP

sP

nsp

nsp

384 14

192 16

12 8

96 22

192 18

192 20

96 18

384 18

96 22

384 18

32 20

48 12

96 18

192 22

192 20

384 16

192 20

192 20

384 I8

192 16

192 18

384 18

192 18

384 16

16 24

16 18

0 0 108 1 I 124

0 0 60 2 I 172 2 1 140

2 2 156

2 1 140

2 1 140 3 1 172

1 I 140

2 2 156 0 0 92

I 1 140 I 1 172

2 I 156 1 I 124 2 2 156 1 I 156 1 1 140

I 1 124

2 2 140

2 2 140

1 1 140 0 0 124

I 1 188

3 2 140

25,724

60 44

6 38

36 40

108 37

92 34

100 35

92 34

92 34

116 32

84 40

100 35

52 43

84 40

100 41

100 35

76 38 100 35

92 41

84 40

16 38

92 34

92 34

84 40

68 45

108 42

100 28

15,656 39.1

a Harvard circuit number used in [6] to identify the circuits.

b The type of the topology of the optimal contact network. (nsp for non-series/parallel and sp for

series/parallel). c The type of the topology of the optimal transistor network.

d The number of four variable switching functions whose optimal implementation is realized by this circuit.

e The number of p-type and n-type transistors in the circuit.

r The number of diffusion gaps using our algorithm.

g The number of diffusion gaps in the optimal solution.

h The width of the layout of the circuit without using transistor chaining.

i The width of the layout of the circuit with transistor chaining.

j The percent improvement in the width of the layout due to transistor chaining (percent difference between

columns 8 and 9).

which are optimally realized by it. The number of switching functions realized by

each circuit is given in column 4 of the table. Contained in column 5 is the number

of transistors required in a static CMOS implementation of the circuit. Also shown in

Table 6 is a comparison of the results of our algorithm to the optimal solution (columns

6 and 7), and a comparison of the widths of the layouts generated by our method with

B.S. Carlson et al. I Discrete Applied Mathematics 90 (1999) 89-114 113

the widths of the layouts of circuits which do not use transistor chaining (column

10). The minimum transistor length is assumed to be 2& minimum separation between

transistor channel and diffusion contact is assumed to be 12, minimum diffusion contact

is assumed to be 4;1 x 4& and minimum separation of like diffusion is taken to be 4;1.

It is clear that the use of our algorithm can significantly decrease layout area. The

average reduction in layout width for all of the examples is 39.1 %,2 and the algorithm

determines the optimal solution for 82.5% of the circuits. In every case but one where

our algorithm misses the optimal solution, it misses by only one diffusion gap. If the

circuit can be constructed with zero diffusion gaps, then our algorithm is guaranteed

to find an optimal solution [3].

6. Conclusions

The algorithm presented in this paper operates on non-series/parallel circuits in addi-

tion to series/parallel circuits, determines very good solutions (optimal in 82.5% of the

test cases) and its time complexity is linear with respect to the number of transistors

in the circuit. Our algorithm is superior to existing algorithms, since it operates on

the most general class of planar circuits and it is efficient. One algorithm has been

published which operates on this class of circuits [ 121; however, its creators assume

that the size of practical circuits is very small. Certainly there is a practical limit on

the size of circuits; however, the limit is continuously increasing due to improvements

in the fabrication processes, and is already much larger than the limit assumed in [12].

Although we do not guarantee an optimal solution to this NP-hard problem, due to its

efficiency our algorithm is not in danger of becoming obsolete.

In addition to introducing an effective technique for chaining the transistors in a

CMOS layout, this paper shows that it is important to consider the implementation of

switching functions with circuits of non-series/parallel topology. A significant reduction

in the number of transistors, and hence layout area is achievable. Moreover, it may be

possible to implement switching functions, which may otherwise require two or more

gates if the topologies are restricted to series/parallel ones, with a single complex gate

by using a non-series/parallel circuit. Furthermore, the use of non-series/parallel circuits

can improve the performance of circuits, since fewer devices in the circuit results in

less resistance between the output and the power rails.

This technique is limited in the sense that it does not consider the height of the

layouts. However, in a standard cell layout system it is rarely necessary to optimize

the height of the cells, and if height reduction is necessary a technique can be applied

after the transistor chains have been formed. It is also possible to incorporate a height

reduction technique into the algorithm which determines the dual path covering set if

it is desired.

*It should be noted that the amount of improvement in layout width cannot exceed 50%

114 B.S. Carlson et al. I Discrete Applied Muthematics 90 (1999) 89-114

It is possible to perform transistor reordering on a circuit without altering its func-

tionality. In many cases reordering the transistors will help to obtain a better solution;

however, one needs to be careful since transistor reordering can have a significant effect

on circuit performance [2]. In addition to reordering, improvements in the layout may

result by relaxing the restriction that the PMOS (respectively, NMOS) network be the

dual of the NMOS (respectively, PMOS) network. There is much more freedom in the

topologies of the two networks if it is not required that they be dual to one another.

In addition, the relaxation of this constraint will allow the graph representations to be

non-planar and therefore expand the class of circuits which can be used. Of course

increasing the solution space decreases the likelihood that good solutions can be found

efficiently. Care must be taken to determine the potential improvement due to increased

freedom versus problem complexity. In many cases it is not advantageous to increase

the complexity, since the potential improvement is very small.

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