Three-dimensional optoelectronic stacked processor by use of free-space optical interconnection and...

Three-dimensional optoelectronic stackedprocessor by use of free-space opticalinterconnection and three-dimensional VLSI chip stacks

Guoqiang Li, Dawei Huang, Emel Yuceturk, Philippe J. Marchand, Sadik C. Esener,Volkan H. Ozguz, and Yue Liu

We present a demonstration system under the three-dimensional �3D� optoelectronic stacked processorconsortium. The processor combines the advantages of optics in global, high-density, high-speed par-allel interconnections with the density and computational power of 3D chip stacks. In particular, acompact and scalable optoelectronic switching system with a high bandwidth is designed. The systemconsists of three silicon chip stacks, each integrated with a single vertical-cavity-surface-emitting-laser–metal-semiconductor-metal detector array and an optical interconnection module. Any input signal atone end stack can be switched through the central crossbar stack to any output channel on the oppositeend stack. The crossbar bandwidth is designed to be 256 Gb�s. For the free-space optical intercon-nection, a novel folded hybrid micro–macro optical system with a concave reflection mirror has beendesigned. The optics module can provide a high resolution, a large field of view, a high link efficiency,and low optical cross talk. It is also symmetric and modular. Off-the-shelf macro-optical componentsare used. The concave reflection mirror can significantly improve the image quality and tolerate a largemisalignment of the optical components, and it can also compensate for the lateral shift of the chip stacks.Scaling of the macrolens can be used to adjust the interconnection length between the chip stacks or makethe system more compact. The components are easy to align, and only passive alignment is required.Optics and electronics are separated until the final assembly step, and the optomechanic module can beremoved and replaced. By use of 3D chip stacks, commercially available optical components, and simplepassive packaging techniques, it is possible to achieve a high-performance optoelectronic switchingsystem. © 2002 Optical Society of America

OCIS codes: 200.0200; 200.4650; 200.4960; 200.2610.

1. Introduction

With the rapid development of VLSI technology, in-tegration density, chip area, and processor clockspeed have been increasing continuously. To effi-ciently exploit the performance of microelectronic cir-

When this research was performed, G. Li �e-mail address:[email protected]�, D. Huang, E. Yuceturk, P. J. Marchand, andS. C. Esener are with the Department of Electrical and ComputerEngineering, University of California, San Diego, 9500 GilmanDrive, La Jolla, California 92093-0407. G. Li is on leave from theShanghai Institute of Optics and Fine Mechanics, AcademiaSinica, Shanghai, China. D. Huang is now with Sun Microsys-tems, San Diego, California 92121. V. H. Ozguz is with IrvineSensors Corporation, 3001 Redhill, Building 3, Costa Mesa, Cali-fornia 92626. Y. Liu is with Honeywell Technology Center, 12001State Highway 55, Plymouth, Minnesota 55441.

Received 29 June 2001; revised manuscript received 27 Septem-ber 2001.

0003-6935�02�020348-13$15.00�0© 2002 Optical Society of America

348 APPLIED OPTICS � Vol. 41, No. 2 � 10 January 2002

cuits and systems, communication bandwidths needto keep pace in chip, board, backplane, and machinelevels. However, electrical interconnections sufferfrom the RC constant associated with the wires, andthis effect becomes more severe as the feature sizescales down and the interconnection length in-creases. High-speed electrical signals also haveelectromagnetic interference, clock skew, wave-frontdegradation, and cross talk. Moreover, the two-dimensional �2D� topology of the VLSI circuits limitsthe number of pin-outs because the pins are placedaround the edges of the chips. Therefore currentinterconnection technology has difficulty in satisfyingthe off-chip bandwidth requirement imposed by fu-ture microelectronics. The memory access bottle-neck is becoming worse because the memory does notscale as well as the processing unit in terms of speedand area. Although the use of copper and otherlower dielectric constant material may alleviate thebottleneck to some extent, new architectures and in-

terconnection technologies must be developed as al-ternative solutions of long-term potential.

Optical interconnection has been widely acceptedas a promising approach for massively parallel datacommunications.1–4 In comparison with their elec-tronic counterparts, optical links have low cross talkand low sensitivity to electromagnetic interference.With a 2D array of optoelectronic transmitters andreceivers, high-density �several thousands of chan-nels�cm2� and high-data-rate �Gb�s� interconnec-tions5,6 can be achieved with a high bandwidth ofseveral Tb��s cm2�. The surface-emitting character-istic of the vertical-cavity surface-emitting lasers�VCSELs� allows the optoelectronic chip to be inte-grated onto the top of the silicon chip so that the thirdspatial dimension can be used for beam routing.Therefore three-dimensional �3D� optical intercon-nects permit a high utility of the chip area, and thenumber of interconnection channels can scale withthe chip area. For two fixed optoelectronic arrays,different links have almost the same optical pathlength, and hence optical interconnects have lesssignal skew. In the past few years, various dem-onstration systems have been reported, especiallyat multiple-chip-module and board levels. Thebeam propagation medium can be free-spaceoptics,7–21 fiber optics,22 or optical waveguides.23

Significant progress has been made in optoelec-tronic devices, integration of optoelectronic deviceswith complementary-metal-oxide-semiconductor cir-cuits, micro-optics fabrication, and system packagingon the basis of optomechanics,8–18,24–26 planar,19 orstacked27 integration.

In parallel, advances in 3D VLSI packaging tech-nologies have made it possible to integrate multiplechips into a smaller volume by stacking electronicchip dies on top of each other.28,29 Three-dimensional chip stacks can realize more powerfulprocessing functions than planar architectures andsignificantly reduce power consumption and latencyby shortening the length of interconnections betweenone chip and its neighbors. However, this approachcannot support the density and globality of electricalinterconnects that are required by many operationswhen the overall system contains several stacks, eachcontaining many chips. In this case, free-space op-tics can provide a much needed global, high-speed,high-density communication capability betweenstacks.

Higher-level digital signal-processing systems re-quire densely distributed nodes �processing ele-ments� with larger complexity and globalconnectivity. By combining the strengths of 3D chippackaging and optoelectronic parallel array intercon-nection technologies, it is possible to build an efficientcompact system that permits fast processing andswitching of large data arrays. The powerful nodesare integrated into the 3D chip stacks with each chipcontaining an array of processing elements or othercomplex circuits. Such a system can be utilized forimplementation of various applications including dig-ital image processing, fast Fourier transform, and

bit-parallel crossbar switch. In particular, one canconstruct a system composed of several processorstacks that are optically interconnected with a cross-bar stack. An all-electronic implementation of thecrossbar network has difficulty in scalability and thushas a limited bandwidth. In this paper we describethe realization of a 3D optoelectronic stacked proces-sor system with a focus on the crossbar switch that isscalable and has a high bandwidth.18,30 The systemconsists of three layers: electronics, optoelectronics,and optics. The electronic layer has three siliconchip stacks with each stack comprising 16 VLSIchips. Each chip corresponds to 16 optical inputs–outputs �I�Os� and realizes 16 � 16 switches at 1Gb�s. The driver for the VCSEL and the receiver forthe metal–semiconductor–metal �MSM� detector arealso built in the chips. The optoelectronic layer in-cludes 16 � 16 VCSEL–detector arrays, which areflip-chip bonded to the top of the silicon chip stacks.The optics module is a folded hybrid micro–macroimaging system that implements global and regularinterconnections. The use of a top concave mirrorsubstantially improves the imaging quality of the op-tical system and allows a relatively large misalign-ment tolerance. The system is symmetric, andmodular design is used. Commercially available op-tical components are employed to reduce the cost.The system also possesses features such as high res-olution, large field of view, high link efficiency, andlow optical cross talk. Scaling of the macrolens canbe used to adjust the interconnection length betweenthe chip stacks. All the optical and optoelectroniccomponents can be packaged with simple passive-alignment technologies. The optics and electronicslayers are separated until the final assembly step.The optomechanic module can be snapped onto theelectrical system via pins and can be removed andreplaced, permitting the system to be reworked.

This paper is organized as follows. Section 2briefly introduces the system architecture, and Sec-tion 3 describes the 3D chip stacks and optoelectronicdevices. In Section 4 the design of the optical mod-ular system is presented. Section 5 discusses thesystem packaging while Section 6 shows some exper-imental testing results of the system. Finally, a con-clusion is given in Section 7.

2. System Concept

Performance of computing systems is becoming in-creasingly dependent on interconnection networks.The crossbar is one of the most general reconfigurablenetworks. Each of the nodes in the input stage canbe switched to any node in the output stage withoutblocking. Because it is a single-stage network, la-tency is minimum compared with that in multipleinterconnection networks. However, the number ofswitching elements increases with N2 as the numberof nodes N increases. The 2D electronic implemen-tation is costly and complex for large N. Thus suchan architecture does not allow good scalability, andthe bandwidth of an electronic crossbar is severelylimited. To achieve a distributed crossbar, multiple

10 January 2002 � Vol. 41, No. 2 � APPLIED OPTICS 349

ssor

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�L� M � M �L � M � N� switches are arranged in amultichip module or in a single chip. For variousarrangements the total area is of the same order.Many optical crossbar switches have been demon-strated on the basis of free-space16,31–34 or wavelength-division-multiplexing35 technologies. However, onlya small number of nodes were handled in some sys-tems. The implementation that uses fan-out op-tics31,32 suffers from low efficiency in energyutilization, and the point-to-point beam-steering op-tics16 that uses angle multiplexing requires an array ofVCSELs for a single data line. Here we present anoptoelectronic system that is scalable and can providea large communication bandwidth by embedding ac-tive electronic switches into chip stacks and incorpo-rating free-space optical interconnections.

Figure 1 shows a schematic diagram of the demon-stration system in which three 3D VLSI stacks areassembled with optoelectronic modules for globalcommunications. Each stack consists of 16 VLSIchips and a single 16 � 16 VCSEL–MSM detectorarray flip-chip bonded on top of the chip stack. Eachchip in the stack supports 16 optical I�Os at 1 Gb�s,which are connected to 64 electronic I�Os at 250 Mb�sthrough 4 to 1 multiplexer and 1 to 4 demultiplexer.Furthermore, the electronic chip implements a 16 �16 crossbar switch that can arbitrarily route datapackets between its inputs and outputs. The elec-tronic switch, transmitter driver, and the detector am-plifier are built in the same layer. In each stack the16 chips are interleaved with diamond layers for heatremoval. A new corner-bonding technique was devel-oped to attach the stack onto a support board. A flex-ible cable attached to the side of the stack provides thesystem electrical address, control, clock, power, andground lines to the stack. An optical interconnectionlayer is designed for global communications betweenneighboring stacks. The chips in the central stack

Fig. 1. Schematic diagram of the 3D optoelectronic proce


are perpendicular to those in the other two stacks sothat a signal in one end stack can be routed to any chipon the opposite end stack. To realize communicationwith both the left and the right neighbors, the opto-electronic array is separated into two halves, and thebeams in the two halves are deflected differently.The crossbar bandwidth is designed to be 256 Gb�swith a 16 Gb�s throughput per chip.

Figure 2 shows the fixed mapping between the twoneighbor optoelectronic arrays; the two arrays areinterleaved as a single array. The VCSEL and thedetector arrays are offset by 250 �m in the transversedirections. The pitch of the VCSEL array and thatof the detector array both are 500 �m. For example,an input signal to the port 0 can be switched in the xdirection to any of the 16 output nodes, and then thissignal is routed by the optical system to the corre-sponding detector on the right stack. After the am-plification and thresholding operations, this signal isfurther switched in the y direction to any of the out-put positions. Finally, this signal can be transmit-ted to the next neighbor stack or back to the leftstack, depending on the operation mode and outputchannel �in the right or left half of the stack�. In thisway, an input signal can be guided in the xy planewith the active electronic switches and the opticalinterconnection in the z dimension, and the 2D dataarray can be switched in parallel. The system iseasier to scale and can achieve a bandwidth muchhigher than the all-electronic system. The use ofchip stacks greatly reduces the footprint area in com-parison with the 2D implementation.

3. Three-Dimensional Chip Stacks and OptoelectronicArray Devices

Three-dimensional stacking of VLSI chips with inter-leaved diamond heat-spreading layers and integra-tion of the optoelectronic array onto the chip stacks

with 3D chip stacks and free-space optical interconnects.

are challenging. When the design of the buffer chip,including the driver and receiver circuits, was final-ized, a buffer prototype cube with a bump-bondedactive VCSEL–detector array was designed for inves-tigating the optoelectronic array integration and forthe testing and understanding of alignment andpackaging issues on chip stacks. Irvine SensorsCorporation stacked the chips in a 3D fashion to forma cubic device, and Honeywell Technology Center fab-ricated the optoelectronic array and integrated thearray with the cube by a flip-chip bonding technique.The I�O side of the cubes has AlN-based ceramicinterface with Au traces. The optoelectronic arrayside has pads with TiWCuAu metalization to allowflip-chip bonding. Figure 3�a� shows the emulatorcube with the optoelectronic array. A new attach-ment process was developed to allow interface withan external test board by use of a flexible cable at-tached to buffer stacks. The process consists of at-taching a flexible cable onto the top cap chip and wirebonding the pads between parts. The opposite endof the flexible cable is designed to fit in a standardconnector and thus can be mounted to a board fortesting. Figure 3�b� shows the top view of the pro-totype cube with five VCSELs at the upper left cornerswitched on. The light intensity versus current�L–I� curve of the VCSEL working at 850 nm is de-picted in Fig. 3�c�. The threshold current and thethreshold voltage are approximately 1.3 mA and 2.0V, respectively. The VCSEL has an aperture of 5�m with a full divergent angle of 30°, and the detec-tor is a 50-�m octagon.

Figure 4�a� shows one of the new cubes to be usedin our system. The size of the cube is 14 mm � 14mm � 8 mm. The threshold current and the thresh-old voltage of the VCSEL are 0.45 mA and 1.65 mV,

Fig. 2. Mapping between two ne

respectively, with a slope efficiency of 0.4 W�A, andthe devices operate at 1 Gb�s. The VCSEL can workover a large temperature range. The responsivity ofthe detector at 850 nm is 0.25 A�W at 5 V �0.2 A�Wat 2 V�. All the electrical I�Os are rerouted to thecenter of the top and bottom surfaces of the cube, andpower and control lines are rerouted to the edges ofthe two surfaces. On the top surface �Fig. 4�b��,there are 1024 pads with TiWNiAu metalization.�Each I�O channel has four pads: two for the VC-SEL and two for the detector. Each chip has 64pads�. The solder dam opening is 40 �m. On thebottom surface �Fig. 4�c��, there are 64 � 16 pads witha pitch of 110 �m � 250 �m, and these pads can beused as the electrical I�Os. The cube is attached tothe rigid section of the flexible cable with the corner-bonding technique, which is based on forming a bumpat the corner of the cube to the substrate. There isan opening at the center of the rigid section of theflexible cable so that the backside of the cube can beprobed. Figure 4�d� shows some VCSELs workingat the threshold current.

4. Optical Design

Owing to the small feature sizes of the VCSELs anddetectors and the relatively large device array, strin-gent requirements are placed on the optical imagingsystem. The general requirements on the free-spaceoptical systems are high resolution �small spot size�,low loss �high link efficiency�, low cross talk, largefield of view, low cost, small volume, large misalign-ment tolerance, simple and cascadable �modular de-sign�. Four types of free-space optical systems havebeen proposed for parallel optical array interconnec-tion: macro-optics with conventional compoundlenses,10–14 micro-optics with a lens array,9,15 hybrid

r VCSEL–MSM detector arrays.
ighbo

3

optics that uses a microlens array and simplemacrolenses,16–20 and mini-optics with a minilens ar-ray or minihybrid lenses.21 Generally speaking, thehybrid optical system is optimal in realizing thegoals. If the VCSEL–detector arrays are coplanar,the optical system should be folded with a reflectionmirror. Here a novel hybrid micro–macro-opticalsystem that satisfies the above requirements is de-signed, with a concave reflection mirror, and themethodology can be extended to other similar appli-cations.

The optical module that interconnects the twoneighboring stacks is shown in Fig. 5. The system isa combination of a pair of small field, low f-numbermicrolenses, a pair of large field, high f-number ma-crolenses, a pair of deflecting elements �prisms orgratings�, and a concave reflection mirror. In thissystem the microlens array is used to collimate thebeams emitting from the VCSELs and refocus thebeams onto the detectors. The macrolenses are used

Fig. 3. Prototype cubic device by integration of a silicon chip stais wire bonded onto the top cap chip. �b� Top view of the optoele


to adjust the interconnection distance. Both the mi-crolens and macrolens are used at infinite conjugates,and the beams are focused at the common focal planeof the two macrolenses. A high resolution is pro-vided by the microlenses, and the macrolenses needto resolve only the aperture of the microlenses.Hence the performance requirements on the macro-lenses are greatly reduced. This system combinesmost of the strengths of the macro- and micro-opticalconfigurations. It is more suitable for the imaging oflarge dilute arrays with a field larger than that inconventional macro-optical imaging, and it does notsuffer from the cross-talk limitations on the intercon-nection length for purely micro-optical imaging. In-finite conjugate systems are easier to align and tendto increase the tolerance to mechanical misalign-ment. The deflecting elements are inserted in thecollimated beam path between the micro- and mac-rolenses so that they do not generate additional ab-errations. Because the aberrations of an imaging

d a VCSEL–MSM detector array. �a� 3D view. A flexible cableic array with five VCSELs on. �c� L–I curve of one VCSEL.

ck anctron

system increase with increasing numerical aperture,it is helpful to use a large f-number macrolens toimprove the imaging quality. The microlens shouldbe chosen to match the VCSEL beam property so thatthere is no beam clipping at the aperture of the mi-crolens. However, in this configuration the smallf-number microlenses have severe mechanical toler-ance constraints. A small alignment error of themicrolens may greatly deteriorate the images. Tocompensate for the aberrations caused by the mis-alignment of the microlens and other optical ele-ments, instead of the use of a flat reflection mirror, aconcave reflection mirror whose radius is close to thefocal length of the macrolens was employed. Fur-ther, to reduce the cost, the macrolenses and theconcave mirror were selected from off-the-shelf com-ponents. The macrolens �KPX088� with a f�2.9 andthe concave mirror �KPC031, with reflection coatingon the concave side� were purchased from NewportCorp.

For the beam-deflecting elements, both prisms anddiffraction gratings have been considered in different

view of the chip stack. �c� Bottom view of the chip stack. �d�
Fig. 4. Cube corner bonded to a flexible cable. �a� 3D view. �b� TopVCSELs operating at threshold current.
Fig. 5. Schematic diagram of the folded hybrid optical systemwith a top concave mirror for the interconnect. The inset depictsa magnified view of the beam focused on the detector.


3

systems. Although the use of blazing gratings makea more compact system, the loss of energy in thesystem could be higher than when prisms are usedbecause fabrication errors affect the diffraction effi-ciency. In particular, in our case, the beams emit-ting from the left and the right parts of the VCSELarray are deflected to different and symmetric direc-tions, and diffraction of the gratings to the undesiredorders will generate communication cross talk. Inthe prism approach, if the two prisms with knifeedges on the sharply acute angle of 21.8 deg areplaced as shown in Fig. 6�a�, two columns of the op-tical I�O channels might be lost because the bevelwidth of the edges is comparable with the pitch of theVCSEL–detector array. To overcome this problem,we would rather have a flat of 0.5 mm and have nobevel �Fig. 6�b��. Then the two prisms are butted up

Fig. 6. Prism design. �a� Alignment of the two prisms with knifeedges facing each other causes the loss of optical I�O channels. �b�New prism design without bevel. �c� The new design can avoidthe loss of optical channels.


so that the 0.5 mm � 15 mm faces touch �Fig. 6�c��.The burden was transferred from the bevel to chip-ping.

By adjustment of the vertical position of the con-cave mirror, the system can tolerate a significantmisalignment of the microlens. The simulation re-sults with CODE V36 are listed in Table 1. For moreaccurate modeling, the object is considered as an ex-tended source that encompasses a diameter set tocontain 99% of the energy of the Gaussian beam.For example, when the mirror is put at the referenceposition, the image spot size is less than 4.8 �m indiameter. Even if the microlens is deviated �30 to30 �m from the reference position, more than 95%of the energy can be encircled in spots no bigger than14.2 and 25.0 �m, in diameter, respectively. Whenthe VCSEL–detector array is outside the focal planeof the microlens, i.e., the beam coming out of themicrolens is convergent, the system has better opticalperformance than when the VCSEL–detector arrayis inside the focal plane of the microlens �the beamleaving the microlens is divergent�. Moreover, im-age shift that is due to the lateral alignment error ofthe cubes can also be compensated for by adjustmentof the top mirror. These features permit the cost ofpackaging to be reduced.

A comparison between use of a concave mirror anduse of a plane mirror can be made in terms of theencircled energy versus the spot size. CODE V mod-eling is shown in Fig. 7, in which ray tracing for threedifferent fields of the object plane is performed.Field 1 is located on axis, field 2 and field 3 are at theedge, and the outmost corner is as shown in Fig. 2.For the Newport macrolens, mentioned above, if theplane mirror is put at the reference position, 50% ofthe energy is encircled in a spot approximately 11 �min diameter while 60% of the energy is encircled in aspot approximately 200 �m in diameter. This effi-ciency and image quality might not be good enoughfor high-speed interconnection. The modelingshows that to guarantee high image quality, the useof a plane mirror requires a specially designed mac-rolens and the tolerance for the misalignment of themicrolens is quite small. Thus the use of a concavemirror has significant advantages.

The optical system we utilized is scalable. Thelarger f-number macrolens is more suitable for appli-cations in which the optoelectronic arrays are

Table 1. Longitudinal Misalignment of the Microlens Can BeCompensated for by Adjustment of the Top Concave Mirror

LongitudinalMisalignment of

the Microlens��m�

VerticalAdjustment ofthe Top Mirror

�mm�Encircled

Energy �%�

SpotDiameter

��m�

30 0 95 14.220 0 100 13.00 0 100 4.8

20 10.8 85 20.030 10.8 95 25.0

sparsely distributed. In our demonstration systemthe chip stacks are put as close as possible to eachother to show the functional density. It is possible todesign lower f-number macrolenses and choose thecorresponding concave reflection mirror. This sys-tem will be even more compact.

5. System Packaging

The whole system includes three layers: the systemprinted circuit board, the optoelectronic module in-cluding the three cubes with the VCSEL–detectorarray and the microlens array, and the optics module.The optoelectronic module and the optics module areassembled separately. The two modules can be re-moved from the system printed circuit board and re-placed, and the optical module can also be removedfrom the optoelectronic module and replaced.

Before the cubes are assembled in the system, themicrolens array is integrated on top of the VCSEL–

Fig. 7. Comparison between the use of a concave mirror and theuse of a flat mirror in terms of the spot size at the detector plane.Simulation results are shown in �a� for the concave mirror and �b�for the flat mirror.

detector array on the basis of a telecentric imagingsystem. Both the microlens array and the VCSEL–detector array have a substrate, and the two sub-strates are integrated together with an adhesive.To align the three cubes into the system, a singlealuminum plate and a photomask with registrationmarks for each other are fabricated. The aluminumplate �MIC 6 Tool Plate, by Euramax Coated Prod-ucts Ltd.� is used to hold the cubes with better heatdissipation and a more rigid structure. Figure 8�a�is a top view of the aluminum plate. There are threesquare openings and some alignment crosses on theplate. At the bottom of the photomask �Fig. 8�b��,there are matched alignment crosses and alignmentmarks registered to the three microlens arrays. Thealignment marks for the microlens array are de-signed in such a way that the distance between thetwo neighbor lines is equal to the diameter of themicrolens. A microscope mounted on a three-axistranslation stage is used for accurate alignment.The photomask is first aligned on the aluminum plateand fixed with Kant-Twist clamps. The cubes arealigned one by one. Figure 9 is a picture of thesetup. The profile of the cube after assembly isshown in Fig. 10. A thin aluminum plate �part 4� isattached to the bottom of each cube �part 3�, then it isfixed to the center of the top surface of a three-axistranslation and three-axis rotation stage, with a gluethat can be released by a corresponding solvent.The edge of the top surface of the chip stack is heldagainst the machined shoulder at the openingsquares of the aluminum plate. The surface of theshoulder is kept parallel to the top surface of thealuminum plate. By adjusting the stage, the cube

Fig. 8. Alignment marks on �a� the aluminum plate and �b� thephotomask.


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will be well positioned when the microlens array ismatched to the alignment marks on the photomask.To fix the cube with the main aluminum plate �part1�, a small aluminum cube �part 5� is attached to bothsides of the thin aluminum plate �part 4�, and thenthe two aluminum plates �parts 1 and 5� are con-nected with each other with a piece of glass �part 6�and UV-cured epoxy.

As shown in Fig. 10, the prisms and the macrolensare assembled into the frame of a single piece of aplastic module. Sufficient alignment precision canbe guaranteed by the mechanic fabrication. Eachtop concave mirror is aligned with a separate plastic

Fig. 9. Cube alignment setup.

Fig. 10. Optomechanic module. 1, main aluminum plate; 2, chipstack; 3, rigid part of the flexible cable; 4, thin aluminum plate; 5,aluminum cube; 6, glass; 7, UV-cured epoxy.

Table 2. Misalignment Values for D

Component x ��m� y ��m�

VCSEL 1 1PrismMirror 5 5PrismDetector 1 1

aThe VCSEL–detector array is assumed to be aligned outside t


piece with screws and springs for adjustment oftranslation in the vertical direction and tilt along thetransverse axes. The optics module and the opto-electronics layer are assembled together with thepin–pinhole technique. They are self-aligned, andno further adjustment is required. Finally, thewhole optomechanics module is assembled to the sys-tem board by a conventional mechanic method.These modules can also be mounted by use ofLEGO.24 Figure 11 is the picture of the optoelec-tronic system. In the whole packaging procedure,only passive alignment is required, and all the com-ponents are easy to align.

Each step of the assembly might generate mis-alignment. The lateral and rotational misalign-ments in the system may result in beam coupling inadjacent channels, and the longitudinal misalign-ments may result in beam clipping at the aperturesand defocusing at the detector. Performance simu-lation of the optical system after assembly can becarried out in CODE V by taking into account all thepossible alignment errors. The aluminum plateholding the cubes can be used as a reference plane.Table 2 lists some typical misalignment errors of var-ious components, and the VCSEL–detector array isassumed to be outside the focal plane of the micro-lens. The image spot diagram for five differentfields is shown in Fig. 12. It can be seen that 90% ofthe energy is encircled in a spot smaller than 12.4 �min diameter. Table 3 lists various misalignment er-rors of the VCSEL–detector array and the top mirrorwhile the other errors are kept the same as in Table2. The VCSEL–detector array is assumed to be in-side the focal plane of the microlens. The image spotdiagram is shown in Fig. 13, and 90% of the energy isencircled in a spot smaller than 22.9 �m in diameter.Therefore, after considering the misalignment errorsof the optical components, the optical system can still

Fig. 11. Assembled optoelectronic system.

s and Components in the Systema

z � �rad� � �rad� �rad�

�m 0.008 0.008 0.0010.008 0.008 0.001

mm 0.01 0.010.008 0.008 0.001

�m 0.008 0.008 0.001

cal plane of the microlens array.

evice

20

1

20

he fo

the misalignment values in Table 2 are taken into account. the misalignment values in Table 3 are taken into account.

satisfy the link requirement well. In the wholepackaging procedure, only passive alignment is re-quired, and all the components are easy to align.

6. Experimental Results

In the preliminary experiment, we tested the align-ment tolerance of the optical components. Charac-terization of the optical link at high speed is beinginvestigated, and the results will be presented in fu-ture publications. As shown in the previous sec-tions, the top concave mirror can compensate for theoptical aberrations and significantly improve the op-tical performance. When all the optical componentsare assembled in the system, the top mirror is theonly element that can be adjusted, and its alignmenthas an important effect on types of interconnectionperformance such as link efficiency and cross talk.In the experiment the top mirror is mounted on asix-axis stage so that it can be moved in the x, y, andz directions and tilted along the x and y axes. Figure14 shows the output signal from the MSM detectorwhen the data rate is 2 K�s. To measure the linkefficiency, a single VCSEL is switched on. The topmirror is adjusted to find the maximum power inci-dent on the corresponding detector, which is obtainedby the photocurrent and the responsivity of the de-tector. The output power of the VCSEL should bemeasured before the microlens is integrated. Thelink efficiency of the optical system is higher than

85%, which is good enough for the receiver at high-speed operation. Cross talk is measured by testingthe photocurrent from the neighbor detectors of thedesired destination. The responses from the detec-tors that are located at different distances from thedestination are almost the same. This indicatesthat the cross talk is not caused by the optical system

Fig. 14. Output signal from the detector when the data rate is 2K�s.

Fig. 12. Simulation of the encircled energy versus spot size after
Fig. 13. Simulation of the encircled energy versus spot size after
Table 3. Misalignment Values for Devices and Components in the Systema

Component x ��m� y ��m� z � �rad� � �rad� �rad�

VCSEL 1 1 20 �m 0.008 0.008 0.001Prism 0.008 0.008 0.001Mirror 5 5 10.7 mm 0.01 0.01Prism 0.008 0.008 0.001Detector 1 1 20 �m 0.008 0.008 0.001

aThe VCSEL–detector array is assumed to be aligned inside the focal plane of the microlens array.


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Fig. 15. Experimental results for the top mirror tolerance. �a� Tolerance for lateral shift in the x direction. �b� Tolerance for lateral shiftin the y direction. �c� Tolerance for vertical shift in the z direction. �d� Tolerance for tilt along the x axis. �e� Tolerance for tilt along
the y axis.

but by electronics. This is consistent with the resultof CODE V modeling because the spot size is muchsmaller than the pitch of the detectors. The de-tected electrical cross talk is approximately 24 dB.The dependence of the performance on the alignmentof the top concave mirror is depicted in Fig. 15. Fig-ures 15�a� and 15�b� show the normalized link effi-ciency versus the lateral translation along the x andy axes, respectively. It can be observed that the tol-erance for a 10% drop from the maximum link effi-ciency can be larger than 100 �m. Figure 15�c�represents the tolerance of the top mirror in the zdirection, and the range of displacement correspond-ing to the 10% drop in link efficiency is much morethan 2 mm. The tilt of the top mirror is measured byuse of an autocollimator that illuminates a beam tothe backside of the mirror. The normalized link ef-ficiencies as the mirror is tilted along the x and y axesare shown in Figs. 15�d� and 15�e�, respectively. Thetolerance for the 10% drop in link efficiency is morethan 7 arc min. In comparison, the optical perfor-mance is more sensitive to the tilt than to the trans-lation in the three dimensions. This result alsovalidates our mechanic positioning of the top mirror,which can be adjusted for tilt along the lateral axesand translation in the longitudinal direction. Tilt ofthe mirror shifts the spot in the detector plane andcan be used to compensate for the lateral misalign-ment of the cubes, whereas translation of the topmirror can be used to compensate for the misalign-ment of the microlens.

7. Conclusion

In this paper we have presented a compact scalableoptoelectronic switching system with a high band-width. It combines the advantages of 3D chip stacksin smaller volume and with high-density powerfulprocessing capability of silicon and those of optics inglobal, high-speed parallel interconnections. Thedemonstrator requires several key technologies, in-cluding the monolithic integration of VCSELs andMSM detectors into a single array, 3D stacking ofsilicon chips, hybrid integration of the optoelectronicdevice array with the silicon chip stacks, optical sys-tem design, and system packaging. For the free-space optical interconnection, a novel folded hybridmicro–macro optical system has been designed. Thesystem can provide a high resolution, a large field ofview, a high link efficiency, and low optical cross talk.The system is also symmetric and modular. Off-the-shelf macro-optical components are used. By em-ployment of a concave reflection mirror, the imagequality can be significantly improved, and it toleratesa large misalignment of the microlens array. Thetop mirror can also compensate for the lateral shift ofthe chip stacks. The scaling of the macrolens can beused to adjust the interconnection length between thechip stacks or make the system more compact. Thecomponents are easy to align, and only passive align-ment is required. We show that by using commer-cially available optical components and simplepassive packaging techniques, it is possible to achieve

a high-performance optical interconnection system.An optoelectronic device array with a high density orlarger footprint area can be utilized and, correspond-ingly, the optical system can be redesigned. Ourfuture research includes characterization of the high-speed optical link and switching function.

The authors thank Mark M. Wang, ChristophBerger, and Xuezhe Zheng for helpful discussions.This effort is sponsored by the Defense AdvancedResearch Projects Agency and the U.S. Air Force Re-search Laboratory under agreement number F30602-97-2-0122.

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