SOC DESIGN METHODOLOGIES

IFIP - The International Federation for Information Processing

IFIP was founded in 1960 under the auspices of UNESCO, following the First World Computer Congress held in Paris the previous year. An umbrella organization for societies working in information processing, IFIP's aim is two-fold: to support information processing within its member countries and to encourage technology transfer to developing nations. As its mission statement clearly states,

IFIP's mission is to be the leading, truly international, apolitical organization which encourages and assists in the development, exploitation and application of information technology for the benefit of all people.

IFIP is a non-profitmaking organization, run almost solely by 2500 volunteers. It operates through a number of technical committees, which organize events and publications. IFIP's events range from an international congress to local seminars, but the most important are:

• The IFIP World Computer Congress, held every second year; • open conferences; • working conferences.

The flagship event is the IFIP World Computer Congress, at which both invited and contributed papers are presented. Contributed papers are rigorously refereed and the rejection rate is high.

As with the Congress, participation in the open conferences is open to all and papers may be invited or submitted. Again, submitted papers are stringently refereed.

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SOC DESIGN METHODOLOGIES

IFlP TC10/ WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on-Chip (VLSI-SOC'Ol) December 3-5, 2001, Montpellier, France

Edited by

Michel Robert Bruno Rouzeyre Christian Piguet Marie-lise Flottes Laboratoire d'lnformatique de Robotique et de Microelectronique de Montpellier (URMM) UMR CNRSjUniversite Montpellier /I France

. . , SPRINGER SCIENCE+BUSINESS MEDIA, LLC

L I R M

Library of Congress Cataloging-in-Publication Data

A C.I.P. Catalogue record for this book is available from the Library of Congress.

SOC Design Methodologies Edited by Michel Robert, Bruno Rouzeyre, Christian Piguet, Marie-Lise Flottes ISBN 978-1-4757-6530-4 ISBN 978-0-387-35597-9 (eBook) DOI 10.1007/978-0-387-35597-9

Copyright © 2002 by Springer Science+Business Media New York Originally published by Kluwer Academic Publishers in 2002

All rights reserved. No part of this work may be reproduced, stored in retrieval system, or transmitted in any form or by any means, electronic, mechanical, photo­copying, microfilming, recording, or otherwise, without written permission from the Publisher Springer Science+Business Media, LLC. with the exception of any material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work.

Printed on acid-free paper.

by IFIP International Federation for Information Processing

The original version of the book frontmatter was revised: The copyright line was incorrect. The Erratum to the book frontmatter is available at DOI: 10.1007/978-0-387-35597-9_40

Contents

Preface

Conference Committees

Architecture for Signal & Image Processing

Two ASIC for Low and Middle Levels of Real Time Image Processing P. Lamaty, B. Mazar, D. Demigny, L. Kessal, M. Karabemou

64 x 64 Pixels General Purpose Digital Vision Chip T. Komuro, M. Ishikawa

A Vision System on Chip for Industrial Control E. Senn, E. Martin

Fast Recursive Implementation of the Gaussian Filter D. Demigny, L. Kessal, 1. Pons

Dynamically Re-configurable Architectures

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3

15

27

39

A Dynamically Reconfigurable Architecture for Low-Power 51 Multimedia Terminals R. David, D. Chillet, S. Pillement, O. Sentieys

Dynamically Reconfigurable Architectures for Digital 63 Signal Processing Applications G. Sassatelli, L. Torres, P. Benoit, G. Cambon, M. Robert, 1. Galy

Reconfigurable Architecture Using High Speed FPGA 75 L. Kessal, R. Bourguiba, D. Demigny, N. Boudouani, M. Karabemou

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vi Contents

CAD Tools

Design Technology for Systems-on-Chip 87 R. Camposano, D. MacMillen

Distributed Collaborative Design over Cave2 Framework 97 L. S. Indrusiak, 1. Becker, M. Glesner, R. Reis

High Performance Java Hardware Engine and Software 109 Kernel for Embedded Systems M. H. Miki, M. Kimura, T. Onoye, I. Shirakawa

An Object-Oriented Methodology for Modeling the Precise 121 Behavior of Processor Architectures J. C. Otero, F. R. Wagner

Interconnect Capacitance Modelling in a VDSM CMOS Technology 133 D. Bernard, C. Landrault, P. Nouet

IP Design & Reuse

Abstract Communication Model and Automatic Interface generation for IP integration in Hardware/Software Co-design C. Araujo, E. Barros

An Evolutionary Approach for Pareto-optimal Configurations in SOC Platforms G. Ascia, V. Catania, M. Palesi

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157

Design of a Branch-Based Carry-Select Adder IP Portable 169 in 0.25 /lm Bulk and Silicon-On-Insulator CMOS Technologies A. Neve, D. Flandre

High Level Design Methodologies

A Standardized Co-simulation Backbone 181 B. A. De Mello, F. R. Wagner

Automatic Code-Transformation and Architecture Refinement 193 for Application-Specific Multiprocessor SoCs with Shared Memory S. Meftali, F. Gharsalli, F. Rousseau, A. A. Jerraya

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Contents

Power Issues

Modeling Power Dynamics for an Embedded DSP Processor Core. An Empirical Model c.B. Gebotys, R. Muresan

Power Consumption Model for the DSP OAK Processor P. Guitton-Ouhamou, C. Belleudy, M. Auguin

Design for Specific Constraints

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205

217

Integration of Robustness in the Design of a Cell 229 1.M. Dutertre, F.M. Roche, G. Cathebras

Impact of Technology Spreading on MEMS design Robustness 241 V. Beroulle, L. Latorre, M. Dardalhon, C. Oudea, G. Perez, F. Pressecq, P. Nouet

Architectures

A New Efficient VLSI Architecture for Full Search Block Matching Motion Estimation N. Roma, L. Sousa

253

Design Considerations of a Low-Complexity, Low-Power Integer 265 Turbo Decoder S. M. Pis uk, P. B. Wu

Low Power, Low Voltage

Low-Voltage Embedded-RAM Technology: Present and Future 277 K. Itoh, H. Mizuno

Low-Voltage 0,25 fJ.m CMOS Improved Power Adaptive Issue 289 Queue for Embedded Microprocessors B. Curran, M. Gifaldi, 1. Martin, A. Buyuktosunoglu, M. Margala, D. Albonesi

Gate Sizing for Low Power Design 301 P. Maurine, N. Azemard, D. Auvergne

Timing Issues

Modeling and Design of Asynchronous Priority Arbiters for On-Chip Communication Systems 1-B. Rigaud, 1. Quartana, L. Fesquet, M. Renaudin

Feasible Delay Bound Definition N. Azemard, M. Aline, P. Maurine, D. Auvergne

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325

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Advance in Mixed Signal

CMOS Mixed-signal Circuits Design on a Digital Array Using Minimum Transistors J. H. Choi, S. Bampi

A VHDL-AMS Case Study: The Incremental Design of an Efficient 3rd Generation MOS Model of a Deep Sub Micron Transistor C. Lallement, F. Pecheux, Y. Herve

Verification & Validation

Contents

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349

Speeding Up Verification ofRTL Designs by Computing 361 One-to-one Abstractions with Reduced Signal Widths P. Johannsen, R. Drechsler

Functional Test Generation using Constraint Logic Programming 375 Z. Zeng, M. Ciesielski, B. Rouzeyre

Test

An Industrial Approach to Core-Based System Chip Testing 389 E. J. Marinissen

Power-Constrained Test Scheduling for SoCs Under a "no session" 401 Scheme M-L. Flottes, J. Pouget, B. Rouzeyre

Random Adjacent Sequences: An Efficient Solution for Logic BIST 413 R. David, P. Girard, C. Landrault, S. Pravossoudovitch, A. Virazel

On-chip Generator of a Saw-Tooth Test Stimulus for ADC BIST 425 F. Azais, S. Bernard, Y. Bertrand, M. Renovell

Built-in Test of Analog Non-Linear Circuits in a SOC Environment 437 L. Carro, A. C. Nacul, D. Janner, M. Lubaszewski

Sensors

Design of a Fast CMOS APS Imager for High Speed Laser 449 Detections B. Casadei, }. P. Le Normand, Y. Hu, B. Cunin

Noise optimisation of a piezoresistive CMOS MEMS for magnetic 461 field sensing V. Beroulle, Y. Bertrand, L. Latorre, P. Nouet

Erratum to: SOC Design Methodologies E1 M. Robert, B. Rouzeyre, C. Piguet, M -L. Flottes

Authors Index 473

Keywords Index 475

Preface

The 11 th IFIP International Conference on Very Large Scale Integration, in Montpellier, France, December 3-5,2001, was a great success. The main focus was about IP Cores, Circuits and System Designs & Applications as well as SOC Design Methods and CAD. This book contains the best papers (39 among 70) that have been presented during the conference. Those papers deal with all aspects of importance for the design of the current and future integrated systems.

System on Chip (SOC) design is today a big challenge for designers, as a SOC may contain very different blocks, such as microcontrollers, DSPs, memories including embedded DRAM, analog, FPGA, RF front-ends for wireless communications and integrated sensors. The complete design of such chips, in very deep submicron technologies down to 0.13 mm, with several hundreds of millions of transistors, supplied at less than 1 Volt, is a very challenging task if design, verification, debug and industrial test are considered.

The microelectronic revolution is fascinating; 55 years ago, in late 1947, the transistor was invented, and everybody knows that it was by William Shockley, John Bardeen and Walter H. Brattein, Bell Telephone Laboratories, which received the Nobel Prize in Physics in 1956. Probably, everybody thinks that it was recognized immediately as a major invention. Not at all!. When Bell Telephone Laboratories announced the invention of the transistor on June 30, 1948, six months later, the general press was almost indifferently. The New-York Times carried the news on the next to the last page of the paper, with four short paragraphs. Even technical journals were slow to appreciate the inherent possibilities of the transistor.

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To stir enthusiasm for the device, Bell Laboratories licensed it freely in US and publicized it extensively in seminars and papers. A free license for the transistor! This means that nobody had understood what was such a device! Its direct concurrent was the vacuum tube, a strongly established commercial product. Engineers did not like transistors; they preferred tubes. The first market pull came from the hearing aids market, for which miniaturization was a must. The first transistorized hearing aid was announced by Sonotone in February 1953; it contained 5 transistors, but still required a pair of miniaturized tubes for the input and driver stages.

How the transistor was invented? Was such a device really needed? The answer is simple; the transistor had its origin in scientific theory rather than in technological developments. From the beginning of the last century, more and more studies have been performed on solid-state physics, metals and semiconductors. In 1935, a patent was issued to O. Heil for a field effect triode, although he was not able to explain how it worked. It is ironic that the concept of field effect transistors, so marvelously simple, provides practical implementations after the invention of the far more complex bipolar transistor. After the War World II, which interrupted many studies in semiconductor materials, new research programs have been decided. Bell Labs had such a program.

The Bell Labs group, including the three inventors of the transistor, decided to limit their research to germanium and silicium, the most simple semiconductors. The group believed that the only explanation for the continued lack of understanding of semiconductors - despite intensive world­wide research - was the diffuse experimentation on so many different complex materials. Silicon and germanium, on the other hand, were elemental, simple; moreover, their atomic structure had revealed the same strong covalent bounding as a diamond, and thus their crystals tended to be striking free of defects. This is a main point to realize working devices; keep them as simple as possible.

In 1958, it was the invention of the integrated circuit. So pressing was the need for fabricating entire circuits in a single semiconductor block that had neither Jack Kilby nor Robert Noyce conceived the integrated circuit in 1958, someone else surely would have done! The device was qualified "as the most significant development by Texas Instrument since ... the commercial silicon transistor". Also in 1958, the first field-effect transistor was working. It was called "Tecnitron" by its creator, S. Teszner, working in France. In 1962, RCA was fabricating multipurpose logic block comprising 16 MOS FETs on a single chip. By 1963, RCA had fabricated large arrays of

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Preface xi

several hundred MOS devices. They were however extremely sensitive to static charge, supply voltage was higher than those of bipolar transistors, and the speed was slower. Production was also plagued with oxide defects. In mid-1965, only two companies were producing MOS ICs - General Microelectronics and General Instruments - the other companies took a wait and see stance.

Everybody knows as the story continues: MOS technology, the first microprocessor in 1971, CISC machines, RISC microprocessors in 1981, superscalar and VLIW machines today, with a shift in CMOS technology in 1984-1985 with the 80386 and 68020. Today, the SIA Roadmappredicts in 2014 a 0.035 mm CMOS process (probably SOn with 19 billions of transistors for high-performance microprocessors, 0.6 Volt, 180 watts and more than 10 GHz as local frequency. There are today more transistors in the world (1017) than ants (1016).

However, what is the future of microelectronics? Are we close to the end of this marvelous story? Is the future belonging to nanotechnologies that could completely replace microelectronics (although 0.035 mm transistors have a 35 nanometers length)? Nano-devices have been constructed, capable of switching a current or single electrons with a ratio between the on/off current of 1 thousand to 1 million. Such elements could be promising as their sizes of some nanometers and extremely low or no power consumption are very attractive. Carbon nanotubes, quantum dots, single electron devices or molecular switches are the most promising nano-devices. For instance, a carbon nanotube has a diameter of 1 nanometer, and depending on its diameter, is a semiconductor device (otherwise, it is a conductor, not usable as a switch). However, if one over 10 nanotubes is semiconductor, how to select and interconnect the semiconductor ones to provide a useful logic function?

Quantum dots are based on the Coulomb blockade effect and electrons are moved one by one from dots to dots. They have been constructed atom by atom by atomic force microscope. Due to noise, it is better to construct cellular automata with several dots, and to define a given state of the automat as the logic "0" and another state as "I". Majority gates have been demonstrated, as well as AND/OR gates. The main problem is still how to interconnect these gates to provide useful functions. Furthermore, it is hard to construct atom by atom a complete chip with several billions of elements.

Design methods could be completely different from today, as nano­devices could be constructed randomly, without any predefined schematic or

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layout. However, a useful function could emerge from this huge number of nano-devices, or some auto-organization could occur. It is a little bit similar to natural selection for which only the useful functions will survive. But it will be hard to design a predefined and very complex function like a Pentium microprocessor.

It is very hard to make predictions, especially for the future (Mark Twain). However, the most probable future is that microelectronics will be used until perhaps 2020. Then it will be not replaced by nanoelectronics, but both technologies, i.e. microelectronics and nanoelectronics will co-exist with probably different applications.

It means that there are many opportunities for next editions of IFIP International Conferences on Very Large Scale Integration dedicated to microelectronics. We thank all people attending to the Montpellier edition and encourage everybody to attend the next edition in 2003 in Germany.

Prof. Christian Piguet CSEM & LAP-EPFL

Dr. Marie-Lise Flottes LIRMM

Prof. Bruno Rouzeyre LIRMM

Prof. Michel Robert LIRMM

xiv

Conference Committees

General Chair

Michel Robert, LIRMM, France

Program Co-Chairs

Christian Piguet, CSEM, Suisse

Bruno Rouzeyre, LIRMM, France

Local Organization Chair

Marie-Lise Floues, LIRMM, France

xiv Conference Committees

Technical Program Committee

Nadine Azemard, LIRMM, France Dominique Borrione, TIMA, France Maciej Ciesielski, University of Massachusetts, USA Luc Claesen, LCI-SMARTpen N.V. & K.U.Leuven, Belgium Claudionor Coelho, UFMG, Brazil Karl heins Diener, FhG IISIEAS, Germany Rolf Drechsler, Siemens, Germany Nikil Dutt, Univ. California Irvine, USA Hans Eveking, Darmstadt Univ. of Technology, Germany Joan Figueras, UPC, Spain Marie-lise Flottes, LIRMM, France Masahiro Fujita, University of Tokyo, Japan Patrick Girard, LIRMM, France Manfred Glesner, University Darmstadt, Germany Reiner Hartenstein, University of Kaiserslautern, Germany John Hayes, University of Michigan, USA Sybille Hellebrand, University of Innsbruck, Austria Jose luis Huertas, Univ. Sevilla, Spain Heinz Hugli, University of Neuchatel, Switzerland Paolo lenne, Swiss Federal Institute of Technology, Switzerland Andre Ivanov, University of British Columbia, Canada Ahmed Jerraya, TIMA, France Paul Jespers, Universite Catholique de Louvain, Belgium Lech Jozwiak Eindhoven, University of Technology, The Netherlands Luciano Lavagno, University of Udine, Italy Wolfgang Nebel, OFFIS, Germany Pascal Nouet, LIRMM, France Irith Pomeranz, Purdue University, U.S.A. Paolo Prinetto, Politecnico di Torino, Italy Ricardo Reis, UFRGS, Brazil Tsutomu Sasao Kyushu, Institute of Technology, Japan Donatella Sciuto, Politecnico di Milano, Italy L. miguel Silveira, Technical University of Lisbon, Portugal Lars Svensson, SwitchCore AB, Sweden Paulo Teixeira, 1ST - INESC-id, Portugal Flavio Wagner, UFRGS, Brazil Neil Weste, Radiata Communications, Australia Tom Williams, Synopsys, USA Hans-joachim Wunderlich, University of Stuttgart, Germany

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Conference Committees

Publicity:

Sponsors:

Plenary Sessions:

Finance:

Registration:

Proceedings & CD:

Social:

Technical Support:

Organizing Committee

N. Azemard-Crestani P. Maurine M. Robert D. Auvergne P. Girard M. Renovell L. Torres D. Deschacht G. Cathebrat L. Latorre V. Beroulle S. Bernard Y. Bertrand L. Latorre A. Virazel C. Landrault Y.Bonhomme P. Faure J. Galy B. Caillard J .M. Dutertre 1. Pouget

Technical Arrangement: G. Cambon I. Vogel

E-submission: P. Nouet

Web: G. Sassatelli F. Azals

Local Arrangement: D. Navarro M. Comte X. Michel V. Rahajandraibe

Conference Secretariat

C6line Berger LIRMM I Universit6 de Montpellier

161 rue Ada 34392 Cedex 5 Montpellier, France http://www.1irmm.fr

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Post-conference Volume Coordination

Laurent Latorre, LIRMM, France

Acknowledgements

This book is the result of the work of many dedicated volunteers: session organizers and moderators, invited lecturers, authors of papers and sponsors.

We thank them all for their contribution and particularly: D. Auvergne, F. Azals, G. Cambon, G. Cathebras, D. Deschacht, J. Galy, P. Georgelin, M. Johann, P. Kalla, A. Krasniewski, C. Landrault, P. Lepinay, A. Mischenko, M. Nahvi, J-L. Paillet, L. Pierre, L. Pozzi, G. Schmacher, E. Sicard, L. Torres, N. Van Der Meijs, M. Velev and Z. Zeng who helped in reviewing the papers.

On behalf of the program committee we thank the LIRMM laboratory (Laboratoire d'Informatique de Robotique et de Microelectronique de Montpellier) from the University of Montpellier and the CNRS (French National Scientific Research Center).

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SOC DESIGN METHODOLOGIES