On-Chip versus Off-Chip Passives Analysis in Radio and Mixed-Signal System-on-Package Design

Xinzhong Duo, Li-Rong Zheng, Mohammed Ismail*, Hannu Tenhunen

Laboratory of Electronics and Computer Systems, Royal Institute of Technology (KTH), Electrum 229, Kista-Stockholm, SE-16440, Sweden

Emails: duo|lrzheng|ismail|hannu@imit.kth.se * Spirea AB, Stockholm, Sweden

Abstract

Advances of VLSI and packaging technologies enable condensed integration of system level functions in a single module, known as SoC and SoP. In order to find a better solution between SoC and SoP, and eliminate constraints between chip and package, a complete solution is needed to co-design and co-optimize chip and package in a total design plan with precise trade-offs of on-chip versus off-chip passives. In this paper, we present a complete and systematic design methodology for RF SoP/SoC. This methodology includes early analysis and design implementation. This early analysis is to estimate the performance and cost of each solution quickly and quantitively. Then, the best solution is found and implemented. For a better presentation, the method and design techniques are demonstrated through the design of a common emitter low noise amplifier (LNA) for 5GHz wireless LAN (local area network). Analytical equations of noise figure and transducer gain for the LNA with lossy package are also developed.

1. Introduction During the last decade, wireless communication

market boomed rapidly. Wireless applications, such as cellular phones, wireless LAN and Bluetooth products, have taken the place of personal computer as a new growth point of electronics. To meet the critical requirements of cost, performance, compactness and power consumption of wireless products in next generation, electronic systems start to be capsulated into a single component, known as system-on-chip (SoC) and system-on-package (SoP) [ 1 , 2 , 3 ]. These trends are accelerated by deep submicron CMOS technologies as well as the emerging technologies of seamless electronic integration and packaging. At the semiconductor level, the continuing technology scaling will soon allow us to put not only giga-scale transistors on a single chip, but also integrate analog/RF and digital circuitry in the same chip, resulting in a mixed signal SoC. At the packaging level, elements (passives, chips) are tightly integrated by advanced packaging technologies, for example single level integrated packaging, resulting in miniaturized, mixed signal, heterogeneous integrated systems or SoP.

Many research works have been focused on SoC and SoP for wireless applications, such as Bluetooth in SoC with 0.25µm CMOS process [4] and wireless LAN front-ends in SoP with MCM-D [5,6] and LTCC [7,8].

However, it is still not clear that whether to choose SoC or SoP as the solution for a specific wireless application. Chip designers always believe that SoC is the

final destination of system level integration. At the same time, some research works show a contrary opinion that SoP could be a better solution, especially for RF and mixed-signal applications. To answer this question, Zheng [9] and Shen [10] gave a whole picture of system level partition and chip-package co-design methodology for SoP/SoC design in terms of cost and performance. In these works, on-chip versus off-chip passives trade-off is considered as one important step in RF SoP/SoC design.

High performance passives, such as inductors and capacitors, are always necessary in RF SoP/SoC. Typical quality factor of inductors embedded in package board is about 20-100, while that of their on-chip counterparts on Si substrate is only 2-12. In addition, on-chip inductors always occupy large chip estate and their sizes don’t scale down with technology. Cost of on-chip passives becomes higher and higher. Therefore, replacing on-chip passives with off-chip ones may significantly improve RF performance and reduce total implementation cost. However, an argument is that, when those passives stay off chip, parasitics from packaging interface (such as bonding wires, I/O pad) will be introduced, which may on the contrary degrade performance. Extra I/O pads to connect chips and passives also counteract the effort to reduce chip size. This is particularly true for small chips where chip size is dominated by I/O pads. In addition to these, most packaging technologies present larger process variations than IC technologies, which consequently cause variation of the circuits’ responses and degradation of robustness. If the variation exceeds certain threshold, these components cannot be used, thus reducing overall yield and increasing product costs. On-chip versus off-chip passives trade-off is to choose proper passives for RF SoP/SoC. Therefore, on-chip versus off-chip passives trade-off is a necessary and indispensable step in RF SoP/SoC design.

In this paper, we develop a design flow and models with cost and performance analysis for RF SoP/SoC. A complete and systematic analysis approach for on-chip versus off-chip passives is presented. In the following chapters, we first introduce the analysis flow of on-chip versus off-chip passives trade-off. Then, cost-performance models for SoP integration are presented. After that, an early analysis of performance and cost estimation for passives trade-offs is given. Finally, the best solution is found and implemented. This method can be implemented in RF/mixed-signal module widely. As an example, a low noise amplifier in SoP is analyzed to demonstrate this method. Analytical equations for gain

and noise figure of LNA with lossy package are developed. Finally, some design guidelines for the trade-off analysis are concluded.

2. Analysis Flow of Passives Trade-offs To find the best solution for a circuit, it is necessary to

analyze each possible solution for the circuit with passives trade-off analysis. In an RF circuit, there are numerous of passives. It is a large amount of work to find the best solution, if each possible solution is designed, simulated and compared. For example, in a circuit with N passive components, there could be 2N possible solutions. Therefore, it is necessary to perform an early analysis to find the best solution, and then this solution is implemented in design. This early analysis includes performance analysis and cost analysis. Performance analysis is to obtain quantitative overall performance of each solution, which consists of passives/package modeling and theoretical analysis for each solution. Cost analysis is to estimate chip/package area, yield, etc. and then, total cost of each solution. After the early analysis, a solution with the highest performance/cost ratio is found and then implemented in design. In the end, a more precise cost analysis is performed with the designed module. In the following sections, each step of the method is analyzed in detail. This method can be implemented widely in RF/mixed signal module design. In order to demonstrate this method, we design a common emitter LNA module for 5GHz WLAN. This module is analyzed and designed with 0.5µm SiGe BiCMOS and MCM technique. Off-chip passives are embedded in MCM substrates. Flip chip bonding is used for chip to substrate connections. Fig. 1(a) and (b) depict schematics of an LNA with all passives on-chip and an LNA with all passives off-chip, respectively.

Lin

Le

Vdd

Output

Vbias

Q1

Q2

Cµ

Cπ

Output

Lb

Le

Vdd

Vbias

Pad

Cπ

Cµ

Q1

Q2

(a) (b) Fig. 1 single ended common emitter LNAs (a) with all passives on chip, (b) with all passives off chip.

3. Performance Analysis Performance analysis is to estimate the overall

performance of each solution quantitively. It includes modeling and theoretical analysis. A. Modeling of Passives and Package

Models of on-chip transistors and passives are always provided by vendors. However, models of off-chip passives and package parasitics sometimes have to be developed by designers themselves.

i) Modeling of Off-Chip Passives PBM (physics based models) is chosen to model off-

chip passives in this work. Equivalent circuits of the components are modeled with their geometry parameters (such as wire widths, wire spaces), process parameters (such as thickness of interlayer dielectrics, conductor thickness) and material parameters (such as dielectric constant, resistivity of conductor). Then a library of the components is built up. Fig. 2 depicts models of some passives. As an example, the equivalent circuit of a spiral inductor in MCM substrates can be modeled as [11]:

)3

5.02(ln2l

twtw

llL +++

+= ( 1)

efftwlR

⋅⋅

=ρ ( 2)

)1( /δδ teff tt −−⋅= ( 3)

die

die

twnC ε

⋅⋅= 23

( 4)

where, l is the length of the wire, w is the width of the wire, δ is the skin depth of the metal, ρ is the resistivity of the metal. n is the number of overlaps between the inductor and its underpass. εdie is the permittivity of the dielectric layer between the metal layers and tdie is the thickness of the dielectric layer.

Fig. 2 Sketches and equivalent circuits of passives embedded in packaging board. (a) spiral inductor, (b) parallel plate capacitor, (c) thin film resistor

ii) Modeling of Packaging Parasitics Packaging parasitics always influence responses of

circuit significantly, especially in RF and high-speed digital circuits [12,13]. In design of SoP, parasitics of package must be considered.

Wire bonding and solder bonding are two of the most popular chip bonding techniques. Sketches of bonding wire and solder bump are shown in Fig. 3(a), and (b), respectively.

(a)

(b)

(c)

(a) (b) (c)

Fig. 3 Sketches of bonding wire (a) and solder bump (b), and their equivalent circuit(c)

Bonding wire Because of their convenient fabrication process,

bonding wires are implemented widely. In this work, bonding wires are first simulated with 3D EM (electro-magnetic) simulator--HFSS, and then PBM are extracted in terms of the heights and lengths of the bonding wires. The equivalent circuit of bonding wires and bonding pads are modeled as the circuit shown in Fig. 3(c) in terms of the heights, lengths, diameters of the bonding wires and the sizes of the bonding pads. Generally, parasitic inductance of a bonding wire could be roughly estimated as 1nH/mm.

Solder bump Solder bumps are preferred in RF and high-speed

digital systems because of their weak parasitics. Electrical responses of solder bumps are also simulated with HFSS, and then PBM are extracted in terms of the diameters and lengths of the solder bumps. The equivalent circuit of solder bumps is similar to that of bonding wires. Parameters in the equivalent circuit are based on the sizes and geometries of the solder bumps. B. Theoretical Analysis for Performance

To analyze trade-offs of on-chip versus off-chip passives theoretically, in the first step, overall performance of the circuit should be expressed as a function of its performance metrics, such as gain, noise, etc.:

...),,,,(

nconsumptiopowerlinearitygainnoiseFePerformanc =

( 5)

In this work, we use FoM (Figure of Merit) to describe the overall performance [ 14 ]. The following equations define FoMs of LNA (Low noise amplifier), VCO (voltage controlled oscillator), PA (power amplifier) and ADC (Analog-to-Digital Converter): FoM of LNA

( ) PNFfIIPGFOM LNA ⋅−

⋅⋅=

13

( 6)

FoM of VCO

PfLffFOM o

VCO )(1

2

∆

∆

=

( 7)

FoM of PA 2fPAEGPFoM outPA ⋅⋅⋅=

( 8) FoM of ADC

PERBWfFoM sampleENOB

ADC )2,min()2( 0 ××= ( 9)

where G power gain; IIP3 the input referenced third order interception

point; f the operating frequency, NF Noise Factor

fo the oscillator frequency of VCO, L(∆f) the phase noise power spectral density at

offset frequency ∆f from fo, P the total power consumption, Pout the output power of power amplifier, PAE power-added-efficiency, ERBW effective resolution bandwidth, fsample sample rate, ENOB0 effective number of bits of ADC. These formulas are only general standards. In special

applications, custom functions of overall performance could be used.

In the second step, performance metrics of each solution are derived and calculated through circuit theories. Parasitics of package must be included in analysis. Then, FoMs of each solution are obtained. C. Case Study

The LNAs depicted in Fig. 1 are analyzed in the following sections. Equivalent circuits of the LNAs are shown in Fig. 4. i) Theoretical Analysis of LNA with Passives On-chip

Equivalent circuit of the LNA is shown in Fig. 4(a). Input impedance Zin is given as:

ππ ω

ω

CjrgL

Cg

LLjrrRRZ

eme

m

beeblelbin

+++

+++++=1

)( ( 10)

where Le is the emitter inductance. Lb is the base inductance. Rlb and Rle are the resistances of Lb and Le, and are modeled as:

on

blb Q

LR ω= and on

ele Q

LR ω= ,

respectively. Qon is the quality factor of on-chip inductors. This is valid for narrow band analysis. rb is the base resistance of Q1. re is the emitter resistance of Q1, gm is the transconductance of Q1. Cπ is the base-emitter capacitance of Q1.

At the resonant frequency π

ωCLL eb )(

10 += , if

the input port is matched, we can get:

em

eblelbins LCgrrRRZRπ

++++== ( 11)

where Rs is the source impedance. At ω0 , transconductance of the LNA is given as:

)(0 eqlb

m

in

m

in

outm RRC

gv

vgvi

G+

=

==

π

π

ω ( 12)

wheree

mleebeq L

CgRrrRπ

+++=

At the output port, µω CLd 2

0

1= , where Cµ is the

collector-base capacitance of Q2. At the working frequency, impedance of the LC tank is:

CL

CLout QQ

QQC

Z+

=µω0

1 , where QL is the quality factor of

Ld, Qc is the quality factor of Cµ. When both input and output ports are matched at ω0,

Zin=Rs, Zout=RL, transducer gain of the LNA is expressed as:

sLm

L

Load

s

s

avs

LT RRG

RV

RV

PPG 2

41

2

2

4

4=== ( 13)

where PL is the power transported to the load, Pavs is the available power from the source ,

If noise contributions of the cascode transistors are neglected and perfect input-impedance matching is assumed, NF is written as:

20

20

2

000

42

211

+

+

++

++++=

TL

s

T

sm

T

sm

sm

s

leeblb

RRRg

RgRg

RRrrR

NF

ωω

ωω

ωω

ββ ( 14)

where β0 is the DC current gain of Q1.

Rs

Rlb''

Lb' Lbond rb

re

Rle

Le

CπCµ

LdRL

CpadGpadGpad Cpad Lbond

CpadGpad

Rs

Rlb Lb rb

Cπ

re

Rle

Le

RLLd

Cµ

Vin

Vπ

gmVπ

(a)

(b)

CpadGpad

Lbond

Fig. 4 Equivalent circuits of LNA with on-chip passives (a) and LNA with off-chip passives (b).

ii) Theoretical Analysis of LNA with Passives Off-chip

Based on the analysis of packaged LNA in [15], loss of package is appended in the analysis of LNA with only off-chip passives:

The equivalent circuit of the LNA is shown in Fig. 4 (b). The packaging parasitics are modeled with Cp and Lbond. In the following analysis, Lbond is absorbed in off-chip inductors. Q of off-chip passives is implemented in the following equations in stead of that of on-chip passives.

Input impedance of the LNA is:

)(1

πω CCjRZ

pinin ++′=′ ( 15)

whereexeqin RkRR +=′ 2 ,

22

222

)( p

peqpex CC

GRCGR

++

=π

π

ωω ,

pCCCk+

=π

π

To match the input port, the base inductance changes from Lb to Lb’

kLL bb =′ ( 16) Transconductance of the LNA with off-chip passives

is Gm’

kkGG mm ′=′ ( 17) where

2221)( eqlbin

eqlb

RCRR

RRk

πω++′

+=′

Capacitance and its quality factor at the output port are:

padL CCC +≈ µ ( 18)

µµ

µµ

QCQCCCQQ

Qpadpad

padpadC +

+≈′

)( ( 19)

Hence, the output impedance is obtained:

′+

′

+=′

CL

CL

padout

QQ

QQCC

Z)(

1

0 µω ( 20)

If the output port is matched, Zout’=RL’, the transducer gain of the LNA is

sLm

L

Load

s

s

avs

LT RRG

RV

RV

PPG ′′=

′

==′ 241

2

2

4

4 ( 21)

Including the contribution from lossy pads, Noise figure of the LNA with off-chip passives is given as:

20

20

2

000

42

2)(

1

′′

+

′′

+

′′+′′

+′′+++

+=′

TL

s

T

sm

T

sm

sm

s

leeblb

kRR

kRg

Rgk

kRg

RkRrrR

FN

ωω

ωω

ωω

ββ ( 22)

where )(2

2

πCCLGGRRk

pppk

++′+′=′′ ,

lbs RRR +=′

When loss from package is neglected, the results fit with those in [15] very well. iii) Analysis Results of Each Solution

With these formulas, gain, noise figure and FoM of the LNAs with each solution are calculated. The results are shown in Table. 1. In the calculation of FoM, IIP3 is not included. It is clear that the LNA with all passives off-chip has the best performance.

4. Cost Analysis

Cost analysis is to estimate the cost of each solution. Together with the results of performance analysis, the best solution of a SoP module could be found. A. Cost models for SoP Integration

Cost of a chip mainly attributes to its chip size, fabrication process, yield, wafer size, package, and testing cost. Total cost for a chip is given by

Table. 1 Performance metrics and FoM of LNAs with each solutions.(“on” means on-chip,“off” means off-chip)

Lb Le Ld NF(dB) GT(dB) FoM On On On 2.2 16.2 1 On On Off 2.2 19.2 2.0 On Off On 1.77 17.2 1.65 On Off Off 1.76 20.2 3.32 Off On On 1.89 17.5 1.83 Off On Off 1.89 20.5 3.25 Off Off On 1.47 18.6 2.85 Off Off Off 1.47 21.6 5.68

( )( )diewaferdiedR

wafer

AANYYmaskprocessrawC

Cchip ,,,

= ( 23)

which does not include a package for the chip, and for a SoP module by

aR

reworkassemblys

substratetest

N

chip

sop YY

CCY

CCCC

++++=∑

1 ( 24)

where Cwafer: the cost of processed wafer, it is a function

of raw substrate, fabrication process type, and mask layers;

Ndie : the number of chips per wafer, it is a function of wafer area and die area;

Cassembly : the cost of chip assembly; Csubstrate : the substrate cost per module; Crework : the cost of rework; N : the number of chips in the SoP, Yd, Ys, and Ya: yield of die, substrate, and assembly,

respectively; YR : the yield caused by distribution of

outcomes. As for chip yield—Yd, we used the model from [16] :

SNd

ASDY

)1(

1

0+= ( 25)

where 0D is the average density of electric defects, N is the number of mask layers in fabrication process, and A is the area of chip. S is the shape factor of (what is assumed to be) the Gamma distribution of electrical defect density.

The values of each cost element can be estimated in the following ways. i) Cost for Module Rework

It should be noticed that SoP may provide some rework capability. If one rework cycle is taken in a SoP, the yield of assembly can be improved from Ya to ,

aY , where 2, 2 aaa YYY −= . ii) Change of Chip Area

Assuming the original chip area Adie, total number of I/Os of this chip NIO, the core area of circuits in the chip Acir, after moving passives off chip, the new number of I/Os and the circuit area become

∑ −−+= CTETPTIOIO NNNNN 2' ( 26)

∑−= ocpcircir AAA ' ( 27) where NPT is the number of terminals in each passive component (e.g. 2 for a two-terminal inductor); NET is the total number of external terminals through which these passives connect to external circuits; and NCT is the total number of terminals through which these passives connected to each other internally.

Assuming the pitch of I/O is PIO, the new chip area (Adie’) can therefore be calculated by the following way:

If the chip I/Os are peripherally distributed and the chip area is circuit limited, i.e.

IOcirIO PAN '4'≤ , we have 2)2'(' IOcirdie PAA += ( 28)

If the chip I/Os are peripherally distributed and the chip area is I/O limited, i.e.

IOcirIO PAN '4'> , we have

2)4'(' IOIOdie PNA ×= ( 29) If the chip I/Os are area-array distributed and the chip

area is circuit limited, i.e. 2'' IOcirIO PAN ≤ , we have

'' cirdie AA = ( 30) If the chip I/Os are area-array distributed and the chip

area is I/O limited, i.e. 2'' IOcirIO PAN > , we have 2'' IOIOdie PNA ×= ( 31)

iii) New Cost of Packaging The extra cost of packaging caused by moving

passives off chip is measured by package substrate area, which is given by

'dieofppkg AAA +=∆ ∑ ( 32)

where ∆Apkg is the variation of package area, Aofp is the total area of these off-chip passives. iv) Testing Cost

Testing cost model from [17] is used in this work. This cost model accounts for the amortized cost of equipment, hardware and software maintenance, and tooling (test fixture and program), as well as burdened labor rates.

( )board

NNCCC

C testerboverheadequipmenttesting

×++= ( 33)

where Cequipment the cost of equipment, Coverhead overhead expense, Cb burdened labor per hour, Ntester the number of testers, Nboard the number of total boards tested per hour.

v) Impact of Process Variation on Product Yield The variations of geometrical, material and process

related parameter values during manufacturing introduce complex distributions and correlations of device outcomes. Monte Carlo method [18] is used to solve the problems. By defining a performance window (the allowable variation range of performance metrics), a final yield YR due to process variation is obtained. As a result, this increases total product cost by a ratio of 1/YR.

Table. 2 Parameters used for cost analysis in the LNA design

Parameters Value Defect density ( #/in2) 0.2 Shape factor 0.6 Wafer diameter 200mmProcess cost per mask layer $1000 MCM-D cost per unit area $3.0 /cm2

Cost of assembly per pin $0.01 Cost of rework $1 Yield of assembly 0.97 Contacted metal pitch (Pw ) 0.56µm MCM-D interconnection pitch(Pw) 20µm SiGe technology (BiCMOS) 0.5µm Total SiGe RF mask layers 16 Mask price for SiGe Technology $500 Cost of processed wafer of SiGe $16000 Cost of wafer bumping /wafer $200 Area array pad pitch (Pa ) 200µm Area array pad dimeter (Da) 100µm Volume 5K yield of robustness (MCM-D )(Ys) 0.976

B. Case Study of Cost Analysis Cost of each solution is analyzed with Eq.(24).

Process and cost parameters for the analysis are shown in Table. 2. It should be mentioned that these parameters can be different from one user to another, depending on technologies and supplies they have chosen. They have no more meanings than that the parameters are for demonstrating the above models and methods. Estimated area of chip /package, cost and relative performance-cost ratio are obtained and shown in Table. 3. In this cost estimation, Ctest is not included. YR can only be obtained after design of schematics.

5. Circuit Design and Implementation

After the early analysis, estimated overall performance and cost for each solution have been obtained. Thus, the best solution is chosen and final schematic and layout of the module is designed. Then, based on parameters of process variation, YR is obtained through Monte Carlo method. Finally, cost of the circuit is analyzed precisely with measured chip/package area and YR.

In the case study, it is clear that the LNA with all passives off-chip (off-chip solution) has the best performance/cost ratio. To demonstrate the analysis results, this solution and another solution with all passives on-chip (single-chip solution) are implemented, respectively. A. Design of LNAs

On chip parts

0.62mm

0.58mm

Off chip parts

inductor

inductor

capacitor

Outline of the chip

0.38mm

3mm

2.4mm

0.59mm

(a) (b) Fig. 5 Layout and photographs of LNAs with single chip solution (a), off-chips solution (b)

In the design, the CAD tools we use are Agilent-ADS

and Cadence. Agilent-ADS is a powerful tool for microwave system design, particularly its ability to simulate RF response of package level circuit with momentum method. In addition, this tool is very suitable for design of off-chip passives and packaging boards.

However, Agilent-ADS is not supported by many IC foundries. Cadence is a powerful tool for IC design and is well supported by most IC foundries. However, Cadence cannot model passives with EM simulation. Therefore, we combine the two CAD tools together to design RF SoP modules. Cadence is used to design on-chip circuit. Agilent-ADS is used to design off-chip components and packaging boards. The on-chip circuit is considered as a component in the whole circuit. Layout and photograph of the LNAs are shown in Fig. 5. The simulation results are shown in Fig. 6. Main results and FoM of both LNAs are list in Table.4. The simulation results fit with the calculation results quite well. The relative FoM of off-chip solution is much larger that one in early estimation. This is because IIP3 is not included in the early estimation.

4G 5G 6G

10

15

20

NF(dB)

Frequency(Hz)

Gai

n(dB

)2.0

2.4

2.8

3.2

3.6 with on-chip passives with off-chip passives

Fig. 6 Gain and Noise Figure of LNAs with all passives on-chip and off-chip

B. Post-Design Cost Analysis of LNAs YR is obtained through Monte Carlo method. Process

variation parameters are shown in Table. 5. The performance window of gain of the LNAs is defined as

Table. 5 Process variation parameters of on-chip and off-chip passives used in Monte Carlo analysis

Off-chip Mean value(deviation)

On-chip Mean value(deviation)

Conductor Width(µm) 50(0.5) 10 (0.1) Space(µm) 30(0.5) 3 (0.1) Thickness(µm) 3 (0.2) 2 (0.05) Conductivity(1/Ωm) 4.5×107 3.5×107 Dielectric Thickness(µm)∗ 2.5(1.25) 2(0.05) Permittivity 2.6(0.05) 4.1(0.1) The mean values and the estimated deviation of the parameters of the technologies. The data are shown as: mean value (deviation)

Table. 3 Estimated area of chip/package, cost, and relative FoM/cost ratio of LNAs with each solution

Area(mm2) Lb Le Ld chip package

Npad CostCostFoM

On On On 0.33 0.36 4 1 1 On On Off 0.21 1.44 4 0.89 2.25On Off On 0.33 0.52 5 1.07 1.54On Off Off 0.21 1.58 5 0.98 3.39Off On On 0.21 1.46 4 0.89 2.06Off On Off 0.16 2.6 4 1.09 2.98Off Off On 0.21 1.58 4 0.97 2.94Off Off Off 0.16 2.7 4 1.17 4.86

Table. 4 Simulated Performance metrics of LNAs with single chip solution and off-chip solution.

Gain(dB) NF(dB) IIP3(dBm) Power(mW) FOMOn 15.6 2.98 1.2 11.25 1 Off 22.8 2.21 7.8 11.25 35.6

Gainmax-1<Gain<Gainmax+1 dB, where Gainmax of LNA with off-chip solution and single-chip solution are 22.8dB and 15.6dB, respectively.

The area of the chip and package is measured from the layout directly. For other parameters, we still use those in Table. 2. Finally, cost of these two solutions is obtained. The cost and performance of the two solutions are presented in Table. 6. Cost analysis results show that the off-chip solution costs 2% more than the single-chip solution. This is because in simple circuits (like that in Fig. 1), the bonding pads for off-chip passives occupy relatively large chip real estate. For example, in single-chip solution, pads occupy 50% of the whole chip, while in off-chip solution, pads occupy over 90%. Consequently, the total implementation costs, which include chip and package, are high. In complex circuits, both cost and performance benefit could be achieved [19]. The results indicate that small RF chips should be merged as a larger one and the integration density of each RF chip should be reasonably high enough.

6. Conclusions

In this paper, we demonstrate a design methodology and analysis techniques for cost-performance analysis and present a systematic and complete picture for on-chip versus off-chip passives trade-off. A detailed analysis for LNA is given as a case study of this method. Analytical equations of gain and noise figure for LNA with lossy package are deduced as well. This method can also be implemented in other RF/mixed module design.

In this paper, it is found that performance of RF modules may often be improved by moving low quality on-chip passives (particular inductors) off chip. However, cost benefits are still a question if the RF chips are too small. In order to obtain cost benefits in RF-SoPs, it is suggested that small RF chips should be merged as a larger chip and the integration density of each RF chip should be high enough. This, however, is emerging the case in multi-band, multi-standard radio chips for future wireless generations, i.e. 3G and beyond.

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Table. 6 Summaries of cost-performance analysis for the LNA design

Off-chip solution Single-chip solutionPackage 1 mm2 0.4 mm2 Area

(mm2) Chip 0.22 mm2 0.37 mm2

YR 0.93 0.97 Relative cost 1.02 1 Relative FoM 35.6 1