IMAPS Advancing Microelectronics, Vol. 47, No. 5 - Allen Press

September/October Vol. 47 No. 5

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Challenges in Fine Feature Solder Paste...

Solder Paste for SiP...

Thermal Materials for Packaging Power...

Advanced MaterialsAdvanced Materials

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S E P T E M B E R / O CT O B E R 2 0 2 0

Features

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On the Cover: Solder Paste Processing for SiP

Challenges in Fine Feature Solder

Paste Printing for SiP ApplicationsSze Pei Lim,

Kenneth Thum, and Dr. Andy C. Mackie

Solder Paste for SiP Printing of the Future

Contact: Li-San Chan

Thermal Materials for Packaging Power

ElectronicsSanjay Misra

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A D V A N C I N GMICROELECTRONICS

C O N T E N T S

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INSIDE BACK COVERCalendar of Events

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S E P T E M B E R / O C T O B E R 2 0 2 0

U P C O M I N G E V E N T SExecutive CouncilPresident Richard Rice ASE US, Inc.President-Elect Beth Keser Intel CorporationFirst Past President Ron HuemoellerVice President of Technology Jon G Aday Illumina, Inc.Vice President of Marketing Adrienne Gerard Finetech, Inc.Secretary Daniel Krueger HoneywellTreasurer Michael Gervais Geib Refining Corporation

Directors Erica C Folk Northrop Grumman Mission Systems Prof Douglas C Hopkins, Ph.D. NCSU Packaging Research in Electronic Energy Systems (PREES) Dr. Ivan Ndip Fraunhofer Institute for Reliability and Microintegration IZM Urmi Ray Consultant Curtis Zwenger Amkor Technology

Ex-Officio (Executive Director) Michael O’Donoghue, IMAPS

Publications CommitteeEditor, Journal of Microelectronics and Electronic Packaging John Pan, Cal Poly State UniversityManaging Editor Advancing Microelectronics Michael O’Donoghue

StaffDirector of Programs Brian Schieman

Advancing Microelectronics (formerly Inside ISHM) is published six times a year and is a benefit of IMAPS membership. The annual subscription price is $95; $15 for a single copy. Copyright 2020 by IMAPS—International Microelectronics Assembly and Packaging Society. All rights reserved. Except as defined in 17 USC, Sec. 107, permission to republish any materials in this publication must be obtained from IMAPS, PO Box 110127, Alexander Business Suites, 68 TW Alexander Drive, Research Triangle Park, NC 27709. Telephone +1-919-293-5000.

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International Conference and Exhibition on Advanced System-in-Package (SiP) TechnologyJune 22-24, 2021

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F R O M T H E G U E S T E D I T O R

Sanjay MisraHenkel Corporation

Two major trends driving the evolution of electronics packaging are advances in Communication Technology and Industry 4.0. The advent of 5G allows user con-nectivity experience to be an order of magnitude higher than current capacity. Increased connectivity also al-lows for increased automation: connected machines and factories that can be managed and controlled re-motely. To achieve their full potential, these trends re-quire electronics packaging that integrates more func-tions in smaller packages as well as allowing for better thermal management for both logic and power devices. The driving trends are only going to be accelerated by Covid-19 driven remote work and reduced density in factories and workplace.

This issue of Advancing Microelectronics includes three timely papers covering technologies that enable the trend to further miniaturization of complex systems, or System in Package (SiP), as well as thermal dissipa-tion to keep the electronics functioning reliably.

The first paper, from Indium Corporation, “Challenges in Fine Feature Solder Paste Printing for SiP Applica-tions,” addresses the challenge of high functional-ity packages with very fine pitch pads — as close as 50 µm. The paper explores how the selection of paste composition and stencil process can address the chal-lenges with bridging.

The second paper, from Heraeus, “Solder Paste for SiP Printing of the Future,” further builds on the theme of solder pastes for packaging. The paper explores in-terconnect solutions that allow for both flip chips with copper pillars as well as surface mount devices in a sin-gle step. This considerably reduces process complexity.

The final paper, from Henkel, “Thermal Materials for Packaging Power Electronics,” addresses the problem of thermal management. With a variety of packaging solutions, there is a need for a broad set of materials solutions. This paper addresses the different thermal materials available on the market as well as their suit-ability for application.

In these uncertain times, professionals across the board are challenged with new realities. Thus the con-tributions in forums like this, to communicate and col-laborate, are of great value. I would like to thank the authors for their effort to prepare these timely and ex-cellent contributions to this online edition.

Sanjay MisraSenior Scientific PrincipalHenkel Corporation18930 W 78th Street, Chanhassen, MN 55317Office: +1.612.552.5415/Mobile: [email protected]

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F E AT U R E A R T I C L E

hallenges in Fine Feature Solder Paste Printing for SiP ApplicationsSze Pei Lim, Kenneth Thum, and Dr. Andy C. Mackie Indium Corporation

C

IntroductionSystem-in-Package (SiP) heterogeneous integration

enables increased functionality in a single package, and is a popular packaging approach that is driven by faster time to market and lower cost as the demand of IoT (wear-ables) surges. Decreased component size and thickness, with embedded passives and smaller boards, continue to push miniaturization to another level. Currently, the use of 01005 passives is the norm in some SiP applications, and the packaging industry is looking at 008004 passives (which is about half the size of 01005) in the near future. Table 1 provides a summary of the size of the passives.

In addition to smaller passives, the gap between neighboring pads is also shrinking in order to pack more components into a single SiP. This gap can be as close as 50µm. Hence, it is very crucial to have a well-controlled and consistent solder paste printing process in order to achieve good manufacturing yields. To overcome this challenging requirement, the selection of correct solder paste, solder powder size, appropriate

AbstractThe rapid development in the Internet of Things (IoT) has seen a surge in demand for System-in-Package (SiP), which is capable of packing more functionality into a single package with a small form factor. This continues to push miniaturization to an even greater level, therefore creating assemblies with smaller com-ponents and greater density. Most of the current SiP technology is using 01005 passive components and the industry is looking at uti-lizing 008004 passive components for the next gen-eration SiP. The stencil aperture design for 008004 will likely be about half of 01005, and a finer pow-der size solder paste will be used. The stencil design, stencil thickness, and the types of stencils being used are crucial in achieving good solder paste printing performance. Due to the need of squeezing more components into a SiP, the gap between neighboring pads can be as close as 50µm; hence, it is crucial to avoid solder bridging for such applications. This pa-per will discuss the challenges in achieving consistent solder paste printing performance for fine feature ap-plications using Type 6 (5–15µm) powder size solder paste. Test results with different stencil designs, print-ing parameters, and different solder pastes will be discussed in detail.Keywords: 008004, IoT, SiP, solder paste, printing

Table 1. Size of capacitor.

stencil design/opening, stencil thickness, and printing parameters becomes very important. These factors will be discussed in detail in this paper.

Solder Powder SizeTable 2 outlines the different solder powder sizes

available in the industry. For most current PCBA ap-plications, solder paste with powder sizes Type 3 and

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continued on page 8

Type 4 are being used. As miniaturization continues to drive smaller stencil apertures, smaller powder sizes Type 5 and Type 6 are becoming more common. Cur-rently, some are already using powder size Type 6 for SiP with 01005, and for next generation packages with 008004, both Type 6 and Type 7 powder sizes are be-ing considered. Figure 1 shows the SEM pictures of powder sizes Type 5, 6, and 7.

It is a general industry guideline that in order to achieve consistent solder paste printing performance, it is important to choose the correct powder size so that a minimum of 5 to 6 solder particles (the large particle size of the range) can be maintained across the aper-ture. According to this rule, the recommended mini-mum stencil aperture for each powder type is shown in Table 2.

Stencil Area RatioBesides choosing the correct powder size for each

application, another essential component is the stencil aperture area ratio [1]. Calculating the area ratio and choosing the correct powder size can assist in proper

Table 2. Powder sizes.

Figure 2. Area ratio calculation.

Figure 1. Type 5, Type 6, and Type 7 powder SEM images.

Table 3. Area ratio for typical stencil aperture.

solder paste-stencil release. The area ratio is the ratio between the area of the aperture opening and the area of the aperture walls. Refer to Figure 2 for details of area ratio calculations. Area ratio of ≥0.66 is recommended for all stencil apertures.

Table 3 summarizes some of the area ratios for typical stencil apertures being used for 01005 and 008004. As shown in the table, choosing the correct stencil thickness and aperture size are important in order to achieve a rea-sonable area ratio for good printing performance.

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Solder Paste Rheology As the diameter of the metal powder shrinks to reduce

variability in the final solder volume, it is possible to esti-mate the particle size needed based on the desired solder volume variability [2]. Decreasing the particle size of the paste also increases the viscosity, since the flux vehicle it-self is thixotropic. The solder paste used in stencil printing is a shear-thinning thixotropic material [3] with a low yield stress, with the rheology being governed by both the flux and the solder powder.

The metal content of the paste is typically around 50% by volume—the level at which particle-particle interactions begin to significantly affect the rheology of the solder paste. This is useful in that a higher metal load can prevent solder spread (sometimes caused by slumping) of the solder paste and reduce voiding after reflow. However, it also makes the paste very susceptible to the loss of solvents by evapora-tion, leading to variability in printing. Note that the term “slump” is an x-y direction expansion of the solder paste deposit caused by gravity. A yield stress in the paste can prevent slump. Too high a metal load can give the paste a very high yield stress and prevent the paste from filling and releasing from stencil apertures. Therefore, optimizing the metal load for the printing process is important and is driven by several factors.

The paste rheology controls three key elements of the printing process (refer to Figure 3):

• aperture filling• stencil release• spreadWork on ultrafine pitch printing of solder paste has

shown that one of the primary failure modes in spread is flux leakage under the stencil during printing. The stencil cannot form a perfect gasket with the underly-ing substrate and the flux component of the paste can flow under the stencil. When the paste releases from the stencil, the fluid can carry solder particles with it, leading to spread.

The release of solder paste from a stencil is some-where within a boundary layer of paste adjacent to the wall of the aperture (Figure 4). The situation in B is most commonly seen, but for finer pitch apertures, A is pre-ferred, which is usually achieved by using high metal loading. In A, the paste has sufficient “tack” (adhesion normal to the substrate) that when the stencil releases, the paste slides out on a film of flux (with the high met-al loading locking the particles together), rather than cleaving inside the bulk of the paste (as in B). The high metal loading also limits the flux leakage, so not only is a complete deposit made, it also does not spread.

Note that over time, solvent evaporates from the flux, so metal loading increases may also speed the rate at which the print quality moves from A to C (little or no re-lease from the stencil). This means that flux formulation also plays a role in the stencil life of the paste.

Solder Paste Printing ExperimentSolder Paste Samples

A printing test was carried out using four different types of T6SG solder pastes, as shown in Table 4. Two of the pastes were mixed with no-clean flux chemis-tries, including an ultra-low residue formula designed for SiP applications, while the other two contained wa-ter-soluble flux chemistries. The solder paste samples have different metal loads because the flux chemistries have different rheological characteristics.

continued from page 7

Figure 3. Key steps in printing solder paste.

Figure 4. Effect of rheology on deposit shape and size.

Table 4. Solder paste samples.

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continued on page 10

Test VehicleA test vehicle was specially designed to mimic a typi-

cal substrate size: 237mm in length, 62mm in width, and 0.5mm thick (Figure 5). It consists of two arrays of print patterns. Each array consists of five columns of print patterns with different gap distances between components, and three rows of different aperture sizes. Pads are arranged in horizontal and vertical positions so that different squeegee wiping directions could be simulated. The pad surface finishing is NiAu (ENIG) and is non-solder mask defined (NSMD). The test vehicle also consists of 01005 pads, but it is not the focus of this study.

Test MethodologyThe stencil used was a laser-cut stencil which has

a relatively rougher wall surface compared to electro-formed stencils. A 60°, 12” squeegee was used in this test. Test vehicles were loaded onto a carrier to provide stiffness during printing. In this printing simulation, a total of 10 strips were printed with each solder paste using the respective optimized printer parameters. Each solder paste required different settings of print-ing speed and pressure to achieve a clean wipe on the stencil surface. The solder paste volume of 10 printed strips was then collected through an SPI machine.Printing Test Results and Discussion

As shown in Figure 8, it is clear that paste D stands out among the four solder paste candidates. Printing of the area ratio down to 0.60 is possible by using the correct rheology, even with a laser-cut stencil. Paste D demonstrates a tight distribution down to 100µm x 150µm aperture size (0.60AR). Paste A is a water-soluble chemistry paste and also performs relatively well in this study. Table 5 shows the Cpk and Ppk of Paste D with a calculation spec of 40% minimum and 150% maximum.

Figure 5. SiP test vehicle.

Figure 6. Print patterns in an array.

Figure 7. “D” is the gap distance between components.

Several aperture sizes were selected in this test to compare the printing volume vs. different area ratios: 125µm x 150µm, 112.5µm x 150µm, and 100µm x 150µm (Figure 6). A laser-cut stencil thickness of 50µm was fabricated in this test, hence yielding area ratios of 0.68, 0.64, and 0.60 for different aperture sizes as shown in Table 3. The 0.68 area ratio pad is expected to be able to print better than other smaller pads with area ratios of 0.64 and 0.60.

Varying gap distances between components are il-lustrated in Figure 7. The gap distances tested were 50µm, 80µm, 100µm, 130µm, and 150µm.

Figure 8. Boxplot of volume vs. aspect ratio vs. solder paste.

Table 5. Cpk of Paste D vs. different area ratios.

All solder pastes encountered paste bridging in 50µm gap distance columns. However, the 80µm gap distance columns show very encouraging results with no solder bridging, despite the tooling combination not being perfect. An electroformed stencil might be able to improve printing in the 50µm gap distance columns; this would be included in future studies.

Using Paste D as an example, it was also observed that with an increasing gap distance between pads, the paste volume also increased, as shown in Figure 9. All solder paste behaves similarly in this observation. This

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could be due to solder starving when the solder paste rolls across the area with a tight gap distance. These denser areas consume more volume and paste can’t re-plenish its position in time when rolling across the sten-cil. Also, a wider gap distance between pads will have thicker and stiffer foil in between apertures. This could affect the paste release mechanism, as well.

In order to further study how viscosity and rheology affect printing performance, a solder paste sample was prepared using flux chemistry D with 0.5% lesser metal load. A lesser metal load will result in lower viscosity. The result is shown in Figure 10 using a comparison be-tween 91% and 90.5% metal loads of flux chemistry D.

A two-sample T-test was performed. It revealed that this slight change in metal load yields statistically sig-nificant differences in printing performance. The 90.5% sample printing has a higher mean volume and tighter distribution compared to the 91%ml sample. Conclusion

In order to achieve consistently good fine feature printing performance for SiP applications, many param-eters play an important role and need to be selected appropriately. Solder paste with suitable rheology, mixed with the correct powder size and flux, should be evaluated and selected accordingly. Stencil apertures


Figure 9. Paste D boxplot of volume % vs. gap distance.

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Figure 10. Comparison of 91%ml and 90.5%ml.

with suitable area ratios, which will maximize the sol-der paste transfer efficiency from stencil to substrate, should be considered, as well. More printing tests will be done in the near future for comparing laser-cut sten-cils to electroformed stencils, different stencil thickness-es, and aperture designs. Acknowledgment

Special thanks to Indium Corporation’s Suzhou Simu-lation Lab team—Ms. Wisdom Qu, Dr. Fiona Chen, and Leon Rao—for their help and support in performing the solder paste printing test in their lab. References1. Indium Corporation Application Note, “Powder Choice Stencil

Design Guidelines.”2. Lim, Thum and Mackie, “Meeting Solder Paste Printing

Challenges for SiP in ‘Smart’ IoT Devices,” Chip Scale Review magazine, Jul–Aug 2016.

3. Kravcik and Vehec, “Study of the Rheological Behavior of Solder Pastes,” Proc. Scientific Conference of Young Researchers 2010, FEI TU of Kovice.

4. Durairaj, Mallik, Seman, Marks and Ekere, “Effect of Wall Slip Effect on Paste Release Characteristic in Flip-Chip Stencil Printing Process,” 10th Electronics Packaging Technology Conference, 2008 G. O. Young, “Synthetic structure of industrial plastics,” in Plastics, 2nd ed. vol. 3, J. Peters, Ed. New York: McGraw-Hill, 1964, pp. 15–64.

First presented at IMAPS 2016, October 12, 2016, Pasadena, California, USA.

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older Paste for SiP Printing of the FutureContact: Li-San Chan, Head of Advanced Packaging Market Segment, Heraeus Electronics [email protected]

S

Electronic devices such as smartphones, tablets or high-end laptops must perform greater tasks and should be as portable and compact as possible. To en-able more functions in a smaller space, System in Pack-age (SiP) technology combines multiple semiconductor chips and many passive components together into a tiny module. This is a challenge for production, as com-plex and numerous steps are necessary to complete the assembly of such SiPs. The result: longer production times, lower capacities and higher costs. With Welco AP5112 Type 7, Heraeus Electronics offers a unique solder paste where passive components and flip-chips with copper-pillars can be assembled simultaneously – while lowering solder defects, and increasing efficiency and quality in production.

“Flip-chip technology plays an important role in the production of modern microelectronics. “More than Moore” concept leverages on flip-chips technology; to

combine a large number of functions in a very small space,” says Li-San Chan, Head of Advanced Pack-aging Market Segment at Heraeus Electronics. “How-ever, the assembly process for SiPs, multiple flip-chips packages require higher complexity process steps to ensure good yield. One example: flux for assembling the flip chip copper column pads and the solder paste for mounting the passive components previously had to be applied in several steps. This is time-consuming and requires additional investments in production ca-pacities and printing stencils. In addition, there could be flip-chips with varying die and Cu pillar sizes in the same package that give co-planarity and open joints challenges. With Welco AP5112 T7, we now offer the industry a convenient and efficient solution.” (Fig. 1) The innovative solder paste from Heraeus Electronics

• simplifies SiP production considerably• significantly reduces flip-chips open-joints defects • helps to eliminate tombstones defects• creates more flexibility for users

Figure 1: Printing in one step: The solder paste Welco AP5112 T7 from Heraeus Electronics is a combination of the flux platform Welco AP5112 and the ultra-fine alloy powder SAC305 type 7. The material can be used to solder both passive components and flip chip Cu pillars assembly. Microelectronics manufacturers can thus save one process step

in SiP production – for higher throughput times and greater efficiency.

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continued on page 14

All-in-One Printing for Cu Pillar Contacts and Passive Components

For Welco AP5112 T7, Heraeus Electronics is us-ing its water-soluble halogen-free AP5112 flux plat-form and combining it with Welco SAC305 Type 7 al-loy powder. With its unique rheology, AP5112 offers excellent printing properties and enables the printing of extremely fine solder dots. Welco Type 7 powder SAC305 is characterized by its perfectly spherical pow-der particles and highly uniform particle size. More than 80 percent of the particles are in the range between 2~11 micrometers – it is highly suited for applications that require ultra-fine pitch. During the reflow process, low oxide surfaces of Welco powder ensure optimum metal coalescence and reliable bonding of the metals.

In combination with both flux and powder, the new Welco AP5112 T7 solder paste achieves printing of flip chip and passive components’ pads in one single step. We can call this technique “All-in-One Printing.” It enables packaging houses and/or OSATs to save a complete process step while achieving extremely fine printing with stencil openings at 70 micrometers and spacing at 50 micrometers – ideal for the vast majority of SiP Cu pillar flip-chips (Fig. 2). “A further advantage:

Welco AP5112 T7 has no splattering. An innovative-ly selected organic component was added to create AP5112 flux platform,” explains Li-San Chan. “With its unique, proprietary flux chemistry Welco AP5112 T7 does not splatter during fast reflow temperature ramps, thus helping to avoid solder beads.”Perfect Distancing (Not Social Distancing!), No Voids – For Perfect Solder Contacts

Just how powerful the new solder paste is, is demon-strated by Heraeus Electronics materials experts via a series of comprehensive tests.

“In one of our tests, we assembled a flip-chip and passive component 008004 onto a substrate, and af-ter the reflow process we examined the solder points in detail,” says Li-San Chan.

The X-ray images show (Fig. 3): The solder joints of the Cu pillar and the passive component are very dense and have only minimal voids of less than one percent. This makes Welco AP5112 T7 the best in class mate-rial for void performance. The innovative solder paste also offers outstanding performance in terms of line spacing and bridging. No solder bridging is found even at very fine pitch.

Figure 2: Fine solder dots for advanced technology: With its unique properties, Welco AP5112 T7 enables high-quality

print results with very small stencil apertures from 70 micrometers and distances from 50 micrometers – ideal for

SiP modules with high packaging density.Figure 3: Reliable contacts, no voids: The x-ray image of

the copper pillar pads from Heraeus Electronics’ test series shows the excellent performance of Welco AP5112 T7

with reliable solder joints and no bridging.

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In the test series, very uniform solder bumps are achieved for Cu pillars as well as for the passive com-ponent 008004 (Fig. 4). The experts from Heraeus Electronics repeated the tests with different stencil openings of 80 to 100 percent against the pad size. The solder height can be controlled very precisely. This allows users to effectively eliminate tombstones – and achieve greater reliability of the soldering joint.Stable Viscosity over 72 Hours – For Flexible Processing

The benefits do not stop here; Welco AP5112 T7 of-fers processing advantages. “Long pot life and stencil life are basic requirements for the industry. The lon-ger printing paste can be processed, the more flexible the processes can be planned,” says Li-San Chan. “To simulate a processing operation, we exposed Welco AP5112 T7 paste in a laboratory environment and measured its viscosity over 72 hours. The results show that the solder material is extremely stable over this long period (Fig. 5). In another test, we examined the viscosity during the printing process.”

For this test, solder dots were printed onto a gold-plated substrate with a DEK stencil printer over several hours and the diameters of the dots were examined. Even after eight hours (typically equivalent to one oper-ator shift in an OSAT), the dots with Welco AP5112 T7 showed very uniform diameter (Fig. 6). Welco AP5112

Figure 5: Excellent pot life over three days: Flexibility in queue time is an important factor in the industry. With a stable viscosity, Welco AP5112 T7 can be optimally processed within 72 hours – for maximum flexibility in

production planning and minimum material waste.

Figure 6: Highly stable viscosity during printing: During the test, Heraeus Electronics printed dots with Welco AP5112 T7 for over eight hours and measured the diameters. The dots showed very uniform diameters over the entire test

period – for a precise print image over 8 hours.

Figure 4: Optimum height control: The solder bumps with Welco AP5112 T7 of the passive component show very uniform solder heights in the test series at Heraeus

Electronics – even with different stencil openings from 80 to 100 percent. Electronics manufacturers can thus effectively

avoid production defects such as tombstones.

T7 retains its rheological behavior over this period. The solder bumps obtain a uniform height after reflow. In addition, the optimized flowability allows flip chips to be fixed more precisely and prevents the components from misalignment and open-joints – for fewer defects and rejects.

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Welco AP5112 T7 – The solder paste high-end technologyIn the new solder paste Welco AP5112 T7, Heraeus Electronics combines the properties of its Welco

AP5112 flux platform and its SAC305 Type 7 ultra-fine alloy powder, which means that this unique material offers many advantages in the manufacture of SiP modules:Simplify processes, increase efficiency

• All-in-one printing for flip chip and SMD pads – for shorter production times and higher yield• Savings on additional tools such as printing plates and production capacity

Higher quality, more demanding applications • Realization of the finest printing structures with stencil openings from 70 micrometers and

distances from 50 micrometers• Leading in void performance thanks to the superior quality of Welco solder powder – for reliable

solder joints• No splashing and no solder beads, even during reflow at higher temperatures • No tombstones and solder bridges thanks to permanently stable rheology

More flexibility in production• Stable viscosity with a pot life of over 72 hours• Uniform solder volume over 8 hours of continuous printing

Quality and Efficiency for the Microelectronics of the Future

With its unique features, Welco AP5112 T7 offers semiconductor packaging houses an easy way to sig-nificantly simplify production processes in the manufac-ture of SiP modules and increase efficiency.

“The demand for miniaturization of semiconduc-tors and higher packaging density of SiP modules will continue to increase in the future,” says Li-San Chan. “Miniaturization remains a distinctive competitive fac-tor. With Welco AP5112 T7, Heraeus Electronics of-fers a unique material to allow production of complex electronic components more efficient, to achieve higher quality – and to meet the production requirements of tomorrow.”

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hermal Materials for Packaging Power ElectronicsSanjay Misra, Henkel Adhesive Technologies, Chanhassen, MN 55317

TIntroduction

Thermal management of power electronics, whether power supplies or power components, requires interfacing the package to a heat sink using a thermal interface material (TIM). Traditionally used thermal greases provide good end-of-line performance but they can degrade. Several alternatives and advances have now expanded that choice to a wide variety of product families. TIMs come in a wide variety of properties, physical formats and automation readiness to suit the wide variety of applications. Additionally, TIMs may be tasked with insulation reliability, adhe-sion, and encapsulation. Typical Thermal Challenge

A typical thermal stack up has several resistances in series. The effective thermal bond line can be quite signifi-cant given the size and warpage of the assembly. The thermal resistance of the interface material can therefore be a significant portion of the total. In many instances the end-of-line thermal resistance of the thermal interface can be 20-40% of the total junction to ambient. The thermal stack up includes materials of several different CTEs and goes through power and thermal cycling – leading to cyclic mechanical load on the interface. Therefore, the thermal interface material should be chosen carefully to balance and optimize lifetime thermal performance.1-4

For example, we show a typical IGBT thermal stack up. The thermal interface material is required to transfer heat during the lifetime of the product and therefore should be designed not only to flow and wet out the interface but also have stability in the interface.

Thermal Interface Material DesignFor thermal performance and long-term reliability, the TIM design needs to be optimized around three main cri-

teria: (1) thermal conductivity of the TIM; (2) the rheology of the TIM, i.e. the deformation behavior of the material under stress; and (3) response to long term cycling. The interface between surfaces has gaps on two different length scales. The first is small-scale roughness typically O (1 µm) – from which air is eliminated by flow and wetting by the interface material. The second is related to larger gaps – O (100 -1000 µm) – due either to the non-planarity of surfaces or poor co-planarity. The thermal interface material needs to be able to conform to the surfaces, with a low external stress to produce deformation without straining the electronic components.

The thermal performance and rheology of thermal interface materials depend on both the polymer microstructure as well as the morphology and loading of the filler material. These properties are interdependent and cannot be manipulated in isolation. Since optimal performance depends on a combination of thermal conductivity and rheology one must match the application carefully to formulate the TIM. 5

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TIM manufacturers like Henkel can adjust formula-tions and processing to customize products to cus-tomer and market requirements. In general, when we think of TIM requirements, we can think of them in three categories: 1. Performance: These are must have properties for

the TIM that are critical to the proper functioning of electronics. These include thermal impedance, insu-lation strength, adhesion, etc.

2. Manufacturing: These properties relate to how the end user will manufacture the power electronics assembly. These include dispensing, working time, automation, shelf life, costs, storage, etc.

3. Reliability and Regulatory: These characteristics are related to how the TIM performs in typical envi-ronmental conditions for the final assembly and also whether certain safety and regulatory standards are met.

Application PerformanceThermal interface materials are available in several

general categories:Thermal Greases: These are relatively lower viscosity

polymer liquids that have been loaded with thermally conductive particulates. These are thermoplastic, i.e. they will deform continuously under external stresses without limit. Greases can migrate or pump out at rates dependent on the viscosity. Thermal greases typically fall in the range of 1 – 5 W/m-K and typically cover bond lines from 50 – 150 microns. These can be dispensed or stenciled onto the heat sink or plate using typical liquid dispensing processes.

Phase Change: These are materials generally solid at room temperature and melt at the phase change temperature. With film or fiberglass reinforcement they provide electrical insulation as well. They are easier to work with, can be automated and are generally better in terms of pump out resistance. In manufacturing, they may need to be over-torqued or re-torqued after phase change. Like greases phase change products are avail-able in the range of 1 – 5 W/m-K and thickness of 50 – 200 microns. They can be automated in label dispens-ing type application. Alternatively, they can be stenciled, or screen printed as well, above their melt point.

Pads: These are materials generally cross-linker polymeric material – typically reinforced with film or fi-berglass to provide electrical insulation. They perform well under higher pressure and provide excellent reli-ability. These are typically used where high cut through resistance is required for insulation purposes. Commer-cially available pads range from 1 – 3 W/m-K and typi-cally range from 150 – 250 microns in thickness.

Curable/Reactive Liquids: These may be either ad-hesives or form-in-place gap fillers and may be one component (1-k) or two components (2-k). These are thermoset materials that crosslink into a network that does not deform. These perform best – performance like grease but strong pump out resistance. The liq-uids can also be tailored to provide adhesion if needed. In addition, there is little mess and great opportunity

for tailoring properties for automated manufacturing. These products come in a range of thermal conduc-tivities – from 1 – 6 W/m-K and are mainly dispensed through specialized equipment for highly filled thermal materials. These also offer the most attractive and flex-ible platform for high volume manufacturing, reduce inventory complexity and accommodate design chang-es easier.

SummaryThermal interface materials come in a variety of formats

and performance attributes – the selection depends on the thermal and electrical insulation needs. In addition, one must consider manufacturability and automation in choosing the right TIM.

ReferencesS. Narumanchi, M. Mihalic, K. Kelley and G. Eesley. Ther-

mal Interface Materials for Power Electronics Applications. NREL CP-540-42972, July 2008.

M. Schultz. Thermal Interface – An Inconvenient Truth. Bodo’s Power System, June 2010.

Y. Nishimura, M. Oonota, F. Momose. Thermal Manage-ment Technology for IGBT Modules. Fuji Electric Review, FER-56-2-079, 2010.

J. E. Sergent, A. Krum. Thermal Management Handbook: For Electronic Assemblies. McGraw Hill 2000.

D. M. Biggs. Thermally Conductive Polymer Compositions. Polymer Composites, 1986, Vol. 7, No. 3, p.125.

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