IEEE TRANSACTIONS ON COMPUTERS, VOL. c-20, NO. 7, JULY 1971

Functional Characteristics of a

Multilingual Processor

HAROLD W. LAWSON, JR., AND BURTON K. SMITH

Abstract-This paper describes the functional characteristics ofthe Standard Computer MLP-900 processor. This microprogrammableprocessor is designed for general-purpose emulation of a widevariety of known processors as well as being adaptable to newgeneral-purpose and special-purpose applications. Two approachesto the design of microprogrammed processors, namely minimallyencoded and highly encoded, are considered. The significant archi-tectural properties that provide the multilingual capability are dis-cussed. A target language-execution strategy for the MLP-900 ispresented followed by a problem-oriented target instruction setwhich provides for packed field operations. Finally, some projecteduses of the processor are considered.

Index Terms-Computer architecture, instruction sets, micro-programming.

I. INTRODUCTIONHE development of microprogrammed processorshas been described by Wilkes [1], [2]. In the past,most microprogrammed processors have been devel-

oped to implement specific system architectures and instruc-tion sets. Emulation of additional architectures and instruc-tion sets has been accomplished by including special-pur-pose emulation hardware. The MLP-900 processor may beviewed as a general-purpose emulation computer. That is, ithas been designed for accommodating the emulation of sev-eral different computer architectures and instruction sets.Previous developments in this direction described byRakoczi [3] and Rosin [4] indicate the prospects for theutilization of this type of processor in the future.

II. MICROPROGRAM PROCESSOR IMPLEMENTATIONTECHNIQUES

In this section we shall consider some of the techniquesused in designing the instruction set and control activities ofmicroprogrammed processors to illustrate how specific andgeneral-purpose microprogrammed processors differ. Weshall consider two strategies of the design of instructionsets; namely, minimally encoded microinstructions andhighly encoded microinstructions. These two techniques areillustrated in Fig. 1.

In the minimally encoded microinstructions scheme inFig. 1(a), the microinstruction contains several fieldsFo, Fl, , F. Predetermined fields are used to directlycontrol the functional hardware facilities such as the adder,the shifter, etc. Other fields in the microinstruction wordare used to specify the source of values used in computing

Manuscript received August 15, 1970; revised January 14, 1971.H. W. Lawson, Jr., was with Standard Computer Corporation, Santa

Ana, Calif. He is now with the Department of Computer Science, Poly-technic Institute of Brooklyn, Brooklyn, N. Y.

B. K. Smith was with Standard Computer Corporation, Santa Ana,Calif. He is now with Burroughs Corporation, Industry, Calif.

|F0 | F1F|2|F3|F4 F5 I... F, IADDER l I_

SHIFTER NEXT ADDRESS BASEBYTE MOVEMEMORY SELECT

INSTRUCTION REGISTER OFFSET SOURCE

y,ky J --

FUNTIONAL HARDWARE CONTROL MEMORYSEQUENCING

(a)

CONTROLMEMORY IF lo, 021 -.o,,LOCATIONCOUNTER

(b)Fig. 1. Microprogrammed processor implementation techniques.

(a) Minimally encoded. (b) Highly encoded.

the control store address of the next microinstruction to beexecuted. In the figure, the field F. is used as the next addressbase and another field F5 is used to specify which registersource is to be used as an offset from the address base. Insome implementations the microinstruction control wordis executed in a single hardware clock cycle. However, inother implementations certain fields take on meaningduring subclock cycles.Using this technique there is very little decoding required.

For example, a field such as Fo contains a coded value desig-nating a particular sequence to be carried out involving theadder. Code 1 may indicate that two particular registersA and B are to be used as adder inputs and that the resultis to be stored back in register A. A code of 2 could indicatealternate source or destination registers for the adder, etc.A code of 0 could indicate that the adder function is to beinhibited during the current clock time or subclock time.The highly encoded microinstruction scheme in Fig. 1(b)

demonstrates the use of more conventional techniques,very much akin to the instruction fetching and execution ofclassical processors. In this scheme, a control memory loca-tion counter is used to access the microinstructions from thecontrol memory. After the instruction is fetched, the func-tion to be performed is based upon an operation code asindicated by F. The microinstruction contains variousoperand fields 01, *-, 0° which are used to control thefunctional hardware activities. The operands may, for ex-ample, specify adder inputs and destinations.

These two techniques are not necessarily exclusive, andin any particular microprogrammed processor one will nor-

732

LAWSON AND SMIH: CHARACTERISTICS OF MULTILINGUAL PROCESSOR

mally find a mixture of both of these techniques. TheMLP-900 utilizes a highly encoded strategy of micropro-gramming.

III. AN OvERvIEWIn this section we will consider the overall structure ofthe

MLP-900 and discuss the various functional areas of theprocessor. In addition, we will consider definitions of vari-ous terms that will be used throughout the paper. Thevarious functional areas of the MLP-900 processor are dis-played in Fig. 2. The MLP-900 communicates with the ex-ternal environment through one to four data and instructionbuses as illustrated by the arrows connecting the externalenvironment with the functional block called the "operatingengine." The external environment in this case could beeither main memories, consoles, I/O devices, controllers,etc. The internal environment consists of the following.

A. Operating EngineThe operating engine contains a group ofgeneral-purpose

registers plus various functional units such as adders andshifters which are capable of performing various data ma-nipulations upon values in the general-purpose registersand returning results to these registers. Most ofthe registersof the emulated system are maintained in this registergroup.-

B. Control EngineThe control engine is responsible for controlling the selec-

tion and execution of microinstructions contained in thecontrol memory. It is also utilized to maintain the state ofthe MLP-900 processor and the state of the processor beingemulated.

C. Control MemoryThe control memory provides for the storage of micro-

instructions. In the MLP-900 architecture the control mem-ory may becomposed ofREAD-ONLY memory orREAD-WRITEmemory or a mixture of these two microprogramming im-plementation medias.

D. Auxiliary RegistersThese registers are optional, and if present may be used

as save areas, high-speed buffers, or for the temporarystorage of information. Some additional uses will be pre-sented in a later section.During future discussions in this paper we will consider

some ofthe attributes ofeach of these particular functionalareas of the MLP-900 processor. Let us now consider thedefinitions of a few terms which are utilized in this paper.

Emulation: The use of a microprogrammed host systemto interpret a target language and simulate the environmentof the associated target system.

Target System: A computer environment that is manipu-lated by the use of a target language. Examples: IBMSystem/360, Burroughs 6500, etc.

Target Language: The set of operations that are used tomanipulate the target system environment.

Host System: A computer environment which is used to

733

EXTERNALENVIRONMENT

EXTERNALENVIRONMENT

I CONTROLENGINE

I ~~~~~~~~~~~~~~~~~~~II ~~~~~-I

CONTROLMEMORY

IINTERNAL

ENVIRONMENT

Fig. 2. An overview.

emulate a target system. Examples: IC-4000, MLP-900,IBM 2050, etc.

MINIFLOW : The language set of primitive operationsused to manipulate the host system environment.

Ministep: A member of the MINIFLOW set.

IV. MINISTEP FETCHING AND EXECUTION CONTROLThe MLP-900 control engine fetches highly encoded

ministeps from the control memory.The location counter used to select ministeps is called the

current ministep address. During each clock time in themachine, two ministeps are fetched from the control mem-ory, namely the ministep identified by the current ministepaddress and the ministep identified by the current ministepaddress plus one. The MLP-900 does provide for certainoverlapped execution of microinstructions; for instancewhen the two instructions are fetched from the controlmemory a determination is made as to whether the currentministep is an operating engine class instruction and thesuccessor ministep is a control engine class instruction. Ifthis is the case, then the instruction pair is executed in par-allel and the current ministep address is incremented by two.Otherwise, the instructions are executed sequentially andthe current ministep address is incremented by one. How-ever, a control engine instruction could change the valueof the current ministep address assuming that a transfer ofcontrol is effected.The execution of a single ministep or a pair of ministeps

as discussed above is accomplished in a single hardwareclock cycle. This clock cycle in the MLP-900 is 128 ns. Thecurrent ministep address referred to above is contained in aregister called the miniflow status word (MSW). The MSWcontains other information which is pertinent to the currentstate ofthe MLP-900 as well as the current ministep address.The first bit ofthe operation code ofeach ministep is used

to classify whether it is an operating engine or control en-gine class ministep. The next three bits are used to deter-mine which ofseven operating engine or which of eight con-trol engine instructions are being executed.

® A trademark of the Standard Computer Corporation.

IEEE TRANSACTIONS ON COMPUTERS, JULY 1971

V. EXTERNAL-INTERNAL COMMUNICATIONThe MLP-900 provides for one to four external buses for

primary communication between the internal environmentand the external environment. For each of these buses thereexists a set of external registers, one designated the exter-nal-in register and one designated the external-out register.Information is transmitted to and from the MLP-900 viathese registers as illustrated in Fig. 3. The external-in regis-ter is used to transmit instructions and input data to theMLP-900 processor. The instructions and input data canbe routed into one of several different internal facilities ofthe MLP-900 processor, including the auxiliary registers,the general registers, and the instruction registers. Someillustrative uses of these particular internal facilities are asfollows.

1) Auxiliary Registers: The auxiliary registers may beused for push-down stacks, high-speed save areas for main-taining environmental control in a multiaccess system orhigh-speed data buffers to be used for data conversion or intranslating higher level language source statements throughthe use of syntax tables.

2) General Registers: The general registers are used asthe primary inputs and outputs for the various functionalunits of the operating engine, namely the adders andshifters. These registers are the inputs and outputs for thedata manipulation facilities of the MLP-900.

3) Instruction Registers: The instruction registers areused to contain target language instruction words for fur-ther interpretation inside the processor.

Information to be transmitted from the MLP-900 maytake the form ofcommands for various types of input-out-put devices, including memories, and for output data to bestored into the various external devices. These values aretransmitted primarily from the auxiliary registers or fromthe general registers. As we shall see later, there are somefacilities in the MLP-900 to expedite and overlap certaininstruction and data fetch operations associated withemulating a target language where operand fetches in theform of commands can be formed and initiated during thesame clock cycle that a target language instruction is beingfetched.The internal-external communication is initiated in the

operating engine via two operating engine ministeps. One ofthese ministeps is the CEDE (Conditional External DataExchange) ministep which provides for the communicationwith main memories, the other is TEXT (Transfer EXTernal)which is used for communication with external input-out-put devices, controllers, etc.

VI. OPERATING ENGINEWe shall now consider some of the facilities of the op-

erating engine. The adder-shifter path of the operating en-gine is the path in which most ofthe significant data manipu-lation capabilities ofthe machine are contained. This adder-shifter path is programmable, i.e., it serves a multifunc-tional role in that it can perform a variety of arithmetic andlogical operations. The general form of an adder-shifteroperation (A+-A op B) is denoted in Fig. 4. In this opera-

INSTRUCTIONREGISTERS

r I

Fig. 3. Primary external-internal communications paths.

SHIFTER

Fig. 4. Operating engine, adder-shifter path.

tion, a general register designated by A is replaced by thevalue formed by taking that same registerA and performingone of 16 functional operations using a second register B asthe second input of the binary operation. The 16 functionaloperations include addition, complement addition, andvarious types of logical operations, AND, OR, EXCLUSIVE OR,etc.The result of the primary adder formed from A op B may

be shifted by the shifter operation, i.e., it may be skewedprior to storing the final result into the A register. The func-tional activity of the adder described thus far is similar tothe adder-shifter paths of many computers. A maskingcapability that makes the MLP-900 adder much more gen-eral is described in the following paragraphs.The ministep which causes the invocation of the adder-

shifter path is called the GEAR (GEneral ARithmetic) mini-step. In addition to specifying the A and B operands for theadder-shifter operation, the GEAR ministep contains anoperand which selects one of 32 mask registers which willbe used during the adder-shifter operation. By specifyingappropriate mask patterns, the effective precision of the

734

735LAWSON AND SMITH: CHARACTERISTICS OF MULTILINGUAL PROCESSOR

adder may be altered. The normal precision is 36 bits (i.e.,the register width), however, by using a mask pattern of12 zeros followed by 24 ones, the adder may be altered tobe a 24-bit adder. It is by this mechanism that precisions forvarious target systems can be accommodated. Certain out-puts developed from the primary adder operation such ascarry-out and zero result ffip-flops are relative to the maskpattern, i.e., the carry-out is relative to the higher ordermasked-in position and the zero result is relative to masked-in positions. Since any mask pattern may be used, a patternof the form 01010101 . . . is permissible during the adder-shifter path and would cause in any operation every otherbit position to be considered. This may not be ofimportancein arithmetic but can be of importance in handling noncon-tiguous fields or in certain problem-oriented applicationssuch as pattern recognition, digital filtering, or connectionmatrices for graphs.The masking capability can be used to perform packed

field operations. For example, the mask pattern selects thebits to be used in the adder operation and is also used duringthe store operation in returning the result to the A register.There are a few modes that are specified in the GEAR mini-step that affect this store operation. First is a clear mode. Ifthe clear mode is on then those masked-out positions arecleared to zero upon the storing back into the A register. Ifthe clear mode is not on then those masked-out positions inthe A registers are left undisturbed.Another mode associated with the GEAR ministep is the

test mode. When the test mode is on, the operation A op Bis performed but the store into A is inhibited. This may bedone in certain cases just to obtain adder outputs, namelycarry-outs and zero results, developed by the operationwithout changing the value of the A register.

Although the usable register size is 36 bits the actual regis-ter size is 40 bits. Throughout the internal environment ofthe MLP-900 processor, a parity checking of nine data bitsplus one parity bit is used. Because of the variable maskingcapabilities certain types ofpredictor logic for parity check-ing found in other processors may not be used in MLP-900adder-shifter path. However, error checking is accom-plished in the MLP-900 by duplicating the adder-shifterpath. A check adder and check shifter are provided. Thesefunctional units are activated with identical inputs at thesame time in the clock cycle, and the results are checked. Ifthey do not agree an interrupt is created in the MLP-900processor.We shall now consider the various ministeps which may

be used in the operating engine. To illustrate the format ofa ministep we shall consider the GEAR ministep as previouslydescribed. The general format of GEAR is presented inFig. 5. This ministep, as all ministeps in the MLP-900, is32 bits in length. The constituents of this ministep are asfollows.

1) The first bit specifies that this is an operating engineclass ministep.

2) The GEAR operation code is specified in bits 1 through3. These three bits of all ministeps specify the general classof the ministep.

GENERAL ARITHMETIC

GEAR ARITH MASK SHIFT IL B0000 CODE ADRS AMOUNTEI A |SEL IA

RT

0 8 16 24 31Fig. 5. Operating engine ministep.

3) The arithmetic code is specified in bits 4 through 7.These bits specify one of 16 different functions which canbe performed by the adder. The operations include addi-tion, subtraction, AND, OR, EXCLUSIVE OR, etc.

4) The mask address is specified in bits 8 through 11.This operand specifies one of 16 different mask registers.In actuality there are 32 mask registers divided into twobanks of 16 each. The bank selection is determined from abit in the control engine.

5) The shift amount is specified in bits 12 through 15. Bit12 controls the direction of the shift, i.e., left or right. Bits13, 14, and 15 are encoded to specify varying shift amounts,namely 0, 1, 2, 4, 6, 8, 12, or 16.

6) The clear mode function is specified in bit 16.7) The test mode function is specified in bit 17.8) The operandA source is specified in bits 18 through 23.

This field designates one of the 32 general registers. Theoperand field is structured such that the general register maybe addressed directly or indirectly through a register in thecontrol engine.

9) The B operand source is controlled via the B selectfield which is specified in bits 24 and 25. This field specifieswhether the source ofB is a general register as in A, an imme-diate constant, or one of several special control engineregisters. The B operand is selected based upon the B selectfield from bits 26 through 31.We shall now consider a brief functional description of

the six other operating engine ministeps.CEDE (Conditional External Data Exchange): This mini-

step is used to control the transmission of information toand from the main memory, i.e., transmitting instructionsand input data to the MLP-900 processor and transmittingcommands, and output data from the MLP-900.

SHIN (Shift Instruction): The SHIN instruction can beused to shift a single register or a double register by anabsolute amount or to shift an indirect amount which hasbeen previously loaded into a control engine register.Another important function of the shift instruction is toassist in performing multiplication and division by permit-ting conditional accumulating or conditional incrementingand decrementing to take place during shifting.

CHAL (Character/Decimal to Left): In addition to theprimary adder mentioned previously, there exists a secondseparate eight-bit adder path in the processor known as thedecimal adder with its corresponding check adder. Thisadder path is activated by the use of the CHAL or CHAR in-

7EEE TRANSACTIONS ON COMPUTERS, JULY 1971

structions. The primary motivation for including an eight-bit path is for efficiently emulating machines which use aneight-bit byte and provide decimal arithmetic. CHAL is usedfor byte selected manipulations on bytes from right to left(such as in decimal arithmetic).CHAR (Character/Decimal to Right): CHAR uses the deci-

mal adder and provides controls for byte selection fromleft to right (such as in byte scanning operations).GENT (General Data Transfer): The general data transfer

is used for transmitting information internal to the operat-ing engine. For example, the transmission of informationfrom a general register into an auxiliary register and viceversa or the transmission of information from a generalregister to mask register and vice versa.TEXT (Transfer External): The text command is used for

external/internal data communication but primarily forcommunicating with peripheral controllers and input/out-put devices.Although all the particulars of the operating engine have

not been presented, one may see that there is quite a bit oflatitude in programming the data manipulation compo-nent ofthe MLP-900 processor. Certain facilities have beenprovided here to allow variability in precision and to pro-vide mechanisms for executing data manipulation targetinstructions for a wide class of target machines. We shallnow consider some of the important constituents of thecontrol engine.

VII. CONTROL ENGINE

The control engine of the MLP-900 processor is used forthe following activities: 1) ministep selection from the con-trol memory and ministep decoding and execution control;2) iteration control in maintaining counts and senses forvariable length operations to be carried out via MINIFLOW;and 3) maintains and responds to the state of the MLP-900processor and the state of the target system.We shall now consider some ofthe facilities ofthe control

engine. Fig. 6 displays the count control and pointer regis-ters. During the execution of particular classes of ministepscertain of the pointer registers have dedicated functions.For example, the first four pointer registers 0 through 3 areused during decimal adder type operations as byte countersand byte pointers. The same four registers are used for con-trol counters when the READ/WRITE control memory is beingloaded. When these registers are not being used for theirdedicated purpose they are available for general use by theMINIFLOW programmer. Registers 4 and 5 are always avail-able, they are not assigned to dedicated functions. Register6 is used to control the level ofa MINIFLOW subroutine stackand register 7 is used to control the execution of indirectshifts.The subroutine stack provides a mechanism whereby

MINIFLOW subroutines may be constructed. It is used tostore the return address upon entrance to a MINIFLOW sub-routine. At the return point of the subroutine the stack ispopped up and the return address is used for transferringcontrol to the calling MINIFLOW program. This sameMINIFLOW subroutine stack is used during interrupts in theMLP-900 processor by saving the return addresses when an

COUNTCONTROL ANDPOINTERREGISTERS

DECIMAL ADDERAND BLOCKTRANSFER COUNTCONTROLUNASSIGNEDSUBROUTINE LEVELINDIRECT SHIFT

LANGUAGE BOARD JPSEUDO REGISTERS .

~5

IO

MINIFLOWSUBROUTINESTACK

15LZ

Fig. 6. Control engine count control and pointer register assignment.

interrupt occurs. On internal interrupts, after stacking thereturn address, control is transferred to a particular controlmemory address where that class of interrupt is handled.The pointer registers labeled 8 through 15 are dedicated toparticular functions which will be described later.

In addition to the pointer registers and count controlregisters the control engine contains 256 addressable stateflip-flops. All of these flip-flops are testable flip-flops, how-ever, some flip-flops may not have a value set explicitly byMINIFLOW; that is, their value is dependent upon the occur-rence of some particular state in the system. Conditionalbranch control is accomplished in the machine by testingone or two of the 256 addressable state flip-flops. This con-trol logic is illustrated in Fig. 7. Note that two flip-flopslabeled A and B are inputs to a decision process involvingsome combinational logic, A op B, where op may be one ofthe logical operators AND, OR, or EXCLUSIVE OR. If the com-binational logic is true then microprogram execution con-tinues at the branch address of the control engine ministep.However, if the combinational logic is false the micropro-gram continues at the updated current ministep address.These ministeps also provide the facilities for complement-ing either or both theA andB operand prior to the combina-tional logic.As we shall see in another section some of these flip-flops

are real flip-flops in the control engine, however, otherpseudo flip-flops are derived from various key points in theprocessor such as the carry-out of the adder, the zero resultof the adder, etc. Additional pseudostate flip-flops may beused for assisting in the emulation of a' particular target sys-tem, by reflecting information about the state of the currenttarget instruction.The general format of a branching type of instruction in

the control engine is displayed in Fig. 8. The constituents ofthis particular ministep, the BRAT ministep, are as follows.

1) The first bit specifies that this is a control engine classministep.

2) The BRAT class operation code is specified in bits 1through 3.

3) A test mode specifies which combinational logic op-eration is to be applied upon the two source flip-flops A andB. This test mode is specified in bits 4 and 5.

4) Bits 6 and 7 specify whether the true values of the Aand B source flip-flops or the complement values are to beused for the decision making process.

736

__-

737LAWSON AND SMITH: CHARACTERISTICS OF MULTILINGUAL PROCESSOR

CONTINUE AT CONTINUE ATBRANCH ADDRESS UPDATED CURRENT

MINSTEP ADDRESS

Fig. 7. Control engine MINIFLOW branching control.

BRANCH TEST

BRAT TEST A B TEST BIT A TEST BIT B RELATIVE1000 MODE A B ADDRESS

I I 1 1 .0 8 16 24 31

Fig. 8. Control engine ministep.

5) Test bit A in bits 8 through 15 specifies the A flip-flopsource.

6) Test bit B in bits 16 through 23 specifies B flip-flopsource.

7) Bits 24 through 31 specify a relative address. This is de-signed such that if the combinational logic test is true, therelative address is added to the current ministep address toform the next instruction sequence to be executed. The rela-tive address is taken as a two's complement value. Thisgives a relative branching capability of a - 128 to + 127from the updated current ministep address.We shall now consider a brief functional description of

the seven other control engine ministeps.BENT (Branch and Enter): This ministep is used to con-

ditionally control the entrance into a MINIFLOW subroutinesequence. Conditional testing is performed as in BRAT. Ifthe condition of the combinational logic is true then thecurrent ministep address is saved in the subroutine stackafter the stack has been pushed down and control is trans-ferred to the new address formed from the relative address.BORE (Branch or Return): This instruction provides for

conditional exiting from a subroutine. If the combinationallogic is false, the subroutine stack is popped up and theaddress obtained from the subroutine stack is used for thereturn.BRAD (Branch and Decrement): This conditional branch

instruction is used for decrementing pointer registers and isof particular importance in creating MINIFLOW loops.BEAD (Branch Extended Address): This ministep provides

for a conditional transfer or subroutine entry to an extendedbranch address. The maximum control memory size in theMLP-900 is 64K as specified in an extended branch addressof 16 bits of this instruction.

BLoT(Block Transfer): This instruction is used for trans-ferring blocks of information between various registers inthe MLP-900 and for transferring information to and froma main memory. Of particular importance is the loading ofcontrol memory.

MAST(Manipulate Status): The MAST provides a capabil-ity for performing some combinational logic on two stateflip-flops A and B as sources and storing the result of thiscombinational logic, either true or false, in a resultant stateflip-flop C. Consequently, the operation is as follows:C*-A op B.MO VE: This ministep provides facilities for transmitting

registers values within the control engine.

VIII. LANGUAGE BOARDS

The MLP-900 is a very general processor capable ofemulating a wide class of existing computer systems andcapable of emulating new machines of experimental design.A basic dilemma is that generality usually means less effi-ciency. This inefficiency normally comes about when ratherstraightforward operations (such as instruction decomposi-tion and operand fetching) in the system are performedfrequently while maintaining a completely general type ofstructure.An extremely important aspect of the MLP-900 design

has been the inclusion of a facility called the languageboards which provide for performing straightforwardoperations, such as instruction decoding and address con-trol in a very efficient manner. These language boards arehardware components which are designed on a per targetsystem emulation basis and each MLP-900 processor maycontain from one to four different addressable languageboards. Language board switching is accomplished bysimply addressing the appropriate language board via twobits in the MINIFLOW status word. The language board ac-tivities of the MLP-900 may be divided into two classes,namely passive associations and activefunctions.

Passive associations are illustrated in Fig. 9. The passiveassociations are provided by designing combinational logicassociated with various key registers in the host system,particularly the external-in register associated with one ofthe four external buses and the instruction registers. Byproviding this logic one can obtain a very fast decodingmechanism for target language instructions. This decodingis accomplished through the use ofpseudo pointer registersand pseudo ffip-flops. As denoted in Fig. 9, registers 8through 15 are pseudo pointer registers. The values of theseregisters are acquired through the combinational logicassociated on the language board such as the external-inregisters and instruction registers. For instance 8 through 14can be derived from any of the bit sources in the instructionregisters. Register 15 can be attained in a similar mannerfrom -the external-in register. As we shall see in a futureexample this association makes it convenient for emulatingtarget system registers on the MLP-900 in that these pseudo

IEEE TRANSACTIONS ON COMPUTERS, JULY 1971

EXTERNAL- INREGISTER

EXTERNALREGISTERSINSTRUCTION REGISTERS

.I I1LINSTRUCTIONREGISTERS

INSTRUCTIONINI FETCH

REG OFFSET

TI_ ___

OUTI I- -

PSEUDO

REAL PSEUDO

Fig. 9. Language board passive associations.

registers may be used as indirect addresses in the GEARministep and in other operating engine ministeps for ad-dressing and manipulating the general registers of theoperating engine. These pseudo pointer registers may alsobe used for branching in a transfer vector sense to a par-ticular op code or sub-op code class of target system in-structions to be interpreted.An example of the use of pseudo pointer registers is as

follows. Consider that a data operand has been brought intothe external-in register and this operand is structured suchthat the first several bits of the word specify the class ofoperand (i.e., descriptor) of the value in the right-hand partof the register. As soon as the value in the external-in regis-ter changes then the value of the pseudo pointer register 15has been changed. Consequently, with a pair of ministeps,executed in one clock cycle, the value may be transmittedfrom the external-in register into one ofthe operating engineregisters and a branch may be taken to a particular placein the control memory where that particular class ofoperand is handled. This branch is used upon pseudo-register 15. This is a very convenient mechanism for a de-scriptor based system like the Burroughs B6500.

In addition to the pseudo pointer registers, some of thestate flip-flops are available for the language board passiveassociations. Any combinational logic in the external-inregister or the instruction registers may be used to derivethe source of a single bit, i.e., true or false. In both casesthe pseudo pointer registers and the pseudo ffip-flops changevalue when the register value is changed. One may forexample wish to check for a null (i.e., zero) element in thelink field of a node of a list structure. This logic could beincorporated on the language board, establishing an as-sociation between the link field bits of the external-inregister value and a single flip-flop.

ILIFig. 10. Language board active functions.

Now let us turn our attention to the active functions ofthe language board. An example of an active function isdisplayed in Fig. 10. Suppose we were emulating a machinein which the instruction words in the external-in registercontain certain bits to specify a target system base registerto be used in developing an operand address. In addition,the instruction word contains an offset to be added to thatregister to form a final operand address. As illustrated here,this function can be performed in one clock cycle. The regis-ter designation is used to locate the target register (i.e.,one of 16 different registers). This register is used as anadder input along with the offset bits from the external-inregister. After forming the operand address (i.e., base+offset) a control word for accessing an operand in themain memory is formed and sent to the external-out registerto start a memory fetch. In addition the instruction itselfwill be placed into one of the two instruction registers forthe processing. This highly repetitive type of operationwould have to be done for practically every instruction inthe emulator. The addressing operation could be performedthroughout several ministeps. However, the languageboard assist is quite important from an efficiency stand-point.Some additional illustrative functions which can be ac-

complished by the language board are as follows: 1) pagefault detection for virtual machine implementations; 2)base and limit register validation for time sharing applica-tions; and 3) byte and bit addressing control.

IX. TARGET LANGUAGE EXECUTION STRATEGYFigs. 11 and 12 illustrate the flow of control in a typical

MINIFLOW execution. The functional activity of a routine orset of routines is indicated below the routines. A hard-wiredloader is entered by pressing a start button. This loader pro-

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LAWSON AND SMITH: CHARACTERISTICS OF MULTILINGUAL PROCESSOR

Fig. 11. Nonoverlapped emulation strategy.

LOAD INITIALIZATION BRANCH TARGETMINIFLOW MINIFLOW VECTOR EXECUTION

Fig. 12. Overlapped emulation strategy.

vides for the initial loading of ministeps. The mnemonicsfor the ministeps used in this section are given in Table IAand B. These mnemonics conform to the MINIFLOW as-sembler for the MLP-900. This assembler was constructedthrough use of ICAP II, a meta-assembler designed forcreating MINIFLOW and target language assemblers. A morecomplete list can be found in [5], [6]. ic refers to a generalregister being used as the Instruction Counter for the targetlanguage. op represents a pointer register which containsthe operation code of the target instruction. In an actualimplementation op may be a translation of the operationcode by the language boards to reflect the values needed foran efficient branch vector and target language execution rou-tines. Note also that in actual implementation many execu-tion routines may have common subroutines or coalesceinto one routine following some preliminary MINIFLOW.

Figs. 11 and 12 depict the MINIFLOW necessary to executea target language. Although the technique used in Fig. 11 ismore straightforward, Fig. 12 illustrates a more efficient useof main memory. Primarily, this efficiency is gained byimbedding the IFETCH routine of Fig. 11 in the other MINI-

TABLE IAOPERATING ENGINE MINISTEPS

CEDE FunctionsFOP-Fetch OPerand (FOP AOP, BOP): AOP + BOP replaces AOP. A FETCH

request is sent to main memory using this result as a memory address.If no BOP then zero is assumed.

FIN-Fetch INstruction (FIN AOP, BOP): AOP+BOP replaces AOP. A FETCHrequest is sent to main memory using this result as a memory address.Ifno BOP then zero is assumed.

RMW-Read Modify Write (RMw AOP, BOP): AOP+BOP replaces AOP. AREAD MODIFY WRITE request is sent to main memory using this resultas a memory address. If no BOP then zero is assumed.

wop-Wait for OPerand (wop AoP): Data from main memory replacesAOP. If the data have not arrived a wait occurs.

WAS-Wait for address Acknowledge and Store (WAS AOP): AOP is sentto be stored into main memory. Ifmain memory has not acknowledgedreceipt of the address to be stored into a wait occurs. When used in aRMW/WOP/WAS sequence a wait never occurs.

woF-Wait for Operand and Fetch next operant (WOF AOP, BOP): Datafrom main memory replaces AOP. If the data have not arrived a waitoccurs. A FETCH request is sent to main memory using BOP as a

memory address.WIN-Wait for INstruction (WIN AOP, BOP): Data from main memory is

added to BOP and the result replaces AOP. This result is used as theaddress for a command word which is sent to main memory. Thecommand can be a FETCH, STORE, or READ MODIFY WRITE dependingon the op-code of the incoming target instruction. Either the addi-tion or the command to memory, or both, can be inhibited underlanguage board control.

GENT FunctionsMVHA-MoVe B operand to operating engine register specified by AOP

(MVBA AOP, BOP): Bop replaces AOP.

GEAR FunctionsADD-ADDition (ADD AOP, BOP, MASK): Masked-in portions, as deter-

mined by MASK, ofAOP+ BOP replace AOP. CORI state flip-flop is set to re-flect the carry-out state of the masked-in portion ofthe adder; ZEFI stateflip-flop is set to reflect the zero result of the masked-in portion of theadder. If no MASK then mask register 00 is assumed.

Sub-ops for Operating Engine MinistepsPD-Pointer as Data (_, PD): If this sub-op code appears then the B

operand must be a pointer register. The eight bits of the pointer registerspecified are brought up as the rightmost eight bits of the B operandwith leading zeros. ifPD is not present then the pointer register is used asan indirect address into the operating engine.

T-Test ( , T): This sub-op code inhibits the result of the ministepfrom being placed into the AOP. The MLP-900 status, however, reflectsthe operation in the usual fashion.

TABLE IB

CONTROL ENGINE MINISTEPS

BRAT FunctionssA-Skip if A operand is true (SA AOP, LABEL): If the state flip-flop ad-

dressed by AOP is a one control is transferred to location LABEL: other-wise control is passed to the continuation.

BEAD Functions

BRU-BRanch Unconditional (BRU LABEL, INDEX): Control is passed tothe location given by the sum of LABEL and the contents of a pointerregister specified by INDEX. If no INDEX then control is transferred toLABEL.

MAST FunctionsMA-Manipulate A operand (MA AOP, RESULT): AOP logically oRed with

itself is placed in RESULT. This provides a simple move of one stateflip-flop to another.

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IEEE TRANSACTIONS ON COMPUTERS, JULY 1971

FLOW routines which permits the overlapping of the targetinstruction fetch time with the execution time of the previ-ous instruction.

Normally, the target language instruction counter update(accomplished as part of the FIN in Fig. 11) becomes part ofthe initialization MINIFLOW, and the placing of the targetinstruction in the instruction register (WIN) becomes the lastministep in the execution MINIFLOW of the previous instruc-tion. During the WIN execution transfer is forced to one ofseveral initialization routines under language board control.The incoming target instruction op-code is usually the de-termining factor as to which initialization routine is acti-vated.

Requesting the target instruction fetch (FIN) can be placedin either the execution MINIFLOW or in the initializationMINIFLOW. The overriding consideration to performing aFIN is that all operand memory fetches for the target instruc-tion being executed are completed. If all data necessary forthe execution MINIFLOW are gathered in the initializationMINIFLOW or if the target instruction does not require anoperand fetch, then the FIN can be performed in the lastclock cycle of the initialization routine in parallel with theindexed branch to the branch vector. The decision as towhether the operand fetching should be completed in theinitialization MINIFLOW or in the execution MINIFLOW in-volves the classic programming dilemma, the space/timeefficiency tradeoff.A hypothetical target language will be described and

used as a vehicle to illustrate the MINIFLOW routines of Fig.12. This language which we will call FEL (field extractionlanguage) is for expository purposes and therefore is notdescribed in full detail. In fact it is not necessarily meant tobe a complete language but might well be a subset of an-other language.

FEL utilizes a 32-bit word, and the instruction format asshown in Fig. 13 specifies two addresses. Each effectiveaddress is obtained by adding one offour active bases to thedisplacement given in the instruction. Normally the opera-tion is performed using both operands, and the result re-places operand 1. The operation is masked by one of 16active masks such that only the bits corresponding to the1 bits of the addressed mask take part in the operation. Theeffect during the operation is that the masked-out (0 bits inthe mask) part ofthe two operands are not considered in theoperation. The masked-out portion of operand 1 is not dis-turbed and the condition codes, zero result, and carry-out,are set to reflect the condition of the masked-in portiononly. Masked-in bits need not be contiguous.The target instruction repertoire includes logical opera-

tions, arithmetic operations, I/O operations, varioustransfer and control instructions, a move instruction, andthe ability to load the 16 mask registers and the four baseregisters. The bases might be used for such functions asstarting addresses for information structures, such asdensely packed arrays, symbol tables, buffered data records,etc. For an example of a FEL target instruction execution,we shall use an addition. The MLP-900 resource allocationassumed for FEL iS given in Table II. Because of the arbi-trary field definition allowed, no sign convention is as-

OPERATION MASK BAS BASEICODE ADDRESS IBOIDISPLACEMENT jDISPLACEMENT

_ _

0 4 8 12 16 20 24 28 31

Fig. 13. FEL instruction format.

TABLE IIRESOURCE ALLOCATION

General RegistersGOO-G15 Loadable mask patternsG16-G19 Base registers 0-3G20 Word 0 addressG21 Word 1 addressG22 Word 0 dataG23 Word 1 dataG24 Target instruction counter

Mask RegistersMOO OFFFFFFFF16 (32 ones)M15 Current mask pattern

State Flip-FlopsGeneral Indicators

GIOO Carry-out state FELGIOI Zero result state condition code

MLP-900 DefinedCOFI Adder carry-outZRF1 Adder zero result

Language Board DefinedCLB03 Store type instruction indicator (derived from

bits 0-5 of FEL instruction).

Pointer RegistersLanguage Board Defined

P08 op-code (bits 0-5 FEL instruction shifted left 1).

P09 Mask (bits 8-11 of FEL instruction).

PlO Base 0 (bits 16-17 of FEL instruction with aforced 1 such that value range is 16-19 ratherthan 0-3).

P11 Displacement 0 (bits 18-23 of FEL instruction).

P12 Base 1 (bits 24-25 of FEL instruction with aforced 1 such that value range is 16-19 ratherthan 0-3).

P13 Displacement 1 (bits 26-31 of the FEL in-struction).

P15 Base 0 (bits 16-17 of FEL instruction with aforced 1 such that value range is 16-19 ratherthan 0-3). This field is obtained from the ex-ternal register and thus is available earlierthan is PlO which requires that the target in-struction be available in the instruction reg-ister.

sumed. All adds are therefore two's complement. Thecarry-out state of the most significant masked-in bit isplaced in general indicator 00, and, the zero result state ofthe masked-in bits is placed in general'indicator 01. Over-flow if applicable can be obtained from these two indica-tors. The ADD conforms to the general instruction layoutas described previously. The flow diagrams in Figs. 14, 15,and 16 show the flow of control for executing the ADD in-struction. The reader should examine the comments ac-companying these diagrams.

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LAWSON AND SMITH: CHARACTERISTICS OF MULTILINGUAL PROCESSOR

INITIALIZE

* MVBA M15, P09

* ADD G24,1

* WOP G22

Load mask pattern to mask 15 from a general register indirectlyspecified in pointer 09. Update instruction counter by an im-mediate 1.Synchronize with main memory; place operand 0 data in gener-al Register 22. Memory fetch started at previous wIN.

3Skip to INITB if target instruction requires a store opera-tion to main memory.

Create address from displacement 1 and base 1 and sendfetch operand command to main memory.

)Branch to target branch vector indexed by the target lan-guage-op-code.

Create address from displacement 1 and base 1; send READMODIFY WRITE command to main memory.

BV, P08 Branch to target branch vector indexed by the target lan-* .* guage op-code.

Fig. 14. INITALIZE 1. The symbol * to the left of the flow diagram indi-cates one clock cycle (128 ns). Using this information in conjunctionwith memory interference allows timings for various paths throughthe diagram to be figured.

BVTr.

BVt 18

WOP G23

BRU ADDBV+ 126

BV + 126

I

The MINIFLOW in these two control memory locations simul-taneously executes the first ministep of op-code 0 and branchesto the execution MINIFLOW.

Synchronize with main memory and place operand 1 data ingeneral register 23.

Branch unconditionally to the MINIFLOW routine to executeADD.

The MINIFLOW in these two control memory locations simul-taneously execute the first ministep of op-code 63 and branchesto the execution MINIFLOW.

Fig. 15. Branch vector (BV).

ADD

ADD G23,G22,M 15

WAS G23

MA COFI, GIOO

FIN G24

MA ZRFI,GIOI

WIN G20, PI 5

Add operand 0 to operand I using specified mask.

Synchronize with main memory; place sum to be stored onmain memory bus.

Set the first bit of the condition code to the carry-out state.

Request a target instruction fetch by sending instructioncounter to main memory.

Set the second bit of the condition code to the zero resultstate.

Synchronize with main memory; place target instruction ininstruction register; create operand 0 address and place inG20; request the fetch ifrequired; and transfer control, as de-termined by language board to proper initialization routine.

Fig. 16. ADD.

MASKREG EQU 10VALREGO EQU 11VALREG1 EQU 12TEMP EQU 13

ADDFIELD LLNRLLRNRARNRXNROR

IST

MASKREG,MASKVALREGO,OPERANDOVALREGO,MASKRBGVALREG1,OPERAND1TEI4P,VALREG1VALREG1,MASKREGVALREGO ,VALREG1VALREGO,MASKREGMASKREG,ALLONESTEMP, MASKREGVALREGO0 TEMPVALREGO,OPERAND1

SET UP MASKFETCH OPERANDSPREPARE OPERANDS00TCH OPERAND1SAVE COPY OF OPERAND1PREPARE OPERANDIADDCLEAR ANY CARRYCOMPLEMENT MASKCLEAR RESULT FIELDINSERT RESULTSTORE RESULT

MASK DS 1OPERANDS DS 1OPERAND1 DS 1ALLONES DC 'FFFFFFFF'

360/

4.4.5.4.2.5.3.5.5.5.5.4.

TIMING (usec)

'50 360/65 370/165

.0 1.2 0.160 1.2 0.16,0 1.25 0.080 1.2 0.16.5 0.65 0.08.0 1.25 0.08.25 0.65 0.080 1.25 0.08.75 2.0 0.16.0 1.25 0.08.0 1.25 0.080 0.93 0.32

52.5 14.08 1.52

Fig. 17. 360 and 370 code.

When any of the arithmetic or logical instruction typesare being brought into the CPU from main memory via aWIN an entry to INITIALIZE I will be forced. Instructions notrequiring a store operation, such as COMPARE, will causeINITA MINIFLOW to be executed; others such as ADD executeINITB instead. If we assume the op-code of ADD to be ninethen a binary left shift of one before being associated withPO8 by the language boards would give a value of 18. Noticethat all entries to be the branch vector BV would be evenlocations relative to BV. We now create pairs of ministepsto be executed simultaneously by removing the first mini-step of the execution routines and placing them into thebranch vector preceding the branches to the executionroutines. This technique of gaining efficiency is not shownon either Fig. 11 or Fig. 12.The last ministep of the execution routine for ADD is an-

other WIN. If the next target instruction, whose fetch wasinitiated by the preceding FIN, residing in the external regis-ter is another ADD the entry to INITLALIZE I would be forcedand the same MINIFLOW routines would be executed.The execution of the ADD instruction assuming the use of

an SC-700 main memory (700-ns cycle time) is accom-plished in 2,6 ps which reflects main memory speed limita-tions. While it is difficult to perform the identical functionwith an IBM System/360, a similar function is encoded asshown in Fig. 17.The main memory target instruction requirements for

accomplishing the operation are 4 bytes for the MLP-900version, and 34 bytes, excluding the mask and operands, forthe System/360 version.

In contrast to the 2.6 ps required for the MLP-900, theSystem/360 timings are 52.5 and 14.08 is for the Models 50and 65, respectively. Assuming all ofthe code, operands andmask are contained in the cache memory, the time for theSystem/370 Model 165 is 1.52 ps.

X. SUMMARY AND CONCLUSIONS

This paper has considered several of the important fea-tures of the MLP-900 processor. In addition, we have con-sidered the basic strategy used in emulating a target lan-guage. The FEL language illustrates the use of the processorfor the efficient handling of arbitrary packed field opera-tions. Operations like those contained in FEL, while veryuseful, are not normally found in general-purpose computerlanguages.

.

0

'0

0/

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IEEE TRANSACTIONS ON COMPUTERS, JULY 1971

The MLP-900 processor, amongst many possible applica-tions, can be used for the emulation of known general-purpose or special-purpose processors, for emulating newlydesigned processors (prior to constructing the hardware),for developing processor languages which are convenientfor the processing of higher level languages, for handlingkey subroutines, and for efficiently handling operating sys-tem functions. A side benefit which has accrued from useof this type of processor has been the development of im-proved processor diagnosis via microdiagnostic programswritten in MiNIFLOW [7]. The use of writable control storeprovides a convenient method of building MINIFLOW codefor monitoring, evaluation, and debugging target system in-structions and software. Several people have contributedresearch results and forecasts in areas which are related tothe development of this new type of processor). We havecited only a few of these references [8}-[18] for the readerwho wishes to explore the development of microprogram-ming. For those who desire a more complete explanationofthe operational characteristics ofthe MLP-900, referenceis made to the MLP-900 principles of operation [19].

ACKNOWLEDGMENTThe authors would especially like to thank D. E. Keefer,

R. M. Guffin, and J. Fridenberg, as well as all their MLP-900 colleagues for their cooperation and valuable sugges-tions in their contribution to the development of the MLP-900 processor.

REFERENCES[1] M. V. Wilkes, "The best way to design an automatic calculating

machine," presented at the Manchester University Comput. Inau-gural Conf. (Manchester, England), 1951, p. 16.

[2] , "The growth of interest in microprogramming," ComputingSurveys, vol. 1, no. 3, Sept. 1969, p. 139.

[3] L. L. Rakoczi, "The computer-within-a-computer, a fourth genera-tion concept," Comput. Group News, vol. 2, 1969, p. 14.

[4] R. F. Rosin, "Contemporary concepts in microprogramming andevaluation," Computing Surveys, vol. 1, no. 4, Dec. 1969, p. 197.

[5] , "ICAP II language, programmers manual," Standard ComputerCorporation, Santa Ana, Calif., form 801027, 1970.

[6] , "ICAP ii language, MLP-900 MINIFLOW supplement," StandardComputer Corporation, Santa Ana, Calif., form 801028, 1970.

[7] R. Guffin, "Microdiagnostics for the standard computer MLP-900processor," submitted to the 3rd Annu. SIGMICRO Workshop.

[81 A. Opler, "Fourth generation software," Datamation, vol. 13, Jan.1967, pp. 22-24.

[9] A. J. Melbourne and J. M. Pugmire, "A small computer for thedirect processing of Fortran statements," Comput. J., vol. 8, 1965, pp.24-27.

[10] H. Weber, "A microprogrammed implementation of Euler on IBM360/30," Commun. Ass. Comput. Mach., vol. 10, 1967, pp. 549-558.

[111 M. J. Flynn and M. D. MacLaren, "Microprogramming revisited,"Proc. 22nd Nat. Conf ACM. Washington, D. C.: Thompson, Aug.1967, p. 457.

[12] H. W. Lawson, Jr., "Programming-language-oriented instructionstreams," IEEE Trans. Comput., vol. C-17, May 1968, pp. 476-485.

[13] W. C. McGee and H. E. Peterson, "Microprogram control for theexperimental sciences," in 1965 Fall Joint Conmput. Conf., AFIPSConf. Proc., vol. 27, pp. 77-91.

[14] G. B. Gerace, "Microprogrammed control for computing systems,"IRE Trans. Electron. Comput., vol. EC-12, Dec. 1963, pp. 733-747.

[15] L. D. Amdahl, "Microprogramming and stored logic," Datamation,vol. 10, Feb. 1964, pp. 24-26.

[16] C. Ramamoorthy and M. Tsuchiyo, "A study of user-micropro-grammable computers," in 1970 Spring Joint Comput. Conf., AFlPSConf. Proc., vol. 36. Montvale, N. J.: AFIPS Press, 1970, pp.165-182.

[17] H. Barsamian, "Firmware sort processor with LSI components,"in 1970 Spring Joint Comput. Conf., AFIPS Conf Proc., vol. 36.Montvale, N. J.: AFIPS Press, 1970, pp. 183-190.

[18] S. Husson, Microprogramming: Principles and Practices. Engle-wood Cliffs, N. J.: Prentice-Hall, 1970.

[19] , "MLP-900 multi-lingual processor, principles of operation,"Standard Computer Corporation, Santa Ana, Calif., form 809001-5,1970.

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