FPGA BASED SERIES ACTIVE FILTER FOR POWER QUALITY ENHANCEMENT

International Electrical Engineering Journal (IEEJ)

Vol. 1 (2011) No. 1, pp. 506-513

ISSN 2078-2365

506

Abstract— In this paper a FPGA based series active filter was

constructed by adding a bi-directional switch to the

conventional bridge topology. A three-phase series active

filter was proposed to compensate voltage unbalances,

suppress voltage sags and swells and hence improve the power

quality of a three-phase ac system. The voltage unbalance

compensation and regulation is only based on the positive

sequence component decomposition of the supply voltage that is

then adjusted to a rated value and used as the reference

voltage This paper proposes a fully digitized hardware design

scheme of a Space Vector Pulse Width Modulation which is

verified and implemented on a single chip Field Programmable

Gate Array (FPGA), for series active filter. This is also

implemented in Digital Signal Processor (DSP) as FPGA and

DSP are the good compromise between the advantage of the

flexibility of a programming solution and the efficiency of a

specific architecture with a high integration density. These

characteristics are quite appropriate for controller design. The

comparison of the experimental results especially, Execution

time and maximum circuit delay from the DSP and FPGA based

implementation respectively, provides guideline on the

superiority of FPGA based solution of Industrial Drives .

Index Terms—: FPGA, PWM, DSP

I.INTRODUCTION

The power quality in distribution system, especially voltage

quality is very important for both industrialized and

developing countries. Computers and sensitive electronic

equipment are used everywhere nowadays. A poor power

quality can damage or degrade these equipments. In industry

and commercial plant insufficient power quality can lead to

the poor quality of products, interruption of important

industrial processes and hence economic losses. The factors

S.S.Darly Assistant Professor,Department of Electrical and Electronics

Engineering , University College of Engineering, Anna University , India.

[email protected]

Dr.P.Vanaja Ranjan, Associate Professor, Department of Electrical and

Electronics Engineering , College of Engineering, Anna University , India.

[email protected]

Dr.B.Justus Rabi, Professor&Head, Department of Electrical and

Electronics Engineering , Madanapalle Institute of Technology and Science,

[email protected]

that affect the voltage quality are voltage unbalance, voltage

sags and swells. Voltage unbalance can occur due to an

incomplete transposition of transmission lines, unbalanced

loads, open delta transformer connection, disconnected

three-phase capacitor bank and the proliferation of nonlinear

and large single-phase loads[1]. Voltage unbalance worsens

the operation of AC electric machines. Then negative

sequence component in voltage unbalance causes large

transient current that leads to reduction of the net torque,

increase in losses and temperature rise[2]. Voltage sags and

partial or total collapses of one or more phases are normally

caused by faults on adjacent feeders such as phase to ground

or phase to phase faults. Voltage swells are caused by power

factor correction capacitors and transformer switching.

Voltage sags or collapse and voltage swells can temporarily

interrupt the operation of electrical machine and equipment.

A number of topologies and algorithm to improve the voltage

quality have been presented in the literature. However, most

of the proposed controllers are open loop based on

three-symmetrical component; zero sequence, negative

sequence and positive sequence, decomposition to balance

and regulate the voltage. This paper proposes a compensation

algorithm using a series active filter associated with the

sliding mode controller to compensate voltage unbalance and

suppress voltage sags and swells. The proposed control

structure is shown in Fig. 1. It is based on a three-phase PWM

voltage source inverter connected in series with the power

lines through transformers.

Compared with Sinusoidal PWM (SPWM) [1], which is

another useful modulation strategy, the linear range of the

SVPWM is 15% higher than the SPWM; furthermore, the

SVPWM can continuously change from linear to over

modulation and six-step mode with a superior utility factor of

the DC bus voltage [2]-[3]. Speed performance of new

components and flexibility inherent of all programmable

solutions, give today many opportunities in the field of digital

implementation for control systems. This is especially true

with software solutions as microprocessor or Digital Signal

Processor (DSP) [4]. However, specific hardware technology

such as Field Programmable Gate Array (FPGA) can also be

considered as an appropriate solution in order to boost the

performance of controllers. Last twenty five years were

outstanding by the revolution of technological possibilities in

the field of digital electronics and this is much within the

context of programmable solutions (Microcontroller, DSP,

FPGA BASED SERIES ACTIVE FILTER FOR

POWER QUALITY ENHANCEMENT

S.S. Darly , Dr.P.Vanaja Ranjan,Dr.B. Justus Rabi

Darly et al. FPGA Based Series Active Filter for Power Quality Enhancement

507 | P a g e

etc.,) than of digital hardware solutions (CPLD/FPGA/ASIC).

Indeed, these generic components combine low cost

development, thanks to their re-programmability, use of

convenient software tools and more and more significant

integration density [5]-[7]. FPGA technology is now

considered by an increasing number of designers in various

fields of application such as telecommunication [8], video,

signal processing [9], embedded control systems, and

electrical control systems [10]. This is because an

FPGA-based implementation of controllers can efficiently

answer current and future challenges of this field. This paper

describes the implementation using FPGA and DSP. The

experimental results are discussed and concluded with future

proposals.

Fig 1.Three-phase Series Active Power Filter (SAPF)

The desired voltage waveform is obtained by

accurately controlling the switching of the insulated gate

bipolar transistors (IGBTs) in the inverter. Control of the

voltage wave shape is limited by the switching frequency of

the inverter and by the available driving voltage across the

interfacing inductance.

The driving voltage across the interfacing inductance

determines the maximum di/dt that can be achieved by the

filter. This is important because relatively high values of di/dt

may be needed to cancel higher order harmonic components.

Therefore, there is a trade-off involved in sizing the interface

inductor. A larger inductor is better for isolation and

protection from transient disturbances. However, the larger

inductor limits the ability of the active filter to cancel higher

order harmonics.

The Inverter (three-phase unit or single-phase unit as

the case may be) in the Series Active Power Filter is a bilateral

converter and it is controlled in the voltage Regulated mode

i.e. the switching of the Inverter is done in such a way that it

delivers a voltage which is equal to the set value of voltage in

the current control loop. Thus the basic principle of Series

Active Power Filter is that it generates a voltage equal in value

and opposite in polarity to the harmonic voltage drawn by the

load and injects it to the point of coupling thereby forcing the

source voltage to be pure sinusoidal. In the mid 1980's Space

Vector Pulse Width Modulation was proposed, which was

claimed to offer significant advantages over natural and

regular sampled PWM in terms of performance, ease of

implementation and maximum transfer ratio [3], [4]. The

principle of SVPWM is based on the fact that there are only

eight possible switch combinations for a three phase inverter.

The basic inverter switch states are shown in Figure 1. Two of

these states (SV0 and SV7) correspond to short circuit while

the other six can be considered to form stationary vectors in

the d-q plane . The magnitude of each of the six active vectors

corresponding to the maximum possible phase voltage is

having identified the stationary vectors, at any point in time;

an arbitrary target output voltage vector can then be made up

by the summation (“averaging”) of the adjacent space vectors

within one switching period. Target vectors in the other five

segments of the hexagon are clearly obtained in a similar

manner

II.IMPLEMENTATION CONTROLLER USING FPGA

DESIGN METHODOLOGY

For very complex designs, modular conception is generally

used to reduce design cycle. This methodology is based on

hierarchy and regularity concepts. Hierarchy is used to divide

a large or complex design into subparts called modules that

are more manageable. Regularity is aimed to maximize the

reuse of already designed modules. This implementation

contains 8 modules in FPGA namely

1.Voltage Variation controlled by input

2. Calculation of modulation index and step value (Δalpha)

3. Clock divider

4. Calculation of ON periods Ta, Tb, To

5. Calculation of number of 100 Mhz pulses for ON time

pulse duration for six Sets.

6. PWM pattern for IGBT Set 1 and IGBTSet 4

7. PWM pattern for IGBT Set 2 and IGBTSet 5

8. PWM pattern for IGBT Set 3 and IGBT Set 6

Figure 2: Spartan III FPGA kit

Start

Initialize Reset o

Initialize clock 1

Get the sector

Calculate sin and cos from lookup

Table

Implement the above Ta and Tb

calculation formula

Calculate T0

Stop


Vol. 1 (2011) No. 1, pp. 506-513

ISSN 2078-2365

508

Fig 3:Flow chart

In a similar manner every module was coded in VHSIC (Very

High Speed Integrated Circuit) Hardware Description

Language (VHDL) algorithmically, tested for its functionality

and then integrated to give a complete system.

Fig.4. PWM simulation samples using XILINX FPGA at Ma = 0.65.

Figures depict the complete schematic which is finally

implemented. The modules in both the diagrams are

numbered with reference to the eight modules listed above.

The ports a,b,c &d are used to generate the pulses.

Fig 5..Multilevel PWM simulation samples using XILINX FPGA at Ma = 1.35.

III.SIMULATION RESULTS

The proposed series active filter has been verified by

simulation. The results are divided into 5 categories

according to the arbitrary imposed supply conditions,

as shown in Fig. 6-9. In each case, the compensator

begins to operate at 40 ms.

Case 1: Balance voltage sags with |MF| = 0.65

Case 2: Balance voltage swells with |MF| = 1.35

Case 3: Unbalance voltage sags with |UF| = 0.261 and |MF| =

0.516

Case 4: Unbalance voltage swells with |UF| = 0.144 and |MF|

= 1.20

Case 5: 1-phase loss with |UF| = 0.552 and |MF| = 0.766

Fig. 6: Case 1: Load phase voltage, compensating voltage and

source phase voltage in case of balance voltage sags with |MF|

= 0.65


source phase voltage in case of balance voltage swells with

|MF| = 1.35


509 | P a g e

Fig. 8: Case3: Load phase voltage, compensating voltage and

source phase voltage in case of unbalance voltage sags with

|UF| = 0.


source phase voltage in case of unbalance voltage swells with

|UF| = 0.144 and |MF| = 1.20

Fig. 10: Case 5: Load phase voltage, compensating voltage

and source phase voltage in case of 1-phase loss with |UF| =

0.552 and |MF| = 0.766

Fig. 11 Experimental set up

Xilinx project navigator tool is used for downloading

the design into the Spartan III XS3S400PQ208-4 FPGA

device. SPARTAN device is fixed in a universal

development board that contains a 4X4 matrix switches.

The switching patterns generated using FPGA as per the

speed setting from the user drives the IGBTs of VSI to inject

the necessary voltage.

Implementation controller using TMS320F2812DSP

The TMS320C2xxx series of DSPs has been designed

specifically for signal processing and control applications. Its

hardware is optimized for numeric computation and has the

necessary processing capabilities to meet the bandwidth

requirements of high performance systems. Through its

internally hardwired logic the DSP can execute most

functions in a single clock cycle. Code Composer Studio

software which integrates all host and target tools in a unified

environment is used for the code development. It also

simplifies DSP system configuration and application design

to help designers get started faster than ever before.

IV.HARDWARE IMPLEMENTATION

The following are the steps to be followed for the

implementation of the first method usingTMS320F24XX

DSP having switching pulse generation hardware.

1. Initialize various Registers.

2. Create a look up table for sine theta

3. Calculate the time values ta, tb, t0.

4. Find the Duty cycle for each pair of transistor based on

sector.

5. Update the PWM.

C code for the algorithm is compiled in Code

Composer Studio and the ASCII output file is converted to

downloadable hex format using debugger and then

voltage

Sensor

D.C

SUPPLY

DRIVER

CIRCUI

T

voltage

SOURCE

INVERTE

R

1

Power

suppl

y

DSP

TMS

320F28

12

3

POWER

SUPPL

Y

3

IM

P

N

R

Y

B

PC


Vol. 1 (2011) No. 1, pp. 506-513

ISSN 2078-2365

510

downloaded to TMS320F2812 DSP kit. The six PWM

patterns generated from the DSP are made to drive the IGBTs

and three phase induction motor acts as the load. The same

approach is followed for FPGA based implementation.

V. EXPERIMENTAL RESULTS

Before realizing the FPGA and DSP based PWM patterns

generated using both the technologies were tested using a

Prototype

Figure 12 Setup used for the experiment

Fig.13 Sample Gate Pulses

The output waveforms are captured and analyzed using power

profiler BMI 3030A and Figure 13 shows a sample pattern

out of the six patterns generated. It is observed the patterns

generated using both the technologies are almost same. The

above Sample Gate Pulses results are for a switching

frequency of 10 kHz and other specifications are as can be

seen in Code Composer

Compilation Report – FPGA based implemenation

Selected Device : 3s400pq208-4

Top Level Output File Name : pwm

Optimization Goal : Speed

Number of Slices: 1438 out of 3584 40%

No. of Slice Flip Flops: 221 out of 7168 3%

No. of 4 input LUTs: 2082 out of 7168 29%

Number of bonded IOBs: 17 out of 141 12%

Number of MULT18X18s: 6 out of 16 37%

NUMBER OF GCLKS 2 OUT OF 8 25%

Maximum cicuit delay time : 9.342ns

(5.960ns logic, 3.382ns route)

(63.8% logic, 36.2% route)

Total equivalent gate counts for design: 44,770

Output summary – DSP based implementation

Selected Device : TMS320F2812

Total no.of Instrution cycles: 167

% of CPU loading: 20.07 @ 40 MHz clock

Total Execution time: 417.5ns

VI. EQUIPMENT USED FOR MEASUREMENT

Measurements were made with power profiler BMI 3030A

that can measure and record the following parameters

Voltage and current imbalance

True power (W)

Apparent power (VA)

Reactive power (VAR)

True power factor

True rms current

Voltage and current harmonic distortion

Frequency

These measurements are displayed real time in the display

window. The instrument also gives reports in thermal paper. It

can process all measured data into graphical representations

for fast and accurate interpretation. More useful monitoring

information is available through the use of summaries over a

user selected interval between 1 to 60 minutes, and also

reports of graphical summation of specific data over user

selected intervals of one hour, one day, one week as required.

11.10.2007.

12:56:00 11.10.2007.

19:26:00

Relation 1 :

1

St+ (VA) Avg

Periodics (pertmp.mdt)

0

39.48

78.96

118.44

157.92

197.40

236.88

276.36

315.84

355.32

394.80

434.28

473.76

513.24

552.72

592.20

631.68

671.16

710.64

750.12

789.60

Pt+ (W) Avg Qti+ (VAr) Avg


511 | P a g e

Fig. 14 Load Variation

Fig. 15 Percentage Voltage THD

From the graphical representation, it is clear that

the level of percentage THD voltage is 7.43%

VII.HARMONIC PROFILE:

Fig. 16 PHASE –I VOLTAGE WAVE FORM

Fundamental-229.5 volts THD voltage 7.1%

Crest factor; 1.38

Table 1 Voltage harmonic content Phase –I

Fig. 17 PHASE –II VOLTAGE WAVE FORM


Crest factor; 1.4

Orde

r

% Amp

Or

der

% Am

p

Ord

er

% A

m

p

2 0.1 0.1 23 0 0 44 0 0

3 0.3 0.7 24 0 0 45 0 0

4 0 0 25 0 0 46 0 0

5 6.2 14.3 26 0 0 47 0 0

6 0.1 0.1 27 0.1 48 0 0

7 2.8 6.5 28 0 0 49 0 0

8 0.1 0.1 29 0 0 50 0 0

9 0.3 0.6 30 0 0 51 0 0

10 0 0 31 0 0 52 0 0

11 1.1 2.4 32 0 0 53 0 0

12 0 0 33 0 0 54 0 0

13 0.3 0.7 34 0 0 55 0 0

14 0 0 35 0.1 56 0 0

15 0.1 0.2 36 0 0 57 0 0

16 0 0 37 0 0 58 0 0

17 0 0 38 0 0 59 0 0

18 0 0 39 0 0 60 0 0

19 0.1 0.1 40 0 0 61 0 0

20 0 0 41 0 0 62 0 0

21 0 0.1 42 0 0 63 0 0

22 0 0 43 0 0

4.88 5.11 5.34 5.57 5.80 6.02 6.25 6.48 6.71 6.94

7.16 7.39 7.62 7.85

8.08 8.30 8.53 8.76 8.99 9.21 9.44

11.10.2007. 12:56:00 12.10.2007. 09:07:33 Relation 1 : 1

thdU1 (%) Avg

thdU2 (%) Avg

thdU3 (%) Avg

-340.0-304.7-269.4-234.1-198.8-163.4-128.1-92.8-57.5-22.213.148.483.7

119.1154.4189.7225.0260.3295.6330.9366.2 trigg time: 12.10.07. 13:17:44.62

V, A

X axis range: 419 pointstrigg + 222 points trigg + 640 points

-436.1-392.7-349.3-305.9-262.5-219.0-175.6-132.2-88.8-45.4-2.041.484.8

128.2171.6215.0258.4301.8345.2388.6432.0 trigg time: 12.10.07. 13:17:44.62

V, A

X axis range: 381 pointstrigg + 260 points trigg + 640 points


Vol. 1 (2011) No. 1, pp. 506-513

ISSN 2078-2365

512

Table 1 Voltage harmonic content Phase –II

Fig. 18 PHASE –III VOLTAGE WAVE FORM


Crest factor; 1.38

Table 1 Voltage harmonic content Phase –III

Fig.19 Harmonics Spectrum based on DSP

Though there is much difference in the final outcome of the

algorithm this attempt is made to throw light on the

advantages and superiority of FPGA based solution for

Industrial Drives. Speed and size are the parameters under

consideration. From the results listed above the total

execution time taken by DSP is obviously higher than the

circuit delay of the FPGA based implementation and

percentage of CPU loading of DSP warns the space

requirement. This is because of the inherent parallelism

present in the FPGA. Other advantages like rapid prototyping,

Orde

r

% A

mp

Orde

r

% Am

p

Orde

r

% Am

p

2 0 0.1 23 0 44 0 0

3 0.2 0.4 24 0 0.1 45 0 0.1

4 0 0 25 0 0 46 0 0

5 6.2 14.

1

26 0 0.1 47 0 0.1

6 0 0.1 27 0 0 48 0 0

7 3.4 7.9 28 0 0.1 49 0 0.1

8 0 0 29 0 0 50 0 0

9 0.3 0.7 30 0 0.1 51 0 0.1

10 0 0.1 31 0 0 52 0 0

11 0.7 1.6 32 0 0.1 53 0 0.1

12 0 0.1 33 0 0 54 0 0

13 0.2 0.4 34 0 0.1 55 0 0.1

14 0 0 35 0 0 56 0 0

15 0 .1 36 0 0.1 57 0 0.1

16 0 0 37 0 0 58 0 0

17 38 0 0.1 59 0 0.1

18 0 0 39 0 0 60 0 0.1

19 0 0.1 40 0 0.1 61 0 0

20 0 0 41 0 0 62 0 0

0 .1 .2 42 0 0 63 0 0

22 0 0 43 0 0.1

Or

de

r

% Amp

Order % Am

p

Order % Am

plit

ude

2 0.1 0.2 23 0.1 0.2 44 0 0

3 0.3 0.6 24 0 0.1 45 0 0.1

4 0.1 0.1 25 0 0 46 0 0

5 6.2 14.1 26 0 0.1 47 0 0.1

6 0 0.1 27 0 0 48 0 0

7 5.2 12 28 0 0.1 49 0 0.1

8 0 0.1 29 0 0 50 0 0

9 0.3 0.7 30 0 0.1 51 0 0.1

10 0 0 31 0 0.1 52 0 0

11 0.9 2 32 0 0.1 53 0 0.1

12 0 0.1 33 0 0.1 54 0 0

13 0.3 0.7 34 0 0.1 55 0 0.1

14 0 0 35 0 0 56 0 0

15 0.1 0.2 36 0 0.1 57 0 0.2

16 0 0.1 37 0 0 58 0 0

17 0 0 38 0 0.1 59 0 0.1

18 0 0 39 0 0 60 0 0.1

19 0 0.1 40 0 0.1 61 0 0

20 0 0 41 0 0 62 0.1 0.2

0 .1 .2 42 0 0 63 0 0

22 0 0 43 0 0.1

3.07 3.12

3.18

3.23

3.29

3.34

3.40

3.45

3.51

3.56

3.61

3.67

3.72 3.78

3.83

3.89

3.94

4.00

4.05

4.11

4.16

09.08.2007. 16:32:00 09.08.2007. 16:40:50

Relation 1 : 1

thdV1 (%) Avg

thdV2 (%) Avg

thdV3 (%) Avg



513 | P a g e

dynamic reconfiguration, high density integration and

availability of Intellectual Property (IP) cores facilitates

computationally intensive high performance Industrial Drives

to be realized at ease.

Fig. 20 Harmonics Spectrum based on FPGA

Harmonic Content is noted to verify the conformity of the

algorithm in both ways of implementation. Table shows the

Harmonic content at two different methods.

PARAMETERS DSP FPGA

Vrms 231.2 229.9

Total Voltage harmonic distortion 3.8% 2.09%

Voltage III harmonic 3.3% 1.6%

Voltage V harmonic 2.7% 1.9%

Voltage VII harmonic 1.6% 1.3%

Power factor 0.97 0.99

Frequency 48.2Hz 49.9Hz

Table 3 Harmonics comparison

VIII. Conclusion

This paper presents the implementation FPGA based series

active filter using TMS320F2812 DSP and

3s400pq208-4–SPARTAN III FPGA individually. The

algorithm was successfully implemented using both ways. As

the entire digital controller fits into a single FPGA device and

since the algorithm was implemented in terms of modules, the

results prompts to two specific conclusions. Firstly, all

specific modules needed for High Performance drives can be

coded in any HDL and kept as a library of reusable IP cores.

As per necessity, modules can be chosen and interconnected

to implement the desired algorithm. Secondly, the comparison

of the results from FPGA with the existing solution namely

DSP based implementation in terms of size (memory) and

execution time confirms the possibility of proposing any

complicated algorithm and their realization on a System on a

Chip (SoC) with fastest execution time, less space and less

time to market. This work was carried out to assess the

possibility of complete digital realization that has become

successful and have been realized as individual modules.

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02.10.2007. 19:55:45 1.83 1.85 1.87 1.88 1.90 1.92 1.94 1.96 1.98 1.99 2.01 2.03 2.05 2.07 2.09 2.11 2.12 2.14 2.16 2.18 2.20

02.10.2007. 19:45:00 Relation 1 : 1

thdU1 (%) Avg

thdU2 (%) Avg

thdU3 (%) Avg


FPGA BASED SERIES ACTIVE FILTER FOR POWER QUALITY ENHANCEMENT

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