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This document is the pre-print version of the final paper:

Naouar, M.-W.; Monmasson, E.; Naassani, A.A.; Slama-Belkhodja, I.; Patin, N., "FPGA-Based Current Controllers for AC Machine Drives—A Review," Industrial Electronics, IEEE Transactions on , vol.54, no.4, pp.1907,1925, Aug. 2007

doi: 10.1109/TIE.2007.898302

keywords: AC motor drives;PI control;digital control;electric current control;field programmable gate arrays;on-off control;AC machine drive;FPGA-based current controller;digital controller;field-programmable gate array;hardware architecture;on-off current controller;predictive current controller;proportional-integral current controller;AC machines;Control systems;Costs;Digital control;Digital signal processing;Field programmable gate arrays;Hardware;Proportional control;Signal processing algorithms;Torque;Alternating current (ac) machine drives;current control;field-programmable gate array (FPGA);hardware architecture design, URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4271569&isnumber=4265775

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FPGA-Based Current Controllers for AC Machine Drives – A Review

M-W. Naouar1, Student Member, IEEE, E. Monmasson2, Senior Member, IEEE, A. A. Naassani3, I. Slama-Belkhodja4, and N. Patin5, Student Member, IEEE

1,4L.S.E-ENIT BP 37-1002 Tunis le Belvédère, Tunisia, email: wissem_naouar@yahoo.fr1, ilhem_slama@enit.rnu.tn4

2SATIE-IUP GEII, rue d’Eragny, 95031 Cergy-Pontoise, France, email: eric.monmasson@iupge.u-cergy.fr

3SATIE, Université d’Alep-Syrie, email : ammar.naassani@iupge.u-cergy.fr

5SATIE-ENS Cachan/CNRS, 61 avenue du Président Wilson, 94235 Cachan, France, email: patin@satie.ens-cachan.fr

AbstractThe aim of this paper is to present the interest of implementing digital controllers using FPGA components. To this purpose, a variety of current control techniques, applied to AC machine drives, is designed and implemented. They consist of ON-OFF current controllers, PI current controller and predictive current controller. The quality of the regulated current is significantly improved. It is mainly due to a very important reduction of the execution time delay. Indeed, in all described techniques, the execution time of the designed hardware architectures is only of a few microseconds. This time reduction derives directly from the possibility offered by FPGAs to design very powerful dedicated architectures. Numerous experimental results are given in order to illustrate the efficiency of FPGA-based solutions to achieve high performance control of electrical systems.

I. INTRODUCTION

During these last twenty years, the control of industrial electrical systems has been the focus of important research and many significant improvements have been achieved [1], [2]. These progresses are mainly due to the technology revolution leading to very powerful components which allow implementing more and more complex control algorithms. With successively improving reliability and performance of digital technologies, digital control techniques have predominated over their analog counterparts. Indeed, compared with traditional analog control, digital control offers many advantages such as flexibility to modify the control schemes, adaptability to different systems and operating conditions, immunity to noise and insensitivity to component variations. Nowadays, digital control techniques are mostly carried out with microcontrollers or Digital Signal Processors (DSP) due to their software flexibility and low cost. Thus, DSP-controllers are considered by many engineers as an appropriate solution [3]. These components have an ALU (Arithmetic Logic Unit) especially dedicated to the real-time computation. They also integrate peripheral units like Analog-to-Digital Converter (ADC) and Timers which are adapted to the needs of electrical system drives. Nevertheless, some advantages of the analog control are still very difficult to be replaced such as accuracy and most of all, no feedback loop delays. In fact, although multiprocessor schemes or high performance DSP processors can deal with this problem, they are still limited for complex algorithm structures and their costs can exceed the benefit they bring [4].

Field Programmable Gate Array (FPGA) can also be considered as an appropriate solution [5] in order to boost performances of controllers and consequently to reduce the gap between the analog and digital world. When associated to fast ADC, the extremely fast computation capability of FPGAs allows a few microseconds real-time computation of control algorithms in spite of their complexities. On the other hand, FPGAs allow the development of well adapted control architecture with freely positioned sampling instants [8], [9]. In the same time they allow the implementation of different control functions for a full System on Chip (SoC) integration [5]-[7]. As a result, FPGAs are quite mature for the electrical

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drive applications. They have already been applied with success to the control of PWM converters [10], machine drives [11], [12] and even to multi-machine control system [13]. Furthermore, as DSP-controllers, FPGAs are very low cost components. Even recently, a company has also introduced an FPGA family that includes several analog functions, such as an ADC [14].

Hence, having in mind to make a synthesis of these reported advantages and also to include new ones, the authors present in this paper a systematic description of a relevant set of FPGA-based current controllers applied to AC machine drives. These types of applications are good examples of high level real-time performances industrial control systems.

An FPGA implementation of ON-OFF current controllers is firstly exposed. Two groups of controllers are analyzed and synthesized. The first group is characterized by a variable switching frequency, while the second one is based on a limited switching frequency. Using FPGA-based controllers permits to improve significantly the quality of the current waveforms due to their very small execution time. In these conditions, the obtained digital current controllers can be approximated quite closely to their analog counterparts.

A PI current controller is then synthesized. It also consists in putting in evidence the contribution of the freely positioned sampling instants to enhance the control performances. Once again, the very small execution time permits the development of a non synchronous PWM strategy which means that the voltage references are refreshed at very high sampling rate (up to 200kHz). This high rate voltage reference refreshment has a great interest for high power applications where low switching frequency is required.

After that, the development and FPGA implementation of a synchronous machine predictive current controller is presented. As known, predictive current controllers require complex on-line computation schemes [15]-[18]. Therefore, the digital implementation of a predictive current controller is characterized by an inevitable delay between the current sensing instant and the moment where the adapted Voltage Source Inverter (VSI) voltage vector is ready to be applied. The control performance in this case depends strongly on the computation time, which must be shorter enough with respect to the sampling period [19]. Otherwise, if the computation time is not short enough, complex algorithmic modifications are needed to ensure basic level performances for the system to be controlled [20], [21]. The proposed FPGA-based predictive current controller ensures a real-time voltage vector computation without adding any algorithmic modifications. In this case, the whole execution time (including AD conversion) is only equal to 4.52µs.

However, reaching a high level of control performances can only be obtained with the help of important design efforts. That is the reason why, authors present in a dedicated section an appropriate FPGA-based design methodology. It results from a necessary compromise solution between two opposite needs: a friendly design environment that does not afraid the non-expert micro-electronics designer and the full respect of control performance requirements.

All the studied current controllers were tested with the experimental set-up presented in Fig. 1. The generic architecture of all these controllers includes the current controller itself, the AD (Analog-to-Digital) and DA (Digital to Analog) converter interfaces and the RS232 serial Universal Asynchronous Receiver Transmitter (UART) interface, leading to a full SoC integration.

Numerous experimental results are presented, which clearly illustrates the benefits and the effectiveness of the proposed FPGA-based current controllers.

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Fig. 1. Synoptic of the experimental set-up

II. FPGA DESIGN METHODOLOGY

FPGA technology allows developing specific hardware architecture within a flexible programmable environment. Comparing to standard architecture of microprocessors and DSPs, this specificity of FPGAs gives to the designer a new degree of freedom since he can build dedicated hardware architectures that match all the requirements in terms of control performances and implementation constraints. Thus, these dedicated architectures are designed on the basis of a perfect adequation between the control algorithm to be implemented and its final hardware realization, allowing for example to preserve all the potential parallelism of the chosen algorithm.

However, in many cases, the design of FPGA-based controller architectures is rather intuitive and require from the designer to master several different knowledges (micro-electronics, control and electrical machines theories). It is particularly true for complex algorithm structures such as the ones found in drive control applications. This naturally leads many control engineers to prefer standard implementations like DSP solution. Thus, in order to make the design of control algorithms more manageable and less intuitive, the designer has to strictly follow a set of steps and rules, which consist in an efficient design methodology. The main characteristics of this kind of methodologies are the reusability of the already made designs, the optimization of the consumed resources of the targeted component, the respect of the control performances and finally the reduction of the development time.

Several authors have already presented interesting design methodologies [22]-[26]. All of them are based on a friendly development procedure where reusability is always of prime importance. As it will be shown in the next paragraphs, the specificity of the proposed methodology depends on the fact that it has been designed having always in mind that the control engineer is not a micro-electronics expert. That is the reason why, an important part of the design steps is achieved within the Simulink-Matlab friendly environment. However, another key-point is that priority is given to the respect of control performances and as a consequence the final hardware architecture needs to be optimized. Therefore, using Matlab does not means here, that the VHDL (Very high speed integrated circuit Hardware Description Language) [27] code is automatically generated with toolboxes proposed by the main FPGA manufacturers, since it necessarily leads to an unoptimized solution in terms of consumed resources. Hence, in the proposed approach, the designer has to code his own architecture in VHDL but he is strongly helped by the Algorithm Architecture Adequation (A3) [28] technique as explained later. As a conclusion, this design methodology is a balanced solution between two opposite needs: a friendly method that does not afraid the non-expert designer and the respect of control performance requirements that necessarily leads to substantial efforts during the design procedure. The main steps of the design methodology are now presented.

FPGA

A/D θdq isa isb

Encoder Host PC

RS232

3-phases VSI

UART

Sa Sb Sc

E

AC machine

Current controller

DA Interface

AD Interface

D/A Scope

RS232

Rectifier 400V/50Hz

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A. Modular Partitioning of the Control Algorithm

This step is crucial when working on complex algorithms. It is aimed to reduce the design cycle also called “time to market”. It consists in partitioning the whole control algorithm into sub-parts called modules, which are easier to develop and, which make sense from a functional point of view. This can be done by identification and extraction of several reusable and independent modules such as regulators, modulation functions, estimators and vector operators according to the hierarchy and regularity concepts [5]. Hierarchy is used to divide a large or complex design into sub-parts that are more manageable. Regularity is aimed to maximize the reuse of already designed modules.

Fig. 2. Specific library of reusable modules

However, in the same time, the designer has to also verify that the chosen algorithm modular partitioning satisfies the integration criterion. This criterion consists in the fact that the implementation process is constrained by the hardware resources of the targeted component. As it will be shown later, an optimization procedure is driven to this purpose [28]. It leads to consume less hardware resources. However, as it is applied separately to each extracted module, greater is the number of extracted modules, lower is the level of performances in terms of hardware resources consumption. Therefore, if the hardware constraints are not satisfied, designer has to reduce the number of extracted modules, even if a certain degree of reusability is lost.

As a result, different reusable modules, with different levels of abstraction, can be extracted and added to a specific library of control of electrical systems. This library, available in [29] but still under construction, is constituted of three main hierarchical levels as shown in Fig. 2. From the experience of the authors, these three hierarchical levels are sufficient to fully characterize the different functions used in the control of electrical systems. The first or lowest hierarchical level includes fine grain operators such as registers, and arithmetic operators (adders, multipliers,…). The second or middle level comprises the modules of the most common used functions in the control of electrical systems such as anti-windup Proportional Integral (PI) controller, Pulse Width Modulations (PWM), (abc-to-dq) transformation,… These modules are built using the first level operators. Finally, the whole control algorithms constitute the third or highest hierarchical level of the library. These blocks are developed using both first and second level modules.

B. Simulation and Algorithm Refinement Procedures

Registers, multiplexers, demultiplexers…

Adder, multipiler, sine-cosine, cordic…

Basic operators Arithmetic operators

PI, PID, Hysteresis controller… Regulation

PWM, SVM…

Modulation

PLL, Torque estimator, Flux estimator…

Estimation

abc-to-αβ, αβ-to-abc, abc-to-dq, dq-to-abc …

Vector operators

Current control, Torque control, Speed control… Full control algorithms

LEVEL 3

LEVEL 2

LEVEL 1

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As mentioned earlier, the simulation procedure is performed under Matlab-Simulink software environment. It is aimed to:

- Verify the functionality of the complete control application,

- Find the suitable sampling period and fixed-point format refinement for each control variables according to the needed control performance constraints.

The functionality verification can be achieved by the development of a functional model using Simulink time-continuous blocks. Then, the parametrization of the per unit digital algorithm is performed by studying the influence of the sampling period and the effects of the chosen fixed-point format. Note that, the choice of the fixed-point format can be derived from adapted methods [30], [31]. At this level, the simulation is realized by the development of a digital fixed-point specification model using System Generator toolbox [32]. A Data Flow Graph (DFG) is then defined for each extracted second level module. DFG is a graphical representation of the algorithm, which includes no timing specifications regarding its expected implementation. It is composed of nodes and edges. Each node represents a simple arithmetic operation or a simple mathematical or logical function and each edge corresponds to a data transfer. For example Fig. 4(a) shows the DFG of a simple 2nd level algorithm characterized by the following simple function

y(t)=A1x1(t)+A2x2(t) (1)

As it can be seen in the associated DFG, the two multiplications can be performed in parallel mode, but the addition depends on the results of the two multiplications and consequently must be done only when the multiplications are achieved. Therefore, DFG clearly shows the data dependencies and the potential parallelism of the considered algorithm.

Fig. 3 represents the different mentioned steps. It can be noted that, up to now, no choice has been made regarding the targeted component since modular partitioning and fixed-point refinement is also applicable to DSP-controllers [33].

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Fig. 3. Development of DFGs

C. Optimization Procedure

The optimization procedure is based on the A3 methodology [28]. The aim of this methodology, when applied to FPGA-based designs, is to find out an optimized hardware architecture for a given application algorithm, while satisfying size and timing constraints. In each DFG, some operations are used several times. If an operator is repeated n times, the A3 factorization process applied to this operator consists in keeping only m realizations of this operator with m < n. Most of the time m is equal to one. Operator has to be understood here as the hardware support of a given operation. The A3 methodology is generally applied to the greediest operators in terms of hardware consumed resources like multipliers. The result of the DFG factorization is the Factorized Data Flow Graph (FDFG).

Fig. 4. Example y(t)=A1x1(t)+A2x2(t) (a) DFG (b) FDFG

For example, Fig. 4(b) presents a FDFG example where the factorization process is applied to the multiplier operator. Note that, the factorization process reduces the hardware consumed resources, but increases the computation time. The final graph, which will be used for the design of the hardware architecture, is thus the result of a compromise between computation time and hardware consumed resources amount. For many electrical system controllers the used sampling period is much greater than the computation time delay. In these cases, objective number one is the reduction of the hardware consumed resources.

Modular Partitioning Reusability Regularity Integration criterion

Matlab Simulink

Verification of the complete application functionality

Choice of the fixed point formats and sampling period

DFG 1

Module (k-1) Module k Module 2 Module 1

Control Algorithm

DFG 2 DFG(k-1) DFG k 2nd Level Library

Simulink

System Generator

Specification model

Functional model

Simulation

FPGA Blocks

Data Flow Graphs

1st Level Library

Simulink Blocks

x x

x1(t)

+

s[n/Q(n-1)] A1 A2 x2(t)

s[n/Q(n-1)]

y(t)

(a) (b)

x x1(t) A1

x2(t) F F

J

+

y(t)

A2

F : Fork J : Join

Factorization Hardware Resources Computation time

Defactorization Hardware Resources Computation time

s[n/Q(n-1)] s[n/Q(n-1)]

s[n/Q(n-1)]

s[n/Q(n-1)]

s[n/Q(n-1)] s[n/Q(n-1)]

s[n/Q(n-1)]

s[n/Q(n-1)] s[n/Q(n-1)]

s[n/Q(n-1)] s[n/Q(n-1)]

s[n/Q(n-1)]

s[n/Q(n-1)]

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D. Modular Hardware Architecture Design

A data-path and a control unit are defined for each module of the library. The data-path of the architecture is always obtained by replacing each node of the final graph with its corresponding operator and every edge with a data bus between operators. Data bus transfers are managed by a control unit, which is a simple Finite State Machine (FSM). Fig. 5(a) and Fig. 5(b) present the architecture corresponding respectively to the DFG and FDFG of Fig. 4. It can be noted that the obtained data-paths are the quasi-copies of their corresponding graphs and that the latency of the factorized architecture is greater than the defactorized one.

Fig. 5. Derived architectures from (a) DFG (b) FDFG

Each developed module of the library is characterized by its inputs and outputs formats, degree of reusability, latency and communication protocol. All these specifications must be clearly indicated in data-sheets for easy reuse of the developed modules architectures. Fig. 6 presents the general structure of reusable module architecture corresponding to a second hierarchical level. The data-path is made of elementary operators such as adder, multiplier, multiplexer, register,… The data transfers between these elementary operators are managed by a control unit, which is synchronized with the clock signal (Clk). The control unit of a module is always activated via a Start pulse signal. When the computation time process is over, an End pulse element signal indicates to the global control unit that the data outputs of the module are ready to be used.

Fig. 6. (a) Generic module architecture (b) Timing diagram of the module

x

A1

y[k]

A2

+

Sel Sel en0

en0

en0

en0

en2 en1

en3

en0

en1

en2

en3

Sel

Data-Path Controller

Module architecture

x1[k]

x2[k]

Clk Reset Clk Reset

Start End

Multiplexer

Register

Wait

en0=1 Sel=0

Sel=0 en1=1

Sel=1 Sel=1 en2=1

en3=1

End=1

Reset

Start A1

y[k]

A2

+

en0

en1

en0

en1

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Data-Path Controller

Module architecture

x1[k] x2[k] Clk Reset

Start End

Wait

End=1

Reset

Start

x

en0 en0

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en0

en0=1

en1=1

Clk Reset

Register

(a) (b)

(b) (a)

Data-path

Control unit

S1 S2

S3 S4

Module name

Input Data

Output Data

Start End

Clk

Inputs(k) Inputs (k+1) Inputs (k+2)

Start

Input Data

Outputs (k) Outputs (k+1) Outputs (k+2)

End

Output Data

Clk

TClk Latency*TClk

Reset

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As for the development of the hardware architecture of a third hierarchical level module, it is performed using the blocks of the first and second hierarchical levels of the library. The data-path is therefore a combination of the instantiations of second and first level modules, which are linked with data-buses. At this level, the architectures of the second hierarchical level modules can be considered as thick grain operators. An A3 factorization process can be once again applied to these thick operators. For example, if the control algorithm includes two PI controllers, the designer can freely choose to use only one factorized PI controller. The second level modules are easy to handle thanks to their Start and End flags. The coordination between these modules is done by a global control unit that activates their local control units at well defined moments as shown in Fig. 7. The global control unit is also activated by a Start pulse signal and generates an End pulse signal when the computation of the data outputs is finished. With such structure, the third level module can be also managed in the same way inside an upper hierarchical level architecture. The architecture of each hierarchical level module is then coded via a structural approach with an hardware description language such as VHDL.

Fig. 7. Architecture of a 3rd hierarchical level module of the library

E. Validation of the Designed Architecture

The first validation step is a co-simulation procedure performed using Modelsim and Matlab software tools. This step allows verifying the good functionality of the designed architecture written in VHDL by testing it with a relevant set of testbench input waveforms. The second validation step, at system level, is done via an hardware in the loop procedure. This procedure is aimed to ensure a first experimental attempt guarantee. It is carried out through the hardware implementation of a test architecture, which is composed of three main modules (See Fig. 8). The first one generates the stimuli patterns, which are stored in FPGA memory blocks. These stimuli patterns are directly derived from the simulation phase, enabling further comparisons with the simulated system. The second module is the architecture to be tested and the third module is a communication interface module that manages a communication link between the FPGA and a host PC. The computed outputs of the architecture to be tested are gathered and sent to the host PC by the communication interface module in order to be compared, in the graphical environment of Matlab, to the simulation results. Once this test procedure is validated, the designed architecture is ready for its actual environment.

Fig. 8. Hardware in the loop procedure

Global Data-path

Input Output

Module Name

Sub-Module 1

Start1 Start2 Start3 Startn End1 End2 End3 Endn

Start End

Clk

Sub-Module 3

Sub-Module 2

Reset

Sub-Module n

Global Control Unit

Sel

M

U

en

Stimuli Patterns (Simulation)

Architecture to be tested

FPGA Target

Configuration link

Communication Interface

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In the next sections, the design of a set of FPGA-based current controllers for AC machine drives applications is going to be presented. These current controllers are ON-OFF current regulators, PI current controller and predictive current controller. All these controllers are realized with the help of the proposed design methodology and in each case benefits and performances of FPGA implementations are presented and discussed.

III. CURRENT CONTROL OF AC MACHINE DRIVES BASED ON ON-OFF REGULATORS

The ON-OFF current control strategies are the simplest current regulation schemes used for the current control of AC machines. They can be classified into two main groups. The first one is based on hysteresis comparators and is characterized by a variable switching frequency [34]. The second one is a special class of the ON-OFF current regulators, which is based on the delta modulation principle [34], [35] and characterized by a limited switching frequency. In the following, the FPGA implementation of AC machine drives current controllers based on these two classes of ON-OFF regulators is analyzed. Specificities of an FPGA implementation solution are also discussed. A. Current Control of AC Machine Drives Based on Variable Switching Frequency ON-OFF Regulators The aim of current controllers based on variable switching frequency ON-OFF regulators is to keep the instantaneous current inside a tolerance band with regard to the reference current. In this paragraph, the FPGA implementation of a space vector based ON-OFF regulator is presented and discussed. The corresponding block scheme is shown in Fig.9. It consists into a space vector based regulator with three level hysteresis comparators and look-up table working in the α-β reference frame.

Fig. 9. Current control of AC machine drives based on variable switching frequency ON-OFF regulators

(a) Block scheme of a space vector based regulator with three level hysteresis comparators and look-up table working in the α-β reference frame (b) Corresponding current error locus

The implementation of such current control techniques is generally made using analog technology. In fact, the instantaneous response of analog controllers allows the vector of the current error to stay within the expected limits. The sensed currents are firstly converted by AD converters and then the switching states resulting from hysteresis comparison are computed digitally. So, if the whole execution time, including analog-to-digital time conversion, is consequent, the current error will exceed the hysteresis band limits. Nevertheless, these current control techniques can also be performed using digital technology such as FPGAs. Indeed, when associated to fast analog-to-digital converters, the high computation capabilities of FPGAs allow avoiding any additional delays within the feedback loops as it will be shown in the next paragraph.

1) FPGA Implementation of Current Control Techniques Based on Variable Switching Frequency ON-OFF Regulators: Fig. 10 presents the developed hardware architecture corresponding to the current control algorithm presented in Fig. 9. The architecture presented in Fig. 10 is the result of a modular partitioning, which includes four second level modules. Among them, two reusable modules can be extracted: the (abc-to-αβ) transformation and the three level hysteresis comparator. It can be noted that, in this architecture, the (abc-to-αβ) transformation module is used two times. A

(b)

+Δhβ/2

β

-Δhβ/2

-Δhα/2 +Δhα/2

(1,1) (-1,1) (0,1)

(1,0) (-1,0)

(0,0)

(1,-1) (0,-1)

(-1,-1)

Δisα

Δisβ Δis

is*

is

α

(X, X) : Sα Sβ levels X : -1, 0, 1 E

AC Machine

Table

Sa Sb

Sc

Sα

Sβ

αβ abc

isa isb isc

+

- +

-

abc

αβ

Δisα

Δisβ

|Δisb|< |Δisc| isb

* isc

* isb isc

isα isβ

isα*

isβ*

isa*

isb*

isc*

(a)

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factorization process could therefore be applied to this module if the hardware constraints of the FPGA target were not satisfied.

Fig. 10. AC machine drive current control architecture of a space vector based regulator with three level hysteresis

comparators and look-up table working in the α-β reference frame

The global control unit of the architecture presented in Fig. 10 is a simple FSM that controls the AD interface module and the ON-OFF current controller module. It is activated via a Start signal and it generates an End signal when the computation of the switching states is achieved. The AD interface module controls the AD conversion process. The architecture of the ON-OFF current controller is third level module and is managed by its own control unit. The computation of the switching states is made in a sequential way. Fig. 11 presents the proposed sequential timing diagram for the switching states computation. Such timing sequences can be easily done by forcing the Start signal of the global control unit presented in Fig. 10 at a permanent active level. For each computation cycle, the global control unit activates in parallel mode the AD interface module and the ON-OFF current controller module via respectively Start_AD and Start_OO signals. The computation time of the architecture presented in Fig. 10 is lower than the AD conversion time tAD. For this reason, the FSM of the global control unit waits on an End_AD signal that indicates the achievement of the AD conversion process to generate an End signal and to restart a new computation cycle. As a consequence, the sampling period Ts is equal to the AD conversion time tAD. Fig. 11 presents the succession of the different operations for the generation of the switching states Sa, Sb and Sc via the architecture shown in Fig. 10. At the instant tk, which corresponds to the beginning of the kth sampling period, the stator currents are sampled and the AD conversion process activated. In the same time, the ON-OFF current controller module is activated. The control unit of this module activates firstly the two (abc-to-αβ) transformation modules. These two modules are activated in parallel mode and have a same computation time equal to tC. They compute the αβ components of the sensed stator currents and of the reference ones. When the computation of the (abc-to-αβ) transformations is achieved, the module of the three level hysteresis comparators is activated in parallel mode with the module that compares the absolute values of the errors Δisb and Δisc. These modules compute the Sα, Sβ and S comparison results. Finally, the table module is activated and, after a computation time equal to tT, the switching states Sa, Sb and Sc of the kth sampling period are applied to the VSI.

Fig. 11. Sequential timing diagram of a current control technique based on variable switching frequency ON-OFF regulators

(Space vector based regulator with three level hysteresis comparators and look-up table working in the α-β reference frame)

AD Control

isα*

isβ*

isa*

isb*

isc*

abc-to-αβ

abc-to-αβ

Sα

Sβ

isα isβ

3 level hysteresis

comparators

Table

isb* isc

* isb isc

AD Interface

isaAD

isbAD Sa Sb Sc

Δhα&Δhβ

Global control unit

Algorithm control unit

Start End

Clk

Clk

Clk

isa isb isc |Δisb|<|Δisc

|

Clk Clk

Clk

Clk

Clk

Start_OO End_OO

End_AD Start_AD ON-OFF Current controller

S

wait

Start_AD=’1’ wait

End=’1’

Start_OO=’1’

Start=’1’

Reset End_AD=’1’

Global control unit FSM

tk

tk-1

tAD

Tex

Sample isa[k] isb[k]

tk+1

Sample isa[k+1] isb[k+1]

Application Sa,b,c[k-1]

Application Sa,b,c[k]

Sample isa[k-1] isb[k-1]

tC tH3 tT

tAD tC tH3 tT Application

Sa,b,c[k+1]

tC tH3 tT tAD Tex=tAD + tC + tH3 + tT Ts

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Thus, compared to the case of DSP or microcontroller solutions where the sampling period cannot be lower than the execution time, the use of FPGA solutions allows measuring the stator currents with a sampling period Ts only equal to the AD conversion time tAD. It can be also noted that, with regard to the beginning of each sampling period, the switching states are not applied instantaneously but after an execution time delay Tex equal to the sum of the AD conversion time and the ON-OFF current controller module computation time. As it will be shown in the next paragraph, the performances of current controllers based on variable switching frequency depend strongly on the obtained execution times.

2) Experimental Results: The experimental procedure is performed using the experimental set-up presented in Fig. 1. A low cost Xilinx SPARTAN3 XCS400PQ208 FPGA, that contains 400.000 logical gates and includes a 50 MHz oscillator (Clock period TCLK equal to 20ns), was used as target component for the implementation of the control architectures.

TABLE I

FPGA TIME/AREA PERFORMANCES OF THE CURRENT CONTROL ARCHITECTURE BASED ON SPACE VECTOR BASED REGULATOR WITH THREE LEVEL HYSTERESIS

COMPARATORS AND LOOK-UP TABLE WORKING IN THE α-β REFERENCE FRAME

Modules Latency Computation time abc-to-αβ 5 tC = 0.1 µs

3-Level hysteresis comparators 4 tH3 = 0.08 µs

|Δisb|<|Δisc| 4 tH3 = 0.08 µs Table 3 tT = 0.06 µs

Execution time = tAD +tC+tH3+tT Tex = 2.64 µs Consumed resources 21%

Table I presents the FPGA time/area performances of the designed architecture. The consumed resources are obtained for a 13 bits fixed-point format, which has been determined after simulation tests. The AD conversion process time tAD is equal to 2.4 µs. The whole computation time of the ON-OFF controller takes only 0.24 µs. The corresponding execution time is therefore of 2.64 µs. Consequently, the high computation capabilities of FPGAs allows obtaining an execution time of the order of the IGBT power switches dead-time. Thus, the corresponding digital feedback loops can be approximated quite closely to an analog one because the effects of sampling and computing delays are very negligible.

Fig. 12. Experimental results for the digital implementation of space vector based regulator with three level hysteresis comparators and look-up table working in the α-β reference frame (Is=Isn,

ΔHα=ΔHβ=0.8A, E=540V) (Left side) Ts=tAD and Tex=2.64µs (right side) Ts=Tex and Tex=50µs

ΔHα

Δisα

isα

ΔHα

Δisα

ΔHβ

Δisβ isβ

isα

ΔHβ

Δisβ isβ

ΔHα

Δisα

isα

ΔHα

Δisα

isα

20 ms

20 ms

20 ms

20 ms

20 ms 20 ms

13

In order to illustrate the effects of the computation time delays on the performances of current control techniques based on variable switching frequency ON-OFF regulators, experimental results corresponding to the obtained execution time in Table I are compared to experimental results obtained with an execution time forced to 50 µs and with a sampling period equal to the execution time. Fig. 12 presents the experimental results obtained for the FPGA implementation of AC machine drives current controller based on three level hysteresis comparators and look-up table working in the α-β reference frame. The experimental results presented in the left side of Fig. 12 are obtained for an execution time equal to 2.64 µs. In the right side of Fig. 12 are presented the obtained experimental results for an execution time forced to 50 µs. These results show that, with an execution time of 2.64 µs, the Δisα and Δisβ instantaneous current error waveforms are kept inside the tolerance band imposed by the three level hysteresis comparators, which is not the case for a computation time delay of 50 µs. B. Current Control of AC Machine Drives Based on Limited Switching Frequency ON-OFF Regulators The limited switching frequency ON-OFF regulators are a special class of ON-OFF regulators. They are based on the delta modulation current control technique [35]. Although this technique looks quite similar to that of current control techniques based on variable switching frequency ON-OFF regulators, the corresponding operating principle is quite different. In fact, the hysteresis comparators are replaced by sign comparators and the switching states are applied every sampling period. Consequently, only the change of error sign is detected by the sign comparators and the switching states are sampled at a fixed rate. As consequence, the applied VSI voltage vector is kept constant during each sampling period and the VSI switching frequency is not exceeding the sampling one. This guarantees safe operation of the VSI semiconductor power devices. In the other hand, the limited switching frequency ON-OFF regulators have a simple structure, which is well adapted for both analog and digital controls. However, due to the sampling mode operation, the current ripples are not constant and depend on the load parameters, the dc-link voltage and the used sampling frequency. Fig. 13 presents the obtained delta current controller. It can be noted that, in Fig. 13, the three level hysteresis comparators of Fig. 9 are replaced by a three level sign comparators and the switching states are sampled every sampling period Ts.

Fig. 13. Current control of AC machine drives based on limited switching frequency ON-OFF regulators,

block scheme of a space vector based regulator with three level sign comparators and look-up table

1) FPGA Implementation of Current Control Techniques Based on Limited Switching Frequency ON-OFF Regulators: Due to the high flexibility of FPGA-based solutions, the development of the FPGA architecture corresponding to the current controller presented in Fig. 13 can be easily built reusing the architecture presented in Fig. 10. Only few modifications are required. It consists in fixing the hysteresis band values to zero, changing the global control unit operating mode and changing the activation mode of the Start signal.

Fig. 14. FSM of the global control unit for limited switching frequency ON-OFF regulators

Fig. 14 presents the developed FSM of the global control unit. Comparing to the case of variable switching frequency ON-OFF regulators, the AD interface module and the current controller algorithm module are not activated at the same time but

AC Machine

E

Table

Sa Sb

Sc

Sα

Sβ

αβ abc

isa isb isc

+

- +

-

abc

αβ

Δisα

Δisβ

|Δisb|< |Δisc| isb

* isc

* isb isc

isα isβ

isα*

isβ*

isa*

isb*

isc*

Ts

wait

Start_AD=’1’ wait

End=’1’

Start=’1’

Reset

Start_OO=’1’

wait

End_AD=’1’

End_OO=’1’

14

in a sequential mode. The Start signal is not forced to an active level but it becomes an active pulse signal with a sampling period equal to Ts. This leads to the sequential timing diagram presented in Fig. 15, which characterizes the FPGA implementation of a current control technique based on limited switching frequency ON-OFF regulators.

Fig. 15. Sequential timing diagram of a current control technique based on limited switching frequency ON-OFF regulators

(Space vector based regulator with three level sign comparators and look-up table working in the α-β reference frame)

Each computation cycle is activated by an active pulse of the Start signal. This signal activates the global control unit, which activates firstly the AD interface module. Then, it waits on the End_AD signal that indicates the achievement of the AD conversion. After that, the ON-OFF current controller module is activated and it computes the switching states. A new computation cycle is activated at the next Start active pulse. The whole execution time Tex is the sum of the AD conversion time and current control algorithm module computation time. The computation processes are activated every sampling period Ts, which is greater than the execution time Tex. Consequently, the produced switching states are applied every sampling period Ts and, as a result, the switching frequency is limited to the sampling one. With regard to the analog controllers, the switching states are not applied instantaneously, but after a computation time delay equal to Tex.

2) Experimental Results: The FPGA implementation performances of the considered current controller of AC machine drives based on limited switching frequency ON-OFF regulators are similar to those presented in Table I. As mentioned previously, current controls of AC machine drives based on limited switching frequency ON-OFF regulators are characterized by current ripples, which are not constant, but depending on the load parameters, the dc link voltage and the used sampling frequency. In the case of digital controllers, the current ripples depend also on the digital computation time delay Tex. In order to illustrate this point, experiments are carried on the experimental set-up presented in Fig. 1 for different execution times.

Fig. 16. Experimental results for the digital implementation of limited switching frequency ON-OFF regulators

(A space vector based regulator with three level sign comparators and look-up table)

(Is=Isn, E=540V) (1) Stator current isa (2) Square current vector error (Δisα²+Δisβ²)

During experiments, the used sampling period Ts was fixed to 100 µs and experimental results corresponding to the obtained execution time of Table I are compared to those corresponding to an execution time forced to 50 µs. Fig. 16 shows the difference between the obtained experimental results. It clearly shows that the stator current ripples increase significantly when a non negligible computation delay exists. Once again, the use of FPGA solutions is advantageous. In fact, the high computation capabilities of FPGA components allow realizing almost real time feedback loops and, consequently, the current ripples dues to the computation time delays are negligible. In this case, the obtained control performances are quite similar to those of analog controllers.

IV. CURRENT CONTROL OF AC MACHINE DRIVES BASED ON PI CONTROLLERS

Ts

tAD tAD

tk

Application Sa,b,c[k]

Sample isa[k] isb[k]

tk+Tex tk+1

Application Sa,b,c[k+1]

Sample isa[k+1] isb[k+1]

tk+1+Tex

Fs

Start

tC tH3 tT tC tH3 tT

Ts Tex Tex=tAD + tC + tH3 + tT

(1) (2) (2) Tex=50 µs Tex=2.64 µs Tex=2.64 µs

THD=8.4 %

10 ms 10 ms

20 ms

(1) Tex=50 µs

THD=11.1 %

20 ms

15

A. Vector Current Control Principle of AC Machine drives Fig. 17 illustrates the principle of a classical vector current control of AC machine drives. It involves the use of two Anti-windup Proportional Integral (PI) controllers applied to each component of the current vector in a d-q synchronous reference frame. The PI controllers calculate the d and q components Vsd

* and Vsq* of the voltage vector reference. Using

the dq-to-abc coordinate transformation, the three phase reference voltages Vsa*, Vsb

* and Vsc* are then computed. They

serve as references for the PWM modulator. In this work, the used PWM modulator is a carrier based PWM with zero-sequence signal addition [36]. In the following, new digital control proprieties are presented thanks to a FPGA-based implementation of a vector current controller of AC machine drives.

Fig. 17. Vector current control of AC machine drives working in the d-q synchronous reference frame

B. FPGA Implementation of a Vector Current Control of AC Machine Drives

Fig. 18 presents the developed architecture for an FPGA-based implementation of a vector current controller for AC machine drives. This architecture results from a modular partitioning, which divides the corresponding algorithm in four reusable modules: the (abc-to-dq) transformation module, the PI module, the (dq-to-abc) transformation module and the PWM module. The global control unit of the vector current controller architecture is activated via a Start signal. This control unit activates the AD conversion module and the module of the vector current controller in a sequential mode. The proposed sequential timing diagram for the development of a synchronized PWM is reported in Fig. 19. In this case, the reference voltages Vsa

*, Vsb* and Vsc

*, which are the inputs of the PWM modulator, must be refreshed exactly at the triangular PWM carrier vertex instants. There, the mean values of the applied VSI voltages are equal to the reference ones [9]. In the case of DSPs or microcontrollers, the feedback current samples must be kept only and exactly at the triangular PWM carrier vertexes (Low and high vertexes) instants [8]. Besides, the reference voltages are available after a computation time delay. As a consequence, the control loop delay cannot be lower than one half of the PWM period, even if the execution time is lower. However, in the case of FPGAs, the free positioning of sampling instants allows the achievement of a control loop delay only equal to the execution time Tex. This last is equal to the sum of the AD conversion time tAD and the computation time of the vector current controller tVC. Every sampling period Ts, equal to one half of the PWM period, the global control unit is activated via a Start signal. An End_VC signal indicates that the reference voltages Vsa

*, Vsb* and Vsc

* are computed and refreshed. It can be noted that, with regard to the carrier vertexes (Low and high vertexes), the active level pulses of the Start signal are applied a time Tex before. Consequently, the reference voltages Vsa

*, Vsb* and Vsc

* are refreshed exactly at the carrier vertexes (Low and high vertexes),, which corresponds to a control loop delay only equal to Tex as shown in Fig. 19.

AC Machine

dq

abc

θdq

E

isa

isb

isd

isq

Sa Sb Sc

dq

abc

PWM modulator

Vsa*

Vsb*

Vsc*

Vsd*

Vsq*

+

- +

-

isd*

isq*

16

Fig. 18. Vector current controller architecture

Fig. 19. Sequential timing diagram vector current controller architecture based on synchronized PWM

Another alternative of FPGA-based PWM control loops consists in the development of a non synchronized PWM modulator. This needs an over sampling strategy and the voltage references must be refreshed with a sampling period, which is very small compared to the switching one. Fig. 20 shows the principle of the over sampling method, which was used for the realization of a vector current controller of AC machine drives based on a non synchronized PWM. The used

abc-to-dq

isd*

isq*

AD Interface

is1AD

is2AD AD Control

Global control unit

Algorithm controller

Start End

Clk

Clk

Clk

Vector current controller

isa isb

Clk

Start_VC End_VC

End_AD Start_AD

PI Clk

Clk PI

dq-to-abc

Clk

Vsd*

Vsq*

PWM

Vsa*

Vsb*

Vsc*

Clk

θdq

Sa Sb Sb

isq isd

wait

Start_AD=’1’ wait

End=’1’

Start=’1’

Reset

Start_VC=’1’

wait

End_AD=’1’

End_VC=’1’ Global control unit FSM

tAD tAD

tk

Application Vsa,b,c

*[k] Sample isa[k] isb[k] θdq[k]

tk+Tex tk+1

Application Vsa,b,c

*[k+1] Sample isa[k+1] isb[k+1] θdq[k+1]

tk+1+Tex

tVC

tPWM/2 Tex

tAD

tk+2

Application Vsa,b,c

*[k+2]

tk+2+Tex

tVC tVC

tPWM/2

Carrier

Start

End_VC

Ts = tPWM/2

Sample isa[k+2] isb[k+2] θdq[k+2]

FPGA

DAC

Carrier DAC Control

Scope

1) Ch 1: 200 mVolt 250 us 2) Ch 2: 2 Volt 250 us

1) Ch 1: 200 mVolt 10 us

2) Ch 2: 2 Volt 10 us

1) Ch 1: 200 mVolt 10 us

2) Ch 2: 2 Volt 10 us

Start OR End_VC

Start End_VC Start End_VC

Tex Tex

Carrier vertex

Carrier vertex

Carrier

Start OR End_VC

Carrier

Ts

250 µs

10 µs 10 µs

17

sampling frequency in this case is equal to 200 KHz. Consequently, the voltage references are refreshed every 5 µs. Note that the maximum over sampling rate can be obtained with an operation mode similar to the one presented in Fig. 11.

Fig. 20. Non synchronized based PWM control loop

C. Experimental Results The FPGA time/area performances of the considered vector current controller of AC machine drives are presented in Table II. The computation time of the vector current controller architecture takes a time equal to 0.88 µs. By adding the AD conversion time, the whole execution time Tex is of 3.28 µs. The consumed resources of Table II are obtained for a 20 bits fixed format.

Application Vsa,b,c

*[k]

Sample isa[k] isb[k] θdq[k]

Carrier

tk tk+1 tk+2

Application Vsa,b,c

*[k+m]

Sample isa[k+m] isb[k+m] θdq[k+m]

tk+m tk+m+1 tk+m+2

Tex

Ts

1) Ch 1: 200 mVolt 2.5 us 2) Ch 2: 1 Volt 2.5 us

Start End_VC

Tex

Carrier

Ts 2,5 µs

Carrier Frequency = 1 KHz

1) Ch 1: 1 Volt 25 ms 2) Ch 2: 1 Volt 25 ms

isa

isb

isa

isb

isa

isb

isq

isd

Vsa

Vsb

(a) (b)

(c) (d)

(e) (f)

Carrier Frequency = 1 KHz

Carrier Frequency = 3 KHz

Carrier Frequency = 1 KHz

THD=8.9%

Carrier Frequency = 3 KHz THD=4.1%

Carrier Frequency = 1 KHz

18

Fig. 21. (a, b) Stator current waveforms for a 1 KHz carrier frequency (c) Stator current waveforms for a 3 KHz carrier frequency (d) Stator current responses of a speed reversal operation (e) Response to a step changes of the isd

* and isq* references

(f) Phase voltage waveforms

TABLE II

FPGA TIME/AREA PERFORMANCES OF THE VECTOR CURRENT CONTROLLER

Modules Latency Computation time abc-to-dq 16 tP = 0.32 µs

PI 8 tPI = 0.16 µs dq-to-abc 14 tIP = 0.28 µs

PWM 6 tPWM = 0.12 µs tVC= tP+ tPI+ tIP+ tPWM tVC = 0.88 µs

Execution time = tAD +tC+tH3+tT Tex = 2.64 µs Consumed resources 21%

Fig. 21(a) and Fig. 21(c) show the experimental results of the stator current waveforms, which was obtained for a non synchronous PWM carrier. The PWM switching frequency was set to 1 KHz (Fig. 21(a)) and 3 KHz (Fig. 21(c)). The carrier frequency was deliberately chosen very low in order to reduce the dead-time effects (Dead-time around 3µs). These results demonstrate that the current waveforms have still a good quality. Fig. 21(d) presents the isa and isb stator current responses of a speed reversal operation under a rated load torque value. Fig. 21(e) presents the responses of isd and isq currents to step changes for the d and q axis current references (The PWM carrier frequency is equal to 1 KHz). It can be noted that, comparing to the case of ON-OFF current controllers, PI current controllers present lower dynamic performances. Finally, Fig. 21(f) illustrates the phase voltages Vsa and Vsb waveforms corresponding to a 1 KHz carrier frequency.

V. CURRENT CONTROL OF SYNCHRONOUS MACHINE BASED ON PREDICTIVE CONTROLLER

In this section, the development and FPGA implementation of a synchronous machine predictive current controller is presented. The interest of using FPGA-based solutions for such types of controllers is also discussed.

A. Predictive Current Controller Principle

The electrical equations of a wound rotor synchronous machine in the d-q rotor reference frame (The d axis is linked to the rotor winding) are given by relations (2) to (7).

sqdqsd

sdssd dtd

iRV

(2)

sddqsq

sqssq dtd

iRV

(3)

rdsrsdsdsd iMiL (4)

sqsqsq iL (5)

sdsrrdrdrd iMiL (6)

19

)(23

sdsqsqsde iipT (7)

Fig. 22. Wound rotor synchronous machine model

Vsd Vsq

Vrd ird

isd

isq

α

θdq

ωdq d

q

β

20

The synchronous machine rating and parameters are presented in the appendix. Supposing that the rotor excitation current ird is kept constant, the state model of the synchronous machine in the d-q rotor reference frame can be expressed as follows

rd

sq

sd

dqsq

sr

sq

sd

sq

sd

sqdq

sq

sd

dqsq

sd

sd

sq

sd

iVV

tLM

L

Lii

Tt

LL

tLL

T

dtdidt

di

)(10

001

1)(

)(1

(8)

where Tsd=Lsd/Rs and Tsq=Lsq/Rs are the electrical time constants on respectively axis d and q.

For the development of the digital predictive current controller algorithm, the previous state model can be simplified by considering that the used sampling period Ts is very small with regard to the electrical time constants Tsd and Tsq. Consequently, the rotation speed value is considered constant during each sampling period Ts. Basing on the forward Euler approximation method, relation (9) shows the obtained digital prediction equations, which are deduced from the state model (8).

][][][][][][][][

][)1(])[][(]1[

][)1(])[][(]1[

kikMkikLkekikLke

where

kiTT

kekVLT

ki

kiTT

kekVLT

ki

rddqsrsddqsdsq

sqdqsqsd

sqsq

ssqsq

sq

ssq

sdsd

ssdsd

sd

ssd

(9)

esd and esq terms refer respectively to the d and q coupling terms. Relation (9) shows that, during each sampling period, the evolution of the d-q stator current components depends on the applied d-q stator voltage

components Vsd and Vsq of the stator voltage vector. The different stator voltage vectors tjsq

jsd

jsdq VVV ][

(j=0..7) expressed in the d-q rotor reference frame can be determined by applying a rotation operation by an angle equal to θdq to the α and β components of the stator voltage vector as shown in Table III and equation (10).

TABLE III

VSI SWITCHING STATES AND CORRESPONDING OUTPUT VOLTAGES )..j(V jsdq 70

Sa Sb Sc Vsαj Vsβj jV j

dqV

0 0 0 0 0 V0 Vsdq0

1 0 0 2E/3 0 V1 Vsdq1

1 1 0 E/3 E/√3 V2 Vsdq2

21

0 1 0 -E/3 E/√3 V3 Vsdq3

0 1 1 -2E/3 0 V4 Vsdq4

0 0 1 -E/3 -E/√3 V5 Vsdq5

1 0 1 E/3 -E/√3 V6 Vsdq6

1 1 1 0 0 V7 Vsdq7

j

s

js

dqdq

dqdqj

sq

jsd

VV

VV

)cos()sin()sin()cos(

(10)

Considering the eight combination possibilities of the VSI switching states, equation (9) can be expressed for

the different possibilities of the d-q stator voltage components jsdV and j

sqV of the voltage vectors jsdqV

as

follows

][][][][][][][][

][)1(])[][(]1[

][)1(])[][(]1[

kikMkikLkekikLke

where

kiTTkekV

LTki

kiTTkekV

LTki

rddqsrsddqsdsq

sqdqsqsd

sqsq

ssq

jsq

sq

sjsq

sdsd

ssd

jsd

sd

sjsd

(11)

Relation (11) shows that, at the beginning of each sampling period, the d and q components of the stator current vector corresponding to the beginning of the next sampling period can be predicted, and this, according to the applied VSI voltage vector. The stator current trajectories jt

, corresponding to the application

of the jsdqV

voltage vectors, are defined as follows

][]1[][ kikikt sdqj

sdqj

(12)

On the other hand, it is possible to predict the error vector ]1[ ki jsdq

. This error vector is defined by the

difference between the reference current vector at the kth sampling period tsqsdsdq kikiki ]][][[][ ***

and the

predicted stator current vector at the (k+1)th sampling period tjsq

jsd

jsdq kikiki ]]1[]1[[]1[

when the

voltage vector ][kV jsdq

is applied.

22

]1[][]1[ * kikiki jsdqsdq

jsdq

(13)

Fig. 23. (a) Predicted current error vector ]1[ ki jsdq

(b) Example of different prediction possibilities

The d-q components ]1[ ki jsd and ]1[ ki j

sq of each error vector ]1[ ki jsdq

are expressed by relations (14)

and (15).

]1[][]1[ * kikiki jsdsd

jsd

(14)

]1[][]1[ * kikiki jsqsq

jsq

(15)

From relations (11), (14) and (15), the square of the module of the error vectors ]1[ ki jsdq

can be deduced

according to relation (16).

222])1[(])1[(]1[ kikiki j

sqj

sdj

sdq

(16)

isdq[k] isdqj[k+1]

isdq*[k]

tj[k]

Δisdqj[k+1]

(a) (b) d

q

isdq[k]

isdq*[k]

t0,7 t4

t5

t6

t3

t2

t1

Δisdq1[k+1]

isdq1[k+1]

23

Fig. 24. Predictive current controller principle

Fig. 24 presents the principle of the proposed predictive current controller. The electrical angular rotor speed ωdq is deduced by derivating the measured position θdq [37]. The isd, isq, esd and esq values are computed using the measured stator currents is1 and is2, the measured position θdq and the estimated electrical angular rotor

speed ωdq. A prediction module allows predicting the different error vectors jsdqi

according to equations (11),

(14) and (15). Finally an optimization procedure is applied. This procedure consists in selecting the switching

states combination that leads to the minimum square module error )(min2

7..0

jsdqj

i

. For example, in Fig. 23(b)

the switching states combination (Sa Sb Sc)=(100) is selected and applied since the first voltage vector 1sdqV leads

to the smallest square module of the current error vector. Note that, when a null vector leads to a minimum square module error, the selected switching states combination is (000) if the switching states applied in the previous sampling period contains at least two low level switching states and (111) otherwise.

B. FPGA Implementation of the Predictive Current Controller Algorithm

Fig. 25 shows the developed architecture corresponding to the considered predictive current controller. A global control unit is activated via a Start signal every sampling period Ts. The global control unit activates firstly the AD interface module. Then, it waits on the End_AD signal that indicates the achievement of the AD conversion process. After that, the module of the predictive current controller is activated and it computes the switching states. This leads to the sequential timing diagram presented in Fig. 26. In this figure, the time tpr refers to the whole computation time of the predictive current controller module. The latter includes three main modules: the abc-to-dq module, the coupling terms module and the prediction and optimization module. In the other hand, an efficient speed estimator module is used for determining the electrical angular rotor speed ωdq. The operating mode of this module is different from other ones and is detailed in [37].

SM

Vrd

θdq

Optimization

E

isd*

isa

isb

isd

isq

esd esq

ωdq

(Δisdqj)(j=0..7)

Sa Sb

Sc Prediction

dq

abc

Coupling terms

d/dt

isq*

p θm

24

Fig. 25. Predictive current controller hardware architecture

Fig. 26. Sequential timing diagram of the proposed predictive controller

C. Experimental Results

As shown in Fig. 26, the VSI switching states are computed every sampling period Ts (100µs), but are applied after only a short execution time delay Tex .This execution time (4.52µs) is equal to the sum of the AD conversion time tAD and the computation time tPr of the predictive current controller module. As mentioned

previously, the square module of the current vector error is predicted for each applied jsdqV

voltage vector and

an optimization procedure allows selecting the appropriate switching states combination that leads to the minimum square module of the current vector error. So, the considered predictive current controller requires complex on-line computations. This controller supposes that the switching states are applied immediately after the sensing operation and the computation time delay is not considered. Therefore, the performances of the developed predictive controller depend strongly on the computation time delay of the implemented architecture. If the computation time is not negligible, the performances of the developed predictive controller are affected and, in this case, the computation time delay must be compensated.

AD Interface

isaAD

isbAD

AD Control

Sa Sb Sc

Global control unit

Algorithm controller

Start End

Clk

Clk Predictive current controller

Start_Pr End_Pr

End_AD Start_AD

EAD

abc-to-dq

Clk

Coupling terms

Clk

Prediction &

optimization

Clk

isd*

isq*

E

isd

isq

esd

esq

Clk

Speed Estimator

Clk

p

θoffset

θdq + +

θm

isa

isb

wait

Start_AD=’1’ wait

End=’1’

Start=’1’

Reset

Start_Pr=’1’

wait

End_AD=’1’

End_Pr=’1’ Global control unit FSM

ωdq

Ts

tAD tAD

tk

Application Sa,b,c[k]

Sample isa[k] isb[k] θdq[k]

tk+Tex tk+1

Application Sa,b,c[k+1]

Sample isa[k+1] isb[k+1] θdq[k+1]

tk+1+Tex

Fs

Start

tPr tPr

Ts Tex

Tex=tAD + tP

25

The FPGA time/area performances of the considered predictive current controller of synchronous machine are presented in Table V. The consumed resources are obtained for a 13 bits fixed-point format. The computation time of the predictive current controller architecture takes a time equal to 2.12 µs. By adding the AD conversion time, the whole execution time Tex is of 4.52 µs. The used sampling period Ts is of 100µs. The execution time is almost very small compared to the sampling period. This is particularly due to the fast computation process ensured by the high computation capabilities of FPGAs. Consequently, the predictive current controller preserves his performances without any need of delay compensation or supplementary modifications, and this in a reliable and single chip environment. Thus, it is very important, for such current controller structures, to use FPGA based solutions in order to ensure real-time computation of the switching states.

TABLE V FPGA TIME/AREA PERFORMANCES OF THE PREDICTIVE CONTROLLER

Module Latency Computation time abc-to-dq 14 tP = 0.28 µs

Coupling terms 10 tC = 0.2 µs Prediction & optimization 82 tP&O = 1.64 µs

tPr=tP+tEMF+tP&O tPr = 2.12 µs Execution time = tAD+tPr Tex = 4.52 µs

Consumed resources 63%

Fig. 27. (Ts=100 µs, Tex=4.52 µs, E=540V) (a) isa and isb current waveforms (b) isa current waveform (c) isa and isb current waveforms for a reversal speed under a rated torque load (d) Simple voltages Vsa andVsb

Fig. 27 and Fig. 28 present the obtained experimental results corresponding to the proposed predictive current controller. In Fig. 27 are presented the stator current waveforms isa and isb and the phase voltage waveform Vsa, Vsb. In Fig. 28 are presented the isd and isq waveform responses to a step changes in the q axis reference under a rated load torque operation. It can be seen that the current transient responses are performed with a good dynamic without overshooting. These results validate the good functionality of the designed predictive current controller hardware architecture.

(b)

(d)

(a)

(c)

isa

isb

isa

Vsa isa

isb

THD=8.8%

Vsb

26

Fig. 28. (a) Response to a step changes of the isq* stator current reference

VI. CONCLUSION

In this paper, the interest of implementing digital controllers using FPGA components has been presented. It has been shown that such FPGA-based controllers can reach the level of their analog counterparts, keeping in the same time a high degree of flexibility.

In order to demonstrate the benefits of using FPGAs, a set of very demanding industrial control systems in terms of real-time performances has been studied in details. This set consists in several current control techniques applied to AC machine drives. They are ON-OFF current controllers, classical PI current controller and predictive current controller. For each case, a dedicated architecture has been designed and relevant experimental results have been carried out. Thanks to a very small execution time (less than 5µs including analog-to-digital conversion time), excellent quality of the current waveforms and high dynamic performances have been obtained. All these developed algorithms, have also clearly illustrated the contribution of the freely positioned sampling instants offered by FPGA-based solution.

APPENDIX

Synchronous Machine Parameters

0.8 KVA, 220V,1.5A, 50 Hz, 3 Phases, Y connection, 2 pole pairs

Stator resistance Rs = 19.9 Ω Rotor resistance Rr = 62.5 Ω d axis stator inductance Lsd = 0.167 H Mutual inductance Msr = 0.64 H q axis stator inductance Lsq = 0.148 H Rated stator current Isn = 2.12 A

-Isn

isq

isd

(b)

Isn

(a)

isq

isd -Isn

Isn

27

Fig. 29. Experimental set-up

NOMENCLATURE

s,r Stator, rotor index

d,q Synchronous reference frame index

V,I,Φ Voltage, Current, Flux

Te,TL Electromagnetic torque, Load torque

R,L Resistance, Inductance

ω,θ Angular speed, Rotor position

f,J Viscous friction coefficient, Rotor inertia

p Pole pairs number

THD Total Harmonic Distortion

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