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Flexible Electronics Based on Solution Processable Organic Flexible Electronics Based on Solution Processable Organic

Semiconductors and Colloidal Semiconductor Nanocrystals Semiconductors and Colloidal Semiconductor Nanocrystals

Yuming Lai University of Pennsylvania, marshell.lai@gmail.com

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Recommended Citation Recommended Citation Lai, Yuming, "Flexible Electronics Based on Solution Processable Organic Semiconductors and Colloidal Semiconductor Nanocrystals" (2014). Publicly Accessible Penn Dissertations. 1337. https://repository.upenn.edu/edissertations/1337

This paper is posted at ScholarlyCommons. https://repository.upenn.edu/edissertations/1337 For more information, please contact repository@pobox.upenn.edu.

Flexible Electronics Based on Solution Processable Organic Semiconductors and Flexible Electronics Based on Solution Processable Organic Semiconductors and Colloidal Semiconductor Nanocrystals Colloidal Semiconductor Nanocrystals

Abstract Abstract Solution-processable semiconductors hold great potential for the large-area, low-cost fabrication of flexible electronics. Recent advances in flexible electronics have introduced new functional devices such as light-weight displays and conformal sensors. However, key challenges remain to develop flexible devices from emerging materials that use simple fabrication processes and have high-performance.

In this thesis, we first use a solution-processable organic semiconductor to build field-effect transistors on large-area plastic with mobility of 0.1 cm^2/Vs. Combined with passive components, we are able to build voltage amplifiers to capture few mV amplitude bio-signals. This work provides a proof of concept on applying solution processable materials in flexible circuits.

In the second part of the thesis, we introduce colloidal CdSe nanocrystals (NCs) as solution-processable "inks" of semiconductor thin film devices. By strongly coupling and doping the CdSe NC thin films, we demonstrate high-performance, flexible nanocrystal field-effect transistors (NC-FETs) with mobility greater than 20 cm^2/Vs under 2V supply. Using these NC-FETs as building blocks, we demonstrate the first flexible nanocrystal integrated circuits (NCICs) with switching speed of 600 µsec. To design reliable integrated circuits with low-noise, we characterize the flicker noise amplitude and origin. We find the figure of merit for noise, the Hooge parameter, to be 3 x 10^-2 for CdSe NC-FETs, comparable to other emerging solution processable organic semiconductors and promising for low-noise circuit applications.As most of NCs are reactive and their devices tend to degrade in air, we develop processes that allow manipulation of the NCs in ambient atmosphere without compromising device performance. These processes open up opportunities for NC-based devices to be fabricated over large area using photolithography. By scaling the devices and reducing device parasitics, we are able to fabricate hundreds of NC-FETs on wafer-scale substrates and integrate them as circuits. We demonstrate voltage amplifiers with bandwidths of a few kHz and ring-oscillators with a stage delay of 3 µsec. We also show functional NCICs NOR and NAND logic. This thesis demonstrates the use of colloidal NCs to realize flexible, large-area circuits and the feasibility of more advanced analog and digital NCICs built on flexible substrates for various applications.

Degree Type Degree Type Dissertation

Degree Name Degree Name Doctor of Philosophy (PhD)

Graduate Group Graduate Group Electrical & Systems Engineering

First Advisor First Advisor Cherie R. Kagan

Keywords Keywords Colloidal nanocrystals, Flexible electronics, Integrated circuits, Low frequency noise, Organic semiconductor, Solution processable

Subject Categories Subject Categories Electrical and Electronics | Mechanics of Materials | Nanoscience and Nanotechnology

This dissertation is available at ScholarlyCommons: https://repository.upenn.edu/edissertations/1337

FLEXIBLE ELECTRONICS BASED ON SOLUTION PROCESSABLE ORGANIC

SEMICONDUCTORS AND COLLOIDAL SEMICONDUCTOR NANOCRYSTALS

Yuming Lai

A DISSERTATION

in

Electrical and Systems Engineering

Presented to the Faculties of the University of Pennsylvania

in

Partial Fulfillment of the Requirements for the

Degree of Doctor of Philosophy

2014

Supervisor of Dissertation

________________________

Cherie R. Kagan

Stephen J. Angello Professor, Electrical and Systems Engineering

Graduate Group Chairperson

________________________

Saswati Sarkar

Professor, Electrical and Systems Engineering

Dissertation Committee

Jan Van der Spiegel, Professor, Electrical and Systems Engineering

Christopher B. Murray, Richard Perry University Professor, Chemistry

Jonathan Viventi, Assistant Professor, Electrical and Computer Engineering, New York University

FLEXIBLE ELECTRONICS BASED ON SOLUTION PROCESSABLE ORGANIC

SEMICONDUCTORS AND COLLOIDAL SEMICONDUCTOR NANOCRYSTALS

COPYRIGHT

2014

Yuming Lai

This work is licensed under the Creative Commons Attribution- NonCommercial-ShareAlike 3.0 License To view a copy of this license, visit

http://creativecommons.org/licenses/by-ny-sa/2.0/

iii

To My Family

iv

ACKNOWLEDGMENT

First and foremost, I would like to thank Prof. Cherie Kagan for her guidance and financial

support in these years. I am deeply appreciated you give me countless advises through my study,

and always being very patient to teach and answer me, even for very fundamental questions.

Your broad knowledge in science and passionate attitude in research is always the model I am

pursing for.

I am very thankful my committee members and their input to my thesis and research.

Prof. Chris Murray provides guidance and invaluable knowledge in chemistry to my experiment.

Prof. Jan Van der Spiegel enthusiastically educates me on circuit theory and design, and help me

troubleshoot when they are not working as expected. I still remember a few late nights I work with

Prof. Jonathan Viventi, and see my designed circuits applied to animals as neural sensors. Those

experiments inspire me to think my research outside the box, and eventually turn into subjects in

my thesis.

I also want to thank my colleagues in Kagan group and Murray group. I enjoy working

with all of you, and thank you for your assist during these years. As both groups are growing so

big, please forgive me if I do not call out your name here. I would like to thank Dr. Sangam

Saudari. You are definitely my graduate mentor, and I am always grateful to do research and

learn from you in my first two years. I also thank my important collaborators, Dr. David Kim and

Benjamin Diroll. I am glad that we all have very similar working style that pushes out some

successful results. My circuit measurement won't be smooth without help from Shang Wei, Brian

Helfer, Scott Stinner and Hank Bink. I also want to thank Wenxiang Chen to work with me on

taking care our lab important tools. I am deeply appreciated E.D. Goodwin and Eric Wong for

those funny jokes and chats.

Besides colleagues in research group, I want to thank my friends, Albert Chen, Chin-

Chen Kuo and Chi-Mon Chen. As PhD students having kids, we can always share and complain

new father experience together. I also enjoy the time we spent outdoor with our family and kids.

v

I am fortunate to have opportunities to use Quattrone Nanofabrication Facility, where they

provide various modern equipment important to my experiment. I want to say special thanks to

Kyle Keenan for his huge help on assisting me maintain our lab key equipments.

Last but not the least, I greatly thank my parents and my brother for their love and strong

support. Although we are always thousands miles apart for many years, you still send me your

warm encouragement whenever I need. I also want to thank my wife, Avon. I am so lucky to have

you, and I will never forget these busy years when we start our family with two lovely kids.

Thank you.

vi

ABSTRACT

FLEXIBLE ELECTRONICS BASED ON SOLUTION PROCESSABLE ORGANIC

SEMICONDUCTORS AND COLLOIDAL SEMICONDUCTOR NANOCRYSTALS

Yuming Lai

Cherie Kagan

Solution-processable semiconductors hold great potential for the large-area, low-cost

fabrication of flexible electronics. Recent advances in flexible electronics have introduced new

functional devices such as light-weight displays and conformal sensors. However, key challenges

remain to develop flexible devices from emerging materials that use simple fabrication processes

and have high-performance.

In this thesis, we first use a solution-processable organic semiconductor to build field-

effect transistors on large-area plastic with mobility of 0.1 cm2/Vs. Combined with passive

components, we are able to build voltage amplifiers to capture few mV amplitude bio-signals. This

work provides a proof of concept on applying solution processable materials in flexible circuits.

In the second part of the thesis, we introduce colloidal CdSe nanocrystals (NCs) as

solution-processable "inks" of semiconductor thin film devices. By strongly coupling and doping

the CdSe NC thin films, we demonstrate high-performance, flexible nanocrystal field-effect

transistors (NC-FETs) with mobility greater than 20 cm2/Vs under 2V supply. Using these NC-

FETs as building blocks, we demonstrate the first flexible nanocrystal integrated circuits (NCICs)

with switching speed of 600 µsec. To design reliable integrated circuits with low-noise, we

characterize the flicker noise amplitude and origin. We find the figure of merit for noise, the

Hooge parameter, to be 3 x 10-2 for CdSe NC-FETs, comparable to other emerging solution

processable organic semiconductors and promising for low-noise circuit applications.

vii

As most of NCs are reactive and their devices tend to degrade in air, we develop

processes that allow manipulation of the NCs in ambient atmosphere without compromising

device performance. These processes open up opportunities for NC-based devices to be

fabricated over large area using photolithography. By scaling the devices and reducing device

parasitics, we are able to fabricate hundreds of NC-FETs on wafer-scale substrates and integrate

them as circuits. We demonstrate voltage amplifiers with bandwidths of a few kHz and ring-

oscillators with a stage delay of 3 µsec. We also show functional NCICs NOR and NAND logic.

This thesis demonstrates the use of colloidal NCs to realize flexible, large-area circuits and the

feasibility of more advanced analog and digital NCICs built on flexible substrates for various

applications.

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TABLE OF CONTENTS

ACKNOWLEDGMENT .............................................................................................................. iv

ABSTRACT .................................................................................................................................. vi

LIST OF TABLES ........................................................................................................................ xi

LIST OF ILLUSTRATIONS ...................................................................................................... xii

CHAPTER 1 Introduction ....................................................................................................... 1

1-1: Colloidal Semiconductor Nanocrystals ................................................................................. 1

1-2: Outline of Thesis .................................................................................................................. 2

1-3: References: .......................................................................................................................... 3

CHAPTER 2 Flexible Organic Electronics for Use in Neural Sensing ...................... 6

2-1: Bio-signal sensors ................................................................................................................ 6

2-2: Flexible Pentacene Thin Film Transistors and Printed Circuit Board Design ......................... 8

2-3: Organic Electronics for Sensors with Amplification ............................................................ 10

2-4: Discussion and Conclusions ............................................................................................... 11

2-5: References ......................................................................................................................... 14

CHAPTER 3 High-Performance Nanocrystal Transistors and Integrated

Circuits on Flexible Plastic .................................................................................................. 16

3-1: Flexible and Low-Voltage Nanocrystal Field-Effect Transistor ............................................ 16

3-2: Nanocrystal Integrated Inverters ....................................................................................... 19

3-3: Nanocrystal Integrated Voltage Amplifiers ........................................................................ 21

3-4: Nanocrystal Integrated Ring Oscillators ............................................................................. 22

3-5: Discussion .......................................................................................................................... 24

3-6: Conclusion ......................................................................................................................... 24

3-7: Methods ............................................................................................................................ 25

ix

3-8: Supplementary Information .............................................................................................. 27

3-9: References ......................................................................................................................... 37

CHAPTER 4 Low Frequency Noise in Nanocrystal Field-Effect Transistors ...... 40

4-1: Models for flicker noise ..................................................................................................... 40

4-2: Flicker Noise Relationship to Device Geometry ................................................................. 42

4-3: Device Hysteresis and Bias-Stress Effects ........................................................................... 46

4-4: Flicker Noise in Nanocrystal Field-Effect Transistors .......................................................... 48

4-5: Nanocrystal Charge Transport and Flicker Noise Mechanism ............................................ 50

4-6: Conclusion ......................................................................................................................... 53

4-7: Methods ............................................................................................................................ 53

4-8: Supplementary Information .............................................................................................. 55

4-9: References ......................................................................................................................... 62

CHAPTER 5 Recoverable Nanocrystal Field-Effect Transistors for Fabrication

and Operation in Air ............................................................................................................. 66

5-1: Recovery of Degraded Nanocrystal Field-Effect Transistors ............................................... 66

5-2: Air-Stable High Performance Devices on Wafer Scale Substrates ...................................... 70

5-3: Conclusions ....................................................................................................................... 73

5-4: Methods ............................................................................................................................ 73

5-5: References ......................................................................................................................... 74

CHAPTER 6 Direct Photolithographic Patterning of Device Electrodes on

Colloidal Nanocrystals Thin Films to Build Wafer-Scale, Integrated Circuits .. 75

6-1: VIA Process and Transistors Characteristics ....................................................................... 76

6-2: Inverters Characteristics and Analysis ............................................................................... 80

6-3: NOR logic ........................................................................................................................... 83

6-4: NAND logic ........................................................................................................................ 83

6-5: Ring-Oscillators ................................................................................................................. 84

x

6-6: Conclusion ......................................................................................................................... 86

6-7: Methods ............................................................................................................................ 86

6-8: Reference .......................................................................................................................... 87

CHAPTER 7 Future Direction ............................................................................................. 91

7-1: Photolithographic Patterning of Nanocrystal Thin Films to Build Integrated Circuitry on

Flexible Plastic .......................................................................................................................... 91

7-2: Mechanical Stability of Flexible Nanocrystal Field-Effect Transistors ............................... 101

7-3: References ....................................................................................................................... 105

CHAPTER 8 Concluding Remarks .................................................................................. 106

xi

LIST OF TABLES

Table 4-1. Device resistances extracted using the transmission line method and carrier mobilities for TC and BC devices. All data shown is at VGS = 50 V. Note: Only saturation regime mobilities are presented in this table, as mobility for NC-FETs is weakly dependent on VDS.30 .................... 44

Table 4-2. Length dependent normalized drain current spectral density relationship for W/L= constant and W= constant. ............................................................................................................ 45

Table 4-S1. Device resistances extracted by the transmission line method and carrier mobilities for top-contact devices at VGS = 40 V and VGS = 30 V. .................................................................. 58

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LIST OF ILLUSTRATIONS

Figure 2-1. (A) Schematic of the organic thin film transistor, a photographic example of which is seen in (B). (C) and (D) are the representative ID-VDS and ID-VGS properties of the devices, respectively. The channel width is 1500 µm and length is 100 µm. These properties were measured in an inert nitrogen environment. .................................................................................... 8

Figure 2-2. The dual PCB board design. The large board contains all elements of the circuit excluding the transistor: the amplifying resistor, low-pass power supply filters, output buffer and high-pass filter, and input/output components. The ribbon cable attaches the transistor to the rest of the circuit. The enlarged image on the left clearly shows the copper fingers used to make pressure contact with the organic TFT underneath. ........................................................................ 9

Figure 2-3. Results from common source amplifier using pentacene TFT showing the (A) representative output versus input and (B) bode plot. Both results shown were taken from the same 100 µm channel length device. ............................................................................................ 11

Figure 2-4. Organic electronic sensor for recording neural signal. (Blue) Pre-recorded human EEG signal, and (Red) measured output from organic electronic sensor. The output signal was inverted for clear comparison. ........................................................................................................ 12

Figure 3-1. Flexible CdSe nanocrystal field-effect transistors (NC-FETs). (A) Schematic and (B) photograph of a flexible CdSe NC-FET atop a Kapton® substrate. (C) Output ID – VDS and (D) transfer ID – VG characteristics of a flexible, CdSe NC-FET. ......................................................... 18

Figure 3-2. Flexible nanocrystal integrated circuit (NCIC) inverter constructed from nanocrystal field-effect transistors (NC-FETs). (A) Photograph and (B) circuit schematic of saturated-load inverters. (1) Load NC-FET and (2) Driver NC-FET. (C) Graphical analysis of constituent driver (black) and load (red) NC-FET output characteristics, sweeping in forward and reverse, comprising the NCIC inverter, and (D) the corresponding voltage transfer characteristics (black, left axis) and gain characteristics (blue, right axis) of the NCIC inverter sweeping forward and reverse at a supply voltage of 2 V (VDD). ....................................................................................... 20

Figure 3-3. Flexible nanocrystal integrated circuit (NCIC) amplifier and Bode plot. (A) Output waveform (blue, right axis) of NCIC voltage amplifier in response to a 50 Hz, 100 mV sinusoidal input on a 0.6V DC bias (black, left axis). (B) Frequency response of a voltage amplifier (black circles). A linear fit (red solid line) shows a 4.59 dB voltage gain at low frequency which is used to find the 3 dB bandwidth (blue dashed line). ................................................................................... 22

Figure 3-4. Flexible nanocrystal integrated circuit (NCIC) ring oscillator constructed from NCIC inverters. (A) Photograph, (B) circuit schematic and (C) output characteristics of a five-stage NCIC ring oscillator with a sixth stage buffer operating at a supply voltage of 2 V (VDD) with a frequency of 165 Hz. ...................................................................................................................... 23

Figure 3-S1. Gate leakage current of 30 nm Al2O3 atomic layer deposited dielectric. The estimated oxide resistance is 0.5TΩ, which is a measure of the input resistance of the nanocrystal integrated circuit (NCIC) inverters. ............................................................................. 27

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Figure 3-S2. Back-gate/bottom-contact CdSe nanocrystal field-effect transistors (NC-FETs). (A) Schematic and (B) output (ID-VDS) and (C) transfer (ID-VG) curves..........................................27

Figure 3-S3. Graphical and Noise Analysis of CdSe nanocrystal integrated circuit (NCIC) inverter. (A) Graphical analysis, only shown to magnifying low ID to 20 µA. (B) the constructed points (red) versus measured (black) voltage transfer characteristic (VTC) for a CdSe NCIC inverter on a plastic substrate. (C) The original VTC (black solid line) overlaid with its mirror image (red solid line). VIN = VOUT (blue dashed line). The inscribed gray squares define the noise margin high and noise margin low to be 0.1 V. Inverter Operation: The fabricated inverter is based on a saturated-load design [Figure 3-2 (A, B)], where one n-type field-effect transistor (FET) acts as an active load and the other n-type FET as a driver. The load FET has its source connected to the inverter’s output (VOUT) and its drain and gate are both connected to the inverter’s supply voltage (VDD). The load FET always operates in saturation because the gate and drain-source voltages are identical ensuring that − < for a positive threshold voltage. The driver FET has its gate connected to the inverter’s input (VIN), its drain connected to the inverter’s output (VOUT) and its source connected to ground (VSS). During device operation when the inverter input is “low” (VIN = 0), the driver FET is in the off-state and exhibits very large resistance. The supply voltage will be divided dropping across the more resistive driver FET than load FET, causing the output voltage to exhibit a “high” voltage that is about the difference between the supply voltage and the load’s threshold voltage ( ) = −

. When the input of the inverter is “high” = , the driver FET will be in the on-state and exhibit very low resistance. The divided voltage will now be predominantly across the load, causing the output node to exhibit a “low” voltage that is close to ground. Inverter Voltage Transfer Characteristics: Graphical analysis of the load and driver FET intercept points are used to construct the inverters’ VTCs.30 The low hysteresis in the NCIC VTCs provides adequate noise margin at both logic high and low regions. Noise margin is evaluated by taking the original VTC overlaid with its’ mirror image (VIN = VOUT as mirror plane). The largest inscribed square area defines the inverter’s noise margin.41 The noise margin ensures the inverter functions correctly in complex integrated circuits, providing logic switching (eg. in the 1st inverter stage, 0.4 V input will output at 1.3 V, and this 1.3 V is the input for the 2nd stage inverter and output at 0.4 V.) ........... 29

Figure 3-S4. CdSe Nanocrystal Integrated Circuit (NCIC) Amplifier Equivalent Circuit Modeling. (A) Small-signal equivalent-circuit model of a common-source amplifier with a saturated-load design. (B) Schematic of parasitic and interconnect capacitances. (C) The simplified model from Supplementary Figure 3-S4 (A) and Figure 3-S4 (B)..................................................................30

Figure 3-S5. Propagation delay definitions in the inverter’s output waveform. ............................. 31

Figure 3-S6. CdSe Nanocrystal Integrated Circuit (NCIC) Ring Oscillator Equivalent Circuit Modeling. An example of parasitic capacitance for a 3-stage ring oscillator with an additional inverter serving as a buffer. Note that the Miller effect is applied to Cgd2. ..................................... 31

Figure 4-1. Device output characteristics (ID-VDS) for (A) top-contact and (B) bottom-contact CdSe NC-FETs. Normalized drain current spectral density (SI/ID

2) vs frequency for (C) top-contact and (D) bottom-contact CdSe NC-FETs, where the channel width over length ratio (W/L) is 15 for all devices and the length is (magenta) 40 µm (green) 50 µm, (blue) 100 µm, (red) 150 µm and (black) 200 µm. Insets in (A) and (B) are schematics of the top-contact and bottom-contact NC-FETs, respectively. Insets in (C) and (D) show the relationship between noise amplitude and device area for a representative frequency of 10 Hz. .................................................................... 43

xiv

Figure 4-2. Normalized drain current spectral density (SI/ID2) as a function of channel length

varying from 30 µm to 200 µm, collected at a fixed frequency of 10 Hz, VDS = 50 V and VGS = 50 V. (A) Representative channel length dependence of SI/ID

2 for top-contact (red) and bottom-contact (green) devices with a constant W/L of 15. (B) Channel length dependence of SI/ID

2 for top-contact devices with constant W/L (blue) and fixed channel width of 1800 µm (cyan). Note: The device channel length of 90 µm and channel width of 1800 µm is common, representing the constant W/L ratio of 20 and the constant channel width of 1800 µm. Slopes of m = -1 and m = -2 lines are shown for reference. ........................................................................................................ 46

Figure 4-3. Spectral current density (SI) of Al2O3-encapsulated, top-contact devices as a function of frequency measured at (A) VDS = 1 V and (B) VDS = 50 V under various VGS. (C) 1/f slope fit from SI vs frequency as a function of VGS at VDS = 1 V (blue) and VDS = 50 V (black). (D) SI vs ID at a frequency of 10 Hz for devices biased in saturation at VDS = 50 V (black) and linear and subthreshold regimes at VDS = 1 V (blue). Slopes (m) of 1, 1.5 and 2 are drawn for reference. Inset: Statistics from 4 devices of the slope of SI vs ID, measured in the saturation, linear and subthreshold regimes respectively. ................................................................................................ 48

Figure 4-4. Mobility and Hooge parameter (αH) as a function of VGS when VDS = 50 V for (A) unencapsulated, top-contact and (B) Al2O3-encapsulated, top-contact devices. Insets in (A) and (B) are NC-FET schematics. (C) Schematic of the carrier concentration in the NC-FET channel, and (D) the density of states for NC thin films and the energy of the Fermi level in the linear (red), saturation (green), and subthreshold (orange) regimes. E0 denotes the mobility edge. Note, in the saturation region pinch off within ∆L of the drain electrode causes the Fermi energy to move further away from the band edge. The density of tail states (blue dashed) is reduced after Al2O3 encapsulation (blue solid). ............................................................................................................. 51

Figure 4-S1. (A) Representative transfer characteristics (ID-VGS) for top-contact (red) and bottom-contact (black) devices, with L = 50 µm and measured at VDS = 50 V. The contact (Rcontact) and channel (Rchannel) resistances are extracted from the total resistance (Rtotal) as a function of channel length using the transmission line method for (B) top-contact and (C) bottom-contact devices respectively, collected at VGS = 30 V (black), VGS = 40 V (red), and VGS = 50 V (blue). (D) A representative SI/ID

2 vs frequency of a top-contact, L = 40 µm device measured in the saturation and linear regimes, showing that noise is weakly dependent on VDS. .......................... 57

Figure 4-S2. Statistics of the length dependence of SI/ID2 for different scaling of the device

geometry. ....................................................................................................................................... 58

Figure 4-S3. Time dependence of the normalized drain-source current (ID) measured under a voltage stress of (A) VDS = 50 V and (B) VDS = 1 V for an unencapsulated, top-contact device (dashed lines) and an Al2O3-encapsulated, top-contact device (solid lines), where VGS = 50 V (black), VGS = 40 V (red), VGS = 30 V (blue) and VGS = 20 V (green). ............................................ 59

Figure 4-S4. Device transfer characteristics ID-VGS for (A) an unencapsulated, top-contact and (B) an Al2O3-encapsulated, top-contact device at VDS = 50 V and VDS = 1 V (inset), where ID-VGS before (black) and after (red) noise collection are presented. The average stress current during noise collection is shown as blue stars at each applied bias and is the average of the current collected in Fig. 4-S3 from 10 sec to the end of applied bias at 70 sec. Note: the calculated interface trap density from the subthreshold swing is 9.67 x 1012 cm-2 for (A) and 9.14 x 1012 cm-2 for (B). ............................................................................................................................................ 59

xv

Figure 4-S5. Traces of ID as a function of time under voltage stress (black) and fits to a stretched exponential function (red) for (A) an unencapsulated, top-contact and (B) an Al2O3-encapsulated, top-contact device under VDS = 1 V, VGS = 50 V and for (C) an unencapsulated, top-contact device and (D) an Al2O3-encapsulated, top-contact device under VDS = 50 V, VGS = 50 V. Insets in (A-D) show fitting parameters (τ and β) as a function of VGS. ........................................................ 60

Figure 4-S6. (A) Representative SI/ID2 vs (VGS-VT) characteristics at a frequency of 10 Hz for an

Al2O3-encapsulated device operated in the linear regime (VDS = 1 V). The slope fit for frequencies between 5 to 10 Hz in a step of 1 Hz is -0.9 ± 0.15. Slopes of -1 and -2 are drawn for reference. (B) Representative SI vs (VGS-VT) at a frequency of 10 Hz for an Al2O3-encapsulated device operated in the saturation regime (VDS = 50 V). The slope fit for frequencies between 5 to 10 Hz in a step of 1 Hz is 3.1 ± 0.27. Slopes of 2 and 3 are drawn for reference. (C) Comparison of the SI/ID

2 and SI dependence on (VGS -VT) for the Hooge (∆µ) and McWhorter (∆N) models for devices operated in linear and saturation modes........................................................................................ 61

Figure 4-S7. Mobility and Hooge parameter (αH) as a function of VGS when VDS = 1 V for (A) unencapsulated, top-contact and (B) Al2O3-encapsulated, top-contact devices. .......................... 62

Figure 5-1. CdSe NC-FET on-current (VG=50 V) in the linear regime (VDS=5 V) monitoring (A) cyclic degradation as a function of air exposure time and recovery upon re-annealing at 200 oC for 5 min, (B) degradation in air versus in pure oxygen environments (open bar : initial, filled bar : exposure), and (C) the evolution in as-prepared FETs (black) upon successive cycles of air exposure for 30 min (red) and recovery by annealing at 200 oC for 5 min (blue). (D) Statistics in on-current recovery after 5 min of annealing at different temperatures. Note: Since all devices recover at an annealing temperature of 200 oC, the scale is narrowed. (E) NC-FET degradation, characterized by the decrease in drain current IDS (after exposure) to IDSO (initial), upon immersion in acetone, chloroform, isopropanol, methanol and water for 10 min at room temperature. Samples were dried using a nitrogen stream before electrical measurement. (Top) On-current recovery upon re-annealing at 200 oC for 5 min after solvent immersion. ..................................... 67

Figure 5-2. ID-VG characteristics of CdSe NC-FETs before and after repeated cycling through 13 times of air exposure and annealing. ............................................................................................. 69

Figure 5-3. (A) A photograph of an array of 144 transistors fabricated by photolithographically patterning source and drain electrodes on [inset] a uniformly spin-cast CdSe NC thin film across a 4 inch Al2O3(20 nm)/SiO2(250 nm)/highly-doped Si wafer. (b) Output and (c) transfer characteristics (VDS=5 V) of NC-FETs (channel length L=30 µm, width W=450 µm). [inset (b)] Schematic of the device structure. (d) Electron mobility of integrated CdSe NC devices over the large-area 4 inch substrate. (e) NC-FET electron mobility (black) and threshold voltage (blue) as a function of time stored and operated in air. ................................................................................. 71

Figure 5-4. (A) A photograph of an array of photolithographically patterned NC-FETs on a 4 inch square Kapton® substrate. (b) Output and (c) transfer characteristics (VDS =0.1 and 2 V) of NC-FETs (channel length L=30 µm, width W=450 µm). [inset] Schematic of the NC-FET structure. .. 72

Figure 6-1. (A) Photograph of wafer-scale CdSe NCICs, where the smallest channel length is 5 µm. (B) Schematic of (top) single transistor and (bottom) transistor with VIA connection to form enhancement-load inverters. (C) Device output characteristics (ID-VDS) and (D) transfer characteristics (ID-VGS) in the saturation regime (VDS = 3 V). Channel width over channel length is (600 µm/40 µm). ............................................................................................................................. 77

xvi

Figure 6-2. (A) The unit capacitance and dielectric constant (epsilon) of ALD grown Al2O3 as a function of frequency. The average epsilon measured from 8 test capacitors is 7.3 ± 0.48 (at 2 kHz). (B) Device transfer characteristics operated in the linear regime (VDS = 0.1 V). Channel width over length is (600 µm/40 µm). (C) Transmission line method used to characterize device contact resistance for devices with channel lengths ranging from 5 µm to 40 µm, under (Black) VGS = 1.5V, (Red) VGS = 2.0V and (Blue) VGS = 2.5V. (D) A summary of extracted contact and channel resistance from the transmission line method. ................................................................. 78

Figure 6-3. Nanocrystal integrated inverter and electrical characteristics. (A) Photograph of an enhancement-load inverter, where (W/L)Load to (W/L)Driver ratio is (10/100), and the channel lengths are constant at 10 µm. (B) Inverter voltage transfer characteristics at (black) VDD = 5 V, (red) 4 V, (blue) 3 V and (olive) 2 V and its associated (C) voltage gain, (D) noise margin and (E) drain current. Voltage amplifier output characteristics for input at (F) 10 Hz and (G) 5 kHz, where (red) output waveform is in response to (black) input signal. (H) Bode plot of voltage amplifier, where blue dashed lines refer to low frequency voltage gain and 3 dB gain at higher frequency. ..............................................................................................................................................79

Figure 6-4. (A) Top and perspective view of VIA test structures, where the red layer is the gate electrode, yellow is the VIA, and blue is the source/drain electrodes. The square VIAs have sizes of 200, 100, 50 and 25 µm. (B) I-V characteristics across 16 VIA holes, described as yellow arrows in (A). .................................................................................................................................. 81

Figure 6-5. Nanocrystal integrated NOR and NAND logics. Photograph of (A) NOR and (D) NAND, where the load FET has a fixed (W/L) ratio of 10 and the driver FETs have a fixed (W/L) ratio of 100. Channel length is constant at 10 µm for load and driver FETs. Circuit symbol and truth table for (B) NOR and (E) NAND logic gates. Voltage transfer characteristics for (C) NOR and (F) NAND logics, where black and blue scans refer to different input configurations, shown as black and blue arrows in (B),(E) truth tables. ................................................................................. 82

Figure 6-6. Nanocrystal integrated 5-stage ring oscillators. (A) Photograph and circuit schematic. (B) Output waveform of a 5-stage ring oscillator at VDD = 5 V. (C) Stage delay statistics as a function of VDD. (D) Summary of the ring oscillator stage delay using active channels from the following classes of solution processable.materials:(green) organic semiconductor, (blue) carbon nanotube networks, (red) metal-oxides, and (black) for colloidal nanocrystal semiconductors (demonstrated in this thesis). Solid circles represent reports of devices fabricated on rigid substrates, and empty circles for devices on flexible plastics. The black empty diamond is the 1st NCIC ring oscillator fabricated on flexible substrate, reported in Chapter 3. ................................. 85

Figure 7-1. (A) Photograph of a large-area, photolithographically-patterned, CdSe nanocrystal thin film. (B) Optical micrograph of a patterned nanocrystal thin film array, where the gap and pitch are both 25 µm. ..................................................................................................................... 92

Figure 7-2. (A) Photograph of 10 x 10 cm square flexible nanocrystal integrated circuit, where CdSe nanocrystals are patterned. (B) Schematic of devices with and without patterned nanocrystals. (C) Optical micrograph of devices with patterned nanocrystals as the active channel (top), and an array of the patterned nanocrystal thin film (bottom). (D) At constant VDS = 5 V, device drain current (ID, black, left y-axis) and gate current (IG, blue,right y-axis) for non-patterned (empty circle) and patterned (solid) nanocrystal thin-film devices. Device channel width over length ratio is 1000 µm / 10 µm. (E) ALD grown Al2O3 gate leakage current as a function of applied voltage, and (F) unit capacitance as a function of frequency.......................................93

xvii

Figure 7-3. Schematic of a nanocrystal thin-film transistor (A) without and (C) with ALD Al2O3 encapsulation. Transfer characteristics (ID-VGS, black, left y-axis) and its square root (blue, right y-axis) in the saturation regime (VDS = 5 V) for devices (B) without and (D) with 50 nm ALD Al2O3 encapsulation. (E) Output characteristics (ID-VDS) and (F) statistics on carrier mobility (µ), threshold voltage (VT), subthreshold swing (S) and dielectric-semiconductor interface trap density (NT) for encapsulated devices. Note: Device channel width over length ratio is 1000 µm / 10 µm in (B,D,E). Saturation regime characteristics are measured at VDS = 5 V, and linear regime characteristics are measured at VDS = 0.1 V. ................................................................................. 94

Figure 7-4. (A) Transmission line method for devices with constant channel width to length ratio of 15, and channel length ranging from 5 µm to 40 µm. (B) Extracted device channel resistance (RCH) and metal-to-semiconductor contact resistance (RCONTACT) as a function of gate voltages. 95

Figure 7-5. Enhancement-load inverter. Voltage transfer characteristics for device (A) without and (C) with encapsulation. Noise margin for devices (B) without and (D) with encapsulation. The channel width (W) to length (L) ratio is 10 for the load, and 100 for driver. Load and driver transistors have constant channel length of 10 µm. ...................................................................... 96

Figure 7-6. (A) Photograph of enhancement-load inverter. (B) Load (red) and driver (black) output characteristics. (C) Inverter voltage transfer characteristics, (D) voltage gain, (E) noise margin, and (F) drain current for (black) VDD = 5 V, (red) 4 V, (blue) 3 V and (olive) 2 V. Voltage amplifier characteristics for an input at (G) 10 Hz and (H) 16 kHz, where (red) the output waveform is measured in response to (black) a sinusoidal, 200 mV peak-to-peak input signal. (I) Bode plot for the voltage amplifier, where blue dashed lines refer to low frequency voltage gain and 3 dB gain at higher frequency. The measured 3dB bandwidth is ~ 16 kHz. ......................... 100

Figure 7-7. Inverter dynamic response at VDD = 5 V. Input (black) and output (red) waveform for (A) 100 Hz 5 V peak to peak input, and (B) 10 kHz 5 V peak to peak input. ............................... 100

Figure 7-8. (A) Photograph of NOR logic. (B) Voltage transfer characteristics for different input sweep configurations, where black refers to the input sweep between [0,0] and [1,1], and blue refers to the input sweep between [0,0] and [0,1]. Inset: NOR truth table. (C) Output characteristics. ............................................................................................................................. 100

Figure 7-9. Schematic for a beam under bending.3 .................................................................... 101

Figure 7-10. Photograph of (A) tension and (B) compression measurement setup. .................. 102

Figure 7-11. (A) Top: Schematic of device under tension and compression tests. Bottom: Device mobility (black) and threshold voltage (VT, blue) relationship to strain in the saturation (VDS = 2 V) and linear (VDS = 0.1 V) regimes. (B) Photograph of device wrapped around a radius of ~ 1.0 mm to emulate extreme bending, equal to -2.5% strain. (C) Device transfer characteristics (ID-VG) in saturation (VDS = 2 V) and linear (VDS = 0.1 V) regime under flat (black), -2.5 % strain (blue) and returned to flat after bending (red). .............................................................................................. 103

Figure 7-12. Device output characteristics (ID-VDS) when sample is (A) flat, (B) under -2.5 % strain, and (C) returned to flat. Gate leakage current (IG-VDS) when sample is (D) flat, (E) under -2.5 % strain, and (F) returned to flat. ........................................................................................... 104

xviii

Figure 7-13. Change in oxide capacitance versus strain, normalized to the original flat oxide capacitance. ................................................................................................................................. 105

Figure 7-14. Proposed measurement where electrodes are extended further and connected by a ZIF connector. .............................................................................................................................. 105

1

CHAPTER 1 Introduction

1-1: Colloidal Semiconductor Nanocrystals

Colloidal semiconductor nanocrystals (NCs) are prized for their size- and shape-tunable

electronic properties.1–4 Wet-chemical methods have enabled the preparation of highly uniform,

monodisperse, crystalline NCs for a wide variety of chemical compositions by commonly

employing long-chain, organic ligands to control NC synthesis and to stabilize NC dispersions.5

These NC solutions capped with long ligands can be easily processed by a variety of solution-

based material deposition methods (spincasting, dipcoating, inkjet printing, dropcasting,

spraycoating) to form uniform thin-films.6–11 While high quality NC synthesis and dispersibility

relies on long ligands, these ligands are insulating and prevent strong coupling and charge

transport between NCs once assembled in the solid state. Until recently, this has posed a

significant challenge to using these colloidal inks as technologically viable electronic materials for

devices12 and integrated circuitry.13 Advances in ligand chemistry have shown that the original,

long ligands used in synthesis can be replaced by shorter inorganic ligands14–17 either in solution,

and still maintain solution-dispersibility and thin-film processability, or in thin-film solids. These

novel ligands preserve the discrete, size-dependent features of quantum confinement and

enhance electronic coupling between the NCs in thin-films. Our group, along with the Talapin

group, have shown that dispersions of NCs exchanged with compact ligands can be spincast to

form dense, crack-free, thin-films that demonstrate excellent performance in single field-effect

transistors (FETs), with high electron mobilities exceeding 15 cm2V-1s-1.16,18–20 The solution-

processability and high-performance of NC-FETs make colloidal NC semiconductors extremely

attractive as colloidal inks for low-cost, large-scale coating and printing of thin-film electronics.

While there has been significant progress in developing single high mobility NC-FETs that further

operate with low-hysteresis18,20 at low-voltage,21 these high-performance NC-FETs have not been

integrated into NC circuits in the literature. All circuit demonstrations have been limited to two

2

single separate FETs connected externally to form an inverter.21,22 In order to realize nanocrystal

integrated circuits (NCICs) for large-area, thin-film electronics, it is necessary to go beyond

discrete FET fabrication, to integrate multiple FETs into circuits and to evaluate device operation,

such as the switching speed and signal amplification of the NC-FET. This requires that NC thin-

films be processed and deposited over a large area to form uniform devices that operate in

concert as circuits.

1-2: Outline of Thesis

The goal of this thesis is to use solution processable materials in flexible electronics and

demonstrate high density, large-area, low-voltage integrated circuits on flexible plastic. In

Chapter 2, we first use solution processable precursor to pentacene the organic semiconductors

to fabricate large-area, flexible FETs with hole mobility of 0.1 cm2/Vs. We integrate them with

passive resistors on printed circuit board to realize voltage amplifiers. We demonstrate these

amplifiers is able to capture mV bio-signals. In Chapter 3, we use colloidal CdSe NCs as active

materials. The original long insulating organic ligands is replaced with compact thiocyanate to

greatly enhance coupling between NCs. The non-corrosive thiocyanate allows fabrication

compatible to flexible plastics. These NC thin films is then doped by thermal diffusion of indium

metals introduced at device electrodes. With strong coupling and doping of NCs, we construct

high-performance NC-FETs with electron mobility greater than 20 cm2/Vs. Using NC-FETs as

building blocks, we fabricate nanocrystal integrated circuits (NCICs) including voltage amplifier,

inverters and ring oscillators. The highest switching speed is 600 µs with supply voltage of 2V. In

Chapter 4, in order to evaluate the noise level for designing reliable circuits with low noise, we

investigate the low-frequency noises in CdSe NC-FETs. We characterize the noise level and

origin. By engineering device geometries and passivating NC surface traps, we find flicker noise

in NC-FETs relates to charge transport through NC electronic structures. We report a figure of

merit for noise, Hooge parameter in CdSe NC-FETs to be 3 x 10-2, comparable to other solution

processable organic semiconductors and promise to the applications require low noise. Since

3

most of NCs are reactive and their electronic properties degrade in exposure to air or chemical

solvents, NC fabrication are generally limited to inert atmosphere. In Chapter 5, we introduce NCs

recovery mechanism where their electronic properties can be repaired, through indium metals to

passivate trap states formed during exposure to air and chemicals. The recovery effects allow NC

to be processed with various techniques in ambient environment, such as large-area

photolithographic patterning or device encapsulation by atomic layer deposition. The

encapsulated NC-FETs show stable operation in air for more than 2 months. In Chapter 6, we

use photolithography to scale high performance NC-FETs to fabricate hundreds of devices, and

integrate them as circuits on four inch Si wafer. The reduced parasitic capacitance pushes the

switching speed to 3 µs. In Chapter 7, we take advantage of wet etcher to selectively remove

CdSe NC thin films to form defined active channels. We successfully translate this to flexible

plastic and demonstrate large-area, flexible NCICs with patterned active layers.

1-3: References:

(1) Bawendi, M. G.; Steigerwald, M. L.; Brus, L. E. The Quantum Mechanics of Larger Semiconductor Clusters (“Quantum Dots”). Annu. Rev. Phys. Chem. 1990, 41, 477–496.

(2) Alivisatos, A. P. Semiconductor Clusters, Nanocrystals, and Quantum Dots. Science (80-. ). 1996, 271, 933–937.

(3) Murray, C. B.; Kagan, C. R.; Bawendi, M. G. Synthesis and Characterization of Monodisperse Nanocrystals and Close-Packed Nanocrystal Assemblies. Annu. Rev. Mater. Sci. 2000, 30, 545–610.

(4) Efros, A. L.; Rosen, M. The Electronic Structure of Semiconductor Nanocrystals. Annu. Rev. Mater. Sci. 2000, 30, 475–521.

(5) Murray, C. B.; Norris, D. J.; Bawendi, M. G. Synthesis and Characterization of Nearly Monodisperse CdE (E= S, Se, Te) Semiconductor Nanocrystallites. J. Am. Chem. Soc. 1993, 115, 8706–8715.

(6) Mitzi, D. B.; Kosbar, L. L.; Murray, C. E.; Copel, M.; Afzali, A. High-Mobility Ultrathin Semiconducting Films Prepared by Spin Coating. Nature 2004, 428, 299–303.

(7) Luther, J. M.; Law, M.; Song, Q.; Perkins, C. L.; Beard, M. C.; Nozik, A. J. Structural, Optical, and Electrical Properties of Self-Assembled Films of PbSe Nanocrystals Treated with 1,2-Ethanedithiol. ACS Nano 2008, 2, 271–280.

4

(8) Wood, V.; Panzer, M. J.; Chen, J.; Bradley, M. S.; Halpert, J. E.; Bawendi, M. G.; Bulović, V. Inkjet-Printed Quantum Dot-Polymer Composites for Full-Color AC-Driven Displays. Adv. Mater. 2009, 21, 2151–2155.

(9) Talapin, D. V; Murray, C. B. PbSe Nanocrystal Solids for N- and P-Channel Thin Film Field-Effect Transistors. Science (80-. ). 2005, 310, 86–89.

(10) Soreni-Harari, M.; Mocatta, D.; Zimin, M.; Gannot, Y.; Banin, U.; Tessler, N. Interface Modifications of InAs Quantum-Dots Solids and Their Effects on FET Performance. Adv. Funct. Mater. 2010, 20, 1005–1010.

(11) Kovalenko, M. V; Spokoyny, B.; Lee, J.-S.; Scheele, M.; Weber, A.; Perera, S.; Landry, D.; Talapin, D. V. Semiconductor Nanocrystals Functionalized with Antimony Telluride Zintl Ions for Nanostructured Thermoelectrics. J. Am. Chem. Soc. 2010, 132, 6686–6695.

(12) Talapin, D. V; Lee, J.-S.; Kovalenko, M. V; Shevchenko, E. V. Prospects of Colloidal Nanocrystals for Electronic and Optoelectronic Applications. Chem. Rev. 2010, 110, 389–458.

(13) Yun, J.; Cho, K.; Kim, S. Flexible Logic Circuits Composed of Chalcogenide-Nanocrystal-Based Thin Film Transistors. Nanotechnology 2010, 21, 235204.

(14) Kovalenko, M. V; Scheele, M.; Talapin, D. V. Colloidal Nanocrystals with Molecular Metal Chalcogenide Surface Ligands. Science 2009, 324, 1417–1420.

(15) Nag, A.; Kovalenko, M. V; Lee, J.-S.; Liu, W.; Spokoyny, B.; Talapin, D. V. Metal-Free Inorganic Ligands for Colloidal Nanocrystals: S(2-), HS(-), Se(2-), HSe(-), Te(2-), HTe(-), TeS(3)(2-), OH(-), and NH(2)(-) as Surface Ligands. J. Am. Chem. Soc. 2011, 133, 10612–10620.

(16) Fafarman, A. T.; Koh, W.; Diroll, B. T.; Kim, D. K.; Ko, D.-K.; Oh, S. J.; Ye, X.; Doan-Nguyen, V.; Crump, M. R.; Reifsnyder, D. C.; et al. Thiocyanate Capped Nanocrystal Colloids: A Vibrational Reporter of Surface Chemistry and a Solution-Based Route to Enhanced Coupling in Nanocrystal Solids. J. Am. Chem. Soc. 2011, 133, 15753–15761.

(17) Rosen, E. L.; Buonsanti, R.; Llordes, A.; Sawvel, A. M.; Milliron, D. J.; Helms, B. a. Exceptionally Mild Reactive Stripping of Native Ligands from Nanocrystal Surfaces by Using Meerwein’s Salt. Angew. Chem. Int. Ed. 2012, 51, 684–689.

(18) Lee, J.-S.; Kovalenko, M. V; Huang, J.; Chung, D. S.; Talapin, D. V. Band-like Transport, High Electron Mobility and High Photoconductivity in All-Inorganic Nanocrystal Arrays. Nat. Nanotechnol. 2011, 6, 348–352.

(19) Chung, D. S.; Lee, J.-S.; Huang, J.; Nag, A.; Ithurria, S.; Talapin, D. V. Low Voltage, Hysteresis Free, and High Mobility Transistors from All-Inorganic Colloidal Nanocrystals. Nano Lett. 2012, 12, 1813–1820.

(20) Choi, J.-H.; Fafarman, A. T.; Oh, S. J.; Ko, D.-K.; Kim, D. K.; Diroll, B. T.; Muramoto, S.; Gillen, J. G.; Murray, C. B.; Kagan, C. R. Bandlike Transport in Strongly Coupled and Doped Quantum Dot Solids: A Route to High-Performance Thin-Film Electronics. Nano Lett. 2012, 12, 2631–2638.

5

(21) Chung, D. S.; Lee, J.-S.; Huang, J.; Nag, A.; Ithurria, S.; Talapin, D. V. Low Voltage, Hysteresis Free, and High Mobility Transistors from All-Inorganic Colloidal Nanocrystals. Nano Lett. 2012, 12, 1813–1820.

(22) Koh, W.-K.; Saudari, S. R.; Fafarman, A. T.; Kagan, C. R.; Murray, C. B. Thiocyanate-Capped PbS Nanocubes: Ambipolar Transport Enables Quantum Dot-Based Circuits on a Flexible Substrate. Nano Lett. 2011, 11, 4764–4767.

Much of this chapter appears in print: © 2011 IEEE. Reprinted, with permission, from Bink, H.*; Lai, Y.*; Saudari, S.R.; Helfer, B.; Viventi, J.; Van der Spiegel, J.; Litt, B.; Kagan, C., "Flexible organic electronics for use in neural sensing," Engineering in Medicine and Biology Society,EMBC, 2011 Annual International Conference of the IEEE pp.5400,5403, Aug. 30 2011-Sept. 3 2011 * Both authors contributed equally

6

CHAPTER 2 Flexible Organic Electronics for Use in Neural Sensing

2-1: Bio-signal sensors

Electrocorticography (ECoG), the process of recording brain activity through electrodes

placed directly on the cortical surface, is a common technique in the assessment and treatment of

neurological disorders, such as epilepsy. ECoG offers a higher spatial and temporal resolution

interface with the brain than extracranial electroencephalography (EEG), since the electrodes are

smaller and located at a much closer distance to the brain. Penetrating microelectrodes, such as

the Utah array,1 can measure neural activity at a higher spatial resolution, including from single

neurons, but are constrained to interface with small regions of the cortex. Further, the long-term

feasibility of this interface is often limited to only 6-12 months,2 either due tissue damage caused

by the inability of the rigid penetrating electrodes to flex and move as the brain swells and

contracts3 or by damage caused from hemorrhage and inflammation from the initial insertion4.

ECoG does not appear to suffer from this stability issue and has demonstrated consistent signal

quality over extended periods of time with minimized irritation and injury to brain tissue.5,6

Further, ECoG and higher resolution micro-ECoG (µECoG) recordings from flexible

arrays of non-penetrating electrodes may offer comparable information content to the neural

signals recorded from penetrating electrodes in some applications, such as BMI,7–9 decoding

motor control signals10 and decoding spoken words.11 High resolution neural interface is also

important to understanding pathologic brain signals.12 In addition to high spatial resolution,

developing electrode arrays with a high degree of conformality is also important. Highly flexible

arrays of electrodes have the ability to conform to the uneven patterns of sulci and gyri on the

7

surface of the brain, resulting in higher signal to noise ratios in recordings and more electrodes in

contact with the brain.13 Current clinical ECoG arrays use metal electrodes that typically have a

diameter of 3 mm on a grid with 1cm center-to-center spacing.14 Because of these dimensions,

the arrays spatially undersample the electrical signals of the brain. µECoG electrode arrays have

been developed that utilize flexible silicon electronics to create a conformal, dense (800 µm

spacing) electrode array capable of covering large areas (14.4 mm x 12.8 mm) of the brain.15

These devices offer recordings with high spatial and temporal resolution and utilize on-chip

multiplexing to reduce the number of wires coming off the grid. Constructing these silicon devices

can be a difficult and expensive process. Alternatively, organic electronics may be able to be

fabricated at lower cost than flexible silicon electronics on the same type of plastic substrates.

Organic materials are considered a promising candidate for flexible electronics due to the

low temperatures required for fabrication. Through intensive research in the past decades,

organic materials have been shown to exhibit carrier mobility comparable to or higher than

amorphous silicon used in modern active-matrix liquid-crystal displays.16 In addition, synthetic

chemistry is able to tailor organic materials in a way that cannot be done with inorganics. The

increased functionality of organic transistors can enable a broad array of biological signal

monitoring applications. Pentacene, among the highest performance organic thin film

semiconductor materials available, is insoluble in most organic solvents. A soluble pentacene

precursor, developed by A. Afzali et al.,17 can be dissolved in a chlorinated solvent, such as

chloroform, and subsequently thermally converted into pentacene. This production technique

opens the door to large area fabrication of organic transistor circuits at low cost.

In this chapter, we demonstrate solution processable organic thin film transistors that can

be integrated directly into neural electrode arrays. We developed photolithographic methods to

fabricate flexible organic thin film transistors. Combining these devices with custom circuits, we

demonstrate common source and common drain amplifier topologies with performance sufficient

for recording neural signals.

8

2-2: Flexible Pentacene Thin Film Transistors and Printed Circuit Board Design

Figure 2-1. (A) Schematic of the organic thin film transistor, a photographic example of which is seen in (B). (C) and (D) are the representative ID-VDS and ID-VGS properties of the devices, respectively. The channel width is 1500 µm and length is 100 µm. These properties were measured in an inert nitrogen environment.

Pentacene thin film transistors (TFTs) were fabricated in bottom-gate, bottom-contact

configuration on a Kapton® substrate.18,19 A schematic of the device is illustrated in Figure 2-1(A).

Gold gate and source/drain contacts were patterned by photolithography with a thickness of 20

nm. A 500 nm parylene-C dielectric layer was deposited through physical vapor deposition. The

pentacene precursor was applied by spin-coating and then thermally converted to pentacene to

form the bottom-gate, bottom-contact configuration TFT. Figure 2-1(B) shows photograph of

-50 -40 -30 -20 -10 0 10

10-10

10-9

10-8

10-7

10-6

10-5

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= - 50V

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I D (

A)

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-2

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-8

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- 30V

VGS

= - 50V

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I D (µA

)

VDS

(V)

(A)

(C) (D)

pentacene

Kapton®

source drain

gate

parylene

(B)

9

Figure 2-2. The dual PCB board design. The large board contains all elements of the circuit excluding the transistor: the amplifying resistor, low-pass power supply filters, output buffer and high-pass filter, and input/output components. The ribbon cable attaches the transistor to the rest of the circuit. The enlarged image on the left clearly shows the copper fingers used to make pressure contact with the organic TFT underneath.

the device electrodes before spin-coating the organic semiconductor. Representative device

characteristics measured under inert nitrogen environment are shown in Figure 2-1 (C) and

Figure 2-1 (D). Hole accumulation can be seen in the ID-VDS curve, characterized by linearity at

low absolute drain-source biases and saturation at large negative biases. The saturation mobility

is 0.123 ± 0.038 cm2/(Vs), extracted from more than 50 transistors fabricated on different

samples. The on/off current ratio is about 105, as shown in ID-VGS curve [Figure 2-1 (D)]. The

pentacene TFTs were tested in both common source and common drain amplifier configurations.

A circuit consisting of all elements of the amplifying configurations except the transistor was

created using a custom printed circuit board (PCB), which is shown in Figure 2-2.

In order to make the electrical connection between the pentacene TFTs on a flexible

substrate and the PCB, the buried bottom gate had to be revealed. This was done by removing

the pentacene over the electrode pads with chloroform. The parylene dielectric was then

10

selectively etched with oxygen plasma, while keeping the active area protected. An additional

small PCB with switches and finger-shaped beryllium copper contacts on the underside was

designed to make mechanical contact with the flexible substrate of the transistor array. By

clamping the small PCB onto the larger PCB with the flexible transistor array in between, the

beryllium copper fingers are able to make solid mechanical contact with the electrodes of the

transistor array, forming the electrical connection to the PCB. The pressure contact PCB is

highlighted in yellow and enlarged in Figure 2-2. A short ribbon cable was used to connect the

gate, source and drain of the organic transistor to their respective locations on the main PCB. The

circuit on the main PCB was designed to be used for either common source or common drain

amplifying circuits. Since the source and drain of the organic transistors are interchangeable,

switching between the two configurations was possible by changing power supply polarity. A

10MΩ resistor was connected to the drain or source of the organic transistor depending on the

desired circuit topology. This large resistance was used in order to yield higher gain. Power was

supplied the organic transistor amplifier through 0.14 Hz low-pass filters in order to reduce noise

coming from voltage supply electronics. The amplifier output was directly connected to a unity-

gain buffer in order to reduce loading by subsequent measurement equipment.

2-3: Organic Electronics for Sensors with Amplification

The common source amplifier configuration was tested with multiple pentacene TFTs on

the dual PCB setup. The source/drain transistor power supplies were kept at a difference of 50 V.

The maximum gain was 5.0 dB for the highest performance device, while the average gain was

2.3 dB. Figure 2-3 (A) shows a characteristic input/output voltage response for the best transistor

with a 100 µm channel. The source supply was +28 V and the drain supply was -22 V. The input

was a 1 Vpp 10 Hz sine wave. The output is inverted due to the common source topology. The

frequency response for the same organic transistor amplifier in the common source configuration

is shown in Figure 2-3 (B). The 3dB cutoff was observed between 700 and 850 Hz, depending on

11

Figure 2-3. Results from common source amplifier using pentacene TFT showing the (A) representative output versus input and (B) bode plot. Both results shown were taken from the same 100 µm channel length device.

the transistor used. The square wave response rise and fall time of the amplifier was found to be

0.5 ms each.

The common drain topology was tested by reversing the polarity of the TFT power

supplies, effectively exchanging the source and drain. The maximum output of the device with a 1

Vpp input was 0.65 Vpp, or an attenuation of 3.7 dB. A frequency sweep revealed a 3dB

bandwidth of 2.8 kHz, much higher than the common source circuit, as expected.

To test the applicability of using organic electronic in sensing neural signal, a pre-

recorded human EEG data was sent as input with appropriate DC bias for amplification. In Figure

2-4, the output from organic sensor (red) is able to record most of input features from human

EEG data (blue), promising organic electronics for neural sensing.

2-4: Discussion and Conclusions

In addition to the gain of the common source amplifier using pentacene TFTs (between

2.3 dB and 5 dB), the preliminary bench test on recording human EEG suggest organic electronic

101

102

103

-1

0

1

2

3

4

5

Ga

in (

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0 200 400-1.0

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Am

plitu

de

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)

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(A) (B)

12

Figure 2-4. Organic electronic sensor for recording neural signal. (Blue) Pre-recorded human EEG signal, and (Red) measured output from organic electronic sensor. The output signal was inverted for clear comparison.

sensor is able to record neural signal in few mV amplitude. Current ECoG arrays use either

passive electrodes or common drain amplifiers with unity gain. Integrating any level of gain

directly at the electrode should improve the overall system performance. The attenuation seen in

the organic transistor in common drain configuration, 3.7 dB, would decrease the overall system

performance, but would still be acceptable for many neural signal acquisition tasks. The tradeoff

for increased gain is decreased bandwidth: ~800 Hz for the common source configuration versus

~2.8 kHz for the common drain configuration. Given that the majority of clinically relevant, cortical

surface brain activity occurs below 500 Hz,20 a bandwidth of 800 Hz would be sufficient for most

applications. However, developing multiplexed electrode arrays may be difficult, given the low

frequency response of the transistors.

One of the challenges faced while testing the amplifiers was the performance reduction of

the pentacene TFTs in ambient atmosphere. Devices were initially characterized directly after

fabrication, while still immersed in a pure nitrogen environment. The devices were subsequently

retested after being exposed to open air. Carrier mobility, and likewise drain current, both

13

continuously decreased as a result of exposure to moisture and oxygen. Several different

encapsulating materials were applied to the TFTs in preliminary attempts to prevent this

degradation. None of the materials so far investigated effectively protected the devices from

reduction in their performance while exposed to air. There are several items remaining to be

addressed before organic transistors can be used to develop large arrays of multiplexed

electrodes. First, the noise performance of the organic transistor amplifiers will be evaluated to

insure sufficient signal to noise levels in the final system, while measuring neural signals of 1 mV

amplitude or less. Initial noise measurements appear promising. Second, the ability to pattern

hundreds of organic transistors on a single flexible substrate will need to be developed.

Prototypes of such devices have been fabricated, utilizing etching and deposition processes to

create vertical integration access (VIA) holes to connect individual transistors using multiple metal

layers. Finally, a new encapsulation system will need to be developed to fully protect the

transistors from exposure to air and biological fluids. New fabrication procedures and

encapsulation materials are being evaluated for their long term reliability.

The devices described in this chapter have been shown to work as amplifiers with

adequate gain and bandwidth required for clinical and research neural sensor applications. While

additional advancements are necessary, the potential advantages of organic µECoG electrode

arrays motivate continued research to bring them to fruition.

14

2-5: References

(1) Campbell, P. K.; Jones, K. E.; Huber, R. J.; Horch, K. W.; Normann, R. a. A Silicon-Based, Three-Dimensional Neural Interface: Manufacturing Processes for an Intracortical Electrode Array. IEEE Trans. Biomed. Eng. 1991, 38, 758–768.

(2) Ryu, S. I.; Shenoy, K. V. Human Cortical Prostheses: Lost in Translation? Neurosurg. Focus 2009, 27, E5.

(3) Griffith, R. W.; Humphrey, D. R. Long-Term Gliosis around Chronically Implanted Platinum Electrodes in the Rhesus Macaque Motor Cortex. Neurosci. Lett. 2006, 406, 81–86.

(4) Polikov, V. S.; Tresco, P. A.; Reichert, W. M. Response of Brain Tissue to Chronically Implanted Neural Electrodes. J. Neurosci. Methods 2005, 148, 1–18.

(5) Chao, Z. C.; Nagasaka, Y.; Fujii, N. Long-Term Asynchronous Decoding of Arm Motion Using Electrocorticographic Signals in Monkeys. Front. Neuroeng. 2010, 3, 3.

(6) Yeager, J. D.; Phillips, D. J.; Rector, D. M.; Bahr, D. F. Characterization of Flexible ECoG Electrode Arrays for Chronic Recording in Awake Rats. J. Neurosci. Methods 2008, 173, 279–285.

(7) Leuthardt, E. C.; Gaona, C.; Sharma, M.; Szrama, N.; Roland, J.; Freudenberg, Z.; Solis, J.; Breshears, J.; Schalk, G. Using the Electrocorticographic Speech Network to Control a Brain–computer Interface in Humans. J. Neural Eng. 2011, 8, 036004.

(8) Brunner, P.; Ritaccio, A. L.; Emrich, J. F.; Bischof, H.; Schalk, G. Rapid Communication with a “P300” Matrix Speller Using Electrocorticographic Signals (ECoG). Front. Neurosci. 2011, 5, 5.

(9) Ball, T.; Nawrot, W.; Pistohl, T.; Aertsen, A.; Schulze-Bonhage, A.; Mehring, C. Towards an Implantable Brain-Machine Interface Based on Epicortical Field Potentials; Biomed. Tech. (Berlin), 2004; pp. 756–759.

(10) Kellis, S. S.; House, P. a; Thomson, K. E.; Brown, R.; Greger, B. Human Neocortical Electrical Activity Recorded on Nonpenetrating Microwire Arrays: Applicability for Neuroprostheses. Neurosurg. Focus 2009, 27, E9.

(11) Kellis, S.; Miller, K.; Thomson, K.; Brown, R.; House, P.; Greger, B. Decoding Spoken Words Using Local Field Potentials Recorded from the Cortical Surface. J. Neural Eng. 2010, 7, 056007.

(12) Stead, M.; Bower, M.; Brinkmann, B. H.; Lee, K.; Marsh, W. R.; Meyer, F. B.; Litt, B.; Van Gompel, J.; Worrell, G. a. Microseizures and the Spatiotemporal Scales of Human Partial Epilepsy. Brain 2010, 133, 2789–2797.

(13) Kim, D.-H.; Viventi, J.; Amsden, J. J.; Xiao, J.; Vigeland, L.; Kim, Y.-S.; Blanco, J. a; Panilaitis, B.; Frechette, E. S.; Contreras, D.; et al. Dissolvable Films of Silk Fibroin for Ultrathin Conformal Bio-Integrated Electronics. Nat. Mater. 2010, 1–8.

15

(14) Epilepsy & Neurosurgery Product Guide; Ad-Tech Medical Instrument Corporation, 2008; p. 32.

(15) Viventi, J.; Kim, D.-H.; Moss, J. D.; Kim, Y.-S.; Blanco, J. a; Annetta, N.; Hicks, A.; Xiao, J.; Huang, Y.; Callans, D. J.; et al. A Conformal, Bio-Interfaced Class of Silicon Electronics for Mapping Cardiac Electrophysiology. Sci. Transl. Med. 2010, 2, 24ra22.

(16) Klauk, H.; Halik, M.; Zschieschang, U.; Schmid, G.; Radlik, W.; Weber, W. High-Mobility Polymer Gate Dielectric Pentacene Thin Film Transistors. J. Appl. Phys. 2002, 92, 5259.

(17) Afzali, A.; Dimitrakopoulos, C. D.; Breen, T. L. High-Performance, Solution-Processed Organic Thin Film Transistors from a Novel Pentacene Precursor. J. Am. Chem. Soc. 2002, 124, 8812–8813.

(18) Saudari, S. R.; Lin, Y. J.; Lai, Y.; Kagan, C. R. Device Confi Gurations for Ambipolar Transport in Flexible , Pentacene Transistors. Adv. Mater. 2010, 22, 5063–5068.

(19) Saudari, S. R.; Frail, P. R.; Kagan, C. R. Ambipolar Transport in Solution-Deposited Pentacene Transistors Enhanced by Molecular Engineering of Device Contacts. Appl. Phys. Lett. 2009, 95, 023301.

(20) Worrell, G. A.; Gardner, A. B.; Stead, S. M.; Hu, S.; Goerss, S.; Cascino, G. J.; Meyer, F. B.; Marsh, R.; Litt, B. High-Frequency Oscillations in Human Temporal Lobe: Simultaneous Microwire and Clinical Macroelectrode Recordings. Brain 2008, 131, 928–937.

Much of this chapter appears in print: Adapted with permission from D.K. Kim*, Y. Lai*, B.T. Diroll, C.B. Murray, C.R. Kagan, Nature Communications, 3 ,1216, 1-6 (2012) Copyright © 2012, Rights managed by Nature Publishing Group doi: 10.1038/ncomms2218 * Both authors contributed equally

16

CHAPTER 3 High-Performance Nanocrystal Transistors and Integrated

Circuits on Flexible Plastic

In this chapter, we report the first NCIC inverters, amplifiers, and ring oscillators

fabricated from high mobility CdSe NC-FETs. We previously introduced high mobility CdSe NC-

FETs that operated at high voltages on rigid substrates, achieved through both strong coupling,

by introducing the compact ligand ammonium thiocyanate, and through doping, by thermal

diffusion of indium at mild temperatures.1 Thiocyanate is an environmentally benign and non-

corrosive ligand, allowing solution-deposition of NC devices on a variety of substrates, including

flexible plastic substrates, which we have previously demonstrated.2 This greatly expands the

applicability of these materials compared to other recently developed novel ligands. For example,

while excellent mobilities have been observed with molecular metal chalcogenide complexes,3,4

these NCs are dissolved in hydrazine, an extremely caustic solvent that is not compatible with

flexible plastics. In addition, since a wide range of flexible electronic applications are typically

powered by small thin-film batteries or radio frequency fields,5,6 it is necessary to show the

scalability of these colloidal inks to minimize energy consumption. We recently demonstrated

low-voltage operation of flexible colloidal nanowire FETs using thin Al2O3 as our robust, high

capacitance and low leakage gate dielectric material compatible with plastics.7 Here, we

demonstrate high-performance NC-FETs that operate at low-voltages on flexible plastics and

serve as the building blocks of complex integrated circuits, demonstrating this class of materials

as a viable flexible, electronic technology.

3-1: Flexible and Low-Voltage Nanocrystal Field-Effect Transistor

To fabricate flexible devices, we used either a 25 or 50 µm thick polyimide substrate and

covered the substrate with 30 nm of atomic layer deposited (ALD) Al2O3 at 250 oC.

17

Encapsulation with Al2O3 preshrinks the polyimide substrate prior to subsequent thermal

processing, which would otherwise cause severe delamination and cracking of the deposited NC

thin-films and metal electrodes. A 20 nm thick Al back gate was deposited by thermal

evaporation through a shadow mask. The device was exposed to an oxygen plasma to increase

the thickness of the native Al2O3 on the Al gate and to create additional hydroxyl groups

necessary for subsequent growth of a 30 nm ALD Al2O3 gate dielectric layer. The measured

capacitance of the dielectric layer was 0.253 +/- 0.019 µF/cm2, allowing for low-voltage operation.

We also characterized the FET gate leakage at pA levels to verify that current modulation arose

from the CdSe NC thin-film channel and to show that the thin layer of ALD Al2O3 formed a robust

gate oxide that is suitable for use in flexible electronics [Supplementary Figure 3-S1].

To prepare the NC dispersion for spincoating, monodisperse CdSe NCs with as-

synthesized long insulating ligands were treated in solution with ammonium-thiocyanate in a

nitrogen glovebox,1,8 replacing the long ligands with the compact thiocyanate ligands, while

maintaining solution dispersibility. The thiocyanate-exchanged NCs were redispersed in

dimethylformamide and spincast atop the flexible substrates to form uniform, crack-free, randomly

close-packed NC thin-film semiconducting channels. Unlike organic semiconductors, where the

morphology and mobility of the material is reported to be highly dependent on the surface

roughness,9 we found that the NC thin-films are largely insensitive to a root mean squared value

as large as a couple nanometers. Inside a nitrogen glovebox with an integrated evaporator, In/Au

(50 nm/40 nm) electrodes were thermally deposited through a shadow mask atop the NC thin-film

to complete back-gate/top-contact FETs [Figure 3-1(A, B)]. We have also fabricated back-

gate/bottom-contact devices, but these devices typically suffer from larger contact resistance and

therefore display poorer device performance [Supplementary Figure 3-S2 (A – C)]. For the back-

18

Figure 3-1. Flexible CdSe nanocrystal field-effect transistors (NC-FETs). (A) Schematic and (B) photograph of a flexible CdSe NC-FET atop a Kapton® substrate. (C) Output ID – VDS and (D) transfer ID – VG characteristics of a flexible, CdSe NC-FET.

gate/top-contact FETs, typical output [drain current versus drain-source voltage (ID-VDS)] [Figure

3-1 (C)] characteristics show n-type device behavior that is modulated by a small positive voltage

as low as 2 V. The extracted electron FET mobilities from the transfer curves [drain current

versus gate voltage (ID-VG)] [Figure 3-1 (D)] in the linear regime (VDS = 0.1 V) are 21.9 +/- 4.3

cm2V-1s-1 and in the saturation regime (VDS = 2 V) are 18.4 +/- 3.6 cm2V-1s-1. We translated our

previous work on high-performance CdSe NC-FETs on rigid wafers operating at high voltages1 to

plastic substrates operating at low voltages. These FETs show high ION/IOFF over 106, low

subthreshold swing (S = 0.28 +/- 0.09 V/dec), low threshold voltage (VT = 0.38 +/- 0.15 V) and low

hysteresis (∆VT = 0.25 +/- 0.07 V) at VDS = 2 V. We attribute the low hysteresis to passivation of

0.0 0.5 1.0 1.5 2.00

10

20

30

40

50

I D (µA)

VDS

(V)

VG = 2V

1.6V

1.2V

0.8V

0 - 0.4V

-2 -1 0 1 210

-1210

-1110

-1010

-910

-810

-710

-610

-510

-410

-310

-2

VDS

= 0.1V

VDS

= 2.0V

I D (

A)

VG (V)

(A)

(C) (D)

(B)

19

the NC surface by indium and the selection of Al2O3 as the gate dielectric material, which we

have shown to reduce the density of trap states at the NC surface and at the semiconductor-gate

dielectric interface that give rise to hysteresis in NC-FETs.1 As such, the small variation in device

parameters and large-area uniformity of these NC-FETs enables their integration in flexible

NCICs.

To demonstrate the applicability of these high-performance, flexible CdSe NC FETs as

building blocks in integrated circuits, we constructed n-type unipolar inverters, amplifiers and ring

oscillators and studied their basic parameters for analog and digital circuit applications. Similar to

our fabrication of flexible NC-FETs, circuits were fabricated on either 25 or 50 µm thick

preshrunk, Al2O3 encapsulated polyimide substrates with thermally deposited 20 nm Al gate

patterns, but here we developed a simple, additive process for Au filled vertical interconnect

access (VIA) holes to integrate device layers. This VIA process is unlike those previously

developed through Al2O3 that required corrosive and subtractive etching.10,11 A VIA shadow mask

was microscopically aligned to the Al gate lines and 60 nm of Au was thermally deposited to

pattern the VIAs. The sample (with both gate and VIAs) was then exposed to an oxygen plasma

to selectively increase the thickness of the native Al2O3 atop the Al lines, which only grows an

unstable oxide atop Au.12,13 ALD Al2O3 then selectively deposits a high quality oxide atop the Al,

but not atop the Au, which still retains conductivity after ALD, as experimentally verified.

Thiocyanate-exchanged CdSe NCs were then spincast uniformly atop the samples, followed by

thermal evaporation of In/Au electrodes through a shadow mask to form different integrated

circuit topologies.

3-2: Nanocrystal Integrated Inverters

Figure 3-2 (A) shows an optical micrograph of solution-deposited CdSe NCIC inverters

fabricated on flexible plastics substrates. The fabricated integrated inverters are based on a

saturated-load design as depicted in the circuit layout [Figure 3-2 (B)], where one n-type FET acts

as an active load and the other n-type FET as a driver. Since the threshold voltage is positive

20

Figure 3-2. Flexible nanocrystal integrated circuit (NCIC) inverter constructed from nanocrystal field-effect transistors (NC-FETs). (A) Photograph and (B) circuit schematic of saturated-load inverters. (1) Load NC-FET and (2) Driver NC-FET. (C) Graphical analysis of constituent driver (black) and load (red) NC-FET output characteristics, sweeping in forward and reverse, comprising the NCIC inverter, and (D) the corresponding voltage transfer characteristics (black, left axis) and gain characteristics (blue, right axis) of the NCIC inverter sweeping forward and reverse at a supply voltage of 2 V (VDD).

and the drain and gate voltages are identical, the load FET always operates in saturation. Our

CdSe NCIC inverters were designed to have a driver with channel length (L) and width (W) ratio

of 40 (L = 40 µm, W = 1600 µm) and to have a load with W/L of 10 (L = 40 µm, W = 400 µm). We

measured the output characteristics of the constituent driver and load FETs of the inverter

element separately to insure that they operated as designed [Figure 3-2 (C)]. The on-current for

the driver is approximately four times larger than that for the load, as expected from the ratio of

channel W/L. Graphical analysis [Figure 3-2 (C) and Supplementary Figure 3-S3 (A)] provides a

construction of the voltage transfer characteristic (VTC) of our integrated inverter from the

0.0 0.5 1.0 1.5 2.00.0

0.5

1.0

1.5

2.0

VIN

(V)V

OUT (

V)

0.0

-0.5

-1.0

-1.5

-2.0

Ga

in (V

/V)

0.0 0.5 1.0 1.5 2.00

20

40

60

80

2.0 1.5 1.0 0.5 0.0

I D (µA

)

V DRIVER

DS = V

OUT (V)

V LOAD

DS = V

DD - V

OUT (V)

VG = 2V

1.6V

1.2V

0.8V0 - 0.4V

(A)

(C) (D)

(B) VDD

VOUTV

IN

VSS

= GND

1

2

D1

S1

D2

S2

21

constituent NC-FET building blocks. A representative VTC measured from a fabricated flexible,

integrated inverter emulates the constructed VTC [Figure 3-2 (D) and Supplementary Figure 3-S3

(B)]. The inverter gets its name from inverting a “low” input signal to a “high” output signal, and a

“high” input signal to “low” output signal. For multiple flexible inverters, VTCs show a 1.5 +/- 0.1

V output swing, which makes use of 75% of the available supply voltage (VDD = 2 V). The output

swing is consistent with that expected for the saturated-load design, where the voltage output

high is limited by the FET threshold voltage to the difference between supply and threshold

voltages VDD-VT. Our inverters show voltage amplification with gains averaging -1.58 +/- 0.26

V/V, reaching as high as the theoretical gain of -2 V/V. The maximum gain of -2 V/V is consistent

with that expected for a metal-oxide semiconductor common-source amplifier with a saturated-

load, defined by the channel dimensions of the constituent FETs = −

14 and

may be tailored by choice of the load and driver geometries, depending on the design

specification. The low hysteresis in the inverter VTC is ascribed to hysteresis in the NC-FET

characteristics. The inverters' VTCs show wide, linear regions of gain, allowing for input signal

amplification, and inversion of logic output high and low at the extremes of the VTCs, enabling

signal switching. On the other hand, owing to the large input resistance (0.5 TΩ) and relatively

low output resistance (few tens of kΩ) [Supplementary Figure 3-S1 and Discussion], these

amplifiers could also serve as a buffer stage in circuitry. The inverter is the most basic element in

circuits, used to construct amplifiers for analog circuits and logic gates for digital circuits. The

NCIC inverters’ VTCs follow circuit design expectations, with wide output swing and proper gain

and show adequate noise margin [Supplementary Figure 3-S3 (C)], large compared to the low

hysteresis, prerequisites for realizing larger and more complex integrated circuits.

3-3: Nanocrystal Integrated Voltage Amplifiers

In Figure 3-3(A) we demonstrate typical characteristics of the NCIC inverter operating as

a common-source with active load voltage amplifier. A 50 Hz, 100 mV sinusoidal signal is

22

Figure 3-3. Flexible nanocrystal integrated circuit (NCIC) amplifier and Bode plot. (A) Output waveform (blue, right axis) of NCIC voltage amplifier in response to a 50 Hz, 100 mV sinusoidal input on a 0.6V DC bias (black, left axis). (B) Frequency response of a voltage amplifier (black circles). A linear fit (red solid line) shows a 4.59 dB voltage gain at low frequency which is used to find the 3 dB bandwidth (blue dashed line).

superimposed on a 0.6V DC bias at the input (black). The output waveform (blue) is a replica of

the input signal that is linearly amplified with no waveform distortion, is sinusoidally varying about

a DC output voltage of 0.95V as anticipated from the inverter’s VTC, and exhibits a 180 degree

phase shift as expected from a common-source gain stage. The measured frequency response

of the voltage amplifier has a 3dB bandwidth (70.7% magnitude of the maximum gain of 4.59 dB)

of 900 Hz [Figure 3-3 (B)], which is limited by parasitic capacitance in our current circuit design.

We studied the single-time-constant network in the voltage amplifier, and estimated a 3dB

bandwidth of 1.4 kHz [Supplementary Figure 3-S4 and Discussion].

3-4: Nanocrystal Integrated Ring Oscillators

Building on the CdSe NCIC inverter as a logic switch, we integrated multiple inverter

stages to construct the first NCIC ring oscillators. Using the same processes for circuit fabrication

and VIA integration described for the inverter and amplifier, 5-stage ring oscillators (10 NC-FETs)

were fabricated over areas of 2 cm by 6 cm on flexible plastic [Figure 3-4 (A)]. The circuit layout

of the ring oscillator is depicted in Figure 3-4(B), showing the output of the fifth inverter stage

connected to the input of the first inverter stage of the oscillator, and an additional sixth inverter

-30 -15 0 15 30

0.5

0.6

0.7

Time (msec)

0.9

1.0

1.1

Ou

tpu

t (V)In

pu

t (V

)

10 100 1000

-4

-2

0

2

4

6

Ga

in (

dB

)

Frequency (Hz)

-3dB

(A) (B)

23

Figure 3-4. Flexible nanocrystal integrated circuit (NCIC) ring oscillator constructed from NCIC inverters. (A) Photograph, (B) circuit schematic and (C) output characteristics of a five-stage NCIC ring oscillator with a sixth stage buffer operating at a supply voltage of 2 V (VDD) with a frequency of 165 Hz.

used as a buffer stage to minimize the load and interconnect capacitances. Figure 3-4(C) shows

the output characteristics of a 5-stage NCIC ring oscillator. The solution-deposited, NC-FETs

fabricated on plastic substrates form devices with uniform parameters over-large areas to operate

in concert as required to realize ring oscillators. The constituent NCIC inverter stages have

adequate noise margin to support signal propagation through logic switching between “0” (low)

and “1”(high). At the low 2 V supply voltages, the ring oscillator output characteristic has no

distortion across the 1 V rail-to-rail swing, spanning 67% of the output swing or 50% of the supply

voltage. The oscillation frequency is ~165 Hz, i.e. the signal delay per inverter is 606 µs. Similar

to the amplifier, the measured frequency of the ring oscillator is limited by parasitic capacitances

rather than by the intrinsic properties of the NC thin-film. We estimated the signal delay per stage

of the constituent inverters in the 5-stage ring oscillator to be 170 µs [Supplementary Figure 3-

S5, S6 and Discussion], and is the first reported NC-FET based ring oscillator.

0 5 10 15 20 250.2

0.4

0.6

0.8

1.0

1.2

1.4

VOUT (

V)

Time (msec)

VDD

VSS

VOUT

(A)

(C)

(B)

24

3-5: Discussion

The switching speed of the NCIC ring oscillator, which successfully operates at desired

low supply voltages, is comparable to other emerging solution-processable materials with similar

channel lengths (40 µm) and low-voltage operation,15,16 suggesting that colloidal semiconductor

NC inks form a promising class for low-cost thin-film analog and digital electronics. The switching

speeds is sufficient for sensor and display applications.17–19 Faster switching times may be

realized by designing circuits with shorter channel lengths and minimizing the parasitic

capacitance. Improved fabrication techniques to achieve better alignment or to even develop

self-aligned20–22 structures will minimize parasitic capacitances to the femto Farad scale,

promising not only faster switching, but CdSe NCIC voltage amplifiers with MHz bandwidths.

3-6: Conclusion

In summary, we report the first NCICs, demonstrating low-voltage NCIC inverters,

amplifiers and ring oscillators constructed from multiple high-performance NC-FET building

blocks. By taking advantage of the non-corrosive thiocyanate ligand and doping of the CdSe NC

thin-film by mild thermal annealing, we fabricated high-performance NC-FETs and NCICs from

colloidal NC inks over large-areas on flexible plastics. The small variation in device parameters

and large-scale uniformity of our solution-processed NC-FETs enabled functional NCIC circuits

for both analog and digital applications. Recent demonstrations of more sophisticated pseudo-

complementary metal-oxide semiconductor circuits based on unipolar devices may be applied to

improve the performance of these flexible NCICs.23 With continued advances in NC ligand

chemistry and doping, this class of solution-processable materials promises to grow beyond

unipolar circuits to complementary metal-oxide semiconductor based NCICs constructed from

high-performance n- and p-type NC-FETs from the wide-range of available colloidal NC ink

chemistries.

25

3-7: Methods

Materials: Anhydrous solvents (highest grade available) were purchased from Acros or purged

and dried by standard methods. Ammonium thiocyanate (Acros, 99.8%+) was recrystallized from

dry alcohol. Trioctylphosphine oxide (90%), tributylphosphine (97%), octadecylamine (99%), and

selenium shot (99.99%) were purchased from Sigma-Aldrich. Cadmium stearate was purchased

from MP Biomedicals. Kapton® was purchased from DuPont.

CdSe Nanocrystal Synthesis: Cadmium selenide nanocrystals were synthesized following a

modified literature procedure:24 20.0 g trioctylphosphine oxide, 20.0 g octadecylamine, and 2.10

g cadmium stearate were held under vacuum 1 hour at 120 °C, then heated to 320 °C under

nitrogen, then 10.0 mL 1.25 M selenium in tributylphosphine solution was injected. Particle

growth continued at 290 °C for 15 min. The peak of the first absorption maximum ranged from

580 to 583 nm across several independently synthesized batches.

Ligand Exchange with Ammonium Thiocyanate: The exchange was performed in nitrogen

atmosphere based on our previously published procedure1,8 and optimized for each individual

batch of NCs. Typically, 1.0 mL of NH4SCN ranging in concentration from 100 to 250 mM in

acetone was combined with 2.0 mL of CdSe NCs dispersed in hexane at an optical density of 5 to

10 per cm3 at the first excitionic absorption feature. The mixture was stirred with a vortexing

mixer at 3000 rpm for 2 min, with complete flocculation observed within seconds. The slurry was

centrifuged at 3000g for 1 min and the clear, colorless supernatant discarded. 2.0 mL of

tetrahydrofuran was added and the slurry mixed at 3000 rpm for 2 min, centrifuged at 3000g for 1

min and the clear, colorless supernatant discarded once more. 2.0 mL of toluene was added and

the slurry mixed at 3000 rpm for 1 min, centrifuged at 3000g for 1 min and the clear, colorless

supernatant discarded. Dimethylformamide was added to the pellet to the desired concentration

and the mixture was gently agitated until the NCs were fully dispersed.

26

Flexible Device Fabrication: N-type unipolar NC-FETs and NCICs (inverters, amplifiers and ring

oscillators) were fabricated on either 25 or 50 µm thick preshrunk, Al2O3 encapsulated polyimide

substrates with thermally deposited 20 nm Al gate patterns. A Cambridge Nanotech Savannah

200 system was used to deposit Al2O3 at 250 oC using trimethylaluminum and water precursors.

For integrated circuits, a subsequent VIA shadow mask was microscopically aligned and 60 nm of

Au was thermally deposited to pattern the VIAs and integrate device layers. Both the FETs (only

gate) and integrated circuits (both gate and VIA) were exposed to an oxygen plasma (75 mTorr,

100 W, 10 min) in a turbo-pumped parallel-plate reactive ion etcher at a base pressure of 3 x 10-6

Torr to selectively increase the thickness of the native Al2O3 atop the Al lines, but grew an

unstable oxide atop Au VIAs in NCICs.13,25 ALD Al2O3 then selectively deposits a high quality

oxide atop the Al, but not atop the Au VIAs in NCICs, which still retain conductivity after ALD, as

verified experimentally. Thiocyanate-exchanged CdSe NCs dispersed in dimethylformamide were

then spincast uniformly atop the flexible substrates. A dispersion with an optical density of 40 was

filtered through a 0.2 µm polytetrafluoroethylene filter and spincast at 500 rpm for 30 seconds,

followed by 800 rpm for 30 seconds to yield dense, crack-free uniform NC thin-films. In/Au

electrodes were thermally evaporated through a shadow mask to either form FETs or integrated

circuits in a nitrogen glovebox with an integrated evaporator. Devices were annealed in a nitrogen

atmosphere for 10 min at 250 ºC.

FET and NCIC Device Measurements: FET device characterization was performed on a Model

4156C semiconductor parameter analyzer (Agilent) in combination with a Karl Suss PM5 probe

station mounted in a nitrogen glovebox. Capacitance measurements (metal/dielectric/metal) were

done using a Hewlett-Packard 4276A LCZ meter. Inverter, amplifier and ring oscillator

measurements were carried out using an oscilloscope from Tektronix, 33220A waveform

generator from Agilent and a low-noise JEFT-input operational amplifier as the unity gain buffer.

27

3-8: Supplementary Information

Supplementary Figures

Figure 3-S1. Gate leakage current of 30 nm Al2O3 atomic layer deposited dielectric. The estimated oxide resistance is 0.5TΩ, which is a measure of the input resistance of the nanocrystal integrated circuit (NCIC) inverters.

Figure 3-S2. Back-gate/bottom-contact CdSe nanocrystal field-effect transistors (NC-FETs). (A) Schematic and (B) output (ID-VDS) and (C) transfer (ID-VG) curves.

-2 -1 0 1 2

10-13

10-12

10-11

10-10

10-9

10-8

10-7

10-6

I D (

A)

VG (V)

J (A

/cm

2)

CdSe NC Film

Kapton®

AlAl

2O3

In

Au

In

Au

Al2O3

-2 -1 0 1 2

10-9

10-8

10-7

10-6

10-5

10-4

VDS

= +2V

I D (

A)

VG (V)

0.0 0.5 1.0 1.5 2.00

4

8

12

16

20

I D (µ

A)

VDS

(V)

(C)(B)

(A)

28

0.0 0.5 1.0 1.5 2.00.0

0.5

1.0

1.5

2.0

VOUT (

V)

VIN

(V)

0.0 0.5 1.0 1.5 2.00.0

0.5

1.0

1.5

2.0

VOUT (

V)

VIN

(V)

0.0 0.5 1.0 1.5 2.00

5

10

15

20

2.0 1.5 1.0 0.5 0.0

0 - 0.4V

0.8V

VG = 1.2V

Load

I D (µA

)

V DRIVER

DS = V

out (V)

Driver

V LOAD

DS = V

DD - V

out (V)

(A) (B)

(C)

29

Figure 3-S3. Graphical and Noise Analysis of CdSe nanocrystal integrated circuit (NCIC)

inverter. (A) Graphical analysis, only shown to magnifying low ID to 20 µA. (B) the constructed

points (red) versus measured (black) voltage transfer characteristic (VTC) for a CdSe NCIC

inverter on a plastic substrate. (C) The original VTC (black solid line) overlaid with its mirror

image (red solid line). VIN

= VOUT

(blue dashed line). The inscribed gray squares define the noise

margin high and noise margin low to be 0.1 V. Inverter Operation: The fabricated inverter is

based on a saturated-load design [Figure 3-2 (A, B)], where one n-type field-effect transistor

(FET) acts as an active load and the other n-type FET as a driver. The load FET has its source

connected to the inverter’s output (VOUT) and its drain and gate are both connected to the

inverter’s supply voltage (VDD). The load FET always operates in saturation because the gate

and drain-source voltages are identical ensuring that − < for a positive

threshold voltage. The driver FET has its gate connected to the inverter’s input (VIN), its drain

connected to the inverter’s output (VOUT) and its source connected to ground (VSS). During device

operation when the inverter input is “low” (VIN = 0), the driver FET is in the off-state and exhibits

very large resistance. The supply voltage will be divided dropping across the more resistive

driver FET than load FET, causing the output voltage to exhibit a “high” voltage that is about the

difference between the supply voltage and the load’s threshold voltage (0) = − . When the input of the inverter is “high” = , the driver FET will be in the on-state and

exhibit very low resistance. The divided voltage will now be predominantly across the load,

causing the output node to exhibit a “low” voltage that is close to ground. Inverter Voltage

Transfer Characteristics: Graphical analysis of the load and driver FET intercept points are

used to construct the inverters’ VTCs.30 The low hysteresis in the NCIC VTCs provides adequate

noise margin at both logic high and low regions. Noise margin is evaluated by taking the original

VTC overlaid with its’ mirror image (VIN = VOUT as mirror plane). The largest inscribed square

area defines the inverter’s noise margin.41 The noise margin ensures the inverter functions

correctly in complex integrated circuits, providing logic switching (eg. in the 1st inverter stage, 0.4

V input will output at 1.3 V, and this 1.3 V is the input for the 2nd stage inverter and output at 0.4

V.)

30

Figure 3-S4. CdSe Nanocrystal Integrated Circuit (NCIC) Amplifier Equivalent Circuit Modeling. (A) Small-signal equivalent-circuit model of a common-source amplifier with a saturated-load design. (B) Schematic of parasitic and interconnect capacitances. (C) The simplified model from Supplementary Figure 3-S4 (A) and Figure 3-S4 (B).

Vout

ro1 = 1/gds1

gm2 Vgs2

ro2 = 1/gds2

1/gm1

+

-

Vin = Vgs2

VDD

VOUT

VIN

VSS

= GND

D1

S1

D2

S2

Cint

cgs1

cgd1

cgd2

cgs2

rtotal

Ctotal

Vout

(A)

(B) (C)

31

Figure 3-S5. Propagation delay definitions in the inverter’s output waveform.

Figure 3-S6. CdSe Nanocrystal Integrated Circuit (NCIC) Ring Oscillator Equivalent Circuit Modeling. An example of parasitic capacitance for a 3-stage ring oscillator with an additional inverter serving as a buffer. Note that the Miller effect is applied to Cgd2.

V90%

= V1

V10%

= V0

1

2 3

VOUT

t

VOH

-Vt

ta

tb

td

te

VOH

VOL t

c

D1

S1

D2

S2

Cgs1

Cgd1

Cgd2

Cgs2

D1

S1

D2

S2

Cgs1

Cgd1

Cgd2

Cgs2

D1

S1

D2

S2

Cgs1

Cgd1

Cgd2

Cgs2

D1

S1

D2

S2

CINT

Cgs1

Cgd1

Cgd2

Cgs2

32

Supplementary Discussion:

Voltage Transfer Function and Frequency Analysis:30,42,43 The Bode plot describes voltage

gain in dB (defined as Gain(dB) = 20log|Gain(VOUT/VIN)|) as a function of input frequency.

Voltage gain is decreasing with increasing input frequency due to the single-time-constant (STC)

networks naturally formed in the circuits. The frequency region where the voltage amplifier’s gain

remains within 3 dB (or 70.7% magnitude of maximum gain) is the amplifier bandwidth (f3dB). To

study STC networks, the small-signal equivalent-circuit model is applied. Each of the load and

driver field-effect transistors (FETs) are defined in terms of their transconductance, output

resistance and parasitic capacitance. In this model, only capacitance components connected to

VOUT node need to be considered, which includes Cgs1 of the load and Cgd2 of the driver. The

transconductance ≡

and output resistance =

=

can be directly extracted

from the discrete nanocrystal field-effect transistor (NC-FET) transfer and output characteristics.

Both load and driver FETs are operating in saturation in the voltage amplifier. We assume that

the major source of Cgs1 includes geometrical overlap capacitance and channel capacitance

resulting from the interaction between gate and channel charges. To account for Cgd2, the Miller

effect is applied to decouple its connection between the input and output. Therefore, Cgd2

will be

replaced by × 1 + at the input node and by × 1 +

at the output node,

respectively. In addition, the interconnect capacitance (CINT) is considered, and is minimized via

a unity-gain buffer during the measurement. All capacitance could be expressed as a lumped

capacitance with respect to ground:

= = + × 1 +1

+

where the average gain of 1.58 +/- 0.26 V/V is used in the following calculation. On the other

hand, the total resistance at the output node is:

= =1

+ +

33

where gds1 and gds2 are negligible compared to gm1 values.

As a result, the entire STC network forms a low-pass filter, where the 3dB bandwidth is defined

by:

=1

2

The 3 dB bandwidth solely depends on the RC time constant inherited in the STC network, and

will be used to estimate the frequency response of the CdSe nanocrystal integrated circuit (NCIC)

voltage amplifier. The extracted transconductances of the constituent FETs in the amplifier are

15.8 µS for gm1 (load) and 28.2 µS for gm2 (driver). The calculated output resistance based on gm1

values is on the scale of tens of kΩ, which is relatively low compared to the 0.5 TΩ input

resistance [Figure 3-S1]. Knowing the unit capacitance (0.253 µF/cm2) and device dimensions,

the calculated parasitic capacitance is 77 pF for Cgs1

(load) and 200 pF for Cgd2 (driver). The

interconnect capacitance (CINT), which mainly is contributed to by the contact probes and

connecting cables, was measured by an LCR meter to give a CINT value of 150 pF. The total

capacitance (CTOTAL) is 554 pF. The estimated f3dB based on the RC product is 4.5 KHz, 5 times

larger than the 3dB bandwidth from [Figure 3-3(B)], suggesting an underestimation of the RC

product. To verify the RC values, we used an impedance analyzer to measure the

transconductance of the constituent load and driver FETs. The measured gm1 is 5.0 µS and gm2

is 7.5 µS. Because of the smaller gm1 and gm2 values, the RC product is enhanced and leads to a

smaller f3dB of 1.4 kHz, which is very similar to the measured bandwidth [Figure 3-3(B)]. The

difference of gm values might be attributed to nonlinearity in the transfer characteristics at low

bias. To enhance the bandwidth for higher frequency applications, R needs to be smaller by

increasing gm, or the undesirable parasitic and interconnect capacitance should be kept as small

as possible.

34

Ring Oscillator and Propagation Delay: 30,42,43 From the oscillation frequency, we can derive

the propagation delay τP per stage:

=1

2 × ×

where f is the oscillation frequency and N is number of stages. This gives a propagation delay of

606 µs. To estimate the propagation delay, we calculated the fall and rise times of the signal at

the inverters output node respectively.

Charging/discharging at the output node via the current during switching is described by:

= −

For a unipolar inverter with a saturated-load design, during the fall time (τFALL) the output node is

pulled down by the driver FET. The driver FET will be in the saturation regime in region (1) and

the linear regime in region (2), where different current expressions will describe different time

segments. On the other hand, during the rise time (τRISE) the output node is pulled up by the

saturated-load FET and the current is described by that of the load FET, which is always in

saturation. From the NCIC inverter VTC, the average highest output (VOH) is 1.6 V, the average

lowest output (VOL) is 0.1 V and the average threshold voltage is 0.4 V. Here we use V10% and

V90% level criteria to describe logic low (V0) and logic high (V1) respectively.

% = = + 0.1 × −

% = = + 0.9 × −

For the fall time, where output V1 is pulled down to output V0, region (1) can be estimated by

assuming the driver FET is in saturation:

=!"#!

2 −

35

= −2 !"#! − $

%

%

& − ' = 2 − + !"#! −

and region (2) by assuming the driver FET in the linear regime:

=!"#!

22 − −

= −2 1

!"#!2 − −

$

%

%

( − & = !"#! × − ln 2 − −

where CLOAD is the total load capacitance, VT is the threshold voltage, and βDRIVER is the product

of !"#$% × &'('') × )*!"#!

. The sum of region (1) and region (2) describes the

fall time. The rise time is where the output is pulled up from V0 to V1 by the saturated-load FET

and is described by:

=2

− − =2

−

= − 1

2

−

%

%

+ − =2 − − − − 1

where βLOAD is the product of !"#$% × &'('') × )*

. In contrast to the single

inverter, the parasitic capacitance of each inverter stage in the ring oscillator has to include Cgs2,

which is the input capacitance of the next inverter, as well as the contribution from Cgd2 because

of the Miller effect. The last inverter includes additional input capacitance of the buffer inverter.

36

The calculated Cgs2 value is 310 pF, where geometrical overlap and channel capacitance is

included, and Cgd2 and Cgs1, as described above, are 200 pF and 77 pF. As a result, the

oscillation frequency can be estimated as follows:

=1

4,($-) + !#($-) + ,(.) + !#(.)

The estimated oscillation frequency is 585 Hz for a 5-stage ring oscillator, with a propagation

delay of 170 µs. The calculation of the fall and rise times is based on an input signal which is an

ideal step function. In a feedback loop such as a ring oscillator, the input signal is not ideal and

will have a delayed response similar to the output waveform. The delayed input will influence the

output response, and therefore lead to slower fall and rise times. More sophisticated models and

simulation work are required to emulate the real ring oscillator operation. However, the calculation

of the fall and rise times provides a reasonable estimation of oscillation frequency.

Supplementary Methods

Mobility Calculations: The devices operate in accumulation mode when a positive gate bias is

applied, exhibiting n-type behavior and well-behaved FET characteristics to be modeled by

standard FET equations.44

For low drain-source voltage (VDS) operation, where the overdrive voltage (gate voltage

minus threshold voltage) − > > 0 (linear regime), the drain current (ID) rises linearly

with gate voltage (VG), and a linear FET mobility can be determined by:

* =+

#, -./0/12

where L is the channel length, W is the channel width, CDIEL is the capacitance per unit area of

the dielectric layer, and

is extracted from a ID vs VG transfer curve at constant VDS.

37

For high VDS operation, where > − > 0 (saturation regime), the saturation FET mobility

can be determined by:

* =2+

#, /0/

where the square-root of the current ID rises linearly with VG and can be used to extract the

transconductance in the saturation regime.

3-9: References

(1) Choi, J.-H.; Fafarman, A. T.; Oh, S. J.; Ko, D.-K.; Kim, D. K.; Diroll, B. T.; Muramoto, S.;

Gillen, J. G.; Murray, C. B.; Kagan, C. R. Bandlike Transport in Strongly Coupled and Doped

Quantum Dot Solids: A Route to High-Performance Thin-Film Electronics. Nano Lett.

2012, 12, 2631–2638.

(2) Koh, W.-K.; Saudari, S. R.; Fafarman, A. T.; Kagan, C. R.; Murray, C. B. Thiocyanate-Capped

PbS Nanocubes: Ambipolar Transport Enables Quantum Dot-Based Circuits on a Flexible

Substrate. Nano Lett. 2011, 11, 4764–4767.

(3) Lee, J.-S.; Kovalenko, M. V; Huang, J.; Chung, D. S.; Talapin, D. V. Band-like Transport,

High Electron Mobility and High Photoconductivity in All-Inorganic Nanocrystal Arrays.

Nat. Nanotechnol. 2011, 6, 348–352.

(4) Chung, D. S.; Lee, J.-S.; Huang, J.; Nag, A.; Ithurria, S.; Talapin, D. V. Low Voltage,

Hysteresis Free, and High Mobility Transistors from All-Inorganic Colloidal Nanocrystals.

Nano Lett. 2012, 12, 1813–1820.

(5) Klauk, H.; Zschieschang, U.; Pflaum, J.; Halik, M. Ultralow-Power Organic Complementary

Circuits. Nature 2007, 445, 745–748.

(6) Ha, M.; Xia, Y.; Green, A. a; Zhang, W.; Renn, M. J.; Kim, C. H.; Hersam, M. C.; Frisbie, C. D.

Printed, Sub-3V Digital Circuits on Plastic from Aqueous Carbon Nanotube Inks. ACS Nano

2010, 4, 4388–4395.

(7) Kim, D. K.; Lai, Y.; Vemulkar, T. R.; Kagan, C. R. Flexible, Low Voltage and Low Hysteresis

PbSe Nanowire Field-Effect Transistors. ACS Nano 2011, 5, 10074–10083.

(8) Fafarman, A. T.; Koh, W.; Diroll, B. T.; Kim, D. K.; Ko, D.-K.; Oh, S. J.; Ye, X.; Doan-Nguyen,

V.; Crump, M. R.; Reifsnyder, D. C.; et al. Thiocyanate Capped Nanocrystal Colloids: A

Vibrational Reporter of Surface Chemistry and a Solution-Based Route to Enhanced

Coupling in Nanocrystal Solids. J. Am. Chem. Soc. 2011, 133, 15753–15761.

38

(9) Sekitani, T.; Zschieschang, U.; Klauk, H.; Someya, T. Flexible Organic Transistors and

Circuits with Extreme Bending Stability. Nat. Mater. 2010, 9, 1015–1022.

(10) Sun, D.; Timmermans, M. Y.; Tian, Y.; Nasibulin, A. G.; Kauppinen, E. I.; Kishimoto, S.;

Mizutani, T.; Ohno, Y. Flexible High-Performance Carbon Nanotube Integrated Circuits.

Nat. Nanotechnol. 2011, 6, 156–161.

(11) Mourey, D. A.; Jackson, T. N. Fast Flexible Plastic Substrate ZnO Circuits. IEEE Electron

Device Lett. 2010, 31, 323–325.

(12) Gottfried, J. Oxidation of Gold by Oxygen-Ion Sputtering. Surf. Sci. 2003, 523, 89–102.

(13) Ron, H.; Matlis, S.; Rubinstein, I. Self-Assembled Monolayers on Oxidized Metals. 2. Gold

Surface Oxidative Pretreatment, Monolayer Properties, and Depression Formation.

Langmuir 1998, 14, 1116–1121.

(14) Sedra; Smith. Microelectronic Circuits, 6th Edn; 6th editio.; Oxford University Press, 2009.

(15) Herlogsson, L.; Cölle, M.; Tierney, S.; Crispin, X.; Berggren, M. Low-Voltage Ring

Oscillators Based on Polyelectrolyte-Gated Polymer Thin-Film Transistors. Adv. Mat.

2010, 22, 72–76.

(16) Xia, Y.; Zhang, W.; Ha, M.; Cho, J. H.; Renn, M. J.; Kim, C. H.; Frisbie, C. D. Printed Sub-2 V

Gel-Electrolyte-Gated Polymer Transistors and Circuits. Adv. Funct. Mater. 2010, 20, 587–

594.

(17) Andersson, P.; Forchheimer, R.; Tehrani, P.; Berggren, M. Printable All-Organic

Electrochromic Active-Matrix Displays. Adv. Funct. Mater. 2007, 17, 3074–3082.

(18) Gelinck, G. H.; Huitema, H. E. A.; van Veenendaal, E.; Cantatore, E.; Schrijnemakers, L.;

van der Putten, J. B. P. H.; Geuns, T. C. T.; Beenhakkers, M.; Giesbers, J. B.; Huisman, B.-

H.; et al. Flexible Active-Matrix Displays and Shift Registers Based on Solution-Processed

Organic Transistors. Nat. Mater. 2004, 3, 106–110.

(19) Someya, T.; Kato, Y.; Sekitani, T.; Iba, S.; Noguchi, Y.; Murase, Y.; Kawaguchi, H.; Sakurai,

T. Conformable, Flexible, Large-Area Networks of Pressure and Thermal Sensors with

Organic Transistor Active Matrixes. Proc. Natl. Acad. Sci. U.S.A. 2005, 102, 12321–12325.

(20) Tseng, H.-Y.; Subramanian, V. All Inkjet Printed Self-Aligned Transistors and Circuits

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(21) Javey, A.; Guo, J.; Farmer, D.; Wang, Q. Self-Aligned Ballistic Molecular Transistors and

Electrically Parallel Nanotube Arrays. Nano Lett. 2004, 4, 1319–1322.

39

(22) Palfinger, U.; Auner, C.; Gold, H.; Haase, A.; Kraxner, J.; Haber, T.; Sezen, M.; Grogger, W.;

Domann, G.; Jakopic, G.; et al. Fabrication of N- and P-Type Organic Thin Film Transistors

with Minimized Gate Overlaps by Self-Aligned Nanoimprinting. Adv. Mat. 2010, 22,

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(23) Huang, T.-C.; Fukuda, K.; Lo, C.-M.; Yeh, Y.-H.; Sekitani, T.; Someya, T.; Cheng, K.-T.

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Much of this work appears in print: Adapted with permission from Y. Lai, H. Li, D.K. Kim, B.T. Diroll, C.B. Murry, C.R. Kagan, ACS NANO, 8,9,9664-9672 (2014) Copyright 2014 American Chemical Society

40

CHAPTER 4 Low Frequency Noise in Nanocrystal Field-Effect Transistors

4-1: Models for flicker noise

Flicker noise (also known as 1/f noise) is often dominant at f < 100 kHz in nearly all

electronic devices. In integrated circuits, flicker noise is known to reduce the noise margin and

lead to unstable circuits.1 1/f noise, while undesirable for device applications, also has developed

into a field of interest to probe the mechanisms of charge transport in electronic materials.2–5 The

1/f noise in electronic materials is commonly explored in the geometry of the field-effect transistor.

Two models have been proposed to explain the origin of the noise. Flicker noise arises from

current fluctuations ∆3 ∝ 45(∆6) + 4(∆5)6, dominated by carrier mobility fluctuations (∆µ), in the

Hooge model,6 or carrier number fluctuations (∆N), in the McWhorter model.7 In the Hooge

model, mobility fluctuations arise from scattering between carriers and phonons or impurities.8,9

The magnitude and frequency dependence of the noise generated by these current fluctuations is

described by the noise spectral density. The noise spectral density expression10 depends on

device operation mode. In the transistor’s linear regime, the noise spectral density is described by

7/8 = 01

234

35956 (4-1)

and in the saturation regime by

7/8 = 34

4√; 1

7 2

8

359 :; (4-2)

where µ is the carrier mobility, αH is the Hooge parameter, W and L are the device channel width

and length, Cox is the oxide unit capacitance, and ID is the device drain-source current. In the

McWhorter model, it is believed that traps inside the gate oxide layer of the transistor serve as

41

centers for trapping-detrapping and lead to the carrier number fluctuations that appear as 1/f

noise. The noise spectral density is given by

7/8 = 0

<=

>724?8

@

A35: (4-3)

where NT is the trap density of states (eV-1 cm-3) near the Fermi energy, γ is the tunneling

parameter of traps (< = = >? ,> = @.=AB), and η is related to the subthreshold swing S defined

as C =06

B2C@DE<= and7 =

FGF(HIJ/)

. This model has been extended to include traps that originate

from imperfections in the semiconductor layer, either from bulk defects or from grain boundaries

in amorphous and polycrystalline materials.11–13 Both Hooge and McWhorter models have been

extensively applied to conventional Si and III-V FETs,14–16 and recently have been used to

describe noise in transistors constructed from novel semiconductor materials, such as organic

semiconductors,17–19 graphene,20–22 carbon nanotubes23,24 and nanowires.25,26 Nonetheless, the

theory of 1/f noise still engenders great debate.

In this chapter, we report a systematic study of the low-frequency noise in CdSe

nanocrystals field-effect transistors (NC-FETs) and show the noise has 1/f behavior. We compare

device performance and 1/f noise amplitude from devices with in top-contact (TC) and bottom-

contact (BC) geometries. The noise in BC NC-FETs is governed by the source-drain to NC thin-

film contacts, whereas in TC NC-FETs noise arises from the nanocrystal (NC) channel, giving us

a platform to study and correlate noise spectral density and charge transport mechanisms in NC

thin films. We show that 1/f noise relates to NC thin-film electronic structure, where the

McWhorter model describes 1/f noise in the subthreshold regime and the Hooge model describes

1/f noise in the device linear and saturation regimes. The noise is described by a Hooge

parameter of 3 x 10-2, comparable to what has been reported in polycrystalline CdSe,27 solution-

deposited organic semicondutor,19 and amorphous InGaZnO thin-film transistors28, and is within

one order of magnitude of that for amorphous-Si transistors.14

42

4-2: Flicker Noise Relationship to Device Geometry

Figure 4-1 (A,B) shows device output characteristics and Supporting Information Figure

4-S1(A) compares device transfer characteristics for TC and BC NC-FETs, respectively. Higher

current levels are seen above threshold in the TC devices as the field-effect mobility for electrons

in TC devices is higher than that in BC devices [Table 4-1]. To study the origin of the performance

difference, the trap density at the semiconductor/gate dielectric interface and the device

resistances are analyzed. The trap density at the semiconductor/gate dielectric interface can be

derived from the subthreshold swing

7 =<=

0× DA=@ × (= +

0>8

) (4-4)

where Nit is the interface trap density (cm-2).29 The subthreshold slope for TC and BC devices is

nearly identical, as expected given that both devices present the same CdSe NC/Al2O3 interface,

and therefore have a similar calculated average interface trap density over several devices of 5.0

± 1.8 x 1012 cm-2 for TC and 5.5 ± 0.5 x 1012 cm-2 for BC configurations. Using the output

characteristics in the linear regime, we calculate the contact resistance according to the

transmission line method [%K%L ∗ , = MK%M% + MNOL ∗ + ]. Supporting Information Figure 4-

S1 (B,C) shows the total device resistance (Rtotal) as a function of channel length for different gate

voltages (VGS) that is used to extrapolate the contact resistance (Rcontact), assuming a uniform

channel resistance (Rchannel). The results are summarized for VGS = 50 V in [Table 4-1]. It is

evident that the BC devices suffer from large contact resistance, as high as 77% of the total

resistance in L = 30 µm devices.

Contact resistance distinctly influences the field-effect mobility of BC devices, such that

high contact resistances at shorter channel lengths reduce the effective device mobility. For TC

devices, Rchannel is dominant over the Rcontact [Table 4-1 and Supporting Information Table 4-S1].

In fact we find negative values of Rcontact, which we believe is an artifact arising from the

assumption of uniform Rchannel adopted in transmission line method. A slight trend of increased

43

Figure 4-1. Device output characteristics (ID-VDS) for (A) top-contact and (B) bottom-contact CdSe NC-FETs. Normalized drain current spectral density (SI/ID

2) vs frequency for (C) top-contact and (D) bottom-contact CdSe NC-FETs, where the channel width over length ratio (W/L) is 15 for all devices and the length is (magenta) 40 µm (green) 50 µm, (blue) 100 µm, (red) 150 µm and (black) 200 µm. Insets in (A) and (B) are schematics of the top-contact and bottom-contact NC-FETs, respectively. Insets in (C) and (D) show the relationship between noise amplitude and device area for a representative frequency of 10 Hz.

mobility for shorter channel devices is observed, which we attribute to nonuniformities in indium

diffusion and doping as the channel length increases.30

Figure 4-1 (C,D) shows representative normalized drain current spectral density (SI/ID2)

vs frequency characteristics for varying channel length TC and BC devices, respectively,

measured in the saturation regime (VDS = 50 V, VGS = 50 V). The low-frequency noise displays

typical 1/f dependence, and clearly shows that BC devices have higher noise than TC devices at

each equivalent channel length. Noise amplitude (A), defined as E = P(Q)

=

R

Q , scales linearly

0 10 20 30 40 50

0.0

0.5

1.0

1.5

2.0

I D (

mA

)

VDS

(V)

VGS

= 50V

40V

30V

20V

0 10 20 30 40 50

0.0

0.1

0.2

0.3

0.4

0.5

I D (

mA

)

VDS

(V)

20V

30V

40V

VGS

= 50V(A) (B)

(C) (D)

10 100

10-14

10-13

10-12

10-11

10-10

10-9

SI/I

D

2

(1/H

z)

Frequency (Hz)10 100

10-13

10-12

10-11

10-10

10-9

10-8

10-7

SI/I

D

2

(1/H

z)

Freqency (Hz)

Gate

CdSeS D

Dielectric

Gate

CdSe

S DDielectric

0

10

20

30

40

50

0

1

2

3

(x10-6µm

2

)

Noise

Amplitude

1/area

(x10-10)

0

10

20

30

40

50

0

10

20

30

40

50

(x10-12)

Noise

Amplitude

1/area

(x10-6

µm2

)

44

Table 4-1. Device resistances extracted using the transmission line method and carrier mobilities for TC and BC devices. All data shown is at VGS = 50 V. Note: Only saturation regime mobilities are presented in this table, as mobility for NC-FETs is weakly dependent on VDS.

30

with device channel area for both TC and BC device configurations [Figure 4-1 (C,D) inset],

consistent with previous reports that noise is inversely proportional to carrier number.14,31

Since Rcontact is extracted from linear regime device characteristics, we compare SI/ID2

measured in the saturation (VDS = 50 V, VGS = 50 V) to that in the linear regime (VDS =5 V, VGS =50

V). Supporting Information Figure 4-S1 (D) shows the noise is similar in the linear and saturation

regimes at VGS = 50 V, suggesting that the noise is weakly dependent on VDS. To validate this,

noise is assumed to be the sum of two uncorrelated noise sources, one from the channel and the

other from the contacts, and is expressed as follows

=

=

=

() (4-5)

where SRchannel and SRcontact are the noises from the channel and contact regions and Rchannel and

Rcontact are the channel and contact resistances, as described above.14,32 These four components

VGS

= 50 V

Channel

Length

(µm)

Top contact Bottom contact

Rtotal

(Ω)Mobility

(cm2/Vs)R

total(Ω)

Mobility

(cm2/Vs)

30 8.8x103 -2.1x103 25.0 7.7x104 5.9x104 2.26

40 9.4x103 -1.6x103 24.5 6.2x104 4.4x104 2.69

50 9.7x103 -1.3x103 22.9 5.3x104 3.6x104 3.11

100 1.0x104 -6.5x102 20.7 - - -

150 1.0x104 -4.3x102 19.9 2.9x104 1.2x104 6.95

200 - - - 2.6x104 8.9x103 9.38

)(ΩW

Rcontact

)(ΩW

Rcontact

45

Table 4-2. Length dependent normalized drain current spectral density relationship for W/L= constant and W= constant.

depend on W and L. We derive the dependence of SI/ID2 on L [Supporting Information Discussion]

for different magnitudes of the noise and resistance sources and summarize the results in [Table

4-2] for both constant W/L and constant W devices. We compare the L dependence of SI/ID2 for

constant W/L TC and BC devices in Figure 4-2 (A). The result differentiates the dominant noise

sources in TC and BC devices, as TC devices follow an L-2 dependence, consistent with channel

noise and resistance dominating over the contributions from the contacts. Whereas for BC

devices, the L-1 relationship supports the dominance of the contact regions to the noise. The use

of the length dependence of the noise to distinguish the noise contributions from channel and

contact regions has been previously applied to studies of organic thin-film transistors.17,33

W/L = const. W = const.

Rchannel

> Rcontact

SRchannel

> SRcontact

Rchannel

> Rcontact

SRcontact

> SRchannel

Rcontact

> Rchannel

SRchannel

> SRcontact

const.

Rcontact

> Rchannel

SRcontact

> SRchannel

const.

2

contactchannel

RcontactRchannel

2

tot

totR

2

D

I

)R(R

SS

R

(f)S

I

(f)S

+

+

==

2L

1∝

L

1∝

L∝

L∝

L

1∝

2L

1∝

46

Figure 4-2. Normalized drain current spectral density (SI/ID2) as a function of channel length

varying from 30 µm to 200 µm, collected at a fixed frequency of 10 Hz, VDS = 50 V and VGS = 50 V. (A) Representative channel length dependence of SI/ID

2 for top-contact (red) and bottom-contact (green) devices with a constant W/L of 15. (B) Channel length dependence of SI/ID

2 for top-contact devices with constant W/L (blue) and fixed channel width of 1800 µm (cyan). Note: The device channel length of 90 µm and channel width of 1800 µm is common, representing the constant W/L ratio of 20 and the constant channel width of 1800 µm. Slopes of m = -1 and m = -2 lines are shown for reference.

However, in the literature constant W is commonly derived and used and not constant W/L. In

order to verify our derivation in Table 4-2, we prepare TC devices where constant W/L and

constant W are both included on the same sample. Indeed, in Figure 4-2 (B), TC devices show L-

1 for constant W and L-2 for constant W/L [statistics are shown in Supporting Information Figure 4-

S2] as the channel region is the major source of noise in this device configuration. As BC devices

suffer from additional 1/f noise originating from high-resistance metal-to-semiconductor contacts,

only TC devices are used as a platform to study the 1/f noise characteristics arising from the NC

thin-film channel.

4-3: Device Hysteresis and Bias-Stress Effects

The gate voltage dependence of the 1/f noise has been widely used to examine the origin

of the low-frequency noise and relate the noise to mechanisms of charge transport in materials

systems.14,32,34 To collect the gate voltage dependent 1/f noise characteristics, devices are under

(A) (B)

10 100 100010

-14

10-13

10-12

10-11

10-10

m = -2

SI/I

D

2

(1

/Hz)

Channel Length (µm)

m = -1

10 100 100010

-14

10-13

10-12

10-11

10-10

m = -2

SI/I

D

2

(1

/Hz)

Channel Length (µm)

m = -1

47

constant voltage stress for an accumulated time of ~25 min. Bias-stress in thin-film transistors

commonly leads to ID that varies over time.35–37 We observe bias-stress effects in our TC devices

when operated in both saturation [Supporting Information Figure 4-S3 (A)] and linear [Supporting

Information Figure 4-S3 (B)] regimes, leading to an abrupt current drop at the onset of stress that

gradually becomes more stable after a few seconds. For each stress bias, ID is therefore based

on averaging the current from 10 sec to the end of the voltage stress [Supporting Information

Figure 4-S4, blue stars]. The observed decay in ID arises from a shift of the device characteristics

toward increased threshold voltage (VT) [Supporting Information Figure 4-S4 (A)]. These stress

effects are more severe at lower VGS, making the determination of ID and device operation mode

more difficult. Note, the effects of bias stress are small in the noise measurements collected at a

single, high VGS as in Figure 4-1(C,D).

We find we can dramatically reduce bias-stress effects in TC devices by encapsulating

the devices with an atomic layer deposition (ALD) grown Al2O3 layer. ALD oxides have been

previously reported to reduce device hysteresis in NC-FETs.37,38 Supporting Information Figure 4-

S3 (A, B) shows the greater stability of encapsulated TC devices in the saturation and linear

regimes respectively. ID remains at 80% of the initial current in encapsulated devices, as opposed

to 40% or lower for devices without encapsulation after 25 min of accumulated stress. The time

dependence of ID fits well to a stretched exponential function, which is commonly used to

describe bias-stress effects in devices [Supporting Information Figure 4-S5 and Supporting

Information Discussion]. Upon encapsulation the device hysteresis is also smaller [Supporting

Information Figure 4-S4 (B)], with nearly no shift in device characteristics before and after noise

measurement. Notably, the average stress current matches the device characteristics in

saturation, linear and subthreshold regions. This additional Al2O3 encapsulation layer minimizes

device uncertainties and provides stable devices for gate voltage dependent 1/f noise

measurements.

48

Figure 4-3. Spectral current density (SI) of Al2O3-encapsulated, top-contact devices as a function of frequency measured at (A) VDS = 1 V and (B) VDS = 50 V under various VGS. (C) 1/f slope fit from SI vs frequency as a function of VGS at VDS = 1 V (blue) and VDS = 50 V (black). (D) SI vs ID at a frequency of 10 Hz for devices biased in saturation at VDS = 50 V (black) and linear and subthreshold regimes at VDS = 1 V (blue). Slopes (m) of 1, 1.5 and 2 are drawn for reference. Inset: Statistics from 4 devices of the slope of SI vs ID, measured in the saturation, linear and subthreshold regimes respectively.

4-4: Flicker Noise in Nanocrystal Field-Effect Transistors

Figure 4-3 (A,B) displays the drain current spectral density (SI) vs frequency for Al2O3-

encapsulated TC devices as a function of VGS, at VDS = 1 V, capturing device operation in the

linear and subthreshold regimes (VT is ~15V), and at VDS = 50 V, showing operation in the

saturation mode. Although 1/f behavior is observed, the frequency exponent (γ in fγ) is not a

constant value of -1. Figure 4-3 (C) depicts the frequency exponent for saturation (VDS = 50 V,

10 10010

-26

10-24

10-22

10-20

10-18

VDS

=1V

Frequency (Hz)

SI (

A2

/Hz)

VGS

50

40

30

20

10

10 10010

-22

10-20

10-18

10-16

Frequency (Hz)

SI (

A2

/Hz)

VGS

50

45

40

35

30

VDS

=50V

(A) (B)

(C) (D)

10 20 30 40 50-0.5

-1.0

-1.5

-2.0

VGS

(V)

1/f

slo

pe

10-7

10-6

10-5

10-4

10-3

10-2

10-24

10-22

10-20

10-18

m = 2

m = 1.5

m = 1

ID(A)

SI(A

2

/Hz)

SAT LIN SUB0.5

1.0

1.5

2.0

2.5

Slope

49

black) and linear to subthreshold (VDS = 1 V, blue) regimes as a function of VGS. For VDS = 50 V, γ

changes from -1 to more negative values with decreasing VGS, whereas for VDS = 1 V, γ is nearly

constant at -1 for a wide range of VGS and then abruptly changes to more negative values as the

device transitions from the linear to subthreshold regimes. Our observations for the noise

behavior in NC-FETs is consistent with the deviation of γ from -1 reported for semiconductors

with a density of trap states in the band gap and is related to the position of the Fermi energy (EF)

as it is shifted through the density of states in different bias regimes.12,39

Another way to view this data is by plotting SI vs ID at a fixed frequency. Figure 4-3 (D) is

a representative plot of SI vs ID at 10 Hz collected at VDS = 1 V with VGS ranging from 50 to 7.5 V

(blue points) and at VDS = 50 V with VGS spanning from 50 to 30 V (black points). The double

logarithm plot shows three distinct slopes. Figure 4-3 (D) inset shows the statistics of the slopes

measured from four devices at frequencies of 5 to 10 Hz (in steps of 1 Hz), where slopes of 1.6 ±

0.04 in the saturation regime, 1.2 ± 0.07 in the linear regime, and 2.0 ± 0.01 in the subthreshold

regime are found. These experimental results closely match the Hooge model for operation in

both saturation [Equation 4-2] and linear [Equation 4-1] regimes, suggesting mobility fluctuations

are responsible for the 1/f noise behavior under strong accumulation of charge. For the

subthreshold regime [Equation 4-3], 1/f noise is consistent with carrier number fluctuation based

on the McWhorter theory. Alternatively, SI/ID2 or SI vs (VGS-VT) relationship can be used to

distinguish between Hooge and McWhorter models.40 In Supporting Information Figure 4-S6, both

linear and saturation regimes are again shown to follow the Hooge model instead of the

McWhorter model, consistent with the results from SI vs ID. Based on the McWhorter model in

[Equation 4-3], the calculated NT is ~ 8.17x1018 (ev-1 cm-3), which is one order of magnitude lower

than that found for a-Si10 and similar to that for a-InGaZnO transistors.34 For unencapsulated

devices, the SI vs ID does not show these trends in all three operation modes, which we believe is

due to bias-stress effects on the measurement of ID.

50

The Hooge parameter (αH) is commonly used as a figure of merit to compare the 1/f

noise level in different systems. The Hooge parameter calculated from the normalized current

spectral density is

=

=

, where A the noise amplitude (described above) is equal to the

Hooge parameter divided by the carrier number =

( − ).

6,40 Figure 4-4 (A,B) and

Supporting Information Figure 4-S7 (A,B) compare the field-effect carrier mobility and Hooge

parameter as a function of VGS in the saturation and linear regimes, respectively, for

unencapsulated and encapsulated devices. For unencapsulated TC devices [Figure 4-4 (A) and

Supporting Information Figure 4-S7 (A)], a strong gate-dependent carrier mobility and Hooge

parameter are observed, with the mobility and Hooge parameter inversely related. Encapsulated

devices retain a consistently small Hooge parameter of around 3 x 10-2, as well as a significantly

weaker gate-dependent carrier mobility of around 10 cm2/Vs. This result highlights the influences

of NC surface states on device carrier mobility and noise magnitude.

4-5: Nanocrystal Charge Transport and Flicker Noise Mechanism

Based on our experimental observations in Figure 4-3 and Figure 4-4 (A,B), we describe

the 1/f noise mechanism by a schematic of the carrier concentration [Figure 4-4 (C)] and

therefore Fermi energy (EF) across the NC-FET channel, accounting for the NC thin-film density

of states [Figure 4-4 (D)]. The density of states for strongly-coupled, NC thin films is consistent

with the formation of extended states above the mobility edge and tail and mid-gap states that

extend into the gap.30,41–43 Site-to-site variation even in highly monodisperse NC samples

introduces dispersion in the energy of NC states that tail below the mobility edge. NCs possess a

large surface-to-volume ratio and therefore the surface is known to play a dominant role on their

physical properties, as dangling bonds, some ligand chemistries, and exposure to oxygen and

water introduce electronic trap states within the band gap.42,44,45 In the transistor geometry, we

showed previously that the semiconductor NC/gate dielectric interface also contributes to the

density of tail states.30 These tail and mid-gap states, either from NC energy dispersion or surface

51

Figure 4-4. Mobility and Hooge parameter (αH) as a function of VGS when VDS = 50 V for (A) unencapsulated, top-contact and (B) Al2O3-encapsulated, top-contact devices. Insets in (A) and (B) are NC-FET schematics. (C) Schematic of the carrier concentration in the NC-FET channel, and (D) the density of states for NC thin films and the energy of the Fermi level in the linear (red), saturation (green), and subthreshold (orange) regimes. E0 denotes the mobility edge. Note, in the saturation region pinch off within ∆L of the drain electrode causes the Fermi energy to move further away from the band edge. The density of tail states (blue dashed) is reduced after Al2O3 encapsulation (blue solid).

states or the NC/gate dielectric interface, when not filled, have a significant influence on NC thin-

film device performance, limiting carrier lifetime46 and mobility and introducing device hysteresis

and instability under bias-stress.37 For CdSe NC-FETs without Al2O3 encapsulation, we assume a

greater density of tail and mid-gap states from incomplete passviation and/or surface

oxygen/water adsorption over time even in nitrogen-filled glovebox [Figure 4-4(D), blue dashed

line], as previously reported for lead chalcogenide NC-FETs.47–49 During ALD Al2O3 growth,

additional indium diffuses from the source and drain electrodes into the NC channel to better

30 35 40 45 50

3

6

9

12

15

V

GS(V)

3

6

9

12

15

Mo

bilit

y (

cm

2

/VS

)

αH (1

x10-2)

30 35 40 45 50

3

6

9

12

15

VGS(V)

Mo

bil

ity (

cm

2

/VS

)

3

6

9

12

15

αH (1

x10-2)

Gate

CdSeS D

Dielectric

Dielectric

Gate

CdSeS D

Dielectric

(A) (B)

(C)

e-e-e-e-e-S D

Linear VGS

-VT

> VDS

> 0

S D

Saturation VDS

> VGS

-VT

> 0

S D

Subthreshold VGS

-VT

< 0

e-

e-

e-

e-

e-

∆L< L

X

e- e-e-

(D)

Energy

Density of states

EFlinear

EFsaturation@source

EFsaturation@drain

EFsubthreshold

E0

E0

∆L

52

passivate the NC surfaces.38 The deposited Al2O3 also encapsulates the NCs and the device

interfaces, preventing oxygen and water from introducing trap states [Figure 4-4(D), blue solid

line].37,38 The calculated CdSe NCs/Al2O3 interface trap density is similar for devices with and

without Al2O3 encapsulation [Supporting Information Figure 4-S4], consistent with the change in

trap density mainly resulting from passivation of NC surface states.

In the transistor geometry, the applied VGS tunes the Fermi energy (EF) in the

semiconductor channel, modulating the free carrier concentration and the occupancy of sub-band

gap states. In encapsulated devices, when VGS > VT, EF lies close to the mobility edge (E0) and a

large concentration of free carriers are accumulated in extended states. Here the current

fluctuations that give rise to 1/f noise are consistent with mobility fluctuations described by the

Hooge model as seen in the linear and saturation regimes in Figure 4-3 (D). The carrier mobility

and Hooge parameter are stable over a range of VGS from 50 to 30 V in the saturation [Figure 4-4

(B)] and linear [Supporting Information Figure 4-S7 (B)] regimes, in agreement with the low

density of unoccupied sub-band gap states. In the linear regime (VDS < VGS - VT), a nearly

constant γ= -1 is observed as a uniform charge accumulation layer exists. Unlike the uniform EF

and carrier concentration in the linear regime, EF in the saturation regime will gradually move

away from the mobility edge as the channel is pinched off due to the reverse bias near the drain

electrode [Figure 4-4 (C)], leaving behind empty, deeper trap states for carriers to communicate

with by trapping-detrapping. Compared to shallow traps, these unoccupied deep trap states give

rise to slow carrier trapping-detrapping and therefore appear as low-frequency 1/f noise,

consistent with the deviation from γ= -1 in the saturation regime (as smaller VGS increases the

width of the pinch-off region as VDS > VGS - VT increases).12 When VGS < VT in the subthreshold

regime, EF is away from the mobility edge and gives rise to an abrupt change in γ [Figure 4-3(C)]

and a transition in the 1/f noise from carrier mobility to number fluctuations in accordance with the

McWhorter model. In contrast, in unencapsulated devices, the high density of tail states results in

appreciable carrier trapping-detrapping. As seen in [Figure 4-4 (A) and Supporting Information

Figure 4-S7 (A)], the mobility and Hooge parameter have a strong VGS dependence in both the

53

linear and saturation regimes, leading in saturation to a factor of four increase in the Hooge

parameter. The relationship between increased density of sub-band gap states and increased low

frequency noise has similarly been reported in a-InGaZnO transistors.28,50 These sub-band gap

states have also been correlated with an increased Hooge parameter and bias instability.

Similarly, our results suggest that unfilled sub-band gap states, contribute to increased 1/f noise,

increased bias-stress effects and lower carrier mobilities.

4-6: Conclusion

In summary, we report 1/f noise behavior at low frequencies in CdSe NC-FETs and

correlate the noise behavior with the nature of charge transport in CdSe NC thin films. The 1/f

noise behavior in the saturation and linear regimes is consistent with charge transport of

accumulated carriers in extended states where mobility fluctuations are caused by scattering.

However in the subthreshold regime, the 1/f noise behavior results from carrier number

fluctuations arising from carrier trapping-detrapping from sub-band gap states introduced by NC

dispersion, the NC surface and/or the semiconductor NC/gate dielectric interface. We find that

passivation of NC surface states give rise to a consistent carrier mobility and Hooge parameter

over a wide range of applied voltages. This is very important for high density integrated circuits

where inconsistent device characteristics and large noise limit their functionality.

4-7: Methods

Device Fabrication: NC-FETs are fabricated in bottom-gate configuration on N+ doped silicon

substrates with 250 nm of thermally grown SiO2 that serve as the back gate and part of the gate

dielectric stack, respectively. An additional 20 nm gate dielectric layer of Al2O3 was grown via

atomic layer deposition (ALD), as the Al2O3 surface reduces the device interface trap density.9,67

40 nm indium followed by 40 nm gold was thermally evaporated through shadow masks to define

source and drain electrodes on top of the CdSe NC layer and complete top contact (TC) devices.

The CdSe NC preparation follows Chapter 3 Methods section. The CdSe NC layer is deposited

54

by spin coating (500 rpm for 30 sec, then 800 rpm for 30 sec) to form uniform, randomly close-

packed NC thin films. The order of metal evaporation is reversed (10 nm gold and 20 nm of

indium) and deposited prior to spin-coating the CdSe NC layer to form bottom contact (BC)

devices. Two source drain electrodes designs are used. For constant W/L = 15, the channel

length varied from 30 to 200 µm. Another design is used for devices with constant W = 2400,

1800, 1200, and 600 µm along with lengths varying to from W/L= 10, 15, 20 and 25. The devices

are annealed at 250 oC for 10 min to allow for the indium, introduced in the contacts, to diffuse

across and dope the NC channel. For device encapsulation, a 50 nm layer of Al2O3 is deposited

by ALD at a temperature of 150 oC. NCFET fabrication steps are carried out in nitrogen-filled

gloveboxes, with the exception of ALD growth of the Al2O3 in dielectric stack and forming the

device encapsulation layer.

Device Characterization and Flicker Noise Collection: FET device characteristics are

collected on 4156C (Agilent) semiconductor parameter analyzer. To collect low frequency noise

in NCFETs, two Keithley 2400 source meters, a SR570 (Stanford Research System) low noise

current preamplifier, and an HP 3582A spectrum analyzer are used, and connected with

appropriate shared grounding and shielding to minimize external electrical interference. The

Keithley 2400 is used to provide a constant voltage source while recording device current over

time (in steps of 30 msec). The SR570 amplified the input device current as output voltage, which

is then connected to the HP 3582 A spectrum analyzer. The amplification is selected based on

the input device current. Through all measurements, 200 µA/V is applied for VDS = 50 V and 2

µA/V was for VDS = 1 V, where the bandwidth for both amplifications is above 104 Hz, far beyond

the frequency range of interest in this 1/f noise study. A 0.03 to 3 kHz band pass filter is selected

on the SR570 amplifier. The spectrum analyzer measured frequencies from 5 to 260 Hz in steps

of 1 Hz, and took 16 times averaging for stable output reading. All measurement are performed

while devices remained in dry nitrogen-filled gloveboxes.

55

4-8: Supplementary Information

Length Dependence of SI/ID2

For a homogenous semiconductor, the noise expression14,32 can be presented as

=

=

( )=

(4-6)

where SRchannel and SRcontact represent two uncorrelated noise sources and Rchannel and Rcontact are

the channel and contact resistances. Using

=

relationship, =

and

=

can be derived, where N is defined as free carriers in the channel or

contact region. The carrier concentrations and resistances in the channel or contact regions are

related to the transistor channel length (L) and width (W), and can be simplified as ∝ ×,

∝

, ∝

and ∝

.14,32 Depending on the magnitude of each term, Equation

4-6 can be simplified into four possible expressions.

> , > =

= ∝

1

×

> , > =

= ∝

> , > =

= ∝

> , > =

= ∝

With the assumption of a constant value of W or W/L, Table 4-2 in the main text is derived.

Stretched Exponential Function

Bias-stress effects are typically described by a stretched exponential function54,55 as

∆! = (" − !#)1 − −( )$ (4-7)

56

where ∆VT is threshold voltage (VT) shift under constant gate-source (VGS) and drain-source bias

(VDS) for an extended period of time. VT0 is the initial value of VT, t is the time the stress is applied,

and τ and β are fitting parameters. This equation can be converted to express bias-stress induced

current degradation via current expressions for ideal thin-film transistors29. For example, the initial

saturation current is

=

%

(" − !#) = (" − !#) (4-8)

and changes to

′ =

%

[" − (!# + ∆!)] = [" − (!# + ∆!)] (4-9).

Expanding Equation (4-9) and using Equation (4-7) and (4-8), the saturation current degradation

as a function of time is ′

= exp[−2

$]. Using the initial linear current

=

%

[2" − !# − ] (4-10)

a similar function for linear current degradation can be derived as ′

= exp[−

$], assuming

(VDS)2 is negligible. These two equations are applied to fit the time dependence of the drain-

source current (ID) in Figure 4-S5. It is obvious that encapsulated devices have orders of

magnitude higher value of τ than unencapsulated devices, suggesting encapsulated devices are

more stable under bias-stress.

57

Figure 4-S1. (A) Representative transfer characteristics (ID-VGS) for top-contact (red) and bottom-contact (black) devices, with L = 50 µm and measured at VDS = 50 V. The contact (Rcontact) and channel (Rchannel) resistances are extracted from the total resistance (Rtotal) as a function of channel length using the transmission line method for (B) top-contact and (C) bottom-contact devices respectively, collected at VGS = 30 V (black), VGS = 40 V (red), and VGS = 50 V (blue). (D) A representative SI/ID

2 vs frequency of a top-contact, L = 40 µm device measured in the saturation and linear regimes, showing that noise is weakly dependent on VDS.

-20-10 0 10 20 30 40 5010

-9

10-8

10-7

10-6

10-5

10-4

10-3

I D (

A)

VGS

(V)

(A) (B)

(C)

10 10010

-15

10-14

10-13

10-12

10-11

10-10

10-9

VDS

=50, VGS

=50

VDS

=5, VGS

=50S

I/ID

2

(1

/Hz)

Frequency (Hz)

(D)

0 50 100 150 2000

50

100

150

200

Channel Length (µm)

Rtotal x

W (

106 o

hm

*µm

)

0 50 100 1500

10

20

30

40

50

60

Rtotal x

W (

106 o

hm

*µm

)

Channel Length (µm)

58

Table 4-S1. Device resistances extracted by the transmission line method and carrier mobilities for top-contact devices at VGS = 40 V and VGS = 30 V.

Figure 4-S2. Statistics of the length dependence of SI/ID2 for different scaling of the device

geometry.

Channel

Length

(µm)

VGS

= 40 V VGS

= 30 V

Rtotal

(Ω)Mobility

(cm2/Vs)R

total(Ω)

Mobility

(cm2/Vs)

30 1.2x104 -2.2x103 19.73 2.1x104 -3.9x102 11.57

40 1.2x104 -1.6x103 19.45 2.1x104 -2.9x102 12.01

50 1.3x104 -1.3x103 17.29 2.1x104 -2.3x102 12.67

100 1.3x104 -6.6x102 15.75 2.2x104 -1.1x102 15.01

150 1.4x104 -4.4x102 15.01 2.2x104 -78.2 14.77

)(ΩW

Rcontact

)(ΩW

Rcontact

TC

W/L=15

BC

W/L=15

TC

W/L=20

TC

W=1800

0

-1

-2

-3

Le

ng

th D

ep

en

de

nc

e

µm

59

Figure 4-S3. Time dependence of the normalized drain-source current (ID) measured under a voltage stress of (A) VDS = 50 V and (B) VDS = 1 V for an unencapsulated, top-contact device (dashed lines) and an Al2O3-encapsulated, top-contact device (solid lines), where VGS = 50 V (black), VGS = 40 V (red), VGS = 30 V (blue) and VGS = 20 V (green).

Figure 4-S4. Device transfer characteristics ID-VGS for (A) an unencapsulated, top-contact and (B) an Al2O3-encapsulated, top-contact device at VDS = 50 V and VDS = 1 V (inset), where ID-VGS before (black) and after (red) noise collection are presented. The average stress current during noise collection is shown as blue stars at each applied bias and is the average of the current collected in Fig. 4-S3 from 10 sec to the end of applied bias at 70 sec. Note: the calculated interface trap density from the subthreshold swing is 9.67 x 1012 cm-2 for (A) and 9.14 x 1012 cm-2 for (B).

0 20 40 60 80

0.2

0.4

0.6

0.8

1.0

Time (sec)

No

rm

alized

ID

VDS

=50

0 20 40 60 80

0.2

0.4

0.6

0.8

1.0

Time (sec)

No

rm

alize

d ID

VDS

=1(A) (B)

-20-10 0 10 20 30 40 5010

-9

10-7

10-5

10-3

I D

(A

)

VGS

(V)

-20-10 0 10 20 30 40 5010

-9

10-7

10-5

10-3

VGS

(V)

I D (

A)

10-8

10-6

10-4

-20 0 20 40

VGS

(V)

I D (

A)

Gate

CdSeS D

Dielectric

10-8

10-6

10-4

-20 0 20 40

I D (

A)

VGS

(V)

(A) (B)

Gate

CdSeS D

Dielectric

Dielectric

60

Figure 4-S5. Traces of ID as a function of time under voltage stress (black) and fits to a stretched exponential function (red) for (A) an unencapsulated, top-contact and (B) an Al2O3-encapsulated, top-contact device under VDS = 1 V, VGS = 50 V and for (C) an unencapsulated, top-contact device and (D) an Al2O3-encapsulated, top-contact device under VDS = 50 V, VGS = 50 V. Insets in (A-D) show fitting parameters (τ and β) as a function of VGS.

0 20 40 60 80

0.5

1.0

1.5

2.0

Time (sec)

Cu

rre

nt

(mA

)

20 30 40 5010

0

101

102

VGS

(V)

τ (

se

c)

0.1

0.2

0.3

0.4

β

30 40 50

200

400

600

800

VGS

(V)

τ (

sec

)

0.1

0.2

0.3

0.4

β

0 20 40 60 80

20

40

60

80

Time (sec)

Cu

rren

t (µ

A)

20 30 40 50

104

105

106

VGS

(V)

τ (

se

c)

0.1

0.2

0.3

0.4

β

0 20 40 60 80

0.5

1.0

1.5

2.0

Cu

rren

t (m

A)

Time (sec)

30 40 50

105

106

107

108

VGS(V)

τ (

se

c)

0.1

0.2

0.3

0.4

β

(C) (D)

(B)(A)

0 20 40 60 80

20

40

60

80

Cu

rre

nt

(µA

)

Time (sec)

61

Figure 4-S6. (A) Representative SI/ID2 vs (VGS-VT) characteristics at a frequency of 10 Hz for an

Al2O3-encapsulated device operated in the linear regime (VDS = 1 V). The slope fit for frequencies between 5 to 10 Hz in a step of 1 Hz is -0.9 ± 0.15. Slopes of -1 and -2 are drawn for reference. (B) Representative SI vs (VGS-VT) at a frequency of 10 Hz for an Al2O3-encapsulated device operated in the saturation regime (VDS = 50 V). The slope fit for frequencies between 5 to 10 Hz in a step of 1 Hz is 3.1 ± 0.27. Slopes of 2 and 3 are drawn for reference. (C) Comparison of the SI/ID

2 and SI dependence on (VGS -VT) for the Hooge (∆µ) and McWhorter (∆N) models for devices operated in linear and saturation modes.

10 20 30 40 50

10-19

10-18

10-17

VGS-V

T (V)

m = 3

SI (

A2

/Hz)

m = 2

(B)

Linear Regime Saturation Regime

∆µ

∆N

)VWL(V

t

I

S

TGS

i

2

D

I

−

∝33

i

3

TGS

L

W

t

)V-(V

IS ∝

2

TGS

2

i

2

D

I

)VWL(V

t

I

S

−

∝3

2

TGS

L

W)V-(V

IS ∝

(C)

10 20 30 40 5010

-12

10-11

10-10

m = -2

SI/I

D

2

(1/H

z)

VGS-V

T (V)

m = -1

(A)

62

Figure 4-S7. Mobility and Hooge parameter (αH) as a function of VGS when VDS = 1 V for (A) unencapsulated, top-contact and (B) Al2O3-encapsulated, top-contact devices.

4-9: References

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30 35 40 45 50

3

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Mo

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Much of this work appears in print: Adapted with permission from J.H. Choi, S.J. Oh, Y. Lai, D.K. Kim, T. Zhao, A.T. Fafarman, B.T. Diroll, C.B. Murray, C.R. Kagan, ACS Nano, 7, 8275-8283 (2013) Copyright 2013 American Chemical Society

66

CHAPTER 5 Recoverable Nanocrystal Field-Effect Transistors for

Fabrication and Operation in Air

In Chapter 3, we demonstrate flexible nanocrystals integrated circuits (NCICs). It is well-

known that when semiconductor devices are exposed to air, their characteristics may be

modified. Oxygen adsorbs to the surface of nanocrystalline (NCs and nanowires) and

polycrystalline thin-film semiconductors, introducing new electronic states. In cadmium

chalcogenides deep-level acceptors are created, acting as electron traps that decrease the

materials conductivity by 2-5 orders of magnitude.1,2 Water adsorption on CdSe NCs has been

reported to initially passivate and then oxidize the surface.3,4

In order to take the full advantages of colloidal nanocrystal as "inks" for large area, low-

cost fabrication, it is necessary to develop processes that allow nanocrystals compatible to use in

ambient atmosphere. In this chapter, in collaboration with Dr. Ji-hyuk Choi et al., we introduce the

concept of using thermally activated indium diffusion to reverse air- and solvent-induced

deterioration of CdSe nanocrystal field-effect transistor (NC-FET) performance.

5-1: Recovery of Degraded Nanocrystal Field-Effect Transistors

In the field-effect transistor (FET) geometry, electrical measurements probe both electron

trapping at the semiconductor NC surface and at the semiconductor-gate oxide interface due to

oxygen and water adsorption. We investigated FETs with a commonly employed SiO2 gate

dielectric layer and an Al2O3/SiO2 gate dielectric stack, which we previously showed reduced the

interface trap density, improving CdSe NC-FET performance.5 We monitored the degradation in

the drain current as a function of air-exposure time before and after repeated recovery by

Figure 5-1. CdSe NC-FET oncyclic degradation as a function of air exposure time and recovery upon refor 5 min, (B) degradation in air exposure), and (C) the evolution in asexposure for 30 min (red) and recovery by annealing at 200 on-current recovery after 5 min of annealing at different temperatures. Note: Since all devices recover at an annealing temperature of 200 characterized by the decreasein acetone, chloroform, isopropanolSamples were dried using a nitrogen stream before electrical measurement. (Top) Onrecovery upon re-annealing at 200

annealing. Representative of transfer c

shown in Figure 5-1 (A). Upon air exposure, CdSe NC

rapidly degraded, whereas those fabricated with an Al

more slowly, indicating the dominant role of semiconductor

confirm the importance of both oxygen and water adsorption on the degrada

compared NC-FETs exposed side

67

FET on-current (VG=50 V) in the linear regime (VDS=5cyclic degradation as a function of air exposure time and recovery upon re-annealing at 200 for 5 min, (B) degradation in air versus in pure oxygen environments (open bar : initial, filled bar : exposure), and (C) the evolution in as-prepared FETs (black) upon successive cycles of air exposure for 30 min (red) and recovery by annealing at 200

oC for 5 min (blue). (D) Statistics in

current recovery after 5 min of annealing at different temperatures. Note: Since all devices recover at an annealing temperature of 200

oC, the scale is narrowed. (E) NC

characterized by the decrease in drain current IDS (after exposure) to IDSO (initial), upon immersion in acetone, chloroform, isopropanol, methanol and water for 10 min at room temperature. Samples were dried using a nitrogen stream before electrical measurement. (Top) On

annealing at 200 oC for 5 min after solvent immersion.

annealing. Representative of transfer characteristics degradation in the linear regime (

Upon air exposure, CdSe NC-FETs with a SiO2 gate dielectric layer

rapidly degraded, whereas those fabricated with an Al2O3/SiO2 gate dielectric stack degraded

indicating the dominant role of semiconductor-dielectric interface trapping

confirm the importance of both oxygen and water adsorption on the degradation of NC

FETs exposed side-by-side to air and to pure oxygen [Figure 5

=5 V) monitoring (A) annealing at 200

oC

in pure oxygen environments (open bar : initial, filled bar : prepared FETs (black) upon successive cycles of air

for 5 min (blue). (D) Statistics in current recovery after 5 min of annealing at different temperatures. Note: Since all devices

C, the scale is narrowed. (E) NC-FET degradation, (initial), upon immersion

, methanol and water for 10 min at room temperature. Samples were dried using a nitrogen stream before electrical measurement. (Top) On-current

haracteristics degradation in the linear regime (VDS=5 V) is

gate dielectric layer

gate dielectric stack degraded

dielectric interface trapping. To

tion of NC-FETs, we

[Figure 5-1 (B)]. While the

68

NC-FET drain current is seen to degrade in pure oxygen, the drain current of NC-FETs exposed

to air degraded more and particularly dramatically for SiO2 gate dielectric layers. Water is known

to adsorb to surface hydroxyl groups on both SiO2 and Al2O3 surfaces, but the larger

concentration of surface hydroxyl versus bridged oxygen groups, gives rise to the more acidic

nature and greater water adsorption on SiO2 in contrast to on more basic Al2O3.6,7

Annealing air-exposed CdSe NC devices, having both SiO2 and Al2O3/SiO2 gate dielectric

layers, at 200 oC for 5 min under nitrogen restored the initial device characteristics, as shown in

Figure 5-1 (A) highlighted as red. The device degradation and recovery can be repeatedly cycled

many times upon air exposure and annealing. We hypothesize that annealing desorbs any

oxygen and water bound to the NC surface, expels water residing at the gate oxide surface and

leads to additional diffusion of indium from the source and drain electrodes to recover the high-

performance device characteristics. Increasing the number of cycles of air exposure (for 30 min)

and re-annealing improves the air-stability of the CdSe NC-FETs, as measured in Figure 5-1 (C)

by the smaller drop in drain current in the linear regime (VDS=5 V) using both Al2O3/SiO2 and

(inset) SiO2 gate dielectric layers. In Figure 5-2, after repeated cycling through 13 times of air

exposure and annealing, the device transfer characteristics did not show significant changes from

the as-prepared, unexposed device behavior. We also note that additional indium diffusion at 200

oC does not significantly dope CdSe NC thin films, maintaining the low device off-currents. The

devices with repeated cycling times of air exposure and annealing exhibit improved air-stability

consistent with greater indium-passivation. Using indium as a recovery agent, integrated into the

electrode architecture of the device provides a powerful route to allow NC device fabrication in

ambient air.

69

Figure 5-2. ID-VG characteristics of CdSe NC-FETs before and after repeated cycling through 13 times of air exposure and annealing.

There is a critical range of annealing temperatures and times to recover the device

characteristics that depends on the semiconductor-gate dielectric interface [Figure 5-1 (D)]. All

devices showed recovered, high-performance behavior upon annealing at 200 oC for 5 min. For

the devices with an Al2O3/SiO2 gate dielectric stack, the recovery temperature can be lowered to

175 oC and 5 min. However, devices with a SiO2 gate dielectric layer did not show as significant a

recovery effect at temperatures < 200 oC.

We tested the electrical stability and recovery of indium-doped CdSe NC films after

exposure to the solvents commonly used in standard photolithographic processing. Devices were

dipped into each of the solvents; acetone, chloroform, isopropanol, methanol, and water; for 10

min at room temperature and then dried under a nitrogen flow before re-probing their FET

characteristics. Figure 5-1 (E) shows the percent degradation in drain current when the NC-FETs,

fabricated using both SiO2 and Al2O3/SiO2 gate dielectric layers, were exposed to various

solvents. Exposure to acetone, chloroform, isopropanol, and methanol results in small reductions

70

in the drain current, while substantial degradation in device performance is seen upon immersion

in water, akin to the adverse effects of air-exposure on device performance. All of the devices,

even devices that had dramatically deteriorated by water exposure, could be recovered upon re-

annealing.

5-2: Air-Stable High Performance Devices on Wafer Scale Substrates

We exploited the ability to recover the device performance after chemical and

environmental exposure to fabricate wafer-scale integrated devices using photolithography and

ALD encapsulation. Uniform CdSe NC thin films were deposited by spin-casting on 4 inch

diameter Al2O3 (20 nm)/SiO2(250 nm)/highly-doped Si substrates as shown inset in Figure 5-3 (A).

Subsequently, sample is briefly annealed at 200 oC for 5 min in nitrogen filled box, followed by an

ultrathin (~1 nm), conformal, sub-monolayer of ALD grown Al2O3. These steps are required to

prevent delamination of the NC thin film that was frequently observed without the ultrathin ALD

oxide layer during subsequent photolithographic patterning. While detailed studies of charge-

transport through NCs embedded in inorganic matrices remains to be explored, ALD oxides have

been reported to offer significant potential in NC surface passivation.8,9 144 sets of source and

drain electrodes were defined using conventional photolithographic techniques to fabricate back-

gate/top-contact FET arrays across the wafer [Figure 5-3 (A)]. The back-gate/top-contact

configuration is desirable for high-performance devices, as we have previously reported that

back-gate/bottom-contact geometry NC transistors display large contact resistance and therefore

poor performance.10 All 144 NC devices could be successfully recovered by re-annealing. The

recovered NC devices showed well-behaved, high-performance FET characteristics when

operated in the nitrogen. Further, by recognizing the recent progress using ALD oxide deposition

on NC devices,8,11 we employed a conventional ALD cleanroom tool to deposit a 50 nm Al2O3

encapsulation layer on NC devices. The temperatures (150 oC) commonly used in the ALD

process make it possible to achieve in-situ indium-diffusion during the Al2O3 deposition, leading to

fully passivated devices integrated in a single step.

Figure 5-3. (A) A photograph of an array of 144 transistors fabricated by photolithographically patterning source and drain electrodes on [inset] a uniformly spin4 inch Al2O3(20 nm)/SiOcharacteristics (VDS=5 V) of NCSchematic of the device structure. (d) Electron mobility of integrated CdSe NC devices over the large-area 4 inch substrate. (e) NCa function of time stored and operated in air.

Figure 5-3 (B), inset shows a schematic of the photolithographically defined and ALD

encapsulated NC device configuration. Figure 5

characteristics of these CdSe NC

characteristics. We compared the characteristics of devices with ALD passivation operating in

ambient air to unencapsulated devices operating in ambient nitrogen. T

with an Al2O3 layer exhibited lower off

encapsulation (∆VT =8.8 V), indicating the encapsulation effectively prevented oxygen adsorption

and repelled surface water.

71

(A) A photograph of an array of 144 transistors fabricated by photolithographically patterning source and drain electrodes on [inset] a uniformly spin-cast CdSe NC thin film across a

(20 nm)/SiO2(250 nm)/highly-doped Si wafer. (b) Output and (c=5 V) of NC-FETs (channel length L=30 µm, width W=450 µm). [inset (b)]

Schematic of the device structure. (d) Electron mobility of integrated CdSe NC devices over the area 4 inch substrate. (e) NC-FET electron mobility (black) and threshold voltage (blue) as

a function of time stored and operated in air.

B), inset shows a schematic of the photolithographically defined and ALD

encapsulated NC device configuration. Figure 5-3 (B,C) present typical output and

characteristics of these CdSe NC-FETs. The devices show good linear and saturation

characteristics. We compared the characteristics of devices with ALD passivation operating in

ambient air to unencapsulated devices operating in ambient nitrogen. The devices passivated

layer exhibited lower off-current and hysteresis (∆VT =2.8 V) than without the Al

V), indicating the encapsulation effectively prevented oxygen adsorption

We characterized the statistics of device performance for FET arrays

(A) A photograph of an array of 144 transistors fabricated by photolithographically cast CdSe NC thin film across a

doped Si wafer. (b) Output and (c) transfer =450 µm). [inset (b)]

Schematic of the device structure. (d) Electron mobility of integrated CdSe NC devices over the (black) and threshold voltage (blue) as

B), inset shows a schematic of the photolithographically defined and ALD

B,C) present typical output and transfer

FETs. The devices show good linear and saturation

characteristics. We compared the characteristics of devices with ALD passivation operating in

he devices passivated

=2.8 V) than without the Al2O3

V), indicating the encapsulation effectively prevented oxygen adsorption

erized the statistics of device performance for FET arrays

Figure 5-4. (A) A photograph of an array of photolithographically patterned NCsquare Kapton® substrate. (b) Output and (c) transfer characteristics (FETs (channel length L=30 µm, width

across large area wafers, such as the example wafer shown in Figure 5

across the 4 inch wafer operated with a linear

ION/IOFF>106 and a low subthreshold swing

work, photolithography enabled the patterning of smaller channel lengths, readily to 2 µm,

providing a route to study scaling in NC devices.

devices were stored and operated in air. Figure 5

threshold voltage of NC-FETs that were characterized over time. The NC device w

encapsulation layer showed excellent operational stability with no decrease in performance over

70 days of measurement.

We further fabricated NC

fabrication steps are described in Ch

recovery processes described above. Figure

characteristics of photolithographically defined

operate stably in ambient air at low

cm2/Vs and a saturation regime (

72

(A) A photograph of an array of photolithographically patterned NCsquare Kapton® substrate. (b) Output and (c) transfer characteristics (VDS =0.1 and 2 V) of NC

=30 µm, width W=450 µm). [inset] Schematic of the NC-

across large area wafers, such as the example wafer shown in Figure 5-3 (D). All of the devices

across the 4 inch wafer operated with a linear regime (VDS=5 V) mobility is 26.9±1.3

and a low subthreshold swing S=2.9±0.5 V/dec. In addition, in contrast to previous

work, photolithography enabled the patterning of smaller channel lengths, readily to 2 µm,

to study scaling in NC devices. To test the air stability of devices, arrays of NC

devices were stored and operated in air. Figure 5-3 (E) demonstrates the carrier mobility and

FETs that were characterized over time. The NC device w

encapsulation layer showed excellent operational stability with no decrease in performance over

We further fabricated NC-FETs on 4 inch flexible, Kapton substrates [Figure 5

fabrication steps are described in Chapter 3, but here using the photolithography, ALD, and

recovery processes described above. Figure 5-4 (B,C) show representative output and transfer

characteristics of photolithographically defined, ALD encapsulated, flexible NC-

ably in ambient air at low-voltages with a linear regime (VDS=0.1 V)

/Vs and a saturation regime (VDS=2 V) mobility is 20.8 cm2/Vs. These NC

(A) A photograph of an array of photolithographically patterned NC-FETs on a 4 inch =0.1 and 2 V) of NC-

-FET structure.

3 (D). All of the devices

9±1.3 cm2/Vs, high

V/dec. In addition, in contrast to previous

work, photolithography enabled the patterning of smaller channel lengths, readily to 2 µm,

To test the air stability of devices, arrays of NC

3 (E) demonstrates the carrier mobility and

FETs that were characterized over time. The NC device with ALD

encapsulation layer showed excellent operational stability with no decrease in performance over

FETs on 4 inch flexible, Kapton substrates [Figure 5-4 (A)]. The

apter 3, but here using the photolithography, ALD, and

,C) show representative output and transfer

-FETs. The devices

=0.1 V) mobility is 21.4

/Vs. These NC-FETs show high

73

ION/IOFF >105, low subthreshold swing (S=0.25 V/dec), low threshold voltage (VT=0.71 V) and low

hysteresis (∆Vth=0.13 V) at VDS=0.1 V.

5-3: Conclusions

In summary, we introduced an in-situ recovery agent, indium metal, that, upon thermal

activation, reverses the detrimental effects of air and solvent exposure that degrade the electronic

properties of high-surface area semiconductor NC thin films and their devices. Employing a

reservoir of indium metal in the electrodes of NC FETs, we exploited the recovery process to

fabricate large-area and flexible, high-performance NC devices. The recovery process may be

extended to other metal recovery agents and NC materials, opening up the wide-range of

conventional and unconventional semiconductor processes for low-cost, large-area fabrication of

NC device technologies.

5-4: Methods

FET Fabrication and Photolithographic Patterning. Device fabrication prior to

photolithographic source and drain patterning followed previously published literatures.5,10 A 1 nm

ultrathin layer of Al2O3, was grown on top of CdSe NC thin films by ALD (described below).

Source and drain electrodes were patterned by standard photolithographic processes, forming

top-contact bottom-gate FETs. For example, Microposit® S1813 photo resist was spun at 4000

rpm for 25 sec, followed by annealing at 115 oC for 60 sec. Alignment was performed using a

Nanonex NX-2600BA with an exposure energy of 90 mJ/cm2. The exposed samples were soaked

in Microposit® MF-319 developer for 45 sec to reveal the source and drain pattern. In/Au

electrodes were thermally evaporated and later lifted-off in MicroChem® Remover-PG.

Atomic layer deposition (ALD) process. A Cambridge Nanotech Savannah 200 ALD system

was used to grow Al2O3 from trimethylaluminum and water precursors. For both ultrathin 1 nm

oxide layers, used to prevent NC thin film delamination, and ~50 nm thick encapsulation layers,

the deposition was carried out at a processing temperature of 150 oC.

74

5-5: References

(1) Samanta, D.; Samanta, B.; Chaudhuri, A. K.; Ghorai, S.; Pal, U. Electrical Characterization of Stable Air-Oxidized CdSe Films Prepared by Thermal Evaporation. Semicond. Sci. Technol. 1996, 548, 548–553.

(2) Wu, C.; Bube, R. H. Thermoelectric and Photothermoelectric Effects in Semiconductors: Cadmium Sulfide Films. J. Appl. Phys. 1974, 45, 648.

(3) Cahen, B. D.; Hodes, G. Advanced Materials Progress Report on Molecules and Electronic Materials **. Adv. Mat. 2002, 14, 789–798.

(4) Cordero, S. R.; Carson, P. J.; Estabrook, R. A.; Strouse, G. F.; Buratto, S. K. Photo-Activated Luminescence of CdSe Quantum Dot Monolayers. J Phys Chem B 2000, 12137–12142.

(5) Choi, J.-H.; Fafarman, A. T.; Oh, S. J.; Ko, D.-K.; Kim, D. K.; Diroll, B. T.; Muramoto, S.; Gillen, G.; Murray, C. B.; Kagan, C. R.; et al. Bandlike Transport in Strongly Coupled and Doped Quantum Dot Solids: A Route to High-Performance Thin-Film Electronics. Nano Lett. 2012, 12, 2631–2638.

(6) Lee, J.-S.; Kovalenko, M. V; Huang, J.; Chung, D. S.; Talapin, D. V. Band-like Transport, High Electron Mobility and High Photoconductivity in All-Inorganic Nanocrystal Arrays. Nat. Nanotechnol. 2011, 6, 348–352.

(7) Aricò, A. S.; Baglio, V.; Blasi, A. D.; Creti, P.; Atnonucci, P. L.; Antonucci, V. Influence of the Acid–base Characteristics of Inorganic Fillers on the High Temperature Performance of Composite Membranes in Direct Methanol Fuel Cells. Solid State Ionics 2003, 161, 251–265.

(8) Liu, Y.; Gibbs, M.; Perkins, C. L.; Tolentino, J.; Zarghami, M. H.; Bustamante, J.; Law, M. Robust, Functional Nanocrystal Solids by Infilling with Atomic Layer Deposition. Nano Lett. 2011, 11, 5349–5355.

(9) Liu, Y.; Tolentino, J.; Gibbs, M.; Ihly, R.; Perkins, C. L.; Liu, Y.; Crawford, N. R. M.; Hemminger, J. C.; Law, M. PbSe Quantum Dot Field-Effect Transistors with Air-Stable Electron Mobilities above 7 cm2 V-1 S-1. Nano Lett. 2013, 13, 1578–1587.

(10) Kim, D. K.; Lai, Y.; Diroll, B. T.; Murray, C. B.; Kagan, C. R. Flexible and Low-Voltage Integrated Circuits Constructed from High-Performance Nanocrystal Transistors. Nat. Commun. 2012, 3, 1216.

(11) Zhuravlev, L. T. The Surface Chemistry of Amorphous Silica. Zhuravlev Model. Colloids Surfaces A Physicochem. Eng. Asp. 2000, 173, 1–38.

75

CHAPTER 6 Direct Photolithographic Patterning of Device Electrodes on

Colloidal Nanocrystals Thin Films to Build Wafer-Scale, Integrated Circuits

Colloidal nanocrystals (NCs) have recently emerged as a new class of solution-

processable semiconductor material for large-area and flexible electronics. This class of solution-

processable “inks” includes semiconductor organics, carbon nanotubes, amorphous metal-oxides

and NCs. They have been successfully demonstrated in a wide range of applications, such as

displays,1,2 solar cells,3,4 sensors,5 RFID6,7 and integrated circuits.8–12 These materials can be

deposited at temperatures that are compatible with flexible plastics and over large-areas, allowing

their device fabrication by low-cost techniques such as spincasting, spray-coating, roll-to-roll

processing, ink-jet printing and dipcoating.10,13–19 This enables the application of bendable and

wearable electronics,20–23 which cannot be easily accessed by conventional crystalline silicon and

III-V materials.

In this chapter, in collaboration with Scott Stinner, Dr. David Kim, Benjamin Diroll and

E.D. Goodwin, we show that photolithography can be used to pattern device electrodes directly

on NC thin films. Using photolithography we pattern the source, drain and gate electrodes of NC-

FETs and realize carrier mobilities > 10 cm2/Vs. Using these NC-FETs as building blocks, we

demonstrate low-voltage NC integrated circuits (NCICs) fabricated on the wafer scale. These

circuits include fundamental building blocks for analog and digital circuits, such as inverters,

voltage amplifiers, NOR and NAND logic gates, and ring oscillators. We measure a switching

speed of 2.9 µs per stage under a supply voltage of 5 V, which is the fastest demonstration using

NCs as the active channel to date.

76

6-1: VIA Process and Transistors Characteristics

We use standard photolithographic techniques to pattern the gate, vertical interconnect

access (VIA) holes and source/drain layers to realize wafer-scale integrated circuits. First, a

photolithographically defined metal stack of Cr/Au/Cr/Al is fabricated to form the gate electrode.

Next, a thin, high-k Al2O3 layer is grown by atomic layer deposition (ALD) on top of aluminum to

form a high quality gate dielectric layer. Holes in the insulating alumina layer are then defined by

photolithography and created by reactive ion etching and then subsequently filled with gold to

form VIAs. The VIA is essential because it connects electrodes between different layers,

necessary for advanced circuits and for greatly reducing the number of contacts in high density

devices. We found the use of a plasma to be very aggressive, which not only etches the Al2O3

dielectric layer, but also damages the underlying aluminum. The presence of Au in the metal

stack preserves the VIA conductivity and connectivity between electrodes (as shown below).

To fabricate the active CdSe NC layer, we took advantage of a process described in

Chapter 5 to recover high-performance CdSe NC-FETs after being exposed to air and common

solvents used in patterning devices.24 To begin with, as synthesized NCs were pre-exchanged

with the short compact ligand thiocyanate prior to spincasting. Films are annealed at 200 oC for 5

minutes in inert atmosphere to promote adhesion of the CdSe NC thin film to the substrate. To

further enhance film adhesion, a thin 10 Å ALD Al2O3 layer is deposited to prevent film

delamination during exposure to solvents. Source/drain electrodes are defined by

photolithography, followed by thermal evaporation of a metal stack of In/Au to form bottom-gate,

top-contact NC-FETs and NCICs. Finally, the samples are annealed at 250 oC for 30 min,

followed by 200 oC for 12 hrs in a glovebox, to allow diffusion of indium metal from the

source/drain electrodes into the channel. Indium both passivates surface states formed by

exposure to ambient air and chemicals used in lithography and dopes the NC channel. Using the

processes developed, we are able to successfully fabricate hundreds of single transistors and

multiple inverters, voltage amplifiers, NOR, NAND and ring oscillators over a four inch wafer.

77

Figure 6-1. (A) Photograph of wafer-scale CdSe NCICs, where the smallest channel length is 5 µm. (B) Schematic of (top) single transistor and (bottom) transistor with VIA connection to form enhancement-load inverters. (C) Device output characteristics (ID-VDS) and (D) transfer characteristics (ID-VGS) in the saturation regime (VDS = 3 V). Channel width over channel length is (600 µm/40 µm).

Figure 6-1 (A,B) is an image and schematic of photolithographically-patterned, bottom-

gate, top-contact CdSe NCICs on a 4 inch wafer. Figure 6-1 (C, D) shows representative n-type

NC-FET device output (ID-VDS) and transfer (ID-VGS) characteristics at 3 V for NC-FETs used to

construct the NCICs. The high-k and thin Al2O3 gate oxide provides a high capacitance of 216

nF/cm2 [Figure 6-2 (A)]. Over 20 measured NC-FETs, the field-effect mobility in the saturation

regime [Figure 6-1 (D)] is 10.0 ± 2.26 cm2/Vs with a threshold voltage (VT) of 1.0 ± 0.11 V, and in

the linear regime [Figure 6-2 (B)] the mobility value is 10.0 ± 2.48 cm2/Vs with a VT of 1.3 ± 0.13

0 1 2 3

10-10

10-9

10-8

10-7

10-6

10-5

10-4

VGS

(V)

I D (

A)

0

-2

-4

-6

-8

-10

Sq

rt ID (m

A1/2)

0 1 2 3

0

10

20

30

40

1.0 V

1.5 V

2.0 V

I D (µA)

VDS

(V)

VGS

= 2.5 V

1cm

(A)

(C) (D)

(B)

78

Figure 6-2. (A) The unit capacitance and dielectric constant (epsilon) of ALD grown Al2O3 as a function of frequency. The average epsilon measured from 8 test capacitors is 7.3 ± 0.48 (at 2 kHz). (B) Device transfer characteristics operated in the linear regime (VDS = 0.1 V). Channel width over length is (600 µm/40 µm). (C) Transmission line method used to characterize device contact resistance for devices with channel lengths ranging from 5 µm to 40 µm, under (Black) VGS = 1.5V, (Red) VGS = 2.0V and (Blue) VGS = 2.5V. (D) A summary of extracted contact and channel resistance from the transmission line method.

V. These FETs have a current on/off ratio of over 105, with an average subthreshold swing of 241

mV per decade. The calculated semiconductor-dielectric interface trap density is (5.5 ± 0.42) x

1012 cm-2, similar to our previous reports on high performance CdSe NC-FETs.10,25 The contact

resistance at the source/drain electrodes is estimated by the transmission line method [Figure 6-2

(C,D)], showing the injection barrier is negligible compared to the channel resistance. This also

shows that the 10 Å of Al2O3 deposited as a CdSe NC protection layer before source/drain

electrode deposition does not impede charge injection.

102

103

104

50

100

150

200

250

300

1.7

3.4

5.1

6.8

8.5

10.2

Ca

pa

cit

an

ce

(n

F/c

m2

)

Frequency (Hz)

Epsilo

n

0 1 2 3

10-9

10-8

10-7

10-6

10-5

VG (V)

I D (

A)

0

2

4

6

8

ID (

µA

)(A) (B)

0 10 20 30 40

0

20

40

60

80

100

RTOTAL (

oh

ms

x m

)

Length (µm)

(C) (D)

VG

RCH

(ohms)

RCONTACT

(ohms * µm)

1.5 1.9 x 106 -1.4 x 106

2.0 8.9 x 105 -4.4 x 104

2.5 5.4 x 105 1.9 x 105

79

Figure 6-3. Nanocrystal integrated inverter and electrical characteristics. (A) Photograph of an enhancement-load inverter, where (W/L)Load to (W/L)Driver ratio is (10/100), and the channel lengths are constant at 10 µm. (B) Inverter voltage transfer characteristics at (black) VDD = 5 V, (red) 4 V, (blue) 3 V and (olive) 2 V and its associated (C) voltage gain, (D) noise margin and (E) drain current. Voltage amplifier output characteristics for input at (F) 10 Hz and (G) 5 kHz, where (red) output waveform is in response to (black) input signal. (H) Bode plot of voltage amplifier, where blue dashed lines refer to low frequency voltage gain and 3 dB gain at higher frequency.

101

102

103

104

0

1

2

3

4

5

6

7

Ga

in (

dB

)

Frequency (Hz)

0.1 0.2 0.3 0.4 0.51.0

1.2

1.4

1.6

1.8

2.0

Am

plitu

de

(V

)

Time (sec)

10 Hz

0.2 0.4 0.6 0.8 1.01.0

1.2

1.4

1.6

1.8

2.0

Am

pli

tud

e (

V)

Time (msec)

5k Hz

0

1

2

3

4

5

VOUT (

V)

0.0

-0.5

-1.0

-1.5

-2.0

-2.5

Ga

in

0

1

2

3

4

5

NMH

VOUT (

V)

NML

0 1 2 3 4 5

10-8

10-7

10-6

10-5

10-4

V

IN (V)

I D (

A)

(B)

(C)

(D)

(E)

(F)

(G)

(H)

(A)

VDD

VOUT

VSSV

IN

80

6-2: Inverters Characteristics and Analysis

To form inverters, two NC-FETs operate in concert, where one is designed as a load and

the other as a driver. Since these NC-FETs are n-type and have a positive VT, an enhancement-

load design is used by connecting the gate of the driver to the drain electrode of the load through

the VIA. Figure 6-3 (A) shows a photograph of an enhancement-load inverter, and a schematic

depicts the VIA connection shown in Figure 6-1 (B). To test VIA conductivity, we measured VIA

holes of various sizes. The result shows ohmic contact of 500 ohms resistance crossing 16 VIA

holes [Figure 6-4]. Figure 6-3 (B-E) show the inverters voltage transfer characteristics (VTCs),

voltage gain, noise margin, and drain current at different supply voltages (VDD). The inverter starts

to function at VDD = 2 V. Upon increased VDD, higher voltage gain, larger noise margin, and more

drain current are observed. In Figure 6-3 (C), the highest gain is measured up to -2.25 V/V, and

the region where voltage gain greater than unity is applicable for analog operation in circuits such

as voltage amplifiers. At VDD = 5 V, a 200 mV peak to peak sinusoidal wave with a DC offset of

1.7 V serves as the input signal, and the amplified output signal is collected. Figure 6-3 (F,G) are

the output waveform of the voltage amplifier with 10 Hz and 5 kHz input respectively. Both output

waveforms are amplified with 180 degree phase shift, a typical characteristic of negative voltage

gain in inverters. For 10 Hz input, the output shows AC gain of -2.0 V/V and DC offset around

1.42 V, in agreement with the inverter VTCs in Figure 6-3 (A). The inverter frequency response

(Bode plot) is shown in Figure 6-3 (H), where a 3 dB bandwidth is estimated to be between 6 kHz

to 7 kHz, and remains greater than unity for amplification up to 10 kHz. This measured 3 dB

bandwidth is 8 times faster than our previous voltage amplifiers (3 dB bandwidth of 900 Hz)

reported in Chapter 3, which we believe is due to the reduced parasitic gate to source/drain

overlap capacitance. In Figure 6-3 (D), the two eyes at each VDD mark output high (NMH) and

output low (NML) noise margins, a prerequisite for multiple stages logic operation.

We follow the method in Chapter 3 to analyze these measured characteristics. For the

enhancement-load inverter, the voltage AC gain is expressed as

81

Figure 6-4. (A) Top and perspective view of VIA test structures, where the red layer is the gate electrode, yellow is the VIA, and blue is the source/drain electrodes. The square VIAs have sizes of 200, 100, 50 and 25 µm. (B) I-V characteristics across 16 VIA holes, described as yellow arrows in (A).

= −__ + _ + _

(6 − 1)

, where gm is transconductance, gds is output conductance, and these can be calculated based on

device characteristics [Figure 6-1 (C,D)]. According to Figure 6-3 (B,E), at VIN = 1.7 V, VOUT is

1.42 V. The VGS drop across load and driver NC-FETs is then 3.58 and 1.42 V respectively.

Therefore, the calculated transconductances for gm_Load and gm_Driver are 4.06 x 10-5 and 1.02 x 10-

4 respectively. Compared to the transconductance, the load and driver output conductance is

negligible, as their calculated values are in the range between 10-6 and 10-7. The estimated

voltage gain based on [Equation (6-1)] is -2.5 V/V, which is very closed to our measured value of

-2.25 V/V. Assuming the carrier mobility for load and driver are identical and independent of VGS,

the ideal voltage gain for an enhancement-load inverter should follow, = −( )

( ), and

0 1 2 3 4 5

0

2

4

6

8

10

I (m

A)

Voltage

(A) (B)

82

Figure 6-5. Nanocrystal integrated NOR and NAND logics. Photograph of (A) NOR and (D) NAND, where the load FET has a fixed (W/L) ratio of 10 and the driver FETs have a fixed (W/L) ratio of 100. Channel length is constant at 10 µm for load and driver FETs. Circuit symbol and truth table for (B) NOR and (E) NAND logic gates. Voltage transfer characteristics for (C) NOR and (F) NAND logics, where black and blue scans refer to different input configurations, shown as black and blue arrows in (B),(E) truth tables.

show -3.3 V/V in our circuit design. Since carrier mobility in NC-FETs shows a gate voltage

dependence at lower VGS, the actual voltage gain becomes = −

×

( )

( ). Using

the conductances and transconductances for load and driver, we also estimate the voltage

amplifier 3 dB bandwidth by calculating the constituent circuit RC time constant. The total output

impedance (R) is

= −1_ + _ + _

(6 − 2)

A

BVOUT

A

BVOUT

0 1 2 3 4 50

1

2

3

4

5

VOUT (

V)

VIN

(V)

strong 1

weak 1

0 1 2 3 4 50

1

2

3

4

5

VOUT (

V)

VIN

(V)

weak 0

strong 0

VDD

VSS

VOUT

VDD

VOUT

A B

VSS

A

B

A B VOUT

0 0 1

0 1 1

1 0 1

1 1 0

A B VOUT

0 0 1

0 1 0

1 0 0

1 1 0

(A) (B) (C)

(D) (E) (F)

83

The capacitive load originates from parasitic capacitance inside the load and driver NC-FETs,

and residual capacitance from the probe connections to the contact pads. The calculated RC time

constant is 3.7 µs, equal to a 3 dB bandwidth of 42 kHz, a factor of 6 to 7 times faster than the

measured bandwidth (6 kHz to 7 kHz). This difference suggests a significant parasitic

capacitance in the measured characteristics, which we suspect it is coming from the experimental

setup.

6-3: NOR logic

Figure 6-5 (A,D) shows photographs of integrated NOR and NAND gates, each

constructed from three NC-FETs. To test NOR function, input A and B are externally tied and

share the same applied voltages. By sweeping them between high voltage to low voltage, input

configuration [1,1] sweeping to [0,0] is achieved, as shown by the black arrow in the Figure 6-5

(B) truth table. The output characteristic from this input sweep is shown in Figure 6-5 (C) as the

black curve. We use the same idea to realize input sweeping from [0,1] to [0,0], where input A is

tied to VSS to remain "0" and input B is swept between high and low voltage. This sweeping input

configuration is shown by blue arrow in Figure 6-5 (B), and the output characteristics in Figure 6-5

(C) as the blue curve. The result is consistent with the NOR truth table, where output reads "0" for

either or both input reading "1". In addition, the distinct two potentials at the "0" state correspond

to NOR circuit operation, where a lower potential is achieved by a larger drain current from two

driver transistors. If only one driver transistor is turned on, the drain current is relatively smaller,

give rise to slightly higher "0".

6-4: NAND logic

Figure 6-5 (D) shows a photograph of NAND logic. We use similar methods to test NAND

logic as above. The input sweep from [1,1] to [0,0], shown as the black arrow in the Figure 6-5 (E)

NAND truth table, is carried out by tying input A and B together. Next, input A is tied to VDD to stay

"1" while input B is swept between "1" and "0". This sweeping input configuration is indicated by

84

the blue arrow in Figure 6-5 (E), and shown in output characteristics in Figure 6-5 (F) as the blue

curve. The result matches well with the NAND truth table, where output reads "1" if either or both

input read "0". For NAND logic, two distinct potentials are shown in output "1". This is due to

leakage current if either driver stays on, giving rise to a lower "1". In theory, NAND and NOR are

two fundamental building blocks from which all complex and functional logic gates are

constructed. The demonstration of robust nanocrystal integrated NAND and NOR show promising

applications for digital circuitry.

6-5: Ring-Oscillators

To measure the switching speed for our NCICs, 5-stage ring oscillators are fabricated,

where a 6-th stage is used as a buffer stage for output collection. Figure 6-6 (A) is a photograph

and circuit schematic of a 5-stage ring oscillator made of inverters as shown in Figure 6-3 (A).

The channel length is 10 µm, and the gate to source/drain overlap is 10 µm. The output waveform

under VDD = 5 V is presented in Figure 6-6 (B). A 1.6 V rail-to-rail swing is oscillating ~34.3 kHz,

equal to a 2.9 µs delay per stage () from =

×× , where N is stage numbers and f is the

oscillation frequency. To the best of our knowledge, this is the fastest switching speed in NCICs.

We use the stage delay analysis described in Chapter 3 and output waveform (output high as 2.0

V and output low as 0.48 V) to calculate the stage delay. The estimated switching speed is 1.8 µs

for VDD = 5 V, matching well with the measured value. Figure 6-6 (C) is the stage delay

relationship to VDD, collected from four 5-stage ring oscillators fabricated on the same substrate.

The output starts to show oscillation when VDD = 2 V. Faster switching speed is seen at higher

VDD as more current [see Figure 6-3 (E)] is able to readily charge/discharge the output load. The

stage delay at VDD = 2 V is 59 µs, one order of magnitude smaller than the first nanocrystal based

ring oscillator ( = 600 µs, in Chapter 3).10 Yet, this switching speed can be improved by

designing smaller channel length NC-FETs and further reducing the electrode overlap in the

devices.

85

Figure 6-6. Nanocrystal integrated 5-stage ring oscillators. (A) Photograph and circuit schematic. (B) Output waveform of a 5-stage ring oscillator at VDD = 5 V. (C) Stage delay statistics as a function of VDD. (D) Summary of the ring oscillator stage delay using active channels from the following classes of solution processable.materials:(green) organic semiconductor, (blue) carbon nanotube networks, (red) metal-oxides, and (black) for colloidal nanocrystal semiconductors (demonstrated in this thesis). Solid circles represent reports of devices fabricated on rigid substrates, and empty circles for devices on flexible plastics. The black empty diamond is the 1st NCIC ring oscillator fabricated on flexible substrate, reported in Chapter 3.

Figure 6-6 (D) summarizes the switching speed of ring oscillators employing solution

processable materials as active channels, including organic semiconductors,26–32 carbon

nanotubes,9,33,34 amorphous metal-oxides11 and colloidal NCs.10 The main challenge for all these

materials relies on integrating materials and developing compatible fabrication processes to

realize devices operating at less than 5 V, crucial for applications in portable electronics and

sensors to be powered by battery or inductive charging. The performance of our NCICs is

0 20 40 60 80 100

0.5

1.0

1.5

2.0

2.5

Am

plitu

de

(V

)

Time (µsec)

VDD

= 5V

2 3 4 510

-6

10-5

10-4

Sta

ge D

ela

y (

s)

VDD

(V)

0.1 1 1010

-7

10-6

10-5

10-4

10-3

10-2

Sta

ge d

ela

y (

s)

Supply Voltage (V)

(A)

VDD

VSS

VOUT

(B)

(C) (D)

86

competitive with other solution processable materials. As these NCs are compatible with

conventional photolithography, NCs can be adapted to currently available large-area fabrication

equipment and techniques, boosting its development toward lost-cost, large-area electronics.

6-6: Conclusion

In summary, we report wafer-scale, low-voltage integrated circuits using colloidal NCs as

active channels. We show functional and robust NCICs applicable for both analog and digital

application, including inverters, voltage amplifiers, NOR and NAND logics, and ring oscillators.

Due to the introduction of photolithography, device parasitic capacitance is reduced. Our voltage

amplifier bandwidth is enhanced to ~7 kHz. The fastest switching speed measured from our 5-

stage ring oscillator reaches 2.9 µs under 5 V supply. This is an important breakthrough as it

opens up the opportunity to adopt NCs for large-area, high-speed circuits.

6-7: Methods

Device Fabrication

Gate, VIA and source/drain electrode patterning are carried out using standard photolithography

procedures. A pre-cleaned SiO2/Si wafer is coated with a 20 nm ALD (Cambridge Nanotech

Savannah 200) Al2O3 as the substrate. A stack of 2 nm Cr/20 nm Au/2 nm Cr/40 nm Al is

thermally evaporated to form the gate electrodes. Samples are then briefly exposed to oxygen

plasma (75 mTorr, 100 W, 10 min, Plasmalab 80 plus) to increase the density of surface hydroxyl

groups on the aluminum gate, followed by deposition of another ALD grown 30 nm Al2O3 that

serves as the gate dielectric layer. The oxide thickness is verified by spectral reflectance

(Filmetrics, F-40) or ellipsometry (J.A. Woollam, V-VASE). Etching of the Al2O3 is carried out by

reactive ion etching (RIE) in an inductively-coupled (ICP) plasma (Trion Phantom III). General

etching parameters for 30 nm of Al2O3 is 15 mTorr of BCl3 with a flow of 50 sccm, RIE power of

300 W and ICP power of 590 W for 30 - 40 sec. A stack of 2 nm Cr/80nm Au is subsequently

deposited and the resist is lifted-off to form conductive VIA holes. CdSe colloidal NCs are

87

synthesized and exchanged in solution with the compact, inorganic thiocyanate following

literature procedures.10,35 Dispersions of thiocyanate-capped CdSe NCs are spin-cast over the

entire wafer to form uniform, randomly close-packed CdSe NC thin films. The sample is annealed

at 200 oC for 5 min, followed by deposition of a 10 Å ALD Al2O3 layer. Source/drain electrodes of

40 nm In/40 nm Au are deposited by thermal evaporation following lithographic patterning of the

source/drain layer. The sample is annealed at 250 oC for 30 min, followed by 200 oC for 12 hours

to allow indium metal diffusion into the CdSe NC channels. All procedures are performed in

ambient air, with exception for the CdSe NC exchange, spin-cast and annealing, which are

carried out inside a nitrogen filled glovebox.

Device characterization

A semiconductor parameter analyzer (Agilent 4156C) is used to collect NC-FETs device

characteristics. An HP/Agilent 4276A LCZ meter is used for capacitance and dielectric constant

measurement. An arbitrary waveform generator (33220 A, Agilent), an oscilloscope (Tektronix,

TDS 2000C) and low-noise JFET Op Amps (serving as a unity gain buffer) are used in the

collection of all AC characteristics of voltage amplifiers. An oscilloscope is used to collect the ring

oscillator output waveform.

6-8: Reference

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(19) Girotto, C.; Moia, D.; Rand, B. P.; Heremans, P. High-Performance Organic Solar Cells with Spray-Coated Hole-Transport and Active Layers. Adv. Funct. Mater. 2011, 21, 64–72.

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(28) Zhao, Y.; Di, C.; Gao, X.; Hu, Y.; Guo, Y.; Zhang, L.; Liu, Y.; Wang, J.; Hu, W.; Zhu, D. All-Solution-Processed, High-Performance N-Channel Organic Transistors and Circuits: Toward Low-Cost Ambient Electronics. Adv. Mater. 2011, n/a–n/a.

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91

CHAPTER 7 Future Direction

7-1: Photolithographic Patterning of Nanocrystal Thin Films to Build Integrated

Circuitry on Flexible Plastic

In Chapter 6, we show nanocrystal integrated circuits (NCICs) on rigid substrates, where

electrodes are patterned directly on nanocrystal films. One of the future directions is to translate

the entire process on to large-area, flexible substrates and develop methods to pattern the

nanocrystal (NC) films. In high density integrated circuits, patterning the semiconductor layer

helps reduce undesirable cross talk currents, which affect device off current and the "0" state. In

collaboration with Dr. David Kim and Scott Stinner, we develop processes to fabricate NCICs on

large-area, flexible substrates, where CdSe NC thin films are photolithographically patterned.

As described in Chapter 6, a brief annealing at 200 oC for 5 min in combination with

deposition of an ultrathin, ALD Al2O3 coating helps to increase the CdSe NC film’s adhesion on

the substrate and makes it immune to chemical exposure. Without these extra steps, we find

CdSe NC films can be soluble to tetramethylammonium hydroxide (TMAH), a common solvent

used in developing exposed photoresist. Here, we take advantage of this solubility in TMAH to

pattern the CdSe NC film. Subsequent to CdSe film casting over the substrate, samples are

directly coated with photoresist and undergo UV exposure. In the developing stage, the exposed

photoresist regions are removed by soaking in TMAH for 30 - 60 sec. Prolonged soaking in

TMAH for another 3 - 10 min, delaminates and etches the CdSe NC film under the exposed

photoresist. The unexposed photoresist remains intact, as well as the CdSe NC film underneath.

To reveal the patterned CdSe NC thin film, unexposed photoresist is readily removed by soaking

in acetone for 2 min. A test example of a patterned CdSe NC thin film on a 4" wafer is shown in

Figure 7-1 (A), where a clean etch with high resolution is shown in Figure 7-1 (B). This approach

is successfully transferred to plastic, and combined with Chapter 6 methods to fabricate large-

area, flexible integrated circuits.

92

Figure 7-1. (A) Photograph of a large-area, photolithographically-patterned, CdSe nanocrystal thin film. (B) Optical micrograph of a patterned nanocrystal thin film array, where the gap and pitch are both 25 µm.

Figure 7-2 (A) shows CdSe NCICs fabricated on 4 inch, flexible Kapton®, where the

CdSe NC thin-film channel is patterned using this method. Devices schematics comparing

unpatterned and patterned NC thin film channels are shown in Figure 7-2 (B). Figure 7-2 (C)

shows optical micrographs of patterned NC thin films and FET building blocks used to construct

the circuits. To verify the cross talk current is reduced by patterning, the device current is

measured for NCICs with and without patterned CdSe NC thin films. In Figure 7-2 (D), the drain

current for both devices is similar, but the cross talk current (gate current) is greatly reduced by

as much as four orders of magnitude. The gate current is a measurement of lateral cross talk

current through non-patterned CdSe NC thin films. The vertical gate leakage current through

oxide is confirmed in Figure 7-2 (E) below to be in the pA range. This gate leakage current is in

agreement with that in Figure 7-2 (D) realized by patterning the NC thin film channel. In Figure 7-

2 (F), the greater than 200 nF/cm2 unit capacitance ensures devices operate at low-voltage.

(A) (B)

50 µm

93

Figure 7-2. (A) Photograph of 10 x 10 cm square flexible nanocrystal integrated circuit, where CdSe nanocrystals are patterned. (B) Schematic of devices with and without patterned nanocrystals. (C) Optical micrograph of devices with patterned nanocrystals as the active channel (top), and an array of the patterned nanocrystal thin film (bottom). (D) At constant VDS = 5 V, device drain current (ID, black, left y-axis) and gate current (IG, blue,right y-axis) for non-patterned (empty circle) and patterned (solid) nanocrystal thin-film devices. Device channel width over length ratio is 1000 µm / 10 µm. (E) ALD grown Al2O3 gate leakage current as a function of applied voltage, and (F) unit capacitance as a function of frequency.

100µm

300µm

(A) (B)

(C) (D)

-1 0 1 2 3 4 510

-12

10-10

10-8

10-6

10-4

10-12

10-10

10-8

10-6

10-4

IG (A

)

I D (

A)

VGS

(V)

102

103

104

50

100

150

200

250

Cap

acit

an

ce (

nF

/cm

2)

Frequency (Hz)-6 -4 -2 0 2 4 6

10-14

10-13

10-12

10-11

I G (

A)

VGS

(V)

(E) (F)

94

Figure 7-3. Schematic of a nanocrystal thin-film transistor (A) without and (C) with ALD Al2O3 encapsulation. Transfer characteristics (ID-VGS, black, left y-axis) and its square root (blue, right y-axis) in the saturation regime (VDS = 5 V) for devices (B) without and (D) with 50 nm ALD Al2O3 encapsulation. (E) Output characteristics (ID-VDS) and (F) statistics on carrier mobility (µ), threshold voltage (VT), subthreshold swing (S) and dielectric-semiconductor interface trap density (NT) for encapsulated devices. Note: Device channel width over length ratio is 1000 µm / 10 µm in (B,D,E). Saturation regime characteristics are measured at VDS = 5 V, and linear regime characteristics are measured at VDS = 0.1 V.

A device schematic and representative transfer characteristics (ID-VGS) in the saturation

regime of a patterned CdSe NC device is shown in Figure 7-3 (A,B), where we are highlighting

the distinct hysteresis in the square root of drain current that causes difficultly in interpreting

device carrier mobility. In Chapter 4, we introduce ALD encapsulation to minimize device

hysteresis and bias-stress effects. Figure 7-3 (C, D) are schematics and device characteristics of

0 1 2 3 4 50

100

200

300

400

500

600

2V

3V

4V

I D (µA)

VDS

(V)

VGS

= 5V

-1 0 1 2 3 4 510

-11

10-9

10-7

10-5

10-3

VGS

(V)I D

(A

)

0

-10

-20

-30

Sq

rt ID (m

A1/2)

-1 0 1 2 3 4 510

-11

10-9

10-7

10-5

10-3

VGS

(V)

I D (

A)

0

-10

-20

-30 Sq

rt ID (m

A1/2)

(A) (B)

(C) (D)

(E) (F)Saturation Linear

µ (cm2/Vs) 3.8 ± 0.70 2.7 ± 0.73

VT (V) 1.0 ± 0.25 1.2 ± 0.85

S (mV/dec) 447 ± 236.0

NT (1/cm2) (9.3 ± 4.93) x 1012

95

.

Figure 7-4. (A) Transmission line method for devices with constant channel width to length ratio of 15, and channel length ranging from 5 µm to 40 µm. (B) Extracted device channel resistance (RCH) and metal-to-semiconductor contact resistance (RCONTACT) as a function of gate voltages.

ALD encapsulated devices, for comparison to those in Figure 7-3 (A, B) prior to encapsulation.

For ALD encapsulated device, the square root of drain current show reduced hysteresis. Figure

7-3 (E) shows representative device output characteristics (ID-VDS) for an ALD encapsulated

device and Figure 7-3 (F) shows the statistics reporting device performance for 26 ALD

encapsulated CdSe NC FETs from the same substrate. The average carrier mobility is ~ 2 to 4

cm2/Vs, a few times smaller than those realized in the NCICs fabricated on Si wafers in Chapter 6

(average carrier mobility is ~10 cm2/Vs). To account for the differences, the contact resistance

and interface trap density (NT) are calculated using the transmission line method and device

subthreshold swing.

As seen in Figure 7-4 (A,B), the contact resistance of patterned, flexible CdSe NCICs is

more than one order of magnitude higher than that for non-patterned NCICs on rigid substrates

reported in Chapter 6. Larger NT is also found on flexible patterned NCICs. Unlike rigid

substrates, flexible substrates are laminated on a rigid wafer that serves as a mechanical carrier

during spin-coating of the NCs and photoresist and photolithographic exposure in a mask aligner.

Due to the very strong pressure applied during UV exposure, extreme bending of the flexible

0 10 20 30 400

50

100

Channel Length (µm)

RTOTAL (

oh

ms x

m)

VG

RCH

(ohms)

RCONTACT

(ohms * µm)

2 2.3 x 106 6.6 x 106

3 1.0 x 106 2.7 x 106

4 7.1 x 105 1.7 x 106

5 5.7 x 105 1.2 x 106

(A) (B)

96

Figure 7-5. Enhancement-load inverter. Voltage transfer characteristics for device (A) without and (C) with encapsulation. Noise margin for devices (B) without and (D) with encapsulation. The channel width (W) to length (L) ratio is 10 for the load, and 100 for driver. Load and driver transistors have constant channel length of 10 µm.

substrates is often required to pull it off the rigid wafer. We believe this is the main cause for the

high NT in flexible NCICs.

Figure 7-5 is the comparison of inverter voltage transfer characteristics (VTCs) and noise

margin between (A, B) bare and (C, D) encapsulated device. As shown, the reduced hysteresis in

encapsulated devices gives rise to a reduction in the variation in VTCs and an improvement in

noise margin. This is important for stable and reliable circuit operation.

0 1 2 3 4 50

1

2

3

4

5

VOUT (

V)

VIN

(V)0 1 2 3 4 5

0

1

2

3

4

5

VIN

(V)

VOUT (

V)

0.0

-0.5

-1.0

-1.5

-2.0

-2.5

Gain

0 1 2 3 4 50

1

2

3

4

5

VOUT (

V)

VIN

(V)0 1 2 3 4 5

0

1

2

3

4

5

VIN

(V)

VOUT (

V)

0.0

-0.5

-1.0

-1.5

-2.0

-2.5

Gain

(A) (B)

(C) (D)

97

Figure 7-6 (A) is a photograph of an enhancement-load inverter. Figure 7-6 (B) shows the

output characteristics for the load (red) and driver (black) transistors. These low hysteresis

transistors are the building blocks used to construct and realize low hysteresis VTCs in Figure 7-6

(C). In Figure 7-6, (D) higher voltage gain, (E) larger noise margin, and (F) higher current are

observed at higher supply voltages (VDD) as expected. Figure 7-6 (G,H) shows two representative

output waveforms for voltage amplifiers in response to 100 Hz and 16 kHz input waveforms,

respectively. Figure 7-6 (I) is the constructed Bode plot, showing a 3 dB bandwidth that now

reaches 16 kHz.

Figure 7-7 is the inverter dynamic response at VDD= 5 V. For a 100 Hz input, an output

swing between 4.5 V to 0.25 V is observed, matching the VTCs in Figure 7-6 (C) at VDD = 5 V.

For a 10 kHz input, the output swing is reduced with the output high only reaching ~ 2.7 V.

Referring to Figure 7-6 (E), this output high and output low shown in Figure 7-7 (B) are within the

noise margin, making the device capable of multistage switching. Using Figure 7-7 (B) we

evaluate the delay per stage using rise time and fall time analysis. The calculated rise time and

fall time are 38 µs and 2 µs respectively, and therefore we calculate an average of 20 µs delay

per stage. This speed is nearly one order of magnitude slower than results from the 5-stage ring

oscillator fabricated on rigid, non-patterned NCICs. We attribute this slower response to the lower

device performance.

Figure 7-8 shows the logic output characteristics for a NOR gate. The measurements are

produced by switching between “0” and “1” using a series of different input configurations. In

Figure 7-8 (B) black curve, input A and B are externally tied and the voltages are swept together

between input "0" and "1". This is carried out to emulate input sweeping between [0,0] and [1,1],

as shown in truth table as black arrows. In Figure 7-8 (B), blue curve has input A externally tied

with VSS (ground), meanwhile input B is swept between "0" and "1". This is to realize input

sweeping between [0,0] and [0,1]. The NOR output characteristics at VDD = 2V and 5V both show

agreement with the NOR truth table and two states of "0". The lower potential (strong "0") is due

98

to greater pull-down current when both driver FETs are turned on in the [1,1] input configuration.

On the other hand, input [0,1] or [1,0] give rise to weaker "0" as current only comes from one

driver FET. Figure 7-8 (C) shows an alternative method to read NOR output characteristics,

where a 5 V amplitude square wave is sent as inputs. The results also match well with the NOR

truth table.

In summary, we have successfully fabricated flexible, patterned CdSe NCICs. By

introducing ALD encapsulation, low hysteresis single transistors, inverters and NOR logic have

shown promising results. However, carrier mobility is lower than expected and not all design

circuits are functional. Initial investigation of the device characteristics suggests that high

resistance contacts and an increased interface trap density are responsible for the degraded

performance. More efforts have begun to boost device performance, such as direct channel

doping and more optimized and reproducible ligand exchange strategies.

99

0

1

2

3

4

5

VOUT (

V)

0.0

-0.5

-1.0

-1.5

-2.0

-2.5

Gain

0 1 2 3 4 5

10-7

10-6

10-5

10-4

I D (

A)

VIN

(V)

0

1

2

3

4

5

VOUT (

V)

101

102

103

104

105

-6

-3

0

3

6

9

Ga

in (

dB

)

Frequency (Hz)

Bandwidth ~ 16k Hz

-0.2 -0.1 0.0 0.1 0.2

-0.2

-0.1

0.0

0.1

0.2

Vo

ltag

e

Time (sec)

10 Hz

-100 -50 0 50 100

-0.2

-0.1

0.0

0.1

0.2

Vo

lta

ge

Time (µsec)

16k Hz

0 1 2 3 4 50

100

200

300

400

500

I D (µA

)

VDS

(V)

VDD

VSS

VIN

VOUT

(A) (B)

(C) (G)

(D)

(E)

(F)

(H)

(I)

100

Figure 7-6. (A) Photograph of enhancement-load inverter. (B) Load (red) and driver (black) output characteristics. (C) Inverter voltage transfer characteristics, (D) voltage gain, (E) noise margin, and (F) drain current for (black) VDD = 5 V, (red) 4 V, (blue) 3 V and (olive) 2 V. Voltage amplifier characteristics for an input at (G) 10 Hz and (H) 16 kHz, where (red) the output waveform is measured in response to (black) a sinusoidal, 200 mV peak-to-peak input signal. (I) Bode plot for the voltage amplifier, where blue dashed lines refer to low frequency voltage gain and 3 dB gain at higher frequency. The measured 3dB bandwidth is ~ 16 kHz.

Figure 7-7. Inverter dynamic response at VDD = 5 V. Input (black) and output (red) waveform for (A) 100 Hz 5 V peak to peak input, and (B) 10 kHz 5 V peak to peak input.

Figure 7-8. (A) Photograph of NOR logic. (B) Voltage transfer characteristics for different input sweep configurations, where black refers to the input sweep between [0,0] and [1,1], and blue refers to the input sweep between [0,0] and [0,1]. Inset: NOR truth table. (C) Output characteristics.

-15 -10 -5 0 5

0

1

2

3

4

5

Am

pli

tud

e (

V)

Time (10-3

sec)-200 -150 -100 -50 0

0

1

2

3

4

5

Am

plitu

de (

V)

Time (10-6

sec)

(A) (B)

0 1 2 3 4 50

1

2

3

4

5

VOUT (

V)

VIN

(V)

01/1000

0.64 V

0.30 V0.25 V

0.08 V

4.4V

4.3V

1.5V

1.4V

VOUT

VDD

VSS

A B

0.0 0.1 0.2 0.3

0

1

2

3

INPUT: 1,1

OUTPUT: 0

INPUT: 0,1/1,0

OUTPUT: 0

VOUT (

V)

Time (sec)

INPUT: 0,0

OUTPUT: 1

(A) (B) (C)A B V

OUT

0 0 1

0 1 0

1 0 0

1 1 0

7-2: Mechanical Stability of Flexible Nanocrystal Field

For flexible electronic applications, it is very important to understand device

characteristics during the application of mechanical stress .

flexible devices typically experience tension or compre

As shown in Figure 7-9, the

as3

where E is the Young's modulus of the material,

is radius of curvature (also known as the bending radius). The neutral axis refers to a plane

where neither tension nor compression is applied during bending. The sign of the equation (1)

indicates the type of stress (negati

Figure 7-9.

Figure 7-9. Schematic for a beam under bending.

In collaboration with Dr. David Ki

Kapton substrates) NC-FETs

different curvature and size were custom made. In Figure 7

glass tube, adhesive gel was used. Figure 7

101

2: Mechanical Stability of Flexible Nanocrystal Field-Effect Transistors

For flexible electronic applications, it is very important to understand device

characteristics during the application of mechanical stress .1,2

In practical applications, these

flexible devices typically experience tension or compression when bent or stretched, respectively.

9, the strain () and stress () during mechanical testing can be expressed

is the Young's modulus of the material, y is the distance from the neutral axis (NA), and

is radius of curvature (also known as the bending radius). The neutral axis refers to a plane

where neither tension nor compression is applied during bending. The sign of the equation (1)

indicates the type of stress (negative for compression and positive for tension), as shown in

. Schematic for a beam under bending.3

In collaboration with Dr. David Kim, we have tested our flexible (on 50 or 25 µm thick

FETs under tension and compression. A series of glass tubes with

different curvature and size were custom made. In Figure 7-10, to mount the flexible device on

glass tube, adhesive gel was used. Figure 7-11 shows the device characteristics measured

Effect Transistors

For flexible electronic applications, it is very important to understand device

In practical applications, these

ssion when bent or stretched, respectively.

) during mechanical testing can be expressed

m the neutral axis (NA), and

is radius of curvature (also known as the bending radius). The neutral axis refers to a plane

where neither tension nor compression is applied during bending. The sign of the equation (1)

ve for compression and positive for tension), as shown in

on 50 or 25 µm thick

under tension and compression. A series of glass tubes with

10, to mount the flexible device on

11 shows the device characteristics measured

102

Figure 7-10. Photograph of (A) tension and (B) compression measurement setup.

during mechanical testing of the sample. Figure 7-11 (A) shows reduced carrier mobility and

increased threshold voltage within strain of ± 0.4 %. When these devices return to 0% strain, the

device characteristics are reversible and recoverable with very little change and no signs of

permanent damage. On the other hand, Figure 7-11 (B,C) shows at more extreme tensions

introducing strain of -2.5%, the bending leads to irreversible degradation of the device transfer

characteristics. The gate leakage current is also monitored in these measurements [Figure 7-12].

When the strain is less than ± 0.4%, the change in gate leakage current is negligible. For strains

exceeding -2.5%, we start to observe increased leakage current and device hysteresis, which are

permanent. The increase in gate leakage is an indication of breakdown of the gate oxide’s

intrinsic insulating properties, and the appearance of hysteresis suggests formation of added

traps at the oxide-to-semiconductor interface. In Figure 7-13, we show the oxide capacitance

during bending measurements. The figure shows increasing capacitance values with more

negative strain values. This is expected, since the oxide thickness will become thicker/thinner in

compression/tension, giving rise to a reduced/increased capacitance.4

(A) (B)

103

Figure 7-11. (A) Top: Schematic of device under tension and compression tests. Bottom: Device mobility (black) and threshold voltage (VT, blue) relationship to strain in the saturation (VDS = 2 V) and linear (VDS = 0.1 V) regimes. (B) Photograph of device wrapped around a radius of ~ 1.0 mm to emulate extreme bending, equal to -2.5% strain. (C) Device transfer characteristics (ID-VG) in saturation (VDS = 2 V) and linear (VDS = 0.1 V) regime under flat (black), -2.5 % strain (blue) and returned to flat after bending (red).

These preliminary results provide some insights for future experiments and sample

design. As transistors are made of different layers of materials, it is important to understand which

layer fails first. Metal layers are unlikely to be the first problem as they are much more malleable

and conductive than the rest of the layers. The oxide layer might experience more stress as

oxides are generally stiffer (higher Young’s modulus) and will not be able to handle significant

amounts of bending. The increase in leakage currents most likely occurs when large numbers of

cracks and pinholes are formed during bending. Surface roughening is also anticipated, which

could cause increased trap density at the oxide-to-semiconductor interface. Regarding the NC

-0.4 -0.2 0.0 0.2 0.40

5

10

15

20

25

0.0

0.5

1.0

Strain (%)

VDS

= 2V

0

5

10

15

20

25

30-0.4 -0.2 0.0 0.2 0.4

0.0

0.5

1.0

1.5

Tension

Compression

VDS

= 0.1V

Mo

bil

ity (

cm

2V-1

s-1

)

VT(V)

R = 1.0 mm

10-10

10-9

10-8

10-7

10-6

10-5

10-4

Post-Bent

-2.5%

Strain

Flat

VDS

= 0.1V

-2 -1 0 1 210

-10

10-9

10-8

10-7

10-6

10-5

10-4

After Bent

-2.5%

Strain

Flat

VDS

= 2V

VG (V)

I D(A

)

(A)

(B)

(C)

104

layer, it would be interesting to understand, compared to other semiconductor nanomaterials, how

much stress and strain can be applied before losing their electrical properties. 2,5,6

Figure 7-12. Device output characteristics (ID-VDS) when sample is (A) flat, (B) under -2.5 % strain, and (C) returned to flat. Gate leakage current (IG-VDS) when sample is (D) flat, (E) under -2.5 % strain, and (F) returned to flat.

One difficulty to perform these experiments is the measurement setup. As seen in Figure

7-10, due to the electrode’s orientation and size, and the use of probe tips, accurate and

reproducible high strain measurements are greatly limited. For the next generation of strain

measurements, extended electrodes combined with a zero-insertion-force (ZIF) connector on a

printed circuit board (PCB) should be considered [see Figure 7-14 as example]. Also, from

equation (1), using a thinner substrate can also help achieve higher strain conditions. On the

other hand, to make highly bendable devices, it has been showed that layering the

semiconducting layer at the neutral axis can enable functional device operation at bending radii

down to 100 µm.2

0.0 0.5 1.0 1.5 2.00

20

40

60

80

100

I D (µA

)

VDS

(V)

Flat

0.0 0.5 1.0 1.5 2.00

5

10

15

20

I D (µA

)

VDS

(V)

Bent

0.0 0.5 1.0 1.5 2.00

2

4

6

8

10

I D (µA

)

VDS

(V)

Post-Bent

0.0 0.5 1.0 1.5 2.0

-0.2

-0.1

0.0

0.1

0.2

I G (pA

)

VDS

(V)

Flat

0.0 0.5 1.0 1.5 2.0

0

5

10

15

20

25

I G (pA

)

VDS

(V)

Bent

0.0 0.5 1.0 1.5 2.0

0

3

6

9

12

15

I G (nA

)

VDS

(V)

Post-Bent

(A) (B) (C)

(D) (E) (F)

105

Figure 7-13. Change in oxide capacitance versus strain, normalized to the original flat oxide capacitance.

Figure 7-14. Proposed measurement where electrodes are extended further and connected by a ZIF connector.

7-3: References

(1) Rogers, J. a; Someya, T.; Huang, Y. Materials and Mechanics for Stretchable Electronics. Science 2010, 327, 1603–1607.

(2) Sekitani, T.; Zschieschang, U.; Klauk, H.; Someya, T. Flexible Organic Transistors and Circuits with Extreme Bending Stability. Nat. Mater. 2010, 9, 1015–1022.

(3) Gramoll, K. Mechanics Theory http://www.ecourses.ou.edu/cgi-bin/ebook.cgi?topic=me&chap_sec=04.1&page=theory.

(4) Sekitani, T.; Kato, Y.; Iba, S.; Shinaoka, H.; Someya, T.; Sakurai, T.; Takagi, S. Bending Experiment on Pentacene Field-Effect Transistors on Plastic Films. Appl. Phys. Lett. 2005, 86, 073511.

(5) Koo, M.; Park, K.-I.; Lee, S. H.; Suh, M.; Jeon, D. Y.; Choi, J. W.; Kang, K.; Lee, K. J. Bendable Inorganic Thin-Film Battery for Fully Flexible Electronic Systems. Nano Lett. 2012, 12, 4810–4816.

(6) Wang, C.; Chien, J.-C.; Takei, K.; Takahashi, T.; Nah, J.; Niknejad, A. M.; Javey, A. Extremely Bendable, High-Performance Integrated Circuits Using Semiconducting Carbon Nanotube Networks for Digital, Analog, and Radio-Frequency Applications. Nano Lett. 2012, 12, 1527–1533.

-0.4 -0.2 0.0 0.2 0.4-4

-3

-2

-1

0

1

2

3

∆C

/Co (

%)

Strain (%)

106

CHAPTER 8 Concluding Remarks

In this thesis, we use solution processable organic semiconductors (OSCs) and colloidal

semiconducting nanocrystals (NCs) as platforms to study their use in flexible electronics. The

goal is to exploit the ease of solution processing to create large flexible electronics, and develop

methods to meet device performance and fabrication demands. In Chapter 2, we show solution

processable OSCs are feasible for flexible circuits and sensors. In Chapter 3, we use strong-

coupled colloidal semiconductor NCs to assemble as thin films for active channel. We then dope

channel to fabricate high performance flexible nanocrystal field-effect transistors (NC-FETs), and

integrate them as circuits in concert. In Chapter 4, we evaluate the flicker noise magnitude in

CdSe NC-FETs, and show the noise level in them is promising for low-noise circuit applications.

In Chapter 5, we discover the recovery mechanism in CdSe NC-FETs that allows the use of

photolithography on them without comprising device performance. By integrating the fabrication

developed in Chapter 3 and 5, we show in Chapter 6 and 7 the preliminary results on wafer scale

NCs integrated circuits on rigid and flexible substrates. These scaled circuits have voltage

amplifier bandwidth of a few kHz and ring oscillators with stage delay of 3 µs. With continued

advances in NCs and more complex circuit design, we envision NCs a viable solution

processable materials for large area, low-cost flexible electronics.