IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 32, NO. 1, FEBRUARY 2009 77

Fabrication Processes for Embedding Thin Chipsin Flat Flexible Substrates

Jonathan Govaerts, Wim Christiaens, Erwin Bosman, and Jan Vanfleteren, Member, IEEE

Abstract—These days, a lot of effort is being put in making elec-tronic devices lighter and compacter, as the electronics market israpidly expanding with all sorts of portable devices for home andeveryday use. In this paper, a technology for embedding thin chipsin flexible substrates is proposed that could be the next step for fur-ther reducing weight, while at the same time enhancing mechanicalflexibility of the electronic circuitry. All stages in the technology’sdevelopment cycle are discussed: from technology flow, test designand actual fabrication, to process optimization and characteriza-tion of the results. An outlook on the following steps of this tech-nology is discussed in the conclusion.

Index Terms—Embedding, flexible package, thin chip.

I. INTRODUCTION

F LEXIBLE substrates are often an interesting alternativefor rigid printed circuit boards (PCBs) because they are

light and conformable. This is especially an advantage when in-tegrating electronic devices for wearable applications. A lightand flexible substrate by itself however does not guarantee alight and flexible end result. The flexibility is often drasticallyreduced when rigid components are assembled onto the sub-strate. Considering the current trend of increasing componentdensity, which is of course welcomed for wearable devices, thebenefit of the flexibility of the substrate is more and more over-shadowed by the rigidity of the components. An obvious wayof tackling this issue is to use smaller and thinner and, there-fore, lighter components. This is a trend already in progress [1],[2], as is clear when one looks at the evolution of packages andcompares them chronologically: from DIP over SO and plasticleaded chip carrier (PLCC) down to chip-size packages (CSP)such as quad flat packs (QFPs) and ball grid arrays (BGAs).Going smaller even still, we encounter assembly of bare dies,e.g. with a flip-chip (FC) technology, and even backlapping thedies before assembly, making them thinner. This trend is de-scribed in [3] and illustrated in Table I and Fig. 1.

In this paper, a technology is proposed and elaborated thatcould mean the next step in the above evolution of going

Manuscript received January 15, 2008. Current version published February13, 2009. This work was supported by the EU through the programmes Flex-iDis under Contract IST-004354 and SHIFT under Contract IST-507745. Thiswork was recommended for publication by Associate Editor T. C.-Chiu uponevaluation of the reviewers comments.

The authors are with the Centre for Microsystems Technology (CMST),IMEC, B-3001 Leuven, Belgium, and the Department of Electronics andInformation Systems (ELIS), Ghent University, B-9000 Ghent, Belgium(e-mail: jonathan.govaerts@UGent.be; wim.christiaens@elis.ugent.be;erwin.bosman@intec.ugent.be; jan.vanfleteren@elis.ugent.be).

Color versions of one or more of the figures in this paper are available athttp://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TADVP.2008.2005838

TABLE IEVOLUTION OF PACKAGES

Fig. 1. Pictures of the packages in Table I.

smaller and lighter. Whereas the backlapping technique cur-rently used reduces the chips’ thickness to 400, maybe 200 ,the technology described in this article uses chips thinneddown to approximately 20 . Such thin chips are too fragileto assemble them onto a substrate with standard die assemblytechniques, while the ultra thin chip packaging (UTCP) tech-nology described in what follows, is designed to cope with thisby actually embedding the thin chips inside the substrate.

More (technical) background on thin chip technologies andembedding can be found in [4] and [5].

II. TECHNOLOGY FLOW

The technology investigated here is an enhanced version ofthe Interuniversity Micro-Electronics Centre’s (IMEC) firstUTCP technology [6] with an updated process flow to realizea symmetrical substrate sandwich. The used process flow isdepicted in Fig. 2. Polyimide (PI) is used as substrate material,because it is a high-quality plastic, capable of withstandinghigh temperatures.

The base PI layer is spincoated onto a rigid (glass) carriersubstrate and cured. Then the photodefinable PI is spincoated,

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78 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 32, NO. 1, FEBRUARY 2009

Fig. 2. Process flow design for the UTCP technology.

Fig. 3. Interconnection test pattern design.

illuminated through a mask and developed to define the chipcavity. After curing, the thinned-down chip is placed face up,using BCB in the cavity as adhesive. The BCB is cured, and thetop layer of PI is spincoated and cured in the same way as thebase PI layer (thus creating a symmetrical substrate sandwich).The via holes to the chip contacts are laser drilled and after themetal pattern is realized on top, the substrate can be releasedfrom its carrier.

III. TEST DESIGN

To test the feasibility of the technology a design for the met-allization was made based on the layout of the used test chips.The metal on the substrate is to be patterned so that, fitting thetest chips, a daisy chain (DC) can be measured at several points,as well as contact resistance with a 4-point-probe method (4PT).The principle is illustrated in Fig. 3.

The chips themselves are 5 mm 5 mm and have beenthinned down from about 500 to approximately 20 .The result of this thinning process is given in Fig. 4, for afunctional chip. Also it is illustrated in Fig. 5 how thin the testchips really are, by illuminating one from the back: the siliconhas become somewhat transparent so that the metal patterns onthe front can easily be identified with illumination only fromthe backside. The bond pads of the test chips have been bumpedwith NiAu, approximately 5 ; this acts as a buffer layer forthe laser drilling, to protect the Al contacts. The test chips’peripheral bond pads are designed with several pitches (100,60, and 40 ), but as this is a first test for the feasibility ofthe technology, this article only describes the work done on thecoarsest pitch of 100 : the bondpads are 70 70 ,with a gap in between two pads of 30 .

Fig. 4. Functional chip before and after thinning.

Fig. 5. Thinned-down test chip: zoom on the different peripheral bond pads tobe used (left) and a view of a backlit test chip illustrating the thinness (right).

IV. UTCP FABRICATION

The device is built up on a glass substrate, 5 cm 5 cm.Three layers of spin-on PI, all supplied by HD Microsystems,are involved, and in what follows, they are referred to as, frombottom to top, the base PI layer, the inner (photodefinable) PIlayer and the top PI layer. This layer buildup is symmetrical,with both base and top layer being PI2611 and the inner layerbeing HD7012, to avoid problems with coefficient of thermalexpansion (CTE) mismatch (usually resulting in curling of thesubstrate when the release is carried out). The base layer is at-tached to the rigid glass carrier with adhesion promotor only atthe edges of the carrier, so that later on, the middle area can becut out and removed off its rigid carrier.

Before spinning the base PI at the final speed, shortly spinningat a lower speed, say 500 rpm for a few seconds, is preferableto spread the highly viscous PI a little. Following this, the spin-ning speed is increased to 3000 rpm for 45 s to get a 5- -thicklayer (this will be the thickness after curing). The curing is donein a vacuum oven (with 5 sccm nitrogen flow), with the fol-lowing temperature profile: from 20 (also known as roomtemperature) to 200 with a ramp of 4 /min, then holdingthis 200 for 30 min, another increase to 350 with a rampof 2.5 /min and finally keeping this 350 for 60 min. Thewhole curing process takes about 7 h. This includes the timeneeded for cooling down, when the substrate is left in the vac-uumoven until the temperature has dropped back to room tem-perature.

The next layer consists of photodefinable PI, wherein the cav-ities for the chips are to be made. The PI used for this is HD7012.This layer is applied in a similar way, on top of the base PI layer,but before spinning, it is preferable to plasma-etch the base layerto improve adhesion. This is done by reactive ion etching (RIE),first 2 min with a plasma and

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GOVAERTS et al.: FABRICATION PROCESSES FOR EMBEDDING THIN CHIPS IN FLAT FLEXIBLE SUBSTRATES 79

Fig. 6. Cavity created in the photodefinable PI layer: two close-up top viewsof the cavity are shown on the right.

next another 2 min with a 25 plasma, both at a powersetting of 150 W and a pressure of 100 mTorr.

Spinning the HD7012 is done with the same parameters,namely 5 s at 500 rpm followed by 45 s at 3000 rpm, althoughthis now results in a thickness after curing of approximately36 (HD7012 is with 31.5 still more viscous thanPI2611 with 11–13.5 ). As this is the photodefinablelayer, the following process steps are somewhat different. Firsta soft-bake is introduced to the PI on a hotplate: 4 min at60 , then 4 min at 90 and ultimately 4 min at 110 .Photodefining the cavities means lithographic processes areinvolved, and in this case illumination is needed for 28 s. Atthis point it is crucial that the substrate is illuminated on a blackbackground: since the substrate is transparent, the UV-lightshould be absorbed to avoid random scattering when it isreflected on a white background (resulting in poorly definededges). It is then advisable to wait for approximately half anhour, allowing the PI to take in the effect of the illumination.

Development should then be successful when the substrateis put in PA400D for 90 s with UltraSonic Agitation and thenrinsed in PA400R for 15 s. Both chemicals PA400D and PA400Rwere again obtained from HD Microsystems. After this dry care-fully but thoroughly with a nitrogen pistol. If this is done prop-erly, the cavities in the PI can easily be identified. The next stepis again to cure this layer as well and the same curing setup andprofile can be used as with PI2611. Fig. 6 shows the results atthis point.

The chip is then placed inside the cavity using a mask aligner.The cavity of the substrate is dotted with BCB that will act as ad-hesive: one drop of 30 nL, applied by micropipette, is sufficientfor 5 mm 5 mm cavities. The substrate is then hung upsidedown in a mask adapted for vacuum holding of substrates, whilethe chip is placed face down on the movable substrate table ofthe mask aligner. When aligning is done (under the microscope),the substrate is lowered carefully onto the chip and the drop ofBCB should flow out evenly under the backside of the chip. Thesubstrate can be released from the mask holder and turned over(the adhesion between chip and cavity bottom is at this point al-ready strong enough due to the BCB. To cure the BCB, heatingup to 300 is sufficient from the BCB’s point-of-view, butsince the next cure step will again go up to 350 (curing of thetop PI layer), it is preferable to also use the same curing schemehere as for the PI layers. In Fig. 7 the curing step is shown, aswell as a height measurement of the result. It is clear that the

Fig. 7. After aligning and placing the chip, the BCB is cured in an oven; anatomic force microscopy measurement shows that the PI layer is thicker thanthe thin chip, and even the bumped contact pads can be spotted.

PI cavity, 36 deep, is actually too thick with regards to thechip, being only 20 thick.

Now that the chip is safely inserted, the top layer needs tobe applied to cover it all up. Again the substrates are plasma-etched to improve adhesion, and as PI2611 is not self-priming,in contrast to HD7012, also adhesion promotor has to be spunonto the plasma-etched active surface. This is done for 30 s at3000 rpm, and is followed by a 1-min softbake at 120 . Thetop layer is spun and cured in the same way as the base layer,to have the same layer thickness and a symmetrical package (incross section).

Now that the chip is embedded and covered up by the top PIlayer, holes have to be drilled through 5 PI so that the chip’sbumps (5- -thick electroless NiAu, as mentioned earlier) canbe contacted. The drilling is done with a 355-nm-YAG-laser(laser via drilling) outside of the cleanroom, using an atten-uation of 300 mW (for a 25- spot size), a circular maskof 200 diameter and a Gaussian beam, with 100 pulses at10 000 Hz. The resulting vias have a diameter of on average12 , and are shown in Fig. 8 below. This combination of at-tenuation and via size corresponds to a power setting of approx-imately 69 mW.

The next layer that needs to be put in place is the metalliza-tion layer, that has to route the chip contacts across the substrate.To achieve this, pattern plating is the preferred option, as barechips typically have fine features, in this case a bond pad pitchof 100 . First, the surface with the top PI layer is preparedby plasma-etching to enhance adhesion in the same way as de-scribed above. Then a metallization seed layer is deposited bysputtering: 50 nm of TiW as interface followed by 500 nm Cu

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80 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 32, NO. 1, FEBRUARY 2009

Fig. 8. Laser drilled via holes in the top PI layer to contact the bumped contactpads of the chip underneath, for all three types of bond pads.

for electroplating. Then the (inverted) pattern is aligned and de-fined in a photoresist layer by standard lithography. Note that,as the Cu will be plated into the holes, it is important to havea sufficiently thick layer of photoresist. Aiming for a Cu thick-ness around 6 , the photoresist is spun at 2000 rpm, nomi-nally resulting in a 7.5- –thick photoresist layer. This layer issoft-baked in an oven, 30 min at 90 and then illuminated for20 s under a UV-lamp with an intensity of 10.5 cm .

After the photoresist has been developed, approximately2 min in a standard developer, and baked for 30 min at 120in an oven, the substrate is ready for electroplating. There is aformula used in practice that allows calculating the time neededfor plating a certain thickness at a certain current intensity anda certain area to be plated [7]. Relying on this formula, platingwould be sufficient (over 6 ) at 10 cm for 30 min (so30 mA if a plating area of 3 cm is used). However, this provedto be false in our setup, as too little plating was achieved and,even worse, this plating was very inhomogenously divided overthe surface. Instead, for the same plating area of 3 cm , 15 minat 120 mA gave satisfying results: approximately 7 overthe whole surface area. The electroplating process is illustratedin Fig. 9.

At this point, the whole surface is evidently still shorted bythe remaining seed layer, so this remains to be etched. Afterstripping the photoresist pattern that has been used for the pat-tern plating process, the seed layer is available for etching. Somestandard ways of etching Cu (which is the top seed layer in thiscase) involves warm solutions of and , but theseturned out to be too aggressive and wiped out most of the platedpatterns, even when diluted four times and at less elevated tem-peratures. A simple solution can however be found, by usinga standard micro-etch solution. An 80-s dip, followed by 10 sin a 10%-HCl-solution to clear any remaining -ions fromthe surface, is sufficient for the used 500-nm Cu seed layer. TheTiW seed layer should then be clearly visible, and can be etched,10 s in warm (52 ) and then 15 s in cold (roomtemperature). Especially the warm etch process has to be carriedout very carefully, as this is a very quick process, meaning that

Fig. 9. Electroplating the UTCP for the metallization layer by pattern plating.

Fig. 10. Schematic representation of the metallization process.

the processing window is rather narrow, and underetch can be aproblem. Rinsing and drying then concludes the process stepsneeded for the metallization layer. The metallization processis summarized in Fig. 10, including soldermask deposition andplating of the contacts on the substrate. Fig. 11 shows some re-sults after the last step of the metallization process, being theseed layer etch.

As is common in PCB and flex technologies (and this is there-fore not elaborated here), soldermask is then applied to cover upeverything but the contact areas, so as to protect the Cu tracksagainst oxidation and corrosion, and the contacts can then beplated up electrolessly with Ni to the desired thickness, typi-cally a few micrometers. A Au finish is finally applied on the Nisurface of the contacts to improve (i.e., lower) the contact resis-tance of the contacts.

Now the finished substrate can be cut out and released fromthe glass carrier.

V. PROCESS CONTROL AND OPTIMIZATION

The fabrication, as described above, evidently involves a lotof processing steps, each of which has its own parameters and

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GOVAERTS et al.: FABRICATION PROCESSES FOR EMBEDDING THIN CHIPS IN FLAT FLEXIBLE SUBSTRATES 81

Fig. 11. Results after the seed layer etch.

sensitivities. This implies that a lot of work can be done on op-timizing the processes individually as well as integrating themin an optimal way.

As a general remark, the substrate material PI absorbs sig-nificant amounts of moisture, called swelling, when left out inthe open (even out in the cleanroom), and this can affect certainprocess steps. To avoid these effects, the substrates should al-ways be treated in an oven before processing to dry them com-pletely (or as good as completely). A few hours at 200 isusually sufficient.

It is also very important to carefully match the chip to thecavity in the PI, for the mechanical robustness (it is preferablein this sense to have smooth layers rather than edges and singu-larities where stresses are focussed), but especially for the met-allization afterwards. The matching has to be done both in thelateral dimensions and in thickness. The thickness of the pho-todefinable layer can be reliably adjusted by changing the spin-ning parameters. For example spinning at 4000 rpm results in a26- -deep cavity, better suiting the 20- -thin chips.

Laser drilling is a step that can be optimized as well, de-pending on bump size and via hole diameter. In the describedprocess in Fig. 8 for example, there is just one hole drilled foreach bump, but if we focus on the larger 70- bumps (ofthe 100- -pitch-pattern), it seems obvious to optimize this bylaser drilling a 3 3 matrix of the same holes on each bump,ensuring more contacting possibilities for the following (sput-tered and plated) metallization layer. This is what has been donein Fig. 12.

Finally, some trials were done to speed up the electroplatingprocess in the metallization step. From 15 min at 120 mA, theplating time could be reduced to 2 min at 1000 mA, withoutapparent problems or differences in the results.

VI. CHARACTERIZATION

The electrical measurements done on the first batch of fab-ricated UTCPs are to be found in Tables II and III. DCx-y inTable III means that the resistance between the contact padsmarked with DCx and DCy has been measured. Please notethat DC8-7 is mentioned twice in Table III, and it should bementioned that the four-point measurements are uncomfortably

Fig. 12. Drilling nine via holes instead of one to increase contact area betweenchip bump and metallization layer.

TABLE II4PT-MEASUREMENTS ���

TABLE IIIDC MEASUREMENTS ���

close to the lower limit of the SMU’s range, meaning that it issignificantly below 10 .

The first batch contained 15 substrates, of which four failed inthe course of processing. Each substrate was patterned with fourfour-point-probe patterns, and one complete peripheral daisychain, measurable at eight contacts. Still a lot of problems occurat the chip-cavity interface, where any gap causes difficultiesfor the metallization that has to bridge this gap. This is shownin Fig. 13 and it means not all contacts are available for mea-surements (as mentioned in Tables II and III). The problem isintroduced during lithography and developing of a photoresistlayer on a nonflat surface, because the layer will not have thesame thickness everywhere: it will be significantly thicker nearthe edges of the gap, as is illustrated in Fig. 13.

Table II shows consistent results for the contact resistance of. This represents the contact resistance of nine

parallel via holes. Table III learns that the metallization on theUTCP, as measured in DC7-6, DC5-4, and DC3-2, has a some-what larger resistance value per square, being approximately

. Using these figures, and the measurements

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82 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 32, NO. 1, FEBRUARY 2009

Fig. 13. Bridging the gap at the chip-cavity interface is the main challenge atthis point.

Fig. 14. Burning the soldermask by electrically overheating through the daisychain did not affect the electrical performance.

in Table III, a recalculation results in a value for the on-chip met-allization resistance of, again approximately, ,which is acceptable for the standard metal (aluminum) layer ofthe test chips.

Lastly, one daisy chain was tested for current loading ca-pacity, and it was found that when 180 mA (corresponding tomore than 2 W) was fed through the daisy chain of a UTCP, stillattached to its carrier, the soldermask started burning. Some pic-tures are shown in Fig. 14. This thermal “treatment” caused thechip to crack (perhaps due to thermally induced tensions be-tween chip and soldermask). Worth mentioning is that all thisseems not to have had any repercussions on the electrical func-tioning of the device, although it should be said that since thisis only a test chip, the same might not be true for a functionalchip with active and doped areas.

VII. CONCLUSION

In this paper, a technology is reported on how to embed ultrathin chips in a flat flexible substrate, thus creating a flat, light-weight, and flexible package. The importance of the packagebeing flat lies mainly in the—near rather than far—future: thenext foreseeable steps would be to embed several chips in thesame flexible substrate and build up more layers on top with ad-ditional active or passive (resistors and capacitors) structures,increasing functionality with reduced area and weight. It is es-pecially these additional (thin-film) layers that require a flat sub-strate surface to begin with.

The feasibility of this technology has been proven byelectrical measurements, although further fabrication testsand measurements are needed to sufficiently guarantee theapplicability and usefulness of the technology. From an in-terconnection point-of-view, the next challenges would be todownsize the dimensions of the interconnection, in particularthe chip contact pitch, and, further on, take a closer look atalignment techniques and achievable accuracies when embed-ding several dies in the same substrate. From a semiconductorpoint-of-view, it should be investigated what the influence isof thinning down, embedding and especially bending—after aswell as during bending—the chip on its electrical behavior.

To conclude: a new packaging technology has been devel-oped, showing promising possibilities in both packaging and insystem-integration industries, although much remains to be in-vestigated before it can be considered a standard industrial tech-nology.

ACKNOWLEDGMENT

This research was carried out at the Centre for MicrosystemsTechnology (CMST), an IMEC associated laboratory at GhentUniversity, Department of Electronics and Information Systems(ELIS).

REFERENCES

[1] K. Y. Chen, R. L. D. Zenner, M. Arneson, and D. Mountain, “Ultra-thinelectronic device package,” IEEE Trans. Adv. Packag., vol. 23, no. 1,pp. 22–26, Feb. 2000.

[2] C. Banda, R. W. Johnson, T. Zhang, Z. Hou, and H. K. Charles, “Flipchip assembly of thinned silicon die on flex substrates,” IEEE Trans.Electron. Packag. Manufact., vol. 31, no. 1, pp. 1–8, Jan. 2008.

[3] C. A. Harper, Electronic Packaging and Interconnection Handbook,4th ed. New York: McGraw-Hill, 2005.

[4] J. Balde, Foldable Flex and Thinned Silicon Chips for Multichip Pack-aging. Boston, MA: Kluwer, 2002.

[5] J. Fjelstadt, Flexible Circuit Technology (Addendum), 3rd ed. Delhi,India: BR Publishing, 2008, pp. 62–78.

[6] W. Christiaens, B. Vandevelde, E. Bosman, and J. Vanfleteren, “UTCP:60 um thick bendable chip package,” presented at the IWLPS, San Jose,CA, Nov. 2006.

[7] M. Schlesinger and M. Paunovic, Modern Electroplating, 4th ed.New York: Wiley, 2000.

Jonathan Govaerts received the degree in electrical engineering, with a special-ization in micro- and opto-electronics, from Ghent University, Ghent, Belgium,and is currently working toward the Ph.D. degree at the Centre for Microsys-tems Technology (CMST), a research laboratory affiliated with both IMEC andGhent University.

His research focuses mainly on the assembly and interconnection of micro-electronics on and in flexible substrates.

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GOVAERTS et al.: FABRICATION PROCESSES FOR EMBEDDING THIN CHIPS IN FLAT FLEXIBLE SUBSTRATES 83

Wim Christiaens was born in Zottegem, Belgium, in 1981. He graduatedfrom Ghent University, Ghent, Belgium, as an Electrical Engineer with majorsin micro- and opto-electronics in 2004. He is currently working toward thePh.D. degree in electrical engineering at Centre for Microsystems Technology(CMST), ELIS Department, Ghent University.

His research is focused on the embedding of active and passive componentsin polyimide substrates.

Erwin Bosman was born in Asse, Belgium, in 1980. He graduated at the GhentUniversity, Gent, Belgium, in 2004 as an Electrical Engineer in telecommuni-cation. Since then has been working in the clean-rooms of the Centre for Mi-crosystems Technology (CMST) at the INTEC Department of the University ofGhent, Gent, Belgium, toward the Ph.D. degree in electrical engineering.

His research was focused on micro-structuring for electronic and optical ap-plications by laser ablation techniques. Later his research shifted towards thefabrication and integration of optical multimode interconnections on flexiblesubstrates.

Jan Vanfleteren (M’01) received the Ph.D. degree in electronic engineeringfrom the University of Ghent, Ghent, Belgium, in 1987.

He is currently a Senior Engineer and Project Manager at IMEC, INTEC/TFCG Microsystems Group, nowadays Centre for Microsystems Technology(CMST), and is involved in the development of novel interconnection, assembly,and substrate technologies, especially in the field of flexible and stretchable elec-tronics. In 2004 he was appointed as part-time Professor at Ghent University.He is (co)-author of over 100 papers in international journals and conferencesand he holds six patents/patent application

Dr.Vanfleteren is a member of IMAPS.

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